ANALOG DEVICES AD5272, AD5274 Service Manual

1024-/256-Position, 1% Resistor Tolerance Error,

I2C Interface and 50-TP Memory Digital Rheostat

FEATURES

Single-channel, 1024-/256-position resolution 20 kΩ, 50 kΩ, 100 kΩ nominal resistance Maximum ±1% nominal resistor tolerance error 50-times programmable (50-TP) wiper memory Rheostat mode temperature coefficient: 5 ppm/°C

2.7 V to 5.5 V single-supply operation ±2.5 V to ±2.75 V dual-supply operation for ac or bipolar

operations

2

I

C-compatible interface Wiper setting readback Power on refreshed from 50-TP memory Thin LFCSP 10-lead, 3 mm × 3 mm × 0.8 mm package Compact MSOP, 10-lead 3 mm × 4.9 mm × 1.1 mm package

APPLICATIONS

Mechanical rheostat replacements Op-amp: variable gain control Instrumentation: gain, offset adjustment Programmable voltage to current conversions Programmable filters, delays, time constants Programmable power supply Sensor calibration

SCL

SDA

ADDR

RESET

AD5272/AD5274

FUNCTIONAL BLOCK DIAGRAM

V

DD

POWER-ON

RESET

I2C

SERIAL

INTERFACE

V

SS

AD5272/AD5274

RDAC

REGIS TER

10/8

50-TP

MEMORY

BLOCK

EXT_CAP GND

Figure 1.

A

W

08076-001

GENERAL DESCRIPTION

The AD5272/AD52741 are single-channel, 1024-/256-position digital rheostats that combine industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package.

The AD5272/AD5274 ensure less than 1% end-to-end resistor tolerance error and offer 50-times programmable (50-TP) memory.

The guaranteed industry leading low resistor tolerance error feature simplifies open-loop applications as well as precision calibration and tolerance matching applications.

1

Protected by U.S. Patent Number 7688240.;

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The AD5272/AD5274 device wiper settings are controllable through the I

2

C-compatible digital interface. Unlimited adjustments are allowed before programming the resistance value into the 50-TP memory. The AD5272/AD5274 do not require any external voltage supply to facilitate fuse blow and there are 50 opportunities for permanent programming. During 50-TP activation, a permanent blow fuse command freezes the wiper position (analogous to placing epoxy on a mechanical trimmer).

The AD5272/AD5274 are available in a 3 mm × 3 mm 10-lead LFCSP package and in a 10-lead MSOP package. The parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C.

AD5272/AD5274

REVISION HISTORY

11/10—Rev. B to Rev. C

Changes to Figure 24...................................................................... 14

5/10—Rev. A to Rev. B

Added LFCSP Package.................................................. Throughout

Changed OTP to 50-TP ................................................ Throughout

Changes to Features Section and Applications Section............... 1

Added Endnote 1.............................................................................. 1

Changes to Table 1............................................................................ 3

Added Table 3.................................................................................... 4

Changes to Table 4............................................................................ 5

Added Table 6.................................................................................... 6

Changes to Table 8 and Table 9....................................................... 9

Added Figure 5................................................................................ 10

Added Exposed Pad Note to Table 10.......................................... 10

Changes to Typical Performance Characteristics....................... 11

Changes to Resistor Performance Mode Section ....................... 23

Updated Outline Dimensions....................................................... 25

Changes to Ordering Guide.......................................................... 26

3/10—Rev. 0 to Rev. A

Changes to Product Title and General Description Section....... 1

Changes to Theory of Operation Section.................................... 15

10/09—Revision 0: Initial Version

Rev. C | Page 2 of 28

AD5272/AD5274

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—AD5272

VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution 10 Bits Resistor Integral Nonlinearity R

R Resistor Differential Nonlinearity2 R-DNL Nominal Resistor Tolerance

R-Perf Mode4 See Table 2 and Table 3 −1 ±0.5 +1 %

Normal Mode ±15 % Resistance Temperature Coefficient Wiper Resistance Code = zero scale 35 70 Ω

RESISTOR TERMINALS

Terminal Voltage Range Capacitance5 A f = 1 MHz, measured to GND, code = half scale 90 pF Capacitance5 W f = 1 MHz, measured to GND, code = half scale 40 pF Common-Mode Leakage Current5 V

DIGITAL INPUTS

Input Logic5

High V

Low V Input Current IIN ±1 µA Input Capacitance5 C

DIGITAL OUTPUT

Output Voltage5

High VOH R

Low VOL R V V Tristate Leakage Current −1 +1 µA Output Capacitance5 5 pF

POWER SUPPLIES

Single-Supply Power Range VSS = 0 V 2.7 5.5 V Dual-Supply Power Range ±2.5 ±2.75 V Supply Current

Positive IDD 1 µA

Negative ISS −1 µA 50-TP Store Current

5, 8

Positive I

Negative I 50-TP Read Current

5, 9

Positive I

Negative I Power Dissipation10 V

2, 3

R-INL RAW= 20 kΩ, |VDD − VSS| = 3.0 V to 5.5 V −1 +1 LSB

= 20 kΩ, |VDD − VSS| = 2.7 V to 3.0 V −1 +1.5 LSB

AW

= 50 kΩ, 100 kΩ −1 +1 LSB

AW

5, 6

Code = full scale 5 ppm/°C

5, 7

V

= VW 50 nA

A

2.0 V

INH

0.8 V

INL

5 pF

IN

= 2.2 kΩ to VDD V

PULL_UP

= 2.2 kΩ to VDD

PULL_UP

= 2.7 V to 5.5 V, VSS = 0 V 0.4 V

DD

= 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V 0.6 V

DD

−1 +1 LSB

V

SS

− 0.1 V

DD

V

DD

DD_OTP_STORE

SS_OTP_STORE

4 mA

−4 mA

DD_OTP_READ

SS_OTP_READ

500 µA

−500 µA = VDD or VIL = GND 5.5 µW

IH

Rev. C | Page 3 of 28

AD5272/AD5274

Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit

Power Supply Rejection Ratio5 PSRR ∆VDD/∆VSS = ±5 V ± 10% dB R R R

DYNAMIC CHARACTERISTICS

5, 11

Bandwidth −3 dB, RAW = 10 kΩ, Terminal W, see Figure 41 kHz R R R Total Harmonic Distortion VA = 1 V rms, f = 1 kHz, code = half scale dB R R R Resistor Noise Density Code = half scale, TA = 25°C, f = 10 kHz nV/√Hz R R R

1

Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions.

3

The maximum current in each code is defined by IAW = (VDD − 1)/RAW.

4

The terms, resistor performance mode and R-Perf mode, are used interchangeably. See the Resistor Performance Mode section.

5

Guaranteed by design and not subject to production test.

6

See Figure 24 for more details.

7

Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar

signal adjustment.

8

Different from operating current, the supply current for the fuse program lasts approximately 55 ms.

9

Different from operating current, the supply current for the fuse read lasts approximately 500 ns.

10

P

is calculated from (IDD × VDD) + (ISS × VSS).

DISS

11

All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V.

= 20 kΩ −66 −55

AW

= 50 kΩ −75 −67

AW

= 100 kΩ −78 −70

AW

= 20 kΩ 300

AW

= 50 kΩ 120

AW

= 100 kΩ 60

AW

= 20 kΩ −90

AW

= 50 kΩ −88

AW

= 100 kΩ −85

AW

= 20 kΩ 50

AW

= 50 kΩ 25

AW

= 100 kΩ 32

AW

Table 2. AD5272 Resistor Performance Mode Code Range

Resistor Tolerance Per Code |VDD − VSS| = 4.5 V to 5.5 V |VDD − VSS| = 2.7 V to 4.5 V

R-TOLERANCE

1% R-Tolerance From 0x078 to 0x3FF From 0x0BE to 0x3FF 2% R-Tolerance From 0x037 to 0x3FF From 0x055 to 0x3FF 3% R-Tolerance From 0x028 to 0x3FF From 0x037 to 0x3FF

Table 3. AD5272 50 kΩ and 100 kΩ Resistor Performance Mode Code Range

Resistor Tolerance Per Code RAW = 50 kΩ RAW = 100 kΩ

R-TOLERANCE

1% R-Tolerance From 0x078 to 0x3FF From 0x04B to 0x3FF 2% R-Tolerance From 0x055 to 0x3FF From 0x032 to 0x3FF 3% R-Tolerance From 0x032 to 0x3FF From 0x019 to 0x3FF

Rev. C | Page 4 of 28

AD5272/AD5274

ELECTRICAL CHARACTERISTICS—AD5274

VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted.

Table 4.

Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit

DC CHARACTERISTICS—

RHEOSTAT MODE Resolution 8 Bits Resistor Integral Nonlinearity Resistor Differential

Nonlinearity

2

Nominal Resistor Tolerance

R-Perf Mode4 See Table 5 and Table 6 −1 ±0.5 +1 % Normal Mode ±15 %

Resistance Temperature

Coefficient

5, 6

Wiper Resistance Code = zero scale 35 70 Ω

RESISTOR TERMINALS

Terminal Voltage Range

5, 7

Capacitance5 A f = 1 MHz, measured to GND, code = half scale 90 pF Capacitance5 W f = 1 MHz, measured to GND, code = half scale 40 pF Common-Mode Leakage

Current

5

DIGITAL INPUTS

Input Logic5

High V

Low V Input Current IIN ±1 µA Input Capacitance5 C

DIGITAL OUTPUT

Output Voltage5

High VOH R

Low VOL R V V Tristate Leakage Current −1 +1 µA Output Capacitance5 5 pF

POWER SUPPLIES

Single-Supply Power Range VSS = 0 V 2.7 5.5 V Dual-Supply Power Range ±2.5 ±2.75 V Supply Current

Positive IDD 1 µA

Negative ISS −1 µA OTP Store Current

5, 8

Positive I

Negative I OTP Read Current

5, 9

Positive I

Negative I Power Dissipation10 V Power Supply Rejection Ratio5 PSRR ∆VDD/∆VSS = ±5 V ± 10% dB R R R

2, 3

R-INL −1 +1 LSB

R-DNL

−1 +1 LSB

Code = full scale 5 ppm/°C

V

2.0 V

INH

0.8 V

INL

5 pF

IN

DD_OTP_STORE

SS_OTP_STORE

DD_OTP_READ

SS_OTP_READ

= VW 50 nA

A

= 2.2 kΩ to VDD V

PULL_UP

= 2.2 kΩ to VDD

PULL_UP

= 2.7 V to 5.5 V, VSS = 0 V 0.4 V

DD

= 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V 0.6 V

DD

4 mA

−4 mA

500 µA

−500 µA = VDD or VIL = GND 5.5 µW

IH

= 20 kΩ −66 −55

AW

= 50 kΩ −75 −67

AW

= 100 kΩ −78 −70

AW

V

SS

− 0.1 V

DD

V

DD

Rev. C | Page 5 of 28

AD5272/AD5274

Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit

DYNAMIC CHARACTERISTICS

Bandwidth −3 dB, RAW = 10 kΩ, Terminal W, see Figure 41 kHz R R R Total Harmonic Distortion VA = 1 V rms, f = 1 kHz, code = half scale dB R R R Resistor Noise Density Code = half scale, TA = 25°C, f = 10 kHz nV/√Hz R R R

1

Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions.

3

The maximum current in each code is defined by IAW = (VDD − 1)/RAW.

4

The terms, resistor performance mode and R-Perf mode, are used interchangeably. See the Resistor Performance Mode section.

5

Guaranteed by design and not subject to production test.

6

See Figure 24 for more details.

7

Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar

signal adjustment.

8

Different from operating current, the supply current for the fuse program lasts approximately 55 ms.

9

Different from operating current, the supply current for the fuse read lasts approximately 500 ns.

10

P

is calculated from (IDD × VDD) + (ISS × VSS).

DISS

11

All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V.

5, 11

= 20 kΩ 300

AW

= 50 kΩ 120

AW

= 100 kΩ 60

AW

= 20 kΩ −90

AW

= 50 kΩ −88

AW

= 100 kΩ −85

AW

= 20 kΩ 50

AW

= 50 kΩ 25

AW

= 100 kΩ 32

AW

Table 5. AD5274 Resistor Performance Mode Code Range

Resistor Tolerance per Code |VDD − VSS| = 4.5 V to 5.5 V |VDD − VSS| = 2.7 V to 4.5 V

R-TOLERANCE

1% R-Tolerance From 0x1E to 0xFF From 0x32 to 0xFF 2% R-Tolerance From 0x0F to 0xFF From 0x19 to 0xFF 3% R-Tolerance From 0x06 to 0xFF From 0x0E to 0xFF

Table 6. AD5274 50 kΩ and 100 kΩ Resistor Performance Mode Code Range

Resistor Tolerance per Code RAW = 50 kΩ RAW = 100 kΩ

R-TOLERANCE

1% R-Tolerance From 0x1E to 0xFF From 0x14 to 0xFF 2% R-Tolerance From 0x14 to 0xFF From 0x0F to 0xFF 3% R-Tolerance From 0x0A to 0xFF From 0x0A to 0xFF

Rev. C | Page 6 of 28

AD5272/AD5274

INTERFACE TIMING SPECIFICATIONS

VDD = 2.5 V to 5.5 V; all specifications T

Table 7.

Limit at T Parameter Conditions1 Min Max Unit Description

2

f

Standard mode 100 kHz Serial clock frequency

SCL

Fast mode 400 kHz Serial clock frequency t1 Standard mode 4 µs t Fast mode 0.6 µs t t2 Standard mode 4.7 µs t Fast mode 1.3 µs t t3 Standard mode 250 ns t Fast mode 100 ns t t4 Standard mode 0 3.45 µs t Fast mode 0 0.9 µs t t5 Standard mode 4.7 µs t Fast mode 0.6 µs t t6 Standard mode 4 µs t Fast mode 0.6 µs t High speed mode 160 ns t t7 Standard mode 4.7 µs t Fast mode 1.3 µs t t8 Standard mode 4 µs t Fast mode 0.6 µs t t9 Standard mode 1000 ns t Fast mode 300 ns t t10 Standard mode 300 ns t Fast mode 300 ns t t11 Standard mode 1000 ns t Fast mode 300 ns t t

Standard mode 1000 ns

11A

Fast mode 300 ns

t12 Standard mode 300 ns t Fast mode 300 ns t t13

3

t

Fast mode 0 50 ns Pulse width of spike suppressed

SP

4, 5

t

500 ns Command execute time

EXEC

t

RDAC_R-PERF

t

RDAC_NORMAL

t

MEMORY_READ

t

MEMORY_PROGRAM

t

RESET

t

POWER-UP

1

Maximum bus capacitance is limited to 400 pF.

2

The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior

of the part.

3

Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode.

4

Refer to t

5

Refer to t

6

Maximum time after VDD − VSS is equal to 2.5 V.

2 µs RDAC register write command execute time (R-Perf mode)

6 µs Memory readback execute time

350 ms Memory program time

600 µs Reset 50-TP restore time

6

2 ms Power-on 50-TP restore time

and t

RDAC_R-PERF

MEMORY_READ

pulse time

RESET

600 ns RDAC register write command execute time (normal mode)

for RDAC register write operations.

RDAC_NORMAL

t

and

MEMORY_PROGRAM

for memory commands operations.

to T

MIN

, unless otherwise noted.

MAX

, T

MIN

MAX

20 ns

, SCL high time

HIGH

, SCL high time

HIGH

, SCL low time

LOW

, SCL low time

LOW

, data setup time

SU;DAT

, data setup time

SU;DAT

, data hold time

HD;DAT

, data hold time

HD;DAT

, set-up time for a repeated start condition

SU;STA

, set-up time for a repeated start condition

SU;STA

, hold time (repeated) start condition

HD;STA

, hold time (repeated) start condition

HD;STA

, hold time (repeated) start condition

HD;STA

, bus free time between a stop and a start condition

BUF

, bus free time between a stop and a start condition

BUF

, setup time for a stop condition

SU;STO

, setup time for a stop condition

SU;STO

, rise time of SDA signal

RDA

, rise time of SDA signal

RDA

, fall time of SDA signal

FDA

, fall time of SDA signal

FDA

, rise time of SCL signal

RCL

, rise time of SCL signal

RCL

, rise time of SCL signal after a repeated start condition and

t

RCL1

after an acknowledge bit

, rise time of SCL signal after a repeated start condition and

t

RCL1

after an acknowledge bit

, fall time of SCL signal

FCL

, fall time of SCL signal

FCL

Minimum RESET low time

Rev. C | Page 7 of 28

AD5272/AD5274

Shift Register and Timing Diagrams

C3

0 0

CONTROL BI TS

SCL

t

6

SDA

t

7

PS S P

RESET

C2

t

2

DB9 (MSB) DB0 (LSB)

C0 C1

D9

D7 D6 D5 D4 D3

D8

Figure 2. Shift Register Content

t

11

t

4

t

12

t

1

t

3

5

Figure 3. 2-Wire Serial Interface Timing Diagram

DATA BIT S

t

6

t

10

D2 D1

t

1

3

D0

08076-003

t

8

t

9

08076-002

Rev. C | Page 8 of 28

AD5272/AD5274

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 8.

Parameter Rating

VDD to GND –0.3 V to +7.0 V VSS to GND +0.3 V to −7.0 V VDD to VSS 7 V VA, VW to GND VSS − 0.3 V, VDD + 0.3 V Digital Input and Output Voltage to GND −0.3 V to VDD + 0.3 V EXT_CAP to VSS 7 V IA, IW

Continuous

RAW = 20 kΩ ±3 mA RAW = 50 kΩ, 100 kΩ ±2 mA

Pulsed1

Frequency > 10 kHz ±MCC2/d3

Frequency ≤ 10 kHz ±MCC2/√d3 Operating Temperature Range4 −40°C to +125°C Maximum Junction Temperature

(T

Maximum)

J

150°C

Storage Temperature Range −65°C to +150°C Reflow Soldering

Peak Temperature 260°C Time at Peak Temperature 20 sec to 40 sec

Package Power Dissipation (TJ max − TA)/θJA

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A and W terminals at a given resistance.

2

Maximum continuous current

3

Pulse duty factor.

4

Includes programming of 50-TP memory.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is defined by JEDEC specification JESD-51 and the value is dependent on the test board and test environment.

Table 9. Thermal Resistance

Package Type θ

1

θ

JA

Unit

JC

10-Lead LFCSP 50 3 °C/W 10-Lead MSOP 135 N/A °C/W

1

JEDEC 2S2P test board, still air (0 m/s air flow).

ESD CAUTION

Rev. C | Page 9 of 28

ANALOG DEVICES AD5272, AD5274 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—AD5272

ELECTRICAL CHARACTERISTICS—AD5274

INTERFACE TIMING SPECIFICATIONS

Shift Register and Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION