ANALOG DEVICES AD 5259 BRMZ Datasheet

AD5259

Rev. C Document Feedback

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05026-001

RDAC

REGISTER

RDAC

DATA

CONTROL

COMMAND

DECODE LOGIC

ADDRESS

DECODE LOGIC

CONTROL LOGIC

AD5259

I2C

SERIAL

INTERFACE

POWER-

ON RESET

A W B

SCL SDA

AD0 AD1

V

DD

V

LOGIC

GND

RDAC

EEPROM

8

05026-003

COMMAND

DECODE LOGIC

ADDRESS

DECODE LOGIC

CONTROL

LOGIC

SCL

SDA

AD0 AD1

GND

EEPROM

I2C

SERIAL

INTERFACE

RDAC

REGISTER

AND

LEVEL

SHIFTER

A

W

B

V

LOGIC

V

DD

05026-002

AD5259

TOP VIEW

(Not to Scale)

W

1

AD0

2

AD1

3

SDA

4

SCL

5

A B V

DD

GND V

LOGIC

10

9 8 7 6

Nonvolatile, I2C-Compatible

Data Sheet

FEATURES

Nonvolatile memory maintains wiper settings 256-position Thin LFCSP-10 (3 mm x 3 mm x 0.8 mm) package Compact MSOP-10 (3 mm × 4.9 mm × 1.1mm) package

2

I

C®-compatible interface

V

pin provides increased interface flexibility

LOGIC

End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Resistance tolerance stored in EEPROM (0.1% accuracy) Power-on EEPROM refresh time < 1ms Software write protect command Address Decode Pin AD0 and Pin AD1 allow

4 packages per bus 100-year typical data retention at 55°C Wide operating temperature −40°C

3 V to 5 V single supply

APPLICATIONS

LCD panel V LCD panel brightness and contrast control Mechanical potentiometer replacement in new designs Programmable power supplies RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment Fiber to the home systems Electronics level settings

adjustment

COM

GENERAL DESCRIPTION

to +125°C

256-Position, Digital Potentiometer

FUNCTIONAL BLOCK DIAGRAMS

Figure 1. Block Diagram

Figure 2. Block Diagram Showing Level Shifters

CONNECTION DIAGRAM

The AD5259 provides a compact, nonvolatile LFCSP-10 (3 mm × 3 mm) or MSOP-10 (3 mm × 4.9 mm) packaged solution for 256-position adjustment applications. These devices perform the same electronic adjustment function as mechanical potentiometers

1

or variable resistors, but

with enhanced resolution and solid-state reliability.

The wiper settings are controllable through an I digital interface that is also used to read back the wiper register and EEPROM content. Resistor tolerance is also stored within EEPROM, providing an end-to-end tolerance accuracy of 0.1%.

A separate V users who need multiple parts on one bus, Address Bit AD0 and Address Bit AD1 allow up to four devices on the same bus.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change with out notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

pin delivers increased interface flexibilit y. For

LOG IC

2

C-compatible

Figure 3. Pinout

1

The terms digital potentiometer, VR (variable resistor), and RDAC are used

interchangeably.

AD5259 Data Sheet

TABLE OF CONTENTS

Specifications ..................................................................................... 3

I2C-Compatible Format ................................................................. 16

Electrical Characteristics ............................................................. 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Test Circuits ..................................................................................... 13

Theory of Operation ...................................................................... 14

Programming the Variable Resistor ......................................... 14

Programming the Potentiometer Divider ............................... 14

I2C-Compatible Interface............................................................... 15

Writi ng ......................................................................................... 15

Storing/Restoring ....................................................................... 15

Reading ........................................................................................ 15

Generic Interface ........................................................................ 16

Write Modes ................................................................................ 16

Read Modes ................................................................................. 17

Store/Restore Modes .................................................................. 17

Tolerance Readback Modes ...................................................... 18

ESD Protection of Digital Pins and Resistor Terminals ........ 19

Power-Up Sequence ................................................................... 19

Layout and Power Supply Bypassing ....................................... 19

Multiple Devices on One Bus ................................................... 19

Evaluation Board ........................................................................ 19

Display Applications ...................................................................... 20

Circuitry ...................................................................................... 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 22

REVISION HISTORY

10/12—Rev. B to Rev. C

Changed Maximum Temperature Value from 85°C to 125°C

(Throughout) .................................................................................... 1

Changes to Table 1 ............................................................................ 3

Updated Outline Dimensions ....................................................... 21

Changes to Ordering Guide .......................................................... 22

5/10—Rev. A to Rev. B

Changes to Figure 5 .......................................................................... 7

Changes to Storing/Restoring Section ......................................... 15

Changes to Table 7 .......................................................................... 16

Changes to Table 14 ........................................................................ 17

Updated Outline Dimensions ....................................................... 21

7/05—Rev. 0 to Rev. A

Added 10-Lead LFCSP ...................................................... Universal

Changes to Features Section and

General Description Section ............................................................ 1

Changes to Table 1 ............................................................................. 3

Changes to Table 2 and Added Figure 4 ......................................... 5

Changes to Table 4 ............................................................................. 7

Changes to Figure 27 Caption ...................................................... 11

Changes to Theory of Operation Section.................................... 14

Changes to I

Changes to Table 5 .......................................................................... 16

Changes to Multiple Devices on One Bus Section ..................... 19

Updated Figure 49 Caption ........................................................... 21

Changes to Ordering Guide .......................................................... 21

2/05—Revision 0: Initial Version

2

C-Compatible Interface Section ............................ 15

Rev. C | Page 2 of 24

Data Sheet AD5259

10 kΩ

−2

±0.2

+2

AB

WFSE

Zero-Scale Error

V

WZSE

Code = 0x00

50 kΩ/100 kΩ

0

0.2

0.5

LSB

W

RESISTOR TERMINALS

A, B, W

Common-Mode Leakage

ICM

VA = VB = VDD/2

10 nA

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD = V

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS:

RHEOSTAT MODE

Resistor Differential Nonlinearity R-DNL RWB, VA = no connect LSB

5 kΩ –1 ±0.2 +1 10 kΩ −1 ±0.1 +1 50 kΩ/100 kΩ −0.5 ±0.1 +0.5

Resistor Integral Nonlinearity R-INL RWB, VA = no connect LSB

5 kΩ –4 ±0.3 +4

50 kΩ/100 kΩ −1 ±0.4 +1 Nominal Resistor Tolerance ΔRAB TA = 25°C, VDD = 5.5 V –30 +30 % Resistance Temperature Coefficient (ΔRAB x 106)/

Total Wiper Resistance RWB Code = 0x00 75 350 Ω

DC CHARACTERISTICS:

POTENTIOMETER DIVIDER MODE Differential Nonlinearity DNL LSB

5 kΩ –1 ±0.2 +1

10 kΩ −0.5 ±0.1 +0.5

50 kΩ/100 kΩ −0.5 ±0.2 +0.5 Integral Nonlinearity INL LSB

5 kΩ –1 ±0.2 +1

10 kΩ −0.5 ±0.1 +0.5

50 kΩ/100 kΩ −0.5 ±0.1 +0.5 Full-Scale Error V

5 kΩ −7 −3 0

10 kΩ −4 −1.5 0

50 kΩ/100 kΩ −1 −0.4 0

= 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C, unless otherwise noted.

LOGIC

Code = 0x00/0x80 500/15 ppm/°C

(R

x ΔT)

Code = 0xFF LSB

5 kΩ −40°C < TA < +85°C 0 2.5 4 LSB

+85°C < TA < +125°C 6 LSB

10 kΩ −40°C < TA < +85°C 0 1 3 LSB

+85°C < TA < +125°C 4 LSB

Voltage Divider Temperature

Coefficient

Voltage Range V Capacitance A, B C

Capacitance W CW f = 1 MHz, measured to GND,

(∆VW x 106)/ (V

x ∆T)

Code = 0x00/0x80 60/5 ppm/°C

GND VDD V

f = 1 MHz, measured to GND,

A, B

45 pF

code = 0x80

60 pF

code = 0x80

Rev. C | Page 3 of 24

AD5259 Data Sheet

SDA, AD0, AD1

VIN = 0 V or 5 V

0.01

±1

DD

LOGIC

−40°C < TA < +85°C

3 6

µA

LOGIC(PROG)

DISS

B

N_WB

Parameter Symbol Conditions Min Typ1 Max Unit

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH 0.7 × VL VL + 0.5 V Input Logic Low VIL −0.5 0.3 × VL V Leakage Current IIL µA

SCL – Logic High VIN = 0 V −2.5 −1.3 +1 SCL – Logic Low VIN = 5 V 0.01 ±1

Input Capacitance CIL 5 pF

POWER SUPPLIES

Power Supply Range V Positive Supply Current IDD 0.1 2 µA Logic Supply V Logic Supply Current I

+85°C < TA < +125°C 9 µA Programming Mode Current (EEPROM) I Power Dissipation P Power Supply Rejection Ratio PSRR VDD = +5 V ± 10%, code = 0x80 ±0.005 ±0.06 %/%

DYNAMIC CHARACTERISTICS

Bandwidth −3 dB BW Code = 0x80

RAB = 5 kΩ 2000 kHz RAB = 10 kΩ 800 kHz RAB = 50 kΩ 160 kHz RAB = 100 kΩ 80 kHz

Total Harmonic Distortion THDW RAB = 10 kΩ, VA = 1 V rms,

VW Settling Time tS RAB = 10 kΩ, VAB = 5 V,

Resistor Noise Voltage Density e

1

Typical values represent average readings at 25°C and VDD = 5 V.

2.7 5.5 V

VIH = 5 V or VIL = 0 V

VIH = 5 V or VIL = 0 V 35 mA

VIH = 5 V or VIL = 0 V, VDD = 5 V 15 40 µW

0.01 %

V

= 0, f = 1 kHz

500 ns

±1 LSB error band

RWB = 5 kΩ, f = 1 kHz 9 nV/√Hz

Rev. C | Page 4 of 24

Data Sheet AD5259

TIMING CHARACTERISTICS

VDD = V

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

I2C INTERFACE TIMING

CHARACTERISTICS SCL Clock Frequency f t

BUF

and Start t

HD;STA

t

LOW

t

HIGH

t

SU;STA

Start Condition t

HD;DAT

t

SU;DAT

tF Fall Time of Both SDA and

SCL Signals tR Rise Time of Both SDA and

SCL Signals t

SU;STO

EEPROM Data Storing Time t EEPROM Data Restoring Time at

Power On EEPROM Data Restoring Time upon

Restore Command EEPROM Data Rewritable Time3 t

FLASH/EE MEMORY RELIABILITY

Endurance4 100 700 kCycles Data Retention5 100 Years

1

Standard I2C mode operation guaranteed by design.

2

During power-up, the output is momentarily preset to midscale before restoring EEPROM content.

3

Delay time after power-on PRESET prior to writing new EEPROM data.

4

Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +125°C; typical endurance at +25°C is 700,000 cycles.

5

Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates

with junction temperature.

= 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C, unless otherwise noted.

LOGIC

1

Bus Free Time Between Stop

Hold Time (Repeated Start) t2

0 400 kHz

SCL

1.3 μs

t

1

After this period, the first clock pulse is

0.6 μs

generated.

Low Period of SCL Clock t3 1.3 μs

High Period of SCL Clock t4 0.6 μs

t

Setup Time for Repeated

0.6 μs

5

Data Hold Time t6 0 0.9 μs

Data Setup Time t7 100 ns

300 ns

t

8

300 ns

t

9

Setup Time for Stop Condition t10 0.6 μs

EEMEM_STORE

t

2

EEMEM_RESTORE1

t

EEMEM_RESTORE2 VDD

EEMEM_REWRITE

26 ms

rise time dependent. Measure without

V

DD

decoupling capacitors at V

DD

and GND.

300 μs

= 5 V. 300 μs

540 μs

t

2

t

5

10

05026-004

P

SCL

SDA

t

8

t

1

PS S

t

2

3

t

8

t

9

t

6

Figure 4. I

t

9

t

4

2

C Interface Timing Diagram

t

7

t

Rev. C | Page 5 of 24

AD5259 Data Sheet

MAX

JMAX

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Value

VDD, V VA, VB, VW to GND I

to GND

LOGIC

−0.3 V to +7 V GND − 0.3 V, VDD + 0.3 V

Pulsed1 ±20 mA Continuous ±5 mA

Digital Inputs and Output Voltage

0 V to 7 V

to GND

Operating Temperature Range Maximum Junction Temperature

(T

)

Storage Temperature Lead Temperature

−40°C to +125°C 150°C

−65°C to +150°C 300°C

(Soldering, 10 sec)

Thermal Resistance2

θ

: MSOP–10

JA

1

Maximum terminal current is bounded by the maximum current handling

of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance.

2

Package power dissipation = (T

– TA)/θJA.

JMAX

200°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. C | Page 6 of 24

Data Sheet AD5259

05026-002

AD5259

TOP VIEW

(Not to Scale)

W

1

AD0

2

AD1

3

SDA

4

SCL

5

A B V

DD

GND V

LOGIC

10

9 8 7 6

NOTES

1. THE EXPOSED PAD SHOULD BE CONNECTED T O GND OR LEFT FLOATING.

4

SDA

Serial Data Input/Output.

LOGIC

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin Mnemonic Description

1 W W Terminal, GND ≤ VW ≤ VDD. 2 ADO Programmable Pin 0 for Multiple Package Decoding. State is registered on power-up. 3 AD1 Programmable Pin 1 for Multiple Package Decoding. State is registered on power-up.

5 SCL Serial Clock Input. Positive edge triggered. 6 V 7 GND Digital Ground. 8 VDD Positive Power Supply. 9 B B Terminal, GND ≤ VB ≤ VDD. 10 A A Terminal, GND ≤ VA ≤ VDD. 11 EPAD Exposed Pad. The exposed pad should be connected to GND or left floating.

Logic Power Supply.

Rev. C | Page 7 of 24

AD5259 Data Sheet

1.5

1.3

1.1

0.9

0.7

0.5

0.3

0.1

–

0.1

–

0.3

–0.5

0 25622419216012896

6432

05026-015

CODE (Decimal)

RHEOSTAT MODE INL (LSB)

2.7V

5.5V

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

0 256224192160128966432

05026-017

CODE (Decimal)

RHEOSTAT MODE DNL (LSB)

2.7V

5.5V

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.25

0 256224

192160128966432

05026-010

CODE (Decimal)

POTENTIOMETER MODE INL (LSB)

TA = –40°C

TA = +25°C

TA = +85°C

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–

0.15

–

0.20

–0.25

0 256224192

160

12896

64

32

05026-012

CODE (Decimal)

POTENTIOMETER MODE DNL (LSB)

–40°C

+25°

C

+85°

C

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.25

0

256224192

160128966432

05026-011

CODE (Decimal)

POTENTIOMETER MODE INL (LSB)

5.5V

2.7V

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.25

0 256224192

160128966432

05026-013

CODE (Decimal)

POTENTIOMETER MODE DNL (LSB)

5.5V

2.7V

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = V

= 5.5 V, RAB = 10 kΩ, TA = +25°C; unless otherwise noted.

LOGIC

Figure 6. R-INL vs. Code vs. Supply Voltage

Figure 7. R-DNL vs. Code vs. Supply Voltage

Figure 9. DNL vs. Code vs. Temperature

Figure 10. INL vs. Supply Voltages

Figure 8. INL vs. Code vs. Temperature

Figure 11. DNL vs. Code vs. Supply Voltage

Rev. C | Page 8 of 24

Data Sheet AD5259

0.5

0.4

0.3

0.2

0.1

0

–0.1

–

0.2

–0.3

–0.4

–

0.5 0 256224

192

160128

96

6432

05026-014

CODE (Decimal)

RHEOSTAT MODE INL (LSB)

–

40

°C

+85

°C

+25

°

C

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

0 256224192160128966432

05026-016

CODE (Decimal)

RHEOSTAT MODE DNL (LSB)

T

A

= –40°C

TA = +85°C

TA = +25°C

0

–3.0

–2.5

–2.0

–

1.5

–1.0

–

0.5

–40 –

20 80604020

0

05026-024

TEMPERATURE (°C)

FSE (LSB)

FSE @ V

DD

= 2.7V

FSE @ V

DD

= 5.5V

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0 –40

–20

806040200

05026-023

TEMPERATURE (°C)

ZSE (LSB)

ZSE @ V

DD

= 2.7V

ZSE @ V

DD

= 5.5V

1

0.1

–40 –

20 80604020

0

05026-020

TEMPERATURE (°

C)

I

DD

, SUPPLY CURRENT (µA)

VDD = 5.5V

6

–1

0

1

2

3

4

5

–40 –20 806040200

05026-021

TEMPERATURE (°C)

I

LOGIC

, LOGIC SUPPLY CURRENT (

µA)

VDD = 2.7V

VDD = 5.5V

Figure 12. R-INL vs. Code vs. Temperature

Figure 13. R-DNL vs. Code vs. Temperature

Figure 15. Zero-Scale Error vs. Temperature

Figure 16. Supply Current vs. Temperature

Figure 14. Full -Scale Error vs. Temperature

Figure 17. Logic Supply Current vs. Temperature vs. V

DD

Rev. C | Page 9 of 24

AD5259 Data Sheet

400

–600

–500

–400

–

300

–

200

–100

0

100

200

300

0 256224

192

160

128

966432

05026-019

CODE (Decimal)

RHEOSTAT MODE TEMPCO (ppm/°C)

5kΩ

10k

Ω

50kΩ

100k

Ω

70

–40

–30

–20

–

10

0

10

20

30

40

50

60

0

256224192

1601289664

32

05026-018

CODE (Decimal)

POTENTIOMETER MODE TEMPCO (ppm/°C)

10kΩ

50kΩ

5kΩ

100kΩ

350

0

50

100

150

200

250

300

–40 –20 806040200

05026-022

TEMPERATURE (°C)

R

WB

@ 0x00

RWB @ VDD = 5.5V

R

WB

@ VDD = 2.7V

120

100

80

60

40

20

0 –40 –20 80

60

4020

0

05026-025

TEMPERATURE (°

C)

TOTAL RESISTANCE (kΩ)

100kΩ Rt @ V

DD

= 5.5V

50kΩ Rt @ VDD = 5.5V

10k

Ω Rt @ V

DD

= 5.5V

5k

Ω Rt @ VDD = 5.5V

05026-026

80

H

40

H

20

H

10

H

08

H

04

H

02

H

01

H

1k 10M

1M100k10k

–60

–54

–48

–42

–

36

–30

–24

–18

–12

–

6

0

FREQUENCY (Hz)

GAIN (dB)

1k 10M1M100k10k

05026-027

80

H

40

H

20

H

10

H

08

H

04

H

02

H

01

H

–60

–54

–48

–42

–36

–30

–24

–18

–12

–6

0

FREQUENCY (Hz)

GAIN (dB)

Figure 18. Rheostat Mode Tempco (ΔR

AB

Figure 19. Potentiometer Mode Tempco (ΔV

x 106)/(RAB x ΔT) vs. Code

x 106)/(VW x ΔT) vs. Code

W

Figure 21. Total Resistance vs. Temperature

Figure 22. Gain vs. Frequency vs. Code, R

= 5 kΩ

AB

Figure 20. R

WB

vs. Temperature

Rev. C | Page 10 of 24

Figure 23. Gain vs. Frequency vs. Code, R

= 10 kΩ

AB

Data Sheet AD5259

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 1M100k10k

80

H

40

H

20

H

10

H

08

H

04

H

02

H

01

H

FREQUENCY (Hz)

Figure 24. Gain vs. Frequency vs. Code, R

= 50 kΩ

AB

05026-028

10k

= V

LOGIC

VIH (V)

VDD = V

= 3V

1k

(A)

LOGIC

I

100

10

012345

V

DD

LOGIC

= 5V

Figure 27. Logic Supply Current vs. Input Voltage

05026-055

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 1M100k10k

80

H

40

H

20

H

10

H

08

H

04

H

02

H

01

H

FREQUENCY (Hz)

Figure 25. Gain vs. Frequency vs. Code, R

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 10M1M100k10k

100k 80kHz

FREQUENCY (Hz)

Figure 26. −3 dB Bandwidth @ Code = 0×80

50k 160kHz

10k 800kHz

= 100 kΩ

AB

5k 2MHz

05026-029

05026-050

80

CODE = MIDSCALE, VA = V

60

40

PSRR @ V

PSRR (dB)

20

0 100 1k 1M100k10k

PSRR @ V

= 3V DC  10% p-p AC

LOGIC

Figure 28. PSRR v s. Frequency

V

200mV/DIV

1

2

5V/DIV

W

SCL

Figure 29. Digital Feedthrough

, VB = 0V

LOGIC

= 5V DC  10% p-p AC

LOGIC

FREQUENCY (Hz)

400ns/DIV

05026-054

05026-051

Rev. C | Page 11 of 24

AD5259 Data Sheet

05026-052

1

V

W

1

µ

s/DIV

50mV/DIV

05026-053

1

2

V

W

SCL

2V/DIV

200ns/DIV

5V/DIV

Figure 30. Midscale Glitch, Code 0×7F to 0×80

Figure 31. Large Signal Settling Time

Rev. C | Page 12 of 24

Data Sheet AD5259

05026-030

V

MS

A

W

B

DUT

V+

V+ = V

DD

1LSB = V+/2

N

05026-031

NO CONNECT

I

W

V

MS

A

W

B

DUT

05026-032

V

MS2

V

MS1

V

W

A

W

B

DUT

I

W

= VDD/R

NOMINAL

R

W

= [V

MS1

– V

MS2

]/I

W

05026-033

∆VMS%

DUT

( )

A

W

B

V+

∆VDD%

∆V

MS

∆V

DD

∆V

DD

V

A

V

MS

V+ = V

DD

±

10% PSRR (dB) = 20 LOG PSS (%/%) =

05026-034

+5V

–5V

W

A

+2.5V

B

V

OUT

OFFSET

GND

DUT

AD8610

V

IN

05026-035

W

B

DUT

I

SW

I

SW

R

SW

GND TO V

DD

CODE = 0x00

=

0.1V

TEST CIRCUITS

Figure 32 through Figure 37 illustrate the test circuits that define the test conditions used in the product Specifications tables.

Figure 32. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)

Figure 33. Test Circuit for Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

Figure 34. Test Circuit for Wiper Resistance

Figure 35. Test Circuit for Power Supply Sensitivity (PSS, PSSR)

Figure 36. Test Circuit for Gain vs. Frequency

Figure 37. Test Circuit for Common-Mode Leakage Current

Rev. C | Page 13 of 24

AD5259 Data Sheet

A

W

B

A

W

B

A

W

B

05026-036

W

AB

WB

RR

D

DR ×+×= 2

256

)(

D5 D4 D3

D7 D6

D2 D1 D0

RDAC

LATCH

AND

DECODER

R

S

R

S

R

S

R

S

A

W

B

05026-037

W

ABWA

RR

D

DR ×+×

−

= 2

256

)(

A

V

I

W

B

V

O

05026-038

B

A

W

V

D

V

D

DV

256

)

(

−

+=

B

AB

WA

A

AB

WB

W

V

R

DR

V

R

DR

DV

)(

)

( +=

THEORY OF OPERATION

The AD5259 is a 256-position digitally-controlled variable resistor (VR) device. EEPROM is pre-loaded at midscale from the factory, and initial power-up is, accordingly, at midscale.

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance (RAB) of the RDAC between Terminal A and Terminal B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal resistance of the VR has 256 contact points accessed by the wiper terminal. The 8-bit data in the RDAC latch is decoded to select one of 256 possible settings.

Figure 38. Rheostat Mode Configuration

The general equation determining the digitally programmed output resistance between Wiper W and Terminal B is

(1)

Similar to the mechanical potentiometer, the resistance of the RDAC between Wiper W and Terminal A produces a digitally controlled complementary resistance, R setting for R

starts at a maximum value of resistance and

WA

. The resistance value

WA

decreases as the data loaded in the latch increases in value. The general equation for this operation is

(2)

Typical device-to-device matching is process lot dependent and may vary by up to ±30%. For this reason, resistance tolerance is stored in the EEPROM, enabling the user to know the actual R

within 0.1%.

AB

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at Wiper W to Terminal B and Wiper W to Terminal A proportional to the input voltage at Terminal A to Terminal B. Unlike the polarity of V across Terminal A to Terminal B, Wiper W to Terminal A, and Wiper W to Terminal B can be at either polarity.

to GND, which must be positive, voltage

DD

where: D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register.

R

is the end-to-end resistance.

AB

R

is the wiper resistance contributed by the ON resistance of

W

each internal switch.

In the zero-scale condition, there is a relatively low value finite wiper resistance. Care should be taken to limit the current flow between Wiper W and Terminal B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or destruction of the internal switch contact can occur.

Figure 40. Potentiometer Mode Configuration

If ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at Wiper W to Terminal B starting at 0 V up to 1 LSB less than 5 V. The general equation defining the output voltage at V

with respect to ground for any valid

W

input voltage applied to Terminal A and Terminal B is

(3)

A more accurate calculation, which includes the effect of wiper resistance, V

Figure 39. AD5259 Equivalent RDAC Circuit

Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the Internal Resistors R

Rev. C | Page 14 of 24

the absolute values.

, is

W

(4)

and RWB and not

WA

Data Sheet AD5259

I2C-COMPATIBLE INTERFACE

The master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 4). The next byte is the slave address byte, which consists of the slave address (first 7 bits) followed by an R/

is high, the master reads from the slave device. When the R/ bit is low, the master writes to the slave device.

The slave address of the part is determined by two configurable address pins, Pin AD0 and Pin AD1. The state of these two pins is registered upon power-up and decoded into a corresponding

2

I

C 7-bit address (see Table 5). The slave address corresponding to the transmitted address bits responds by pulling the SDA line low during the ninth clock pulse (this is termed the slave acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its serial register.

bit (see Tabl e 6). When the R/W bit

W

WRITING

In the write mode, the last bit (R/W) of the slave address byte is

logic low. The second byte is the instruction byte. The first three bits of the instruction byte are the command bits (see Table 6). The user must choose whether to write to the RDAC register, EEPROM register, or activate the software write protect (see Tabl e 7 to Ta ble 10). The final five bits are all zeros (see Tab le 13 to Tabl e 14). The slave again responds by pulling the SDA line low during the ninth clock pulse.

The final byte is the data byte MSB first. With the write protect mode, data is not stored; rather, a logic high in the LSB enables write protect. Likewise, a logic low disables write protect. The slave again responds by pulling the SDA line low during the ninth clock pulse.

STORING/RESTORING

In this mode, only the address and instruction bytes are necessary. The last bit (R/

low. The first three bits of the instruction byte are the command bits (see Tabl e 6). The two choices are transfer data from RDAC to EEPROM (store), or from EEPROM to RDAC (restore). The final five bits are all zeros (see Tabl e 13 to Table 14). In addition, users should issue an NOP command immediately after restoring the EEMEM setting to RDAC, thereby minimizing supply current dissipation.

) of the address byte is logic

W

READING

Assuming the register of interest was not just written to, it is necessary to write a dummy address and instruction byte. The instruction byte will vary depending on whether the data that is wanted is the RDAC register, EEPROM register, or tolerance register (see Table 11 and Tabl e 16).

After the dummy address and instruction bytes are sent, a repeat start is necessary. After the repeat start, another address byte is needed, except this time the R/

address byte is the readback byte containing the information requested in the instruction byte. Read bits appear on the negative edges of the clock.

The tolerance register can be read back individually (see Tabl e 15) or consecutively (see Tab le 16). Refer to the Read Modes section for detailed information on the interpretation of the tolerance bytes.

After all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-tohigh transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition (see Figure 46). In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the tenth clock pulse, and then raises SDA high to establish a stop condition (see Figure 47).

A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. For example, after the RDAC has acknowledged its slave address and instruction bytes in the write mode, the RDAC output is updated on each successive byte until a stop condition is received. If different instructions are needed, the write/read mode has to start again with a new slave address, instruction, and data byte. Similarly, a repeated read function of the RDAC is also allowed.

bit is logic high. Following this

W

Rev. C | Page 15 of 24

AD5259 Data Sheet

AD0 Address Pin

I

2

C Device Address

C2

C1

C0

Command Description

I2C-COMPATIBLE FORMAT

The following generic, write, read, and store/restore control registers for the AD5259 all refer to the device addresses listed in Table 5; the mode/condition reference key (S, P, SA, MA,

W

NA,

, R, and X) is listed below.

S = Start Condition

P = Stop Condition

SA = Slave Acknowledge

MA = Master Acknowledge

NA = No Acknowledge

W

= Writ e

R = Read

X = Don’t Care

GENERIC INTERFACE

Table 6. Generic Interface Format

7-Bit Device Address

S

(See Table 5)

Slave Address Byte Instruction Byte Data Byte

R/W

SA C2 C1 C0 A4 A3 A2 A1 A0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P

AD1 and AD0 are two-state address pins.

Table 5. Device Address Lookup

AD1 Address Pin

0 0 0011000 1 0 0011010 0 1 1001100 1 1 1001110

Table 7. RDAC-to-EEPROM Interface Command Descriptions

0 0 0 Operation Between Interface and RDAC. 0 0 1 Operation Between Interface and EEPROM. 0 1 0 Operation Between Interface and Write Protection Register. See Table 10. 1 0 0 NOP. 1 0 1 Restore EEPROM to RDAC.1 1 1 0 Store RDAC to EEPROM.

1

This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state.

WRITE MODES

Table 8. Writing to RDAC Register

7-Bit Device Address

S

(See Table 5) 0 SA 0 0 0 0 0 0 0 0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P

Slave Address Byte Instruction Byte Data Byte

Table 9. Writing to EEPROM Register

7-Bit Device Address

S

(See Table 5) 0 SA 0 0 1 0 0 0 0 0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P

Slave Address Byte Instruction Byte Data Byte

Table 10. Activating/Deactivating Software Write Protect

7-Bit Device Address

S

(See Table 5) 0 SA 0 1 0 0 0 0 0 0 SA 0 0 0 0 0 0 0 WP SA P

Slave Address Byte Instruction Byte Data Byte

In order to activate the write protection mode, the WP bit in Table 10 must be logic high. To deactivate the write protection, the command must be sent again, except with the WP in logic zero state. WP is reset to the deactivated mode if power is cycled off and on.

Rev. C | Page 16 of 24

Data Sheet AD5259

0

READ MODES

Read modes are referred to as traditional because the first two bytes for all three cases are dummy bytes, which function to place the pointer towards the correct register; this is the reason for the repeat start. Theoretically, this step can be avoided if the user reads a register previously written to. For example, if the EEPROM was just written to, the user can then skip the two dummy bytes and proceed directly to the slave address byte, followed by the EEPROM readback data.

Table 11. Traditional Readback of RDAC Register Value

7-Bit Device Address

S

(See Table 5)

Slave Address Byte Instruction Byte Slave Address Byte Read Back Data

↑

Repeat start

0 SA 0 0 0 0 0 0 0 0 SA S

Table 12. Traditional Readback of Stored EEPROM Value

7-Bit Device Address

S

(See Table 5) Slave Address Byte Instruction Byte Slave Address Byte Read Back Data ↑

Repeat start

0 SA 0 0 1 0 0 0 0 0 SA S

STORE/RESTORE MODES

Table 13. Storing RDAC Value to EEPROM

7-Bit Device Address

S

(See Table 5) 0 SA 1 1 0 0 0 0 0 0 SA P

Slave Address Byte Instruction Byte

7-Bit Device Address

(See Table 5)

7-Bit Device Address

(See Table 5)

1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P

Table 14. Restoring EEPROM to RDAC1

7-Bit Device Address

S

(See Table 5) 0 SA 1

Slave Address Byte Instruction Byte

1

User should issue an NOP command immediately after this command to conserve power.

1 0 0 0 0 0 SA P

Rev. C | Page 17 of 24

AD5259 Data Sheet

↑

Repeat start

S

(See Table 5)

0

SA 0 0 1 1 1 1 1 0

SA

S

(See Table 5)

1

SA

D7

D6

D5

D4

D3

D2

D1

D0

MA

D7

D6

D5

D4

D3

D2

D1

D0

NA

P

↑

05026-005

A A A

D7 D6 D5 D4 D3 D2 D1 D0

SIGN

7 BITS FOR INTEGER NUMBER

26252423222

120

D7 D6 D5

D4 D3 D2 D1 D0

8 BITS FOR DECIMAL NUMBER

2

–8

2–12–22–32–42–52–62

–7

TOLERANCE READBACK MODES

Table 15. Traditional Readback of Tolerance (Individually)

7-Bit Device Address

S

(See Table 5) 0 SA

0 0 1 1 1 1 1 0 SA S

Slave Address Byte Instruction Byte Slave Address Byte Sign + Integer Byte

Repeat start

7-Bit Device Address

S

(See Table 5) 0 SA 0 0 1 1 1 1 1 1 SA S

Slave Address Byte Instruction Byte Slave Address Byte Decimal Byte

Table 16.Traditional Readback of Tolerance (Consecutively)

7-Bit Device Address

(See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P

7-Bit Device Address

(See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P

Slave Address Byte

Instruction Byte

Slave Address Byte

Sign + Integer Byte Decimal Byte

Repeat start

Calculating RAB Tolerance Stored in Read-Only Memory

Figure 41. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions.

The AD5259 features a patented RAB tolerance storage in the nonvolatile memory. The tolerance is stored in the memory during factory production and can be read by users at any time. The knowledge of stored tolerance allows users to accurately calculate R

. This feature is valuable for precision, rheostat

AB

mode, and open-loop applications where knowledge of absolute resistance is critical.

(Unit is Percent. Only Data Bytes are Shown.)

In the first memory location, the MSB is designated for the sign (0 = + and 1= −) and the seven LSBs are designated for the integer portion of the tolerance. In the second memory location, all eight data bits are designated for the decimal portion of tolerance. Note the decimal portion has a limited accuracy of only 0.1%. For example, if the rated R and the data readback from Address 11110 shows 0001 1100,

= 10 kΩ

AB

and Address 11111 shows 0000 1111, then the tolerance can

The stored tolerance resides in the read-only memory and is

be calculated as expressed as a percentage. The tolerance is stored in two memory location bytes in sign magnitude binary form (see Figure 41).

MSB: 0 = +

Next 7 MSB: 001 1100 = 28 The two EEPROM address bytes are 11110 (sign + integer) and 11111 (decimal number). The two bytes can be individually accessed with two separate commands (see Table 15). Alternatively, readback of the first byte followed by the second

8 LSB: 0000 1111 = 15 × 2

Toleranc e = +28.06%

Rounded Tolerance = +28.1% and therefore,

R

AB_ACTUAL

= 12.810 kΩ

–8

= 0.06

byte can be done in one command (see Table 16). In the latter case, the memory pointer will automatically increment from the first to the second EEPROM location (increments from 11110 to 11111) if read consecutively.

Rev. C | Page 18 of 24

Data Sheet AD5259

GND

A

W

B

V

DD

05026-039

GND

SCL

SDA

V

LOGIC

05026-040

V

DD

GND

V

DD

C2

10µFC10.1µF

AD5259

+

05026-041

05026-042

ESD PROTECTION OF DIGITAL PINS AND RESISTOR TERMINALS

The AD5259 VDD, V boundary conditions for proper 3-terminal and digital input operation. Supply signals present on Terminal A, Terminal B, and Terminal W that exceed V internal forward biased ESD protection diodes (see Figure 42). Digital Input SCL and Digital Input SDA are clamped by ESD protection diodes with respect to V Figure 43.

Figure 42. Maximum Terminal Voltages Set by V

, and GND power supplies define the

LOG IC

or GND are clamped by the

DD

and GND as shown in

LOGIC

and GND

DD

LAYOUT AND POWER SUPPLY BYPASSING

It is good practice to use compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with minimum conductor length. Ground paths should have low resistance and low inductance.

Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with disc or chip ceramic capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 44). The digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce.

Figure 43. Maximum Terminal Voltages Set by V

and GND

LOGIC

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 42), it is important to power GND/V

DD/VLOG IC

voltage to Terminal A, Terminal B, and Terminal W; otherwise, the diode is forward biased, so the V unintentionally and may affect the user’s circuit. The ideal powerup sequence is in the following order: GND, V inputs, and then V V

, VB, VW, and the digital inputs is not important as long as

A

they are powered after GND/V

, VB, VW. The relative order of powering

A

DD/VLOG IC

before applying any

DD

and V

are powered

LOGIC

, V

DD

LOGIC

.

, digital

Figure 44. Power Supply Bypassing

MULTIPLE DEVICES ON ONE BUS

The AD5259 has two configurable address pins, Pin AD0 and Pin AD1. The state of these two pins is registered upon powerup and decoded into a corresponding I

2

C-compatible 7-bit address (see Table 5). This allows up to four devices on the bus to be written to or read from independently.

EVALUATION BOARD

An evaluation board, with all necessary software, is available to program the AD5259 from any PC running Windows® 98/ 2000/ XP. The graphical user interface, as shown in Figure 45, is straightforward and easy to use. More detailed information is available in the board’s user manual.

Figure 45. AD5259 Evaluation Board Software

Rev. C | Page 19 of 24

AD5259 Data Sheet

05026-006

A

B

W

R2 10k

Ω

R1 70kΩ

R3 25kΩ

V

DD

V

LOGIC

SCL SDA GND

–

+

U1

AD8565

3.5V < V

COM

< 4.5V

14.4VVCC (~3.3V) 5V

AD5259

MCU

C1

1µF

R5

10kΩ

R6

10kΩ

05026-007

A

B

W

R2 10kΩ

R1 70kΩ

R3 25kΩ

V

DD

V

LOGIC

SCL SDA GND

–

+

U1

AD8565

3.5V < V

COM

< 4.5V

14.4VVCC (~3.3V)

AD5259

MCU

C1

1µF

R5

10kΩ

R6

10kΩ

SUPPLIES POWER TO BOTH THE MICRO AND THE LOGIC SUPPLY OF THE DIGITAL POT

DISPLAY APPLICATIONS

CIRCUITRY

A special feature of the AD5259 is its unique separation of the V

and VDD supply pins. The separation provides greater

LOG IC

flexibility in applications that do not always provide needed supply voltages.

In particular, LCD panels often require a V range of 3 V to 5 V. The circuit in Figure 46 is the rare exception in which a 5 V supply is available to power the digital potentiometer.

Figure 46. V

Adjustment Application

COM

voltage in the

COM

For this reason, V

and VDD are provided as two separate

LOGIC

supply pins that can either be tied together or treated independently; V and V

biasing up the A, B, and W terminals for added

DD

supplying the logic/EEPROM with power,

LOGIC

flexibility.

Figure 47. Circuitry When a Separate Supply is Not Available for V

DD

For a more detailed look at this application, refer to the article, “Simple VCOM Adjustment uses any Logic Supply Voltage” in the September 30, 2004 issue of EDN magazine.

In the more common case shown in Figure 47, only analog

14.4 V and digital logic 3.3 V supplies are available. By placing discrete resistors above and below the digital potentiometer, V

can now be tapped off the resistor string itself. Based on the

DD

chosen resistor values, the voltage at V

in this case equals 4.8

DD

V, allowing the wiper to be safely operated all the way up to 4.8 V. The current draw of V because it is only on the order of microamps. V the M C U’s 3.3 V digital supply because V

will not affect that node’s bias

DD

LOGIC

will draw the 35

LOG IC

is tied to

mA which is needed when writing to the EEPROM. It would be impractical to try and source 35 mA through the 70 kΩ resistor, therefore, V

is not connected to the same node as VDD.

LOG IC

Rev. C | Page 20 of 24

Data Sheet AD5259

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

6

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

1

0.50 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 48. 10-Lead Mini Small Outline Package [MSOP]

3.10

3.00 SQ

2.90

5.15

4.90

4.65

5

15° MAX

6° 0°

0.23

0.13

0.30

0.15

1.10 MAX

(RM-10)

Dimensions shown in millimeters

2.48

2.38

2.23

0.70

0.55

0.40

0.50 BSC

091709-A

PIN 1 INDEX

AREA

0.80

0.75

0.70

SEATING

PLANE

TOP VIEW

0.30

0.25

0.20

0.50

0.40

0.30

0.05 MAX

0.02 NOM COPLANARITY

0.20 REF

0.08

6

EXPOSED

PAD

5

BOTTOM VIEW

FOR PRO P ER CONNECTIO N OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTIO N DE S CRI P T I ONS SECTION OF THIS DATA SHEET.

10

1.74

1.64

1.49

1

N

1

I

P

R

C

I

A

O

T

N

I

D

)

5

1

.

R

0

(

2-27-2012-B

Figure 49. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

Rev. C | Page 21 of 24

AD5259 Data Sheet

Model1

Package Description

Package Option

AD5259BCPZ100-R7

100 k

–40°C to +125°C

10-Lead LFCSP_WD

CP-10-9

D4S

ORDERING GUIDE

RAB (Ω)

Temperature

AD5259BRMZ5 5 k –40°C to +125°C 10-Lead MSOP RM-10 D4P AD5259BRMZ5-R7 5 k –40°C to +125°C 10-Lead MSOP RM-10 D4P AD5259BCPZ5-R7 5 k –40°C to +125°C 10-Lead LFCSP_WD CP-10-9 D4P AD5259BRMZ10 10 k –40°C to +125°C 10-Lead MSOP RM-10 D4Q AD5259BRMZ10-R7 10 k –40°C to +125°C 10-Lead MSOP RM-10 D4Q AD5259BCPZ10-R7 10 k –40°C to +125°C 10-Lead LFCSP_WD CP-10-9 D4Q AD5259BRMZ50 50 k –40°C to +125°C 10-Lead MSOP RM-10 D4R AD5259BRMZ50-R7 50 k –40°C to +125°C 10-Lead MSOP RM-10 D4R AD5259BCPZ50-R7 50 k –40°C to +125°C 10-Lead LFCSP_WD CP-10-9 D4R AD5259BRMZ100 100 k –40°C to +125°C 10-Lead MSOP RM-10 D4S AD5259BRMZ100-R7 100 k –40°C to +125°C 10-Lead MSOP RM-10 D4S

EVAL-AD5259DBZ Evaluation Board2

1

Z = RoHS Compliant Part.

2

The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.

Branding

Rev. C | Page 22 of 24

Data Sheet AD5259

NOTES

Rev. C | Page 23 of 24

AD5259 Data Sheet

NOTES

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

D05026-0-10/12(C)

Rev. C | Page 24 of 24

ANALOG DEVICES AD 5259 BRMZ Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

THEORY OF OPERATION

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

I2C-COMPATIBLE INTERFACE

WRITING

STORING/RESTORING

READING

I2C-COMPATIBLE FORMAT

GENERIC INTERFACE

WRITE MODES

READ MODES

STORE/RESTORE MODES

TOLERANCE READBACK MODES

Calculating RAB Tolerance Stored in Read-Only Memory

ESD PROTECTION OF DIGITAL PINS AND RESISTOR TERMINALS

LAYOUT AND POWER SUPPLY BYPASSING

POWER-UP SEQUENCE

MULTIPLE DEVICES ON ONE BUS

EVALUATION BOARD

DISPLAY APPLICATIONS

CIRCUITRY

OUTLINE DIMENSIONS

ORDERING GUIDE