ANALOG DEVICES AD 5259 BRMZ Datasheet

AD5259

Rev. C Document Feedback

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05026-001

RDAC

REGISTER

RDAC

DATA

CONTROL

COMMAND

DECODE LOGIC

ADDRESS

DECODE LOGIC

CONTROL LOGIC

AD5259

I2C

SERIAL

INTERFACE

POWER-

ON RESET

A
W
B

SCL
SDA

AD0
AD1

V

DD

V

LOGIC

GND

RDAC

EEPROM

8

8

05026-003

COMMAND

DECODE LOGIC

ADDRESS

DECODE LOGIC

CONTROL

LOGIC

SCL

SDA

AD0
AD1

GND

EEPROM

I2C

SERIAL

INTERFACE

RDAC

REGISTER

AND

LEVEL

SHIFTER

A

W

B

V

LOGIC

V

DD

05026-002

AD5259

TOP VIEW

(Not to Scale)

W

1

AD0

2

AD1

3

SDA

4

SCL

5

A
B
V

DD

GND
V

LOGIC

10

9
8
7
6

Nonvolatile, I2C-Compatible

Data Sheet

FEATURES

Nonvolatile memory maintains wiper settings
256-position
Thin LFCSP-10 (3 mm x 3 mm x 0.8 mm) package
Compact MSOP-10 (3 mm × 4.9 mm × 1.1mm) package

2

I

C®-compatible interface

V

pin provides increased interface flexibility

LOGIC

End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Resistance tolerance stored in EEPROM (0.1% accuracy)
Power-on EEPROM refresh time < 1ms
Software write protect command
Address Decode Pin AD0 and Pin AD1 allow

4 packages per bus
100-year typical data retention at 55°C
Wide operating temperature −40°C

3 V to 5 V single supply

APPLICATIONS

LCD panel V
LCD panel brightness and contrast control
Mechanical potentiometer replacement in new designs
Programmable power supplies
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
Fiber to the home systems
Electronics level settings

adjustment

COM

GENERAL DESCRIPTION

to +125°C

256-Position, Digital Potentiometer

FUNCTIONAL BLOCK DIAGRAMS

Figure 1. Block Diagram

Figure 2. Block Diagram Showing Level Shifters

CONNECTION DIAGRAM

The AD5259 provides a compact, nonvolatile LFCSP-10
(3 mm × 3 mm) or MSOP-10 (3 mm × 4.9 mm) packaged
solution for 256-position adjustment applications. These
devices perform the same electronic adjustment function
as mechanical potentiometers

1

or variable resistors, but

with enhanced resolution and solid-state reliability.

The wiper settings are controllable through an I
digital interface that is also used to read back the wiper register
and EEPROM content. Resistor tolerance is also stored within
EEPROM, providing an end-to-end tolerance accuracy of 0.1%.

A separate V
users who need multiple parts on one bus, Address Bit AD0 and
Address Bit AD1 allow up to four devices on the same bus.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change with out notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

pin delivers increased interface flexibilit y. For

LOG IC

2

C-compatible

Figure 3. Pinout

1

The terms digital potentiometer, VR (variable resistor), and RDAC are used

interchangeably.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] ©2005–2012 Analog Devices, Inc. All rights reserved.

AD5259 Data Sheet

TABLE OF CONTENTS

Specifications ..................................................................................... 3

I2C-Compatible Format ................................................................. 16

Electrical Characteristics ............................................................. 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Test Circuits ..................................................................................... 13

Theory of Operation ...................................................................... 14

Programming the Variable Resistor ......................................... 14

Programming the Potentiometer Divider ............................... 14

I2C-Compatible Interface............................................................... 15

Writi ng ......................................................................................... 15

Storing/Restoring ....................................................................... 15

Reading ........................................................................................ 15

Generic Interface ........................................................................ 16

Write Modes ................................................................................ 16

Read Modes ................................................................................. 17

Store/Restore Modes .................................................................. 17

Tolerance Readback Modes ...................................................... 18

ESD Protection of Digital Pins and Resistor Terminals ........ 19

Power-Up Sequence ................................................................... 19

Layout and Power Supply Bypassing ....................................... 19

Multiple Devices on One Bus ................................................... 19

Evaluation Board ........................................................................ 19

Display Applications ...................................................................... 20

Circuitry ...................................................................................... 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 22

REVISION HISTORY

10/12—Rev. B to Rev. C

Changed Maximum Temperature Value from 85°C to 125°C

(Throughout) .................................................................................... 1

Changes to Table 1 ............................................................................ 3

Updated Outline Dimensions ....................................................... 21

Changes to Ordering Guide .......................................................... 22

5/10—Rev. A to Rev. B

Changes to Figure 5 .......................................................................... 7

Changes to Storing/Restoring Section ......................................... 15

Changes to Table 7 .......................................................................... 16

Changes to Table 14 ........................................................................ 17

Updated Outline Dimensions ....................................................... 21

7/05—Rev. 0 to Rev. A

Added 10-Lead LFCSP ...................................................... Universal

Changes to Features Section and

General Description Section ............................................................ 1

Changes to Table 1 ............................................................................. 3

Changes to Table 2 and Added Figure 4 ......................................... 5

Changes to Table 4 ............................................................................. 7

Changes to Figure 27 Caption ...................................................... 11

Changes to Theory of Operation Section.................................... 14

Changes to I

Changes to Table 5 .......................................................................... 16

Changes to Multiple Devices on One Bus Section ..................... 19

Updated Figure 49 Caption ........................................................... 21

Changes to Ordering Guide .......................................................... 21

2/05—Revision 0: Initial Version

2

C-Compatible Interface Section ............................ 15

Rev. C | Page 2 of 24

Data Sheet AD5259

10 kΩ

−2

±0.2

+2

AB

WFSE

Zero-Scale Error

V

WZSE

Code = 0x00

50 kΩ/100 kΩ

0

0.2

0.5

LSB

W

RESISTOR TERMINALS

A, B, W

Common-Mode Leakage

ICM

VA = VB = VDD/2

10 nA

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD = V

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS:

RHEOSTAT MODE

Resistor Differential Nonlinearity R-DNL RWB, VA = no connect LSB

5 kΩ –1 ±0.2 +1
10 kΩ −1 ±0.1 +1
50 kΩ/100 kΩ −0.5 ±0.1 +0.5

Resistor Integral Nonlinearity R-INL RWB, VA = no connect LSB

5 kΩ –4 ±0.3 +4

50 kΩ/100 kΩ −1 ±0.4 +1
Nominal Resistor Tolerance ΔRAB TA = 25°C, VDD = 5.5 V –30 +30 %
Resistance Temperature Coefficient (ΔRAB x 106)/

Total Wiper Resistance RWB Code = 0x00 75 350 Ω

DC CHARACTERISTICS:

POTENTIOMETER DIVIDER MODE
Differential Nonlinearity DNL LSB

5 kΩ –1 ±0.2 +1

10 kΩ −0.5 ±0.1 +0.5

50 kΩ/100 kΩ −0.5 ±0.2 +0.5
Integral Nonlinearity INL LSB

5 kΩ –1 ±0.2 +1

10 kΩ −0.5 ±0.1 +0.5

50 kΩ/100 kΩ −0.5 ±0.1 +0.5
Full-Scale Error V

5 kΩ −7 −3 0

10 kΩ −4 −1.5 0

50 kΩ/100 kΩ −1 −0.4 0

= 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C, unless otherwise noted.

LOGIC

Code = 0x00/0x80 500/15 ppm/°C

(R

x ΔT)

Code = 0xFF LSB

5 kΩ −40°C < TA < +85°C 0 2.5 4 LSB

+85°C < TA < +125°C 6 LSB

10 kΩ −40°C < TA < +85°C 0 1 3 LSB

+85°C < TA < +125°C 4 LSB

Voltage Divider Temperature

Coefficient

Voltage Range V
Capacitance A, B C

Capacitance W CW f = 1 MHz, measured to GND,

(∆VW x 106)/
(V

x ∆T)

Code = 0x00/0x80 60/5 ppm/°C

GND VDD V

f = 1 MHz, measured to GND,

A, B

45 pF

code = 0x80

60 pF

code = 0x80

Rev. C | Page 3 of 24

AD5259 Data Sheet

SDA, AD0, AD1

VIN = 0 V or 5 V

0.01

±1

DD

LOGIC

LOGIC

−40°C < TA < +85°C

3 6

µA

LOGIC(PROG)

DISS

B

N_WB

Parameter Symbol Conditions Min Typ1 Max Unit

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH 0.7 × VL VL + 0.5 V
Input Logic Low VIL −0.5 0.3 × VL V
Leakage Current IIL µA

SCL – Logic High VIN = 0 V −2.5 −1.3 +1
SCL – Logic Low VIN = 5 V 0.01 ±1

Input Capacitance CIL 5 pF

POWER SUPPLIES

Power Supply Range V
Positive Supply Current IDD 0.1 2 µA
Logic Supply V
Logic Supply Current I

+85°C < TA < +125°C 9 µA
Programming Mode Current (EEPROM) I
Power Dissipation P
Power Supply Rejection Ratio PSRR VDD = +5 V ± 10%, code = 0x80 ±0.005 ±0.06 %/%

DYNAMIC CHARACTERISTICS

Bandwidth −3 dB BW Code = 0x80

RAB = 5 kΩ 2000 kHz
RAB = 10 kΩ 800 kHz
RAB = 50 kΩ 160 kHz
RAB = 100 kΩ 80 kHz

Total Harmonic Distortion THDW RAB = 10 kΩ, VA = 1 V rms,

VW Settling Time tS RAB = 10 kΩ, VAB = 5 V,

Resistor Noise Voltage Density e

1

Typical values represent average readings at 25°C and VDD = 5 V.

2.7 5.5 V

2.7 5.5 V

VIH = 5 V or VIL = 0 V

VIH = 5 V or VIL = 0 V 35 mA

VIH = 5 V or VIL = 0 V, VDD = 5 V 15 40 µW

0.01 %

V

= 0, f = 1 kHz

500 ns

±1 LSB error band

RWB = 5 kΩ, f = 1 kHz 9 nV/√Hz

Rev. C | Page 4 of 24

Data Sheet AD5259

TIMING CHARACTERISTICS

VDD = V

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

I2C INTERFACE TIMING

CHARACTERISTICS
SCL Clock Frequency f
t

BUF

and Start
t

HD;STA

t

LOW

t

HIGH

t

SU;STA

Start Condition
t

HD;DAT

t

SU;DAT

tF Fall Time of Both SDA and

SCL Signals
tR Rise Time of Both SDA and

SCL Signals
t

SU;STO

EEPROM Data Storing Time t
EEPROM Data Restoring Time at

Power On
EEPROM Data Restoring Time upon

Restore Command
EEPROM Data Rewritable Time3 t

FLASH/EE MEMORY RELIABILITY

Endurance4 100 700 kCycles
Data Retention5 100 Years

1

Standard I2C mode operation guaranteed by design.

2

During power-up, the output is momentarily preset to midscale before restoring EEPROM content.

3

Delay time after power-on PRESET prior to writing new EEPROM data.

4

Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +125°C; typical endurance at +25°C is 700,000 cycles.

5

Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates

with junction temperature.

= 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C, unless otherwise noted.

LOGIC

1

Bus Free Time Between Stop

Hold Time (Repeated Start) t2

0 400 kHz

SCL

1.3 μs

t

1

After this period, the first clock pulse is

0.6 μs

generated.

Low Period of SCL Clock t3 1.3 μs

High Period of SCL Clock t4 0.6 μs

t

Setup Time for Repeated

0.6 μs

5

Data Hold Time t6 0 0.9 μs

Data Setup Time t7 100 ns

300 ns

t

8

300 ns

t

9

Setup Time for Stop Condition t10 0.6 μs

EEMEM_STORE

t

2

2

EEMEM_RESTORE1

t

EEMEM_RESTORE2 VDD

EEMEM_REWRITE

26 ms

rise time dependent. Measure without

V

DD

decoupling capacitors at V

DD

and GND.

300 μs

= 5 V. 300 μs

540 μs

t

2

t

5

10

05026-004

P

SCL

SDA

t

8

t

t

1

PS S

t

2

3

t

8

t

9

t

6

Figure 4. I

t

9

t

4

2

C Interface Timing Diagram

t

7

t

Rev. C | Page 5 of 24

AD5259 Data Sheet

MAX

JMAX

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Value

VDD, V
VA, VB, VW to GND
I

to GND

LOGIC

−0.3 V to +7 V
GND − 0.3 V, VDD + 0.3 V

Pulsed1 ±20 mA
Continuous ±5 mA

Digital Inputs and Output Voltage

0 V to 7 V

to GND

Operating Temperature Range
Maximum Junction Temperature

(T

)

Storage Temperature
Lead Temperature

−40°C to +125°C
150°C

−65°C to +150°C
300°C

(Soldering, 10 sec)

Thermal Resistance2

θ

: MSOP–10

JA

1

Maximum terminal current is bounded by the maximum current handling

of the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Package power dissipation = (T

– TA)/θJA.

JMAX

200°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. C | Page 6 of 24

Data Sheet AD5259

05026-002

AD5259

TOP VIEW

(Not to Scale)

W

1

AD0

2

AD1

3

SDA

4

SCL

5

A
B
V

DD

GND
V

LOGIC

10

9
8
7
6

NOTES

1. THE EXPOSED PAD SHOULD
BE CONNECTED T O GND OR
LEFT FLOATING.

4

SDA

Serial Data Input/Output.

LOGIC

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin Mnemonic Description

1 W W Terminal, GND ≤ VW ≤ VDD.
2 ADO Programmable Pin 0 for Multiple Package Decoding. State is registered on power-up.
3 AD1 Programmable Pin 1 for Multiple Package Decoding. State is registered on power-up.

5 SCL Serial Clock Input. Positive edge triggered.
6 V
7 GND Digital Ground.
8 VDD Positive Power Supply.
9 B B Terminal, GND ≤ VB ≤ VDD.
10 A A Terminal, GND ≤ VA ≤ VDD.
11 EPAD Exposed Pad. The exposed pad should be connected to GND or left floating.

Logic Power Supply.

Rev. C | Page 7 of 24

AD5259 Data Sheet

1.5

1.3

1.1

0.9

0.7

0.5

0.3

0.1

–

0.1

–

0.3

–0.5

0 25622419216012896

6432

05026-015

CODE (Decimal)

RHEOSTAT MODE INL (LSB)

2.7V

5.5V

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

0 256224192160128966432

05026-017

CODE (Decimal)

RHEOSTAT MODE DNL (LSB)

2.7V

5.5V

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.25

0 256224

192160128966432

05026-010

CODE (Decimal)

POTENTIOMETER MODE INL (LSB)

TA = –40°C

TA = +25°C

TA = +85°C

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–

0.15

–

0.20

–0.25

0 256224192

160

12896

64

32

05026-012

CODE (Decimal)

POTENTIOMETER MODE DNL (LSB)

–40°C

+25°

C

+85°

C

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.25

0

256224192

160128966432

05026-011

CODE (Decimal)

POTENTIOMETER MODE INL (LSB)

5.5V

2.7V

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.25

0 256224192

160128966432

05026-013

CODE (Decimal)

POTENTIOMETER MODE DNL (LSB)

5.5V

2.7V

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = V

= 5.5 V, RAB = 10 kΩ, TA = +25°C; unless otherwise noted.

LOGIC

Figure 6. R-INL vs. Code vs. Supply Voltage

Figure 7. R-DNL vs. Code vs. Supply Voltage

Figure 9. DNL vs. Code vs. Temperature

Figure 10. INL vs. Supply Voltages

Figure 8. INL vs. Code vs. Temperature

Figure 11. DNL vs. Code vs. Supply Voltage

Rev. C | Page 8 of 24