ANALOG DEVICES AD5251, AD5252 Service Manual

Dual 64-/256-Position I2C® Nonvolatile

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FEATURES

AD5251: Dual 64-position resolution
AD5252: Dual 256-position resolution
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Nonvolatile memory
Power-on refreshed with EEMEM settings in 300 μs typ
EEMEM rewrite time = 540 μs typ
Resistance tolerance stored in nonvolatile memory
12 extra bytes in EEMEM for user-defined information

2

C-compatible serial interface

I
Direct read/write access of RDAC
Predefined linear increment/decrement commands
Predefined ±6 dB step change commands
Synchronous or asynchronous dual-channel update
Wiper setting readback
4 MHz bandwidth—1 kΩ version
Single supply 2.7 V to 5.5 V
Dual supply ±2.25 V to ±2.75 V
2 slave address decoding bits allow operation of 4 devices
100-year typical data retention, T
Operating temperature: –40°C to +85°C

APPLICATIONS

Mechanical potentiometer replacement
General-purpose DAC replacement
LCD panel V

COM

White LED brightness adjustment
RF base station power amp bias control
Programmable gain and offset control
Programmable voltage-to-current conversion
Programmable power supply
Sensor calibrations

GENERAL DESCRIPTION

The AD5251/AD5252 are dual-channel, I2C, nonvolatile mem­ory, digitally controlled potentiometers with 64/256 positions,
respectively. These devices perform the same electronic adjust­ment functions as mechanical potentiometers, trimmers, and
variable resistors. The parts’ versatile programmability allows
multiple modes of operation, including read/write access in the
RDAC and EEMEM registers, increment/decrement of resistance,
resistance changes in ±6 dB scales, wiper setting readback, and
extra EEMEM for storing user-defined information, such as
memory data for other components, look-up table, or system
identification information.

1

stores wiper setting w/write protection

2

and EEMEM registers

= 55°C

A

adjustment

Memory Digital Potentiometers

AD5251/AD5252

FUNCTIONAL BLOCK DIAGRAM

V

DD

V

SS

DGND

WP

SCL
SDA

AD0
AD1

I2C

SERIAL

INTERFACE

POWER-

ON RESET

The AD5251/AD5252 allow the host I
any of the 64-/256-step wiper settings in the RDAC registers
and store them in the EEMEM. Once the settings are stored,
they are restored automatically to the RDAC registers at system
power-on; the settings can also be restored dynamically.

The AD5251/AD5252 provide addi
decrement, +6 dB step change, and –6 dB step change in
synchronous or asynchronous channel update mode. The
increment and decrement functions allow stepwise linear
adjustments, with a ± 6 dB step change equivalent to doubling
or halving the RDAC wiper setting. These functions are useful
for steep-slope, nonlinear adjustments, such as white LED
brightness and audio volume control.

The AD5251/AD5252 have a patented resistance-tolerance
s

toring function that allows the user to access the EEMEM and
obtain the absolute end-to-end resistance values of the RDACs
for precision applications.

The AD5251/AD5252 are available in TSSOP-14 packages in
1 kΩ, 10 kΩ, 50
guaranteed to operate over the –40°C to +85°C extended
industrial temperature range.

1

The terms nonvolatile memory and EEMEM are used interchangeably.

2

The terms digital potentiometer and RDAC are used interchangeably.

RDAC EEMEM

EEMEM

POWER-ON

REFRESH

DATA

CONTROL

RAB
TOL

COMMAND

DECODE LOGIC

ADDRESS

DECODE LOGIC

CONTROL LOGIC

Figure 1.

RDAC1
REGIS-

TER

RDAC3
REGIS-

TER

AD5251/

AD5252

2

C controllers to write

tional increment,

kΩ, and 100 kΩ options. All parts are

RDAC1

RDAC3

A1
W1
B1

A3
W3
B3

03823-0-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD5251/AD5252

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TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Electrical Characteristics ................................................................. 3

1 kΩ Version.................................................................................. 3

10 kΩ, 50 kΩ, 100 kΩ Versions .................................................. 5

Interface Timing Characteristics................................................ 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 10

2

I

C Interface..................................................................................... 14

2

I

C Interface General Description............................................ 14

2

I

C Interface Detail Description............................................... 15

2

I

C-Compatible 2-Wire Serial Bus ........................................... 20

Theory of Operation ...................................................................... 21

Linear Increment/Decrement Commands ............................. 21

±6 dB Adjustments (Doubling/Halving Wiper Setting) ....... 21

Digital Input/Output Configuration........................................ 22

Multiple Devices on One Bus................................................... 22

Terminal Voltage Operation Range......................................... 22

Power-Up and Power-Down Sequences.................................. 22

Layout and Power Supply Biasing............................................ 23

Digital Potentiometer Operation............................................. 23

Programmable Rheostat Operation......................................... 23

Programmable Potentiometer Operation ............................... 24

Applications..................................................................................... 25

LCD Panel V

Current-Sensing Amplifier ....................................................... 25

Adjustable High Power LED Driver ........................................ 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 27

Adjustment.................................................... 25

COM

REVISION HISTORY

9/05—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Change to Figure 6 ......................................................................... 10

Changes to Figure 28...................................................................... 15

Changes to Figure 29...................................................................... 17

Changes to RDAC/EEMEM Quick Commands Section .......... 18

Changes to EEMEM Write Protection Section........................... 18

Changes to Figure 37...................................................................... 22

Deleted Table 13 and Table 14 ......................................................23

Change to Figure 42 ....................................................................... 24

Change to Figure 46 ....................................................................... 25

Changes to Ordering Guide.......................................................... 27

6/04—Revision 0: Initial Version

Rev. A | Page 2 of 28

AD5251/AD5252

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ELECTRICAL CHARACTERISTICS

1 kΩ VERSION

VDD = 3 V ± 10% or 5 V ± 10%, VSS = 0 V or VDD/VSS = ±2.5 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ
DC CHARACTERISTICS—

RHEOSTAT MODE
Resolution N AD5251 6 Bits
AD5252 8 Bits
Resistor Differential Nonlinearity
R
R
R
Resistor Nonlinearity

2

R
R
R
Nominal Resistor Tolerance ΔRAB/RAB T

2

R-DNL RWB, RWA = NC, VDD = 5.5 V, AD5251 –0.5 ±0.2 +0.5 LSB

, RWA = NC, VDD = 5.5 V, AD5252 –1.00 ±0.25 +1.00 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5251 –0.75 ±0.30 +0.75 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5252 –1.5 ±0.3 +1.5 LSB

WB

R-INL RWB, RWA = NC, VDD = 5.5 V, AD5251 –0.5 ±0.2 +0.5 LSB

, RWA = NC, VDD = 5.5 V, AD5252 –2.0 ±0.5 +2.0 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5251 –1.0 +2.5 +4.0 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5252 –2 +9 +14 LSB

WB

= 25°C –30 +30 %

A

Resistance Temperature Coefficient (ΔRAB/RAB) × 106/ΔT 650 ppm/°C
Wiper Resistance RW I
I
Channel-Resistance Matching ΔR

DC CHARACTERISTICS—

/ΔR

AB1

0.15 %

AB3

= 1 V/R, VDD = 5 V 75 130 Ω

W

= 1 V/R, VDD = 3 V 200 300 Ω

W

POTENTIOMETER DIVIDER MODE
Differential Nonlinearity

3

DNL AD5251 –0.5 ±0.1 +0.5 LSB
AD5252 –1.00 ±0.25 +1.00 LSB
Integral Nonlinearity

3

INL AD5251 –0.5 ±0.2 +0.5 LSB
AD5252 –2.0 ±0.5 +2.0 LSB
Voltage Divider Tempco (ΔVW/VW) × 106/ΔT Code = half scale 25 ppm/°C
Full-Scale Error V

Code = full scale, VDD = 5.5 V, AD5251 –5 –3 0 LSB

WFSE

Code = full scale, VDD = 5.5 V, AD5252 –16 –11 0 LSB
Code = full scale, VDD = 2.7 V, AD5251 −6 –4 0 LSB
Code = full scale, VDD = 2.7 V, AD5252 –23 –16 0 LSB
Zero-Scale Error V

Code = zero scale, VDD = 5.5 V, AD5251 0 3 5 LSB

WZSE

Code = zero scale, VDD = 5.5 V, AD5252 0 11 16 LSB
Code = zero scale, VDD = 2.7 V, AD5251 0 4 6 LSB
Code = zero scale, VDD = 2.7 V, AD5252 0 15 20 LSB

RESISTOR TERMINALS

Voltage Range
Capacitance5 A, B CA, CB

Capacitance5 W CW

Common-Mode Leakage Current ICM V

4

VA, VB, VW V

f = 1 kHz, measured to GND,

ode = half scale

c
f = 1 kHz, measured to GND,

ode = half scale

c

= VB = VDD/2 0.01 1 μA

A

VDD V

SS

85 pF

95 pF

1

Max Unit

Rev. A | Page 3 of 28

AD5251/AD5252

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Parameter Symbol Conditions Min Typ

1

Max Unit

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V
V
Input Logic Low VIL V
Output Logic High (SDA) VOH R
Output Logic Low (SDA) VOL R

I

WP Leakage Current

WP

= 5 V, VSS = 0 V 2.4 V

DD

= 2.7 V/0 V or VDD/VSS = ± 2.5 V 2.1 V

DD/VSS

= 5 V, VSS = 0 V 0.8 V

DD

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9 V

PULL-UP

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 0.4 V

PULL-UP

WP

= VDD

5 μA
A0 Leakage Current IA0 A0 = GND 3 μA
Input Leakage Current

(Other than WP

Input Capacitance

and A0)

5

II V

CI 5 pF

= 0 V or VDD ±1 μA

IN

POWER SUPPLIES

Single-Supply Power Range VDD V

= 0 V 2.7 5.5 V

SS

Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD V
Negative Supply Current ISS

EEMEM Data Storing Mode Current I
EEMEM Data Restoring Mode

Power Dissipation

Current

6

7

V

DD_STORE

I

DD_RESTORE

P

V

V

DISS

= VDD or VIL = GND 5 15 μA

IH

= VDD or VIL = GND, VDD = 2.5 V,

V

IH

= –2.5 V

V

SS

= VDD or VIL = GND 35 mA

IH

= VDD or VIL = GND 2.5 mA

IH

= VDD = 5 V or VIL = GND 0.075 mW

IH

–5 –15 μA

Power Supply Sensitivity PSS ΔVDD = 5 V ± 10% −0.025 +0.010 +0.025 %/%
ΔVDD = 3 V ± 10% –0.04 +0.02 +0.04 %/%

DYNAMIC CHARACTERISTICS

5, 8

Bandwidth –3 dB BW RAB = 1 kΩ 4 MHz
Total Harmonic Distortion THD VA = 1 V rms, VB = 0 V, f = 1 kHz 0.05 %
VW Settling Time tS V
Resistor Noise Voltage e

N_WB

= VDD, VB = 0 V 0.2 μs

A

= 500 Ω, f = 1 kHz

R

WB

3

nV/√Hz

(thermal noise only)

Digital Crosstalk CT

= VDD, VB = 0 V, measure VW with

V

A

–80 dB

adjacent RDAC making full-scale
change

Analog Coupling CAT

1

Typical values represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the

relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at V

2.7 V, IW = VDD/R for both VDD = 3 V and VDD = 5 V.

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

4

Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

6

Command 0 NOP should be activated after Command 1 to minimize I

7

P

is calculated from IDD × VDD = 5 V.

DISS

8

All dynamic characteristics use VDD = 5 V.

Signal input at A1 and measure the
output a

current consumption.

DD_READ

t W3, f = 1 kHz

–72 dB

=

DD

Rev. A | Page 4 of 28

AD5251/AD5252

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10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = +3 V ± 10% or +5 V ± 10%, VSS = 0 V or VDD/VSS = ± 2.5 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +85°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ
DC CHARACTERISTICS—

RHEOSTAT MODE
Resolution N AD5251 6 Bits
AD5252 8 Bits
Resistor Differential

Nonlinearity

2

R
Resistor Nonlinearity

2

R
Nominal Resistor Tolerance ΔRAB/RAB T
Resistance Temperature

R-DNL RWB, RWA = NC, AD5251 −0.75 ±0.10 +0.75 LSB

, RWA = NC, AD5252 −1.00 ±0.25 +1.00 LSB

WB

R-INL RWB, RWA = NC, AD5251 −0.75 ±0.25 +0.75 LSB

, RWA = NC, AD5252 −2.5 ±1.0 +2.5 LSB

WB

= 25°C −20 +20 %

A

(ΔR

) × 106/ΔT 650 ppm/°C

AB/RAB

Coefficient
Wiper Resistance RW I
I
Channel-Resistance Matching ΔR

AB1

/ΔR

R

AB2

R

DC CHARACTERISTICS—

= 1 V/R, VDD = 5 V 75 130 Ω

W

= 1 V/R, VDD = 3 V 200 300 Ω

W

= 10 kΩ, 50 kΩ 0.15 %

AB

= 100 kΩ 0.05 %

AB

POTENTIOMETER DIVIDER MODE
Differential Nonlinearity

3

DNL AD5251 −0.5 ±0.1 +0.5 LSB
AD5252 −1.0 ±0.3 +1.0 LSB
Integral Nonlinearity

3

INL AD5251 −0.50 ±0.15 +0.50 LSB
AD5252 −1.5 ±0.5 +1.5 LSB
Voltage Divider

(ΔV

) × 106/ΔT Code = half scale 15 ppm/°C

W/VW

Temperature Coefficient

Full-Scale Error V

Code = full scale, AD5251 −1.0 −0.3 0 LSB

WFSE

Code = full scale, AD5252 −3 −1 0 LSB
Zero-Scale Error V

Code = zero scale, AD5251 0 0.3 1.0 LSB

WZSE

Code = zero scale, AD5252 0 1.2 3.0 LSB

RESISTOR TERMINALS

Voltage Range
Capacitance5 A, B CA, CB

Capacitance5 W CW

Common-Mode Leakage Current ICM V

4

VA, VB, VW V

f = 1 kHz, measured to GND,

ode = half scale

c
f = 1 kHz, measured to GND,

ode = half scale

c

= VB = VDD/2 0.01 1.00 μA

A

VDD V

SS

85 pF

95 pF

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V
V
Input Logic Low VIL V
V
Output Logic High (SDA) VOH R
Output Logic Low (SDA) VOL R

I

WP Leakage Current

WP

= 5 V, VSS = 0 V 2.4 V

DD

= +2.7 V/0 V or VDD/VSS = ±2.5 V 2.1 V

DD/VSS

= 5 V, VSS = 0 V 0.8 V

DD

= +2.7 V/0 V or VDD/VSS = ±2.5 V 0.6 V

DD/VSS

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9 V

PULL-UP

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 0.4 V

PULL-UP

WP

= VDD

5 μA
A0 Leakage Current IA0 A0 = GND 3 μA
Input Leakage Current

(Other than WP

and A0)

V

I

I

= 0 V or VDD ±1 μA

IN

Input Capacitance5 CI 5 pF

1

Max Unit

Rev. A | Page 5 of 28

AD5251/AD5252

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Parameter Symbol Conditions Min Typ

1

Max Unit

POWER SUPPLIES

Single-Supply Power Range VDD V

= 0 V 2.7 5.5 V

SS

Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD V
Negative Supply Current ISS

I

EEMEM Data Storing Mode

V

DD_STORE

= VDD or VIL = GND 5 15 μA

IH

= VDD or VIL = GND, VDD = 2.5 V,

V

IH

= −2.5 V

V

SS

= VDD or VIL = GND, TA = 0°C to 85°C 35 mA

IH

−5 −15 μA

Current

EEMEM Data Restoring Mode

Current

6

Power Dissipation7 P

I

DD_RESTORE

V

V

DISS

= VDD or VIL = GND, TA = 0°C to 85°C 2.5 mA

IH

= VDD = 5 V or VIL = GND 0.075 mW

IH

Power Supply Sensitivity PSS ΔVDD = 5 V ± 10% −0.005 +0.002 +0.005 %/%
ΔVDD = 3 V ± 10% −0.010 +0.002 +0.010 %/%

DYNAMIC CHARACTERISTICS

5, 8

–3 dB Bandwidth BW RAB = 10 kΩ/50 kΩ/100 kΩ 400/80/40 kHz
Total Harmonic Distortion THDW V
VW Settling Time tS

Resistor Noise Voltage e

N_WB

= 1 V rms, VB = 0 V, f = 1 kHz 0.05 %

A

= VDD, VB = 0 V,

V

A

= 10 kΩ/50 kΩ/100 kΩ

R

AB

= 10 kΩ/50 kΩ/100 kΩ,

R

AB

1.5/7/14 μs

9/20/29

nV/√Hz
code = midscale, f = 1 kHz
(thermal noise only)

Digital Crosstalk CT

= VDD, VB = 0 V, measure VW with

V

A

−80 dB
adjacent RDAC making full-scale
change

Analog Coupling CAT

1

Typical values represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the

relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at VDD = 2.7 V,
IW = VDD/R for both VDD = 3 V and VDD = 5 V.

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

4

Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

6

Command 0 NOP should be activated after Command 1 to minimize I

7

P

is calculated from IDD × VDD = 5 V.

DISS

8

All dynamic characteristics use VDD = 5 V.

Signal input at A1 and measure
output a

DD_READ

t W3, f = 1 kHz

current consumption.

−72 dB

Rev. A | Page 6 of 28

AD5251/AD5252

www.BDTIC.com/ADI

INTERFACE TIMING CHARACTERISTICS

All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching
characteristics are measured using both V

Table 3. Interface Timing and EEMEM Reliability Characteristics (All Parts)

Parameter Symbol Conditions Min Typ Max Unit

INTERFACE TIMING

SCL Clock Frequency f
t

Bus-Free Time Between Stop and Start t1 1.3 μs

BUF

t

Hold Time (Repeated Start) t2

HD;STA

t

Low Period of SCL Clock t3 1.3

LOW

t

High Period of SCL Clock t4 0.6

HIGH

t

Set-up Time for Start Condition t5 0.6

SU;STA

t

Data Hold Time t6 0 0.9 μs

HD;DAT

t

Data Set-up Time t7 100

SU;DAT

tF Fall Time of Both SDA and SCL Signals t8
tR Rise Time of Both SDA and SCL Signals t9
t

Set-up Time for Stop Condition t10 0.6 μs

SU;STO

EEMEM Data Storing Time t
EEMEM Data Restoring Time at Power-On

EEMEM Data Restoring Time upon Restore

Command or Reset Operation

2

EEMEM Data Rewritable Time (Delay Time

After Power-On or Reset Before EEMEM
Can Be Written)

FLASH/EE MEMORY RELIABILITY

Endurance
Data Retention

1

Guaranteed by design; not subject to production test. See Figure 23 for location of measured values.

2

During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM data restoring time, whereas RDAC3 has the longest.

3

Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.

4

Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates

with junction temperature in Flash/EE memory.

3

4

= 3 V and 5 V.

DD

SCL

2

EEMEM_STORE

t

EEMEM_RESTORE1

t

EEMEM_RESTORE2

t

EEMEM_REWRITE

100 k cycles
100 Years

1

400 kHz

After this period, the first clock pulse is

ated.

gener

0.6

300 ns
300 ns

μs

μs
μs
μs

ns

26 ms

rise time dependent. Measure

V

DD

without decoupling capacitors at V
and V

.

SS

300 μs

DD

VDD = 5 V. 300 μs

540 μs

Rev. A | Page 7 of 28

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V, +7 V
VSS to GND +0.3 V, −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS, VDD
Maximum Current

IWB, IWA Pulsed ±20 mA
IWB Continuous (RWB ≤ 1 kΩ, A Open)
IWA Continuous (RWA ≤ 1 kΩ, B Open)1 ±5 mA
IAB Continuous

(R

= 1 kΩ/10 kΩ/50 kΩ/100 kΩ)1

AB

Digital Inputs and Output Voltage to GND 0 V, 7 V
Operating Temperature Range −40°C to +85°C
Maximum Junction Temperature (T
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
TSSOP-14 Thermal Resistance2 θJA 136°C/W

1

Maximum terminal current is bound by the maximum applied voltage across

any two of the A, B, and W terminals at a given resistance, the maximum
current handling of the switches, and the maximum power dissipation of the
package. VDD = 5 V.

2

Package power dissipation = (T

− TA)/θJA.

JMAX

1

±5 mA

±5 mA/±500 μA/
±100 μA/±50 μA

) 150°C

JMAX

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 8 of 28

AD5251/AD5252

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V
AD0

WP
W1

B1
A1

SDA

DD

1

2

AD5251/

3

AD5252

4

TOP VIEW

(Not to Scale)

5

6

7

14

W3

13

B3

12

A3

11

AD1

10

DGND

9

SCL

8

V

SS

03823-0-002

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 VDD

Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply, where

VDD – VSS ≤ 5.5 V. VDD must be able to source 35 mA for 26 ms when storing data to EEMEM.
2 AD0 I2C Device Address 0. AD0 and AD1 allow four AD5251/AD5252 devices to be addressed.
3

WP
4 W1 Wiper Terminal of RDAC1. VSS ≤ VW1 ≤ VDD.
5 B1 B Terminal of RDAC1. VSS ≤ VB1 ≤ VDD.
6 A1 A Terminal of RDAC1. VSS ≤ VA1 ≤ VDD.
7 SDA

Write Protect, Active Low. VWP ≤ VDD + 0.3 V.

1

1

1

Serial Data Input/Output Pin. Shifts in one bit a

t a time upon positive clock edges. MSB loaded first.

Open-drain MOSFET requires pull-up resistor.

8 VSS

Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where V
V

9 SCL

Serial Input Register Clock Pin. Shifts in one bit at a time upon positiv

is used in dual supply, VSS must be able to sink 35 mA for 26 ms when storing data to EEMEM.

SS

e clock edges. V

– VSS ≤ +5.5 V. If

DD

SCL

Pull-up resistor is recommended for SCL to ensure minimum power.
10 DGND Digital Ground. Connect to system analog ground at a single point.
11 AD1 I2C Device Address 1. AD0 and AD1 allow four AD5251/AD5252 devices to be addressed.
12 A3 A Terminal of RDAC3. VSS ≤ VA3 ≤ VDD.
13 B3 B Terminal of RDAC3. VSS ≤ VB3 ≤ VDD.
14 W3 Wiper Terminal of RDAC3. VSS ≤ VW3 ≤ VDD.

1

For quad-channel device software compatibility, the dual potentiometers in the parts are designated as RDAC1 and RDAC3.

1

1

1

≤ (VDD + 0.3 V).

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