Datasheet AD5251 Datasheet (Analog Devices)

Dual 64-and 256-Position I2C Nonvolatile

FEATURES

AD5251: Dual 64-position resolution AD5252: Dual 256-position resolution 1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Nonvolatile memory Power-on refreshed with EEMEM settings in 300 µs typ EEMEM rewrite time = 540 µs typ

Resistance tolerance stored in nonvolatile memory 12 extra bytes in EEMEM for user-defined information

C compatible serial interface

I Direct read/write access of RDAC Predefined linear increment/decrement commands Predefined ±6 dB step change commands Synchronous or aysynchronous dual channel update Wiper setting read back 4 MHz bandwidth—1 kΩ version Single supply 2.7 V to 5.5 V Dual supply ±2.25 V to ±2.75 V 2 slave address decoding bits allow operation of 4 devices 100-year typical data retention T Operating temperature –40°C to +85°C

APPLICATIONS

Mechanical potentiometer replacement General purpose DAC replacement LCD panel V

COM

GENERAL DESCRIPTION

The AD5251/AD5252 are dual-channel, I2C, nonvolatile memory, digitally controlled potentiometers with 64/256 positions, respectively. These devices perform the same electronic adjustment functions as mechanical potentiometers, trimmers, and variable resistors. The parts’ versatile programmability allows multiple modes of operation, including read/write access in the RDAC and EEMEM registers, increment/decrement of resistance, resistance changes in ±6 dB scales, wiper setting readback, and extra EEMEM for storing user-defined information such as memory data for other components, look-up table, or system identification information.

The AD5251/AD5252 allow the host I any of the 64- or 256-step wiper settings in the RDAC registers and store them in the EEMEM. Once the settings are stored,

stores wiper setting w/write protection

and EEMEM registers

= 55°C

adjustment

C controllers to write

Memory Digital Potentiometers

AD5251/AD5252

White LED brightness adjustment RF base station power amp bias control Programmable gain and offset control Programmable voltage-to-current conversion Programmable power supply Sensor calibrations

FUNDAMENTAL BLOCK DIAGRAM

DGND

SCL SDA

AD0 AD1

I2C

SERIAL

INTERFACE

POWER-

ON RESET

The terms nonvolatile memory and EEMEM are used interchangeably.

The terms digital potentiometer and RDAC are used interchangeably.

they are restored automatically to the RDAC registers at system power-on; the settings can also be restored dynamically.

The AD5251/AD5252 provide additional increment, decrement, +6 dB step change, and –6 dB step change in synchronous or asynchronous channel update modes. The increment and decrement functions allow stepwise linear adjustments, while ±6 dB step changes are equivalent to doubling or halving the RDAC wiper setting. These functions are useful for steep-slope nonlinear adjustments such as white LED brightness and audio volume control. The parts have a patented resistance tolerance storing function which enable the user to access the EEMEM and obtain the absolute end-to-end resistance values of the RDACs for precision applications.

The AD5251/AD5252 are available in TSSOP-14 packages in 1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options and all parts can operate over the –40°C to +85°C extended industrial temperature range.

RDAC EEMEM

EEMEM

POWER-ON

REFRESH

DATA

CONTROL

RAB TOL

COMMAND

DECODE LOGIC

ADDRESS

DECODE LOGIC

CONTROL LOGIC

Figure 1.

RDAC1 REGIS-

TER

RDAC3 REGIS-

TER

RDAC1

RDAC3

AD5251/

AD5252

A1 W1 B1

A3 W3 B3

03823-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

AD5251/AD5252

TABLE OF CONTENTS

Electrical Characteristics ................................................................. 3

Interface Timing Characteristics................................................ 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Description .............................. 9

C Interface Timing Diagram.................................................... 9

C Interface General Description................................................ 10

C Interface Detail Description ................................................... 11

RDAC/EEMEM Write ............................................................... 11

C Compatible 2-Wire Serial Bus................................................ 15

Typical Performance Characteristics ........................................... 16

Operational Overview.................................................................... 20

Linear Increment and Decrement Commands ...................... 20

±6 dB Adjustments (Doubling/Halving WIPER Setting)..... 20

Digital Input/Output Configuration........................................ 21

Multiple Devices on One Bus ................................................... 21

Terminal Voltage Operation Range ......................................... 21

Power-Up and Power-Down Sequences .................................. 21

Layout and Power Supply Biasing ............................................ 22

Digital Potentiometer Operation ............................................. 22

Programmable Rheostat Operation......................................... 22

Programmable Potentiometer Operation ............................... 23

Applications..................................................................................... 24

LCD Panel V

Adjustment ..................................................... 24

com

Current-Sensing Amplifier ....................................................... 24

Adjustable High Power LED Driver ........................................ 24

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 25

REVISION HISTORY

6/04—Revision 0: Initial Version

Rev.0 | Page 2 of 28

AD5251/AD5252

ELECTRICAL CHARACTERISTICS

1 kΩ Version. VDD = 3 V ± 10% or 5 V ± 10%; VSS = 0 V or VDD/VSS = ± 2.5 V ± 10%; VA = +VDD, VB = 0 V, –40°C < TA < +85°C, unless otherwise noted. Table 1.

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS RHEOSTAT MODE

Resolution N AD5251/AD5252 6/8 Bits Resistor Differential

Nonlinearity

R R R Resistor Nonlinearity2 R-INL RWB, RWA = NC, VDD = 5.5 V, AD5251 –0.5 ±0.2 +0.5 LSB R R R Nominal Resistor Tolerance ∆RAB/R Resistance Temperature

Coefficent Wiper Resistance R I Channel Resistance Matching ∆R

DC CHARACTERISTIC POTENTIOMETER DIVIDER MODE

Differential Nonlinearity

AD5252 –1 ±0.25 +1 LSB Integral Nonlinearity3 INL AD5251 –0.5 ±0.2 +0.5 LSB AD5252 –2 ±0.5 +2 LSB Voltage Divider Temperature

Coefficent Full-Scale Error V Code = full scale, VDD = 5.5 V, AD5252 –16 –11 0 LSB Code = full scale, VDD = 2.7 V, AD5251

Code = full scale, VDD = 2.7 V, AD5252 –23 –16 0 LSB Zero-Scale Error V Code = zero scale, VDD = 5.5 V, AD5252 0 11 16 LSB Code = zero scale, VDD = 2.7 V, AD5251 0 4 6 LSB Code = zero scale, VDD = 2.7 V, AD5252 0 15 20 LSB

RESISTOR TERMINALS

Voltage Range

Capacitance5 Ax, Bx CA, C

Capacitance5 Wx C

Common-Mode Leakage

Current

DIGITAL INPUTS and OUTPUTS

Input Logic High V V Input Logic Low V Output Logic High (SDA) V Output Logic Low (SDA) V

R-DNL RWB, RWA = NC, VDD = 5.5 V, AD5251 –0.5 ±0.2 +0.5 LSB

, RWA = NC, VDD = 5.5 V, AD5252 –1 ±0.25 +1 LSB

, RWA = NC, VDD = 2.7 V, AD5251 –0.75 ±0.3 +0.75 LSB

, RWA = NC, VDD = 2.7 V, AD5252 –1.5 ±0.3 +1.5 LSB

, RWA = NC, VDD = 5.5 V, AD5252 –2 ±0.5 +2 LSB

, RWA = NC, VDD = 2.7 V, AD5251 –1 +2.5 +4 LSB

, RWA = NC, VDD = 2.7 V, AD5252 –2 +9 +14 LSB

TA = 25°C –30 +30 %

IW = 1 V/R, VDD = 5 V 75 130 Ω

= 1 V/R, VDD = 3 V 200 300 Ω

0.15 %

(∆R

) × 106/∆T 650 ppm/°C

AB/RAB

/∆R

AB1

AB3

DNL AD5251 –0.5 ±0.1 +0.5 LSB

(∆V

VA, VB, V

) × 106/∆T Code = half scale 25 ppm/°C

W/VW

WFSE

WZSE

Code = full scale, VDD = 5.5 V, AD5251 –5 –3 0 LSB

−6

–4 0 LSB

Code = zero scale, VDD = 5.5 V, AD5251 0 3 5 LSB

V f = 1 kHz, measured to GND,

85 pF

VDDV

Code = half scale

f = 1 kHz, measured to GND,

95 pF

Code = half scale

VA = VB = VDD/2 0.01 1 µA

VDD = 5 V, VSS = 0 V 2.4 V

= 2.7 V/0 V or VDD/VSS = ± 2.5 V 2.1 V

DD/VSS

VDD = 5V, VSS = 0 V 0.8 V R

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9 V

PULL-UP

= 2.2 kΩ to VDD =5 V, VSS = 0 V 0.4 V

PULL-UP

Rev. 0 | Page 3 of 28

AD5251/AD5252

Parameter Symbol Conditions Min Typ1Max Unit

Leakage Current

A0 Leakage Current I Input Leakage Current (Other

than

and A0)

Input Capacitance5 C

= V

A0 = GND 3 µA VIN = 0 V or V

5 pF

POWER SUPPLIES

Single-Supply Power Range V

Dual-Supply Power Range VDD/V Positive Supply Current I Negative Supply Current I

EEMEM Data Storing Mode

DD_STORE

VSS = 0 V 2.7 5.5 V ±2.25 ±2.75 V VIH = VDD or VIL = GND 5 15 µA VIH = VDD or VIL = GND, VDD = +2.5 V,

= –2.5 V

VIH = VDD or VIL = GND 35 mA

Current EEMEM Data Restoring Mode

Current Power Dissipation

DD_RESTORE

DISS

VIH = VDD or VIL = GND 2.5 mA

VIH = VDD = 5 V or VIL = GND 0.075 mW Power Supply Sensitivity PSS ∆VDD = 5 V ± 10% −0.025 0.01 0.025 %/% ∆VDD = 3 V ± 10% –0.04 0.02 0.04 %/%

DYNAMIC CHARACTERISTICS

5, 8

Bandwidth –3 dB BW RAB = 1 kΩ 4 MHz Total Harmonic Distortion THD VA = 1 V rms, VB = 0 V, f = 1 kHz 0.05 % VW Settling Time t Resistor Noise Voltage e

Digital Crosstalk C

N_WB

VA = VDD, VB = 0 V 0.2 µs

RWB = 500 Ω, f = 1 kHz (thermal noise only) 3

VA = VDD, VB = 0 V, measure VW with

adjacent RDAC making full-scale change Analog Coupling C

Signal input at A1 and measure the

output at W3, f = 1 kHz

Typical represents the average reading at 25°C and VDD = 5 V.

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at V

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL

specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

Guaranteed by design and not subject to production test.

cmd 0 NOP should be activated after cmd 1 to minimize I

DISS

All dynamic characteristics use VDD = 5 V.

= 2.7 V, IW = VDD/R for both VDD = 3 V or VDD = 5 V.

is calculated from IDD × VDD = 5 V.

current consumption.

DD_READ

5 µA

±1 µA

–5 –15 µA

nV/√

–80 dB

–72 dB

Rev. 0 | Page 4 of 28

AD5251/AD5252

10 kΩ, 50 kΩ, 100 kΩ Versions. VDD = +3 V ± 10% or + 5 V ± 10%. VSS = 0 V or VDD/VSS = ± 2.5 V ± 10%. VA = +VDD, VB = 0 V, –40°C < T Table 2.

Parameter Symbol Conditions Min Ty p DC CHARACTERISTICS RHEOSTAT MODE

Resolution N AD5251/AD5252 6/8 Bits Resistor Differential NL R Resistor Nonlinearity2 R-INL RWB, RWA = NC, AD5251 −0.75 ±0.25 +0.75 LSB R Nominal Resistor Tolerance ∆RAB/R Resistance Temperature

Coefficent Wiper Resistance R I

Channel Resistance Matching ∆R R DC CHARACTERISTICS POTENTIOMETER DIVIDER

MODE

Differential Nonlinearity

AD5252 −1 ±0.3 +1 LSB

Integral Nonlinearity3 INL AD5251 −0.5 ±0.15 +0.5 LSB

AD5252 −1.5 ±0.5 +1.5 LSB

Voltage Divider

Temperature Coefficent (∆VW/VW) × 106/∆T Code = half scale 15 ppm/°C

Full-Scale Error V

Code = full scale, AD5252 −3 −1 0 LSB

Zero-Scale Error V Code = zero scale, AD5252 0 1.2 3 LSB RESISTOR TERMINALS

Voltage Range

Capacitance5 Ax, Bx CA, C

Capacitance5 Wx C

Common-Mode Leakage

Current DIGITAL INPUTS and OUTPUTS

Input Logic High V

Input Logic Low V

Output Logic High (SDA) V

Output Logic Low (SDA) V

Leakage Current

A0 Leakage Current I

Input Leakage Current

(Other than WP and A0)

Input Capacitance5 C POWER SUPPLIES

Single-Supply Power Range V

< +85°C, unless otherwise noted.

R-DNL RWB, RWA = NC, AD5251 −0.75 ±0.1 +0.75 LSB

(∆R

AB/RAB

/∆R

AB1

DNL AD5251 −0.5 ±0.1 +0.5 LSB

WFSE

WZSE

VA, VB, V

, RWA = NC, AD5252 −1 ±0.25 +1 LSB

, RWA = NC, AD5252 −2.5 ±1 +2.5 LSB

Max Unit

TA = 25°C −20 +20 %

) × 106/∆T 650 ppm/°C

IW = 1 V/R, VDD = 5 V 75 130 Ω

= 1 V/R, VDD = 3 V 200 300 Ω

AB2

RAB = 10 kΩ, 50 kΩ 0.15 %

= 100 kΩ 0.05 %

Code = full scale, AD5251 −1 −0.3 0 LSB

Code = zero scale, AD5251 0 0.3 1 LSB

V f = 1 kHz, measured to GND,

85 pF

VDDV

Code = half scale f = 1 kHz, measured to GND,

95 pF

Code = half scale VA = VB = VDD/2 0.01 1 µA

VDD =5 V, VSS = 0 V 2.4 V

= +2.7 V/0 V or VDD/VSS = ±2.5 V 2.1 V

DD/VSS

VDD = 5 V, VSS = 0 V 0.8 V

= +2.7 V/0 V or VDD/VSS =±2.5 V 0.6 V

DD/VSS

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9 V

PULL-UP

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 0.4 V

PULL-UP

= V

5 µA

A0 = GND 3 µA

VIN = 0 V or V

±1 µA

5 pF

VSS = 0 V 2.7 5.5 V

Rev. 0 | Page 5 of 28

AD5251/AD5252

Parameter Symbol Conditions Min Ty p

Dual-Supply Power Range VDD/V Positive Supply Current I Negative Supply Current I

±2.25 ±2.75 V VIH = VDD or VIL = GND 5 15 µA VIH = VDD or VIL = GND, VDD = +2.5 V, VSS

−5 −15 µA

Max Unit

= -2.5 V

EEMEM Data Storing Mode

DD_STORE

VIH = VDD or VIL = GND, TA = 0°C to 85°C 35 mA

Current EEMEM Data Restoring Mode

Current

Power Dissipation7 P

DD_RESTORE

DISS

VIH = VDD or VIL = GND, TA = 0°C to 85°C 2.5 mA

VIH = VDD = 5 V or VIL = GND 0.075 mW

Power Supply Sensitivity PSS ∆VDD = 5 V ±10% −0.005 +0.002 +0.005 %/% ∆VDD = 3 V ±10% −0.01 +0.002 +0.01 %/% DYNAMIC CHARACTERISTICS

5, 8

–3 dB Bandwidth BW RAB = 10 kΩ/50 kΩ/100 kΩ 400/80/40 kHz

Total Harmonic Distortion THD

VW Settling Time t

VA = 1 Vrms, VB = 0 V, f = 1 kHz 0.05 % VA = VDD, VB = 0 V, R

= 10 kΩ/50

1.5/7/14 µs

kΩ/100 kΩ

Resistor Noise Voltage e

N_WB

10 kΩ/50 kΩ/100 kΩ, code = midscale,

9/20/29

nV/√

f = 1 kHz (thermal noise only)

Digital Crosstalk C

VA = VDD, VB = 0 V, Measure VW with

-80 dB adjacent RDAC making full scale change

Analog Coupling C

Signal input at A1 and measure output

-72 dB at W3, f = 1kHz

Typical represents the average reading at 25°C and VDD = 5 V.

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at V

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL

specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

Guaranteed by design and not subject to production test.

cmd 0 NOP should be activated after cmd 1 to minimize I

DISS

All dynamic characteristics use VDD = 5 V.

= 2.7 V, IW = VDD/R for both VDD = 3 V or VDD = 5 V.

is calculated from IDD × VDD = 5 V.

current consumption.

DD_READ

Rev. 0 | Page 6 of 28

AD5251/AD5252

INTERFACE TIMING CHARACTERISTICS

Guaranteed by design, not subject to production test. See Figure 3 for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V), and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V Table 3. Interface Timing and EEMEM Reliability Characteristics (All Parts).

Parameter Symbol Conditions Min Typ Max Unit

INTERFACE TIMING

SCL Clock Frequency f tBUF Bus Free Time between STOP and

START t

Hold Time (Repeated START) t

HD;STA

Low Period of SCL Clock t

LOW

High Period of SCL Clock t

HIGH

Setup Time For START Condition t

SU;STA

HD;DAT

Data Setup Time t

SU;DAT

tF Fall Time of Both SDA and SCL Signals t tR Rise Time of Both SDA and SCL Signals t t

Setup Time for STOP Condition t

SU;STO

EEMEM Data Storing Time t EEMEM Data Restoring Time at

Power-On

EEMEM Data Restoring Time Upon Restore Command or RESET Operation

EEMEM Rewritable Time (delay time after Power On or RESET before EEMEM can be written)

FLASH/EE MEMORY RELIABILITY

Endurance Data Retention

During power-up, all outputs preset to midscale before restoring to the final EEMEM contents. RDAC0 has the shortest, whereas RDAC3 has the longest EEMEM data

restoring time.

Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates

with junction temperature.

When the part is not in operation, the SDA and SCL pins should be pulled to high. When these pins are pulled to low, the I2C interface at these pins conducts current of

about 0.8 mA at V

= 3 V and 5 V.

Data Hold Time t

= 5.5 V and 0.2 mA at VDD = 2.7 V.

SCL

400 kHz

1.3 µs

After this period, the first clock pulse

0.6

µs

is generated

EEMEM_STORE

EEMEM_RESTORE1

EEMEM_RESTORE2

EEMEM_REWRITE

1.3

0.6

0.6 0 100

0.6

0.9 µs

300 ns 300 ns µs

26 ms VDD rise time dependent. Measure

without decoupling capacitors at V

and V

300 µs

VDD = 5 V 300 µs

540 µs

µs µs µs

100 kCycles 100 Years

Rev. 0 | Page 7 of 28

AD5251/AD5252

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted . Table 4.

Parameter Rating

VDD to GND −0.3 V, +7 V VSS to GND +0.3 V, −7 V VDD to V

VA, VB, VW to GND VSS, V

7 V

Maximum Current IWB, IWA Pulsed ±20 mA IWB Continuous (RWB ≤ 1 kΩ, A Open)

±5 mA IWA Continuous (RWA ≤ 1 kΩ, B Open)1 ±5 mA IAB Continuous

= 1 kΩ/10 kΩ/50 kΩ/100 kΩ)1

Digital Inputs and Output Voltage

±5 mA/±500 µA/

±100 µA/±50 µA

0 V, 7 V to GND

Operating Temperature Range −40°C to +85°C Maximum Junction Temperature

)

J MAX

150°C

Storage Temperature −65°C to +150°C Lead Temperature (Soldering,10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C TSSOP-14 Thermal Resistance2 θ

136°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Maximum terminal current is bounded by the maximum applied voltage

across any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. V

Package power dissipation = (TJMAX − TA)/θJA.

= 5 V.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev.0 | Page 8 of 28

AD5251/AD5252

PIN CONFIGURATION AND FUNCTION DESCRIPTION

AD0

WP W1

SDA

B1 A1

AD5251/

AD5252

TOP VIEW

(Not to Scale)

AD1

DGND

SCL

03823-0-002

Figure 2. AD5251/AD5252 in TSSOP-14

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 V

Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply, where V

– VSS ≤ 5.5 V. VDD must be able to source 35 mA for 26 ms when storing data to

EEMEM. 2 AD0 I2C Device Address 0. AD0 and AD1 allow four AD5251/AD5252s to be addressed. 3

4 W1 Wiper Terminal of RDAC1. VSS ≤ VW1 ≤ VDD.

Write Protect, Active Low. VWP ≤ VDD + 0.3 V.

5 B1 B Terminal of RDAC1. VSS ≤ VB1 ≤ VDD.1 6 A1 A Terminal of RDAC1. VSS ≤ VA1 ≤ VDD.1 7 SDA

Serial Data Input/Output Pin. Shifts in one bit at a time on positive clock edges. MSB loaded

first. Open-drain MOSFET requires pull-up resistor. 8 V

Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where VDD – VSS ≤

+5.5 V. If V

is used, other than grounded, in dual supply, VSS must be able to sink 35 mA for

26 ms when storing data to EEMEM. 9 SCL

Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. V

+ 0.3 V). Pull-up resistor is recommended for SCL to ensure minimum power.

10 DGND Digital Ground. Connect to system analog ground at a single point. 11 AD1 I2C Device Address 1. AD0 and AD1 allow four AD5251/AD5252s to be addressed. 12 A3 A Terminal of RDAC3. VSS ≤ VA3 ≤ VDD.1 13 B3 B Terminal of RDAC3. VSS ≤ VB3 ≤ VDD.1 14 W3 W Terminal of RDAC3. VSS ≤ VW3 ≤ VDD.1

For quad-channel device software compatibility, the dual potentiometers in the parts are designated as RDAC1 and RDAC3.

SCL

≤

I2C INTERFACE TIMING DIAGRAM

SCL

PS P

Figure 3. I

C Timing Diagram

Rev. 0 | Page 9 of 28

03823-0-003

AD5251/AD5252

I2C INTERFACE GENERAL DESCRIPTION

FROM MASTER TO SLAVE FROM SLAVE TO MASTER

S = START CONDITION P = STOP CONDITION A = ACKNOWLEDGE (SDA LOW) A = NOT ACKNOWLEDGE (SDA HIGH) R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW

SLAVE ADDRESS

(7-BIT)

R/W A/AS

0 WRITE

Figure 4. I

C—Master Writing Data to Slave

INSTRUCTIONS

(8-BIT)

DATA TRANSFERRED

(N BYTES + ACKNOWLEDGE)

DATA

(8-BIT)

03823-0-004

SLAVE ADDRESS

(7-BIT)

R/W AS

1 READ

Figure 5. I

DATA

(8-BIT)

(N BYTES + ACKNOWLEDGE)

C—Master Reading Data from Slave

DATA TRANSFERRED

DATA

(8-BIT)

03823-0-005

SLAVE ADDRESS

(7-BIT)

R/W R/WS

READ OR WRITE (N BYTES +

DATA

ACKNOWLEDGE)

Figure 6. I

A/A

SLAVE ADDRESS

REPEATED START READ

C—Combined Write/Read

OR WRITE

DIRECTION OF TRANSFER MAY

CHANGE AT THIS POINT

DATA

(N BYTES +

ACKNOWLEDGE)

A/A

03823-0-006

Rev. 0 | Page 10 of 28

AD5251/AD5252

I2C INTERFACE DETAIL DESCRIPTION

FROM MASTER TO SLAVE FROM SLAVE TO MASTER

S = START CONDITION P = STOP CONDITION A = ACKNOWLEDGE (SDA LOW) A = NOT ACKNOWLEDGE (SDA HIGH) R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW EE/RDAC = EEMEM REGISTER, LOGIC HIGH/RDAC REGISTER, LOGIC LOW A4, A3, A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES

S 0 1 0 1 1 A

0 A A4A3A2A1A0A PDATA0

CMD/

REG

EE/

RDAC

SLAVE ADDRESS INSTRUCTIONS

0 WRITE

0 REG

AND ADDRESS

(1 BYTE +

ACKNOWLEDGE)

03823-0-007

Figure 7. Single Write Mode

S 0 1 0 1 1 A

RDAC SLAVE ADDRESS RDAC INSTRUCTIONS

0 A A4A3A2A1A

0 WRITE

CMD/

REG

0 REG

EE/

RDAC

AND ADDRESS

Figure 8. Consecutive Write Mode

(N BYTES +

RDAC3

DATA

ACKNOWLEDGE)

PA ARDAC1

03823-0-008

Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/

A4 A3 A2 A1 A0

RDAC Data Byte Description

= 0, CMD/

REG

= 0, EE/

RDAC

= 0)

0 0 0 0 0 Reserved 0 0 0 0 1 RDAC1 6- or 8 bit wiper setting (2 MSBs of AD5251 are X) 0 0 0 1 0 Reserved 0 0 0 1 1 RDAC3 6- or 8 bit wiper setting (2 MSBs of AD5251 are X) 0 0 1 0 0 Reserved : : : : : 0 1 1 1 1 Reserved

RDAC/EEMEM WRITE

Setting the wiper position requires an RDAC write operation. The single write operation is shown in Figure 7, and the consecutive write operation is shown in Figure 8. In the consecutive write operation, if the

address starts at 00001, the first data byte goes to RDAC1 and the second data byte goes to RDAC3. The RDAC address is shown in Table 6.

While the RDAC wiper setting is controlled by a specific RDAC register, each RDAC register corresponds to a specific EEMEM location, which provides nonvolatile wiper storage functionality. The addresses are shown in Table 7. The single and consecutive write operations apply also to EEMEM write operations.

is selected and the

RDAC

Rev. 0 | Page 11 of 28

There are 12 nonvolatile memory locations: EEMEM4 to EEMEM15. Users can store a total of 12 bytes of information, such as memory data for other components, look-up tables, or system identification information.

In a write operation to the EEMEM registers, the device disables

C interface during the internal write cycle. Acknowledge

the I polling is required to determine the completion of the write cycle. See EEMEM Write-Acknowledge Polling.

AD5251/AD5252

Table 7. Addresses for Writing (Storing) RDAC Settings and User-Defined Data to EEMEM Registers (R/

CMD/

A4 A3 A2 A1 A0

REG

= 0, EE/

RDAC

= 1)

Data Byte Description

0 0 0 0 0 Reserved 0 0 0 0 1

Store RDAC1 setting to

EEMEM1 0 0 0 1 0 Reserved 0 0 0 1 1

Store RDAC3 setting to

EEMEM3 0 0 1 0 0 Store user data to EEMEM4 0 0 1 0 1 Store user data to EEMEM5 0 0 1 1 0 Store user data to EEMEM6 0 0 1 1 1 Store user data to EEMEM7 0 1 0 0 0 Store user data to EEMEM8 0 1 0 0 1 Store user data to EEMEM9 0 1 0 1 0 Store user data to EEMEM10 0 1 0 1 1 Store user data to EEMEM11 0 1 1 0 0 Store user data to EEMEM12 0 1 1 0 1 Store user data to EEMEM13 0 1 1 1 0 Store user data to EEMEM14 0 1 1 1 1 Store user data to EEMEM15

User can store any of the 64 RDAC settings for AD5251 or any of the 256

RDAC settings for AD5252.

RDAC/EEMEM Read

The AD5251/AD5252 provide two different RDAC or EEMEM read operations. For example, Figure 9 shows the method of reading the RDAC0 to RDAC3 contents without specifying the address, assuming Address RDAC0 was already selected from the previous operation. If RDAC_N, other than Address 0, is

S 0 1 0 1 1 A

D 1

= 0,

1 A PARDAC1 D 0

EEMEM OR REGISTER DATA

selected previously, readback starts with Address N, followed by N + 1, and so on.

Figure 10 illustrates a random RDAC or EEMEM read operation. This operation lets users specify which RDAC or EEMEM register is read by first issuing a dummy write command to change the RDAC address pointer, and then proceeding with the RDAC read operation at the new address location.

Table 8. Addresses for Reading (Restoring) RDAC Settings and User Data from EEMEM (R/

EE/

A4 A3 A2 A1 A0

RDAC

= 1)

Data Byte Description

= 1, CMD/

REG

= 0,

0 0 0 0 0 Reserved 0 0 0 0 1

Read RDAC1 Setting from

EEMEM1 0 0 0 1 0 Reserved 0 0 0 1 1

Read RDAC3 Setting from

EEMEM3 0 0 1 0 0 Read user data from EEMEM4 0 0 1 0 1 Read user data from EEMEM5 0 0 1 1 0 Read user data from EEMEM6 0 0 1 1 1 Read user data from EEMEM7 0 1 0 0 0 Read user data from EEMEM8 0 1 0 0 1 Read user data from EEMEM9 0 1 0 1 0 Read user data from EEMEM10 0 1 0 1 1 Read user data from EEMEM11 0 1 1 0 0 Read user data from EEMEM12 0 1 1 0 1 Read user data from EEMEM13 0 1 1 1 0 Read user data from EEMEM14 0 1 1 1 1 Read user data from EEMEM15

RDAC3

EEMEM OR REGISTER DATA

RDAC SLAVE ADDRESS (N BYTES + ACKNOWLEDGE)

Figure 9. RDAC Current Read (Restricted to Previously Selected Address Stored in the Register).

0 WRITE

1 READ

A0A

ADDRESS

REPEATED START 1 READ

Figure 10. RDAC or EEMEM Random Read

SLAVE ADDRESSINSTRUCTION AND

A1S

RDAC OR

EEMEM DATA

(N BYTES + ACKNOWLEDGE)

03823-0-009

A/A

PS SLAVE ADDRESS

03823-0-010

Rev. 0 | Page 12 of 28

AD5251/AD5252

RDAC/EEMEM Quick Commands

The AD5251/AD5252 feature 12 quick commands that facilitate easy manipulation of RDAC wiper settings and provide RDACto-EEMEM storing and restoring functions. The command

FROM MASTER TO SLAVE FROM SLAVE TO MASTER

S = START CONDITION P = STOP CONDITION A = ACKNOWLEDGE (SDA LOW) A = NOT ACKNOWLEDGE (SDA HIGH) AD1, AD0 = I R/W = READ ENABLE BIT, LOGIC HIGH/WRITE ENABLE BIT, LOGIC LOW CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW C3, C2, C1, C0 = COMMAND BITS A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES

S 0 1 0 1 1 A

C DEVICE ADDRESS BITS. MUST MATCH WITH THE LOGIC STATES AT PINS AD1, AD0

0 A C3C2C1C0A2A1A0A P

CMD/

REG

format is shown in Figure 11 and the command descriptions are shown in Table 9.

RDAC SLAVE ADDRESS

Figure 11. RDAC Quick Command Write (Dummy Write)

0 WRITE

1 CMD

Table 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/

03823-0-011

= 1, A2 = 0)

REG

C3 C2 C1 C0 Command Description

0 0 0 0 NOP 0 0 0 1 Restore EEMEM (A1, A0) to RDAC (A1, A0)

0 0 1 0 Store RDAC (A1, A0) to EEMEM (A1, A0) 0 0 1 1 Decrement RDAC (A1, A0) 6 dB 0 1 0 0 Decrement all RDACs 6 dB 0 1 0 1 Decrement RDAC (A1, A0) one step 0 1 1 0 Decrement all RDACs one step 0 1 1 1 Reset: Restore EEMEMs to all RDACs 1 0 0 0 Increment RDACs (A1, A0) 6 dB 1 0 0 1 Increment all RDACs 6 dB 1 0 1 0 Increment RDACs (A1, A0) one step 1 0 1 1 Increment all RDACs one step 1 1 0 0 Reserved : : : : 1 1 1 1 Reserved

This command leaves the device in the EEMEM read power state, which consumes power. Users should issue the NOP command to return the device to the idle state.

Table 10. Address Table for Reading Tolerance (CMD/

A4 A3 A2 A1 A0

Data Byte Description

REG

= 0, EE/

RDAC

= 1, A4 = 1)

0 0 0 0 0 Reserved : : : : : 1 1 0 0 1 Reserved 1 1 0 1 0 Sign and 7-bit integer values of RDAC1 tolerance (read only) 1 1 0 1 1 8-bit decimal value of RDAC1 tolerance (read only) 1 1 1 0 0 Reserved 1 1 1 0 1 Reserved 1 1 1 1 0 Sign and 7-bit integer values of RDAC3 tolerance (read only) 1 1 1 1 1 8-bit decimal value of RDAC3 tolerance (read only)

Rev. 0 | Page 13 of 28

AD5251/AD5252

Figure 12. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions. (Unit is percent. Only data bytes are shown.)

D7 D6 D5 D4 D3 D2 D1 D0

6252423222120

SIGN

7 BITS FOR INTEGER NUMBER

Tolerance Stored in Read-Only Memory

The AD5251/AD5252 feature patented RAB tolerances storage in the nonvolatile memory. The tolerance of each channel is stored in the memory during the factory production and can be read by users at any time. The knowledge of stored tolerance, which is the average of R to predict R

over all codes (see Figure 28), allows users

accurately. This feature is valuable for precision, rheostat mode, and open-loop applications where knowledge of absolute resistance is critical.

The stored tolerances reside in the read-only memory, and are expressed as a percentage. The tolerance is stored in two memory locations (see Table 10). The data format of the tolerance is in sign magnitude binary form. An example is shown in Figure 11. In the first memory location, the MSB is designated for the sign (0 = + and 1= –) and the 7 LSBs are designated for the integer portion of the tolerance. In the second memory location, all eight data bits are designated for the decimal portion of tolerance. As shown in Table 10 and Figure 12 for example, if the rated R

= 10 kΩ and the data

readback from Address 11000 shows 0001 1100 and Address 11001 shows 0000 1111, then RDAC0 tolerance can be calculated as

D7 D6 D5 D4 D3 D2 D1 D0

2–12–22–32–42–52–62

8 BITS FOR DECIMAL NUMBER

–7

–8

03823-0-012

EEMEM Write-Acknowledge Polling

After each write operation to the EEMEM registers, an internal

write cycle begins. The I determine if the internal write cycle is complete and the I interface is enabled, interface polling can be executed. I

C interface of the device is disabled. To

interface polling can be conducted by sending a start condition

followed by the slave address + the write bit. If the I

C interface responds with an ACK, the write cycle is complete and the interface is ready to proceed with further operations. Other-

C interface polling can be repeated until it succeeds.

wise, I Commands 2 and 7 also require acknowledge polling.

EEMEM Write Protection

Setting the WP pin to a logic LOW after EEMEM programming protects the memory and RDAC registers from future write

operations. In this mode, the EEMEM and RDAC read operations operate as normal. When write protection is enabled, Command 1 (Restore from EEMEM to RDAC) and Command 7 (Reset) function normally to allow RDAC settings to be refreshed from the EEMEM to the RDAC registers.

MSB: 0 = + Next 7 MSB: 001 1100 = 28

–8

8 LSB: 0000 1111 = 15 × 2

= 0.06 Tolerance = +28.06% and therefore R

AB_ACTUAL

= 12.806 kΩ

Rev. 0 | Page 14 of 28

AD5251/AD5252

XXXXXXX

I2C COMPATIBLE 2-WIRE SERIAL BUS

SCL

START B

MASTER

SLAVE ADDRESS BYTE

AD1 AD0

FRAME 1

SCL

SDA

START BY

MASTER

SLAVE ADDRESS BYTE

The first byte of the AD5251/AD5252 is a slave address byte (see Figure 12 and Figure 13). It has a 7-bit slave address and an

bit. The 5 MSBs of the slave address are 01011, and the following 2 LSBs are determined by the states of the AD1 and AD0 pins. AD1 and AD0 allow the user to place up to four parts on one bus.

AD5251/AD5252 can be controlled via an I bus, and are connected to this bus as slave devices. The 2-wire

C serial bus protocol (see Figure 13 and Figure 14) follows:

1. The master initiates a data transfer by establishing a start

condition, such that SDA goes from high to low while SCL is high (see Figure 13). The following byte is the slave address byte, which consists of the 5 MSBs of a slave address defined as 01011. The next two bits are AD1 and

C device address bits. Depending on the states of

AD0, I their AD1 and AD0 bits, four parts can be addressed on the same bus. The last LSB, the R/

bit, determines

whether data is read from or written to the slave device.

The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is called an acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register.

2. In the write mode (except when restoring EEMEM to the

RDAC register), there is an instruction byte that follows the slave address byte. The MSB of the instruction byte is labeled CMD/

. MSB = 1 enables CMD, the command

REG instruction byte; MSB = 0 enables general register writing. The third MSB in the instruction byte, labeled EE/ is true only when MSB = 0 or is in general writing mode. EE enables the EEMEM register and REG enables the RDAC register. The 5 LSBs, A4 to A0, designate the

R/W

ACK. BY

AD525x

Figure 13. General I

FRAME 1

AD1

AD0

Figure 14. General I

C compatible serial

RDAC

FRAME 2

INSTRUCTION BYTE

91 9

R/W

ACK. BY AD525x

D6 D5

ACK. BY

AD525x

C Write Pattern

D7 D6 D5 D4 D3 D2

FRAME 2

RDAC REGISTER

C Read Pattern

D4 D3 D2 D1

FRAME 1

DATA BYTE

D1 D0

NO ACK. BY

MASTER

STOP BY MASTER

ACK. BY

AD525x

03823-0-014

STOP BY MASTER

addresses of the EEMEM and RDAC registers, (see Figure 7 and Figure 8). When MSB = 1 or when in CMD mode, the four bits following MSB are C3 to C1, which correspond to 12 predefined EEMEM controls and quick commands; there also are four factory reserved commands. The 3 LSBs—A2, A1, and A0—are four addresses, but only 001 and 011 are used for RDAC1 and RDAC3, respectively (see Figure 10). After acknowledging the instruction byte, the last byte in the write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 13).

3. In current read mode, the RDAC0 data byte immediately

follows the acknowledgment of the slave address byte. After an acknowledgement, RDAC1 follows, then RDAC2, and so on (there is a slight difference in write mode, where the last eight data bits representing RDAC3 data are followed by a no acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 14). Another reading method, random read method, is shown in Figure 10.

4. When all data bits have been read or written, a stop

condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition (see Figure 13). In read mode, the master issues a no acknowledge for the ninth clock pulse, i.e., the SDA line remains high. The master then brings the SDA line low

before the 10

clock pulse, which goes high to establish a

stop condition (see Figure 14).

03823-0-013

Rev.0 | Page 15 of 28

AD5251/AD5252

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

R-INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

TA= –40°C, +25°C, +85°C, +125°C

CODE (Decimal)

Figure 15. R-INL vs. Code

03823-0-015

1.0

0.8

0.6

0.4

0.2

–0.2

INL (LSB)

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

= –40°C, +25°C, +85°C, +125°C

CODE (Decimal)

Figure 18. DNL vs. Code

03823-0-018

1.0

0.8

0.6

0.4

0.2

–0.2

R-DNL (LSB)

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

TA = –40°C, +25°C, +85°C, +125°C

CODE (Decimal)

Figure 16. R-DNL vs. Code

1.0

0.8

0.6

0.4

0.2

–0.2

INL (LSB)

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

= –40°C, +25°C, +85°C, +125°C

CODE (Decimal)

Figure 17. INL vs. Code

03823-0-016

03823-0-017

–2

–4

SUPPLY CURRENT (µA)

–6

–8

–10

–40 –20 0 20 40 60 80 100 120

IDD @ VDD= +5.5V

IDD @ VDD= +2.7V

ISS @ VDD= +2.7V, VSS= –2.7V

TEMPERATURE (°C)

Figure 19. Supply Current vs. Temperature

0.1

(mA)

0.01

VDD= 2.7V

0.001

0.0001 0123456

DIGITAL INPUT VOLTAGE (V)

VDD= 5.5V

Figure 20. Supply Current vs. Digital Input Voltage, T

= 25°C

03823-0-019

03823-0-020

Rev.0 | Page 16 of 28

AD5251/AD5252

240 220 200 180 160 140

(Ω)

120

100

80 60 40 20

10 23456

VDD= 2.7V

= 25°C

BIAS

(V)

Figure 21. Wiper Resistance vs. V

VDD= 5.5V

= 25°C

DATA = 0x00

BIAS

03823-0-021

VDD= 5V T

= –40°C/+85°C

POTENTIOMETER MODE TEMPCO (ppm/°C)

0 32 64 96 128 160 192 224 256

CODE (Decimal)

= V

VB= 0V

Figure 24. AD5252 Potentiometer Mode Tempco V

/T vs. Code

03823-0-024

(%)

∆R

–2

–4

–6

–40 –20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 22. Change of R

RHEOSTAT MODE TEMPCO (ppm/°C)

0 32 64 96 128 160 192 224 256

CODE (Decimal)

Figure 23. AD5252 Rheostat Mode Tempco R

vs. Temperature

VDD= 5V T

= –40°C/+85°C

= V

VB= 0V

/T vs. Code

03823-0-022

03823-0-023

–6

–12

–18

–24

–30

0x08

GAIN (dB)

–36

–42

–48

–54

–60

0x04

0x02

0x01

1k 10k10 100 100k 1M 10M

FREQUENCY (Hz)

Figure 25. AD5252 Gain vs. Frequency vs. Code, R

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

0xFF 0x80

0x40 0x20

0x10

0x08 0x04

0x01 0x00

0x02

1k 10k10 100 100k 1M 10M

FREQUENCY (Hz)

Figure 26. AD5252 Gain vs. Frequency vs. Code, R

0x40 0x20

0x10

0x00

0xFF

0x80

= 1 kΩ

= 10 kΩ

03823-0-025

03823-0-026

Rev. 0 | Page 17 of 28

AD5251/AD5252

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

Figure 27. AD5252 Gain vs. Frequency vs. Code, R

0xFF 0x80

0x40 0x20

0x10

0x08 0x04

0x01 0x00

0x02

1k 10k10 100 100k 1M 10M

FREQUENCY (Hz)

= 50 kΩ

03823-0-026

1.2

1.0

0.8

0.6

(mA)

0.4

0.2

1 10010 1k 10k 100k 1M 10M

CLOCK FREQUENCY (Hz)

TA= 25°C

VDD= 5.5V

VDD= 2.7V

Figure 30. Supply Current vs. Digital Input Clock Frequency

03823-0-030

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

0x80

0x40

0x20

0x10

0x08

0x04 0x02 0x01

1k 10k10 100 100k 1M 10M

FREQUENCY (Hz)

Figure 28. AD5252 Gain vs. Frequency vs. Code, R

100

)

Ω

(

∆

–20

–40

–60

–80

–100

0 32 64 96 128 160 192 224 256

100k

Ω

CODE (Decimal)

Figure 29. AD5252 ∆R

10k

Ω

50k

Ω

vs. Code, TA = 25°C

0xFF

0x00

= 100 kΩ

VDD = 5.5V

03823-0-028

03823-0-029

CLK VDD = 5V

DIGITAL FEEDTHROUGH

Figure 31. Clock Feedthrough and Midscale Transition Glitch

VDD (NO DECOUPLING CAPS)

VWB1 (0x3F STORED IN EEMEM)

VWB3 (0x3F STORED IN EEMEM)

MIDSCALE PRESET

RESTORE RDAC1 SETTING TO 0x3F

Figure 32 .t

RESTORE RDAC3 SETTING TO 0x3F

VDD = VA1 = VA3 = 3.3V GND = VB1 = VB3

EEMEM_RESTORE

03823-0-031

03823-0-032

Rev. 0 | Page 18 of 28

AD5251/AD5252

RAB= 1k

Ω

RAB= 1k

Ω

(mA)

WB_MAX

RAB= 10k

THEORETICAL I

RAB= 100k

0 8 16 24 32 40 48 56 64

Ω

RAB= 50k

Ω

CODE (Decimal)

Figure 33. AD5251 I

max vs. Code

VA= VB= OPEN T

=25°C

03823-0-033

(mA)

WB_MAX

RAB= 10k

RAB= 50k

Ω

CODE (Decimal)

THEORETICAL I

RAB= 100k

0 32 64 96 128 160 192 224 256

Figure 34. AD5252 I

VA= VB= OPEN TA=25°C

max vs. Code

03823-0-034

Rev. 0 | Page 19 of 28

AD5251/AD5252

OPERATIONAL OVERVIEW

The AD5251/AD5252 are dual-channel digital potentiometers in 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ that allow 64 and 256 linear resistance step adjustments. The AD5251/AD5252 employ double-gate CMOS EEPROM technology that allows resistance settings and user-defined data to be stored in the EEMEM registers. The EEMEM is nonvolatile, such that settings remain when power is removed. The RDAC wiper settings are restored from the non-volatile memory settings during device power-up and can also be restored at any time during operation.

The AD5251/AD5252 resistor wiper positions are determined by the RDAC register contents. The RDAC register acts like a scratch-pad register, allowing unlimited changes of resistance settings. RDAC register contents can be changed using the device’s serial I the commands to program the RDAC registers are discussed in the I2C Interface Detail Description section.

The four RDAC registers have corresponding EEMEM memory locations that provide nonvolatile storage of resistor wiper position settings. The AD5251/AD5252 provide commands to store the RDAC register contents to their respective EEMEM memory locations. During subsequent power-on sequences, the RDAC registers are automatically loaded with the stored value.

Whenever the EEMEM write operation is enabled, the device activates the internal charge pump and raises the EEMEM cell gate bias voltage to a high level, essentially erasing the current content in the EEMEM register and allowing subsequent storage of the new content. Saving data to an EEMEM register consumes about 35 mA of current and lasts about 26 ms. Because of charge pump operation, all RDAC channels may experience noise coupling during the EEMEM writing operation.

The EEMEM restore time in power-up or during operation is about 300 µs. Note that the power up EEMEM refresh time depends on how fast V supply voltage decoupling capacitors limit the EEMEM restore time during power-up. Figure 32 shows the power up profile where V is applied with a digital signal. The device initially resets the measured RDACs to midscale before reaching their final values during EEMEM restoration.

In addition, users should issue a NOP Command 0 immediately after using Command 1 to restore the EEMEM setting to RDAC, to minimize supply current dissipation. Directly reading user data from EEMEM does not require similar NOP command execution.

In addition to the movement of data between RDAC registers and EEMEM memory, the AD5251/AD5252 provide other shortcut commands that facilitate the users’ programming needs, as shown in Table 11.

C interface. The format of the data-words and

reaches its final value. As a result, any

, without any decoupling capacitors connected to it,

Table 11. AD5251/AD5252 Quick Commands

Commmand Description

0 NOP 1

2 Store RDAC register setting to EEMEM. 3 Decrement RDAC 6 dB (shift data bits right). 4

5 Decrement RDAC one step. 6 Decrement all RDACs one step. 7 Reset EEMEM contents to all RDACs. 8 Increment RDAC 6 dB (shift data bits left). 9 Increment All RDACs 6 dB (shift all data bits left). 10 Increment RDAC one step. 11 Increment all RDACs one step. 12–15 Reserved.

Restore EEMEM content to RDAC. User should issue NOP immediately after this command to conserve power.

Decrement all RDACs 6 dB (shift all data bits right).

LINEAR INCREMENT AND DECREMENT COMMANDS

The increment and decrement commands (10, 11, 5, and 6) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to send just an increment or decrement command to the AD5251/AD5252. The adjustments can be directed to an individual RDAC or to all four RDACs.

±6 dB ADJUSTMENTS (DOUBLING/HALVING WIPER SETTING)

The AD5251/AD5252 accommodates ±6 dB adjustments of the RDAC wiper positions by shifting the register contents to left/right for increment/decrement operations, respectively. Commands 3, 4, 8, and 9 can be used to increment or decrement the wiper positions in 6 dB steps synchronously or asynchronously.

Incrementing the wiper position by +6 dB is essentially doubling the RDAC register value, while decrementing by –6 dB is halving the register content. Internally, the AD5251/AD5252 use shift registers to shift the bits left and right to achieve a ±6 dB increment or decrement. The maximum number of adjustments is nine and eight steps for increment from zero scale and decrement from full scale, respectively. These functions are useful for various audio/video level adjustments, especially for white LED brightness settings where human visual responses are more sensitive to large than small adjustments.

Rev. 0 | Page 20 of 28

AD5251/AD5252

DIGITAL INPUT/OUTPUT CONFIGURATION

SDA is a digital input/output with an open-drain MOSFET that requires a pull-up resistor for proper communication. On the other hand, SCL and

resistors are recommended to minimize the MOSFETs cross conduction current when the driving signals are lower than

. SCL and WP have ESD protection diodes, as shown in

Figure 35 and Figure 36.

can be permanently tied to VDD without a pull-up resistor if

WP the write-protect feature is not used. If internal current source pulls it low to enable write-protect. In applications where the device is not being programmed on a frequent basis, this allows the part to default to write-protect after any one-time factory programming or field calibration without the use of an on board pull-down resistor. Because there are protection diodes on all these inputs, their signal levels must not be greater than V diodes.

are digital inputs for which pull-up

is left floating, an

to prevent forward biasing of the

03823-0-035

GND

Figure 35. SCL Digital Input

INPUTS

Table 12. Multiple Devices Addressing

AD1 AD0 Device Addressed

0 0 U1 0 1 U2 1 0 U3 1 1 U4

+5V

MASTER

SDA SCL AD1

AD0

SDA SCL AD1

AD0

SDA SCL AD1

AD0

SDA AD1 AD0

SDA

SCL

03823-0-016

Figure 37. Multiple AD5251/AD5252s on a Single Bus

TERMINAL VOLTAGE OPERATION RANGE

The AD5251/AD5252 are designed with internal ESD diodes for protection; these diodes also set the boundary of the terminal operating voltages. Positive signals present on Terminal A, B, or W that exceed V forward biased diode. Similarly, negative signals on Terminal A, B, or W that are more negative than V Figure 38). In practice, users should not operate V

to be higher than the voltage across VDD to VSS, but VAB,

, and VWB have no polarity constraint.

are clamped by the

are also clamped (see

, VWA, and

03823-0-018

03823-0-036

GND

Figure 36. Equivalent

Digital Input

MULTIPLE DEVICES ON ONE BUS

The AD5251/AD5252 are equipped with two addressing pins, AD1 and AD0, that allow up to four AD5251/AD5252s to be operated on one I AD1 and AD0 on each device must first be defined. An example is shown in Table 12 and Figure 37. In I device is issued a different slave address—01011(AD1)(AD0)— to complete the addressing.

C bus. To achieve this result, the states of

C programming, each

Figure 38. Maximum Terminal Voltages Set by V

POWER-UP AND POWER-DOWN SEQUENCES

Because the ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 38), it is important to power-on V B, and W. Otherwise, the diodes are forward-biased such that

are powered unintentionally and may affect the rest of

DD/VSS

the user’s circuit. Similarly, V last. The ideal power-up sequence is in the following order: GND, V

powering V long as they are powered after V

before applying any voltage to Terminals A,

DD/VSS

should be powered down

DD/VSS

, VSS, digital inputs, and VA/VB/VW. The order of

, VB, VW, and the digital inputs is not important, as

DD/VSS

and V

Rev. 0 | Page 21 of 28

AD5251/AD5252

LAYOUT AND POWER SUPPLY BIASING

It is always a good practice to employ a compact, minimum lead-length layout design. The leads to the input should be as direct as possible, with a minimum conductor length. Ground paths should have low resistance and low inductance.

Similarly, it is also good practice to bypass the power supplies with quality capacitors. Low equivalent series resistance (ESR) 1 µF to 10 µF tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and filter low frequency ripple. Figure 39 illustrates the basic supply bypassing configuration for the AD5251/AD5252.

AD5251/AD5252

10µF

0.1µF

10µF

0.1µF

GND

03823-0-039

Figure 39. Power Supply Bypassing

The ground pin of the AD5251/AD5252 is used primarily as a digital ground reference. To minimize the digital ground bounce, the AD5251/AD5252 ground terminal should be joined remotely to the common ground (see Figure 39).

DIGITAL POTENTIOMETER OPERATION

The structure of the RDAC is designed to emulate the performance of a mechanical potentiometer. The RDAC contains a string of resistor segments, with an array of analog switches acting as the wiper connection to the resistor array. The number of points is the resolution of the device. For example, the AD5251/AD5252 emulates 64 or 256 connection points with 64 or 256 equal resistance, R better than 1.5%/0.4% settability resolution.

Figure 40 provides an equivalent diagram of the connections between the three terminals that make up one channel of the RDAC. Switches SW switches SW(0) to SW(2

and SWB are always ON, while one of

N–1

) is ON one at a time, depending on the setting decoded from the data bit. Because the switches are nonideal, there is a 75 Ω wiper resistance, R is a function of supply voltage and temperature; lower supply voltages and higher temperatures result in higher wiper resistances. Consideration of wiper resistance dynamics is important in applications where accurate prediction of output resistance is required.

, allowing it to provide

. Wiper resistance

SW(2N–1)

RDAC

WIPER

AND

DECODER

= RAB/2

DIGITAL

IRCUITR MITTED FOR LARIT

SW(2N–2)

SW(1)

SW(0)

03823-0-040

Figure 40. Equivalent RDAC Structure

PROGRAMMABLE RHEOSTAT OPERATION

If either the W-to-B or W-to-A terminal is used as a variable resistor, the unused terminal can be opened or shorted with W; such operation is called rheostat mode (see Figure 41). The resistance tolerance can range ± 20%.

Figure 41. Rheostat Mode Configuration

The nominal resistance of the AD5251/AD5252 has 64 or 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 6-or 8-bit data-word in the RDAC register is decoded to select one of the 64 or 256 settings. The wiper’s first connection starts at the B terminal for Data 0x00. This B-terminal connection has a wiper contact resistance, R of 75 Ω, regardless of the nominal resistance. The second connection (the AD5251 10 kΩ part) is the first tap point where

= 231 Ω (RWB = RAB/64 + RW = 156 Ω + 75 Ω) for Data

0x01, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at

= 9893 Ω. See Figure 40 for a simplified diagram of the

equivalent RDAC circuit.

The general equation that determines the digitally programmed output resistance between W and B, is

AD5251: R

AD5252: R

(D) = (D/64) × RAB + 75 Ω (1)

(D) = (D/256) × RAB + 75 Ω (2)

03823-0-041

Where D is the decimal equivalent data contained in the RDAC latch and R

Rev. 0 | Page 22 of 28

is the nominal end-to-end resistance.

AD5251/AD5252

(%)

100

PROGRAMMABLE POTENTIOMETER OPERATION

If all three terminals are used, the operation is called potentiometer mode and the most common configuration is the voltage divider operation (see Figure 43).

Figure 43. Potentiometer Mode Configuration

03823-0-043

Figure 42. AD5251 R

16 32 48 63

D (Code in Decimal)

(D) and RWB(D) vs. Decimal Code

Table 13. RWB vs. Codes; RAB = 10 kΩ, A Terminal = Open

D (DEC) RWB (Ω) Output State

63 9918 Full scale 32 5075 Midscale 1 231 1 LSB 0 75 Zero scale (wiper resistance)

Note that in the zero-scale condition, a 75 Ω finite wiper resistance is present. Care should be taken to limit the current conduction between W and B in this state to no more than ±5 mA continuous for a total resistance of 1 kΩ, or a ±20 mA pulse, to avoid degradation or possible destruction of the internal switch contact.

Similar to the mechanical potentiometer, the resistance of the RDAC between Wiper W and Terminal A also produces a digitally controlled complementary resistance, R

. When these

terminals are used, the B terminal can be opened. Setting the resistance value for R

starts at a maximum value of resistance

and decreases as the data loaded in the latch increases in value (see Figure 40). The general equation for this operation is

AD5251: R

(D) = [(64 – D)/64] × RAB + 75 Ω (3)

03823-0-042

If the wiper resistance is ignored, the transfer function is simply

AD5251:

AD5252:

V +×=

256

(5)

(6)

A more accurate calculation, which includes the wiper resistance effect, yields

Where 2

)(

= (7)

is the number of steps. Unlike in rheostat mode

operation where the tolerance is high, potentiometer mode operation yields an almost ratiometric function of D/2N with a relatively small error contributed by the R

terms. Therefore,

the tolerance effect is almost cancelled. Similarly, the ratiometric adjustment also reduces the temperature coefficient effect to 50 ppm/°C, except at low value codes where R

dominates.

Potentiometer mode operations include other applications such as op amp input, feedback resistor networks, and other voltage scaling applications. The A, W, and B terminals can in fact be input or output terminals, provided |V

|, |VW|, and |VB| do not

exceed VDD to VSS.

AD5252: R

(D) = [(256 – D)/256] × RAB + 75 Ω (4)

Table 14. RWA vs. Codes; AD5251, RAB=10 kΩ, B Terminal Open

D (DEC) RWA (Ω) Output State

63 231 Full scale 32 5075 Midscale 1 9918 1 LSB 0 10075 Zero scale

The typical distribution of RAB from channel-to-channel matches about ±0.15% within a given device. On the other hand, device-to-device matching is process-lot dependent with ±20% tolerance.

Rev. 0 | Page 23 of 28

AD5251/AD5252

APPLICATIONS

LCD PANEL V

Large LCD panels usually require an adjustable V centered around 6 V to 8 V with ±1 V swing and small steps adjustment. This example represents common DAC applications where the window of adjustments is small and centered at any level. High voltage and high resolution DACs can be used but it is far more cost-effective to use low voltage digital potentiometers with level shifting, such as the AD5251 or AD5252, to achieve the objective.

Assume a V

COM

step adjustment, as shown in Figure 44. The AD5252 can be configured in voltage divider mode with an op amp gain. With ±20% tolerance accounted for by the AD5252, this circuit can still be adjusted from 5 V to 7 V with an 8 mV/step in the worst case.

+5V

Figure 44. Apply 5 V Digital Potentiometer AD5251 in a 6 V ±1 V Application.

CURRENT-SENSING AMPLIFIER

The dual channel, synchronous update, and channel-to-channel resistance matching characteristics make the AD5251/AD5252 suitable for current sensing applications, such as LED brightness control. In the circuit shown in Figure 45, when RDAC1 and RDAC3 are programmed to the same settings, it can be shown that

V +−

As a result, the current through a sense resistor connected between V circuit makes it adaptable to systems that require different sensitivities. If the op amp has very low offset and low bias current, the major source of error comes from the digital potentiometer channel-to-channel resistance mismatch, which is typically

0.15%. The circuit accuracy is about 9 bits, which is adequate for LED control and other general purpose applications.

and V2 can be known. The programmability of this

ADJUSTMENT

COM

voltage

COM

voltage requirement of 6 V ±1 V with a ±20 mV

+14.4V

±1%

350k

AD5252

10k

±20%

18.5k

()

−

VVV

REF

+14.4V

V+

V–

2.2p

6V ± 1V

COM

(8)

03823-0-044

RDAC1

10kΩ

AD5252

RDAC3

10kΩ

+5V

V+

AD8628

V–

VREF

03823-0-045

SENSE

0.1kΩ

Figure 45. Current-Sensing Amplifier.

ADJUSTABLE HIGH POWER LED DRIVER

Figure 46 shows a circuit that can drive three to four high power LEDs. The ADP1610 is an adjustable boost regulator that provides adequate headroom and current for the LEDs. Because its FB pin voltage is 1.2 V, the digital potentiometer AD5252 and the op amp form an average gain of 12 feedback networks that servo the sensing and feedback voltages. As a result, the voltage across R AD5252’s setting. An adjustable LED current is

= (9)

LED

should be small to conserve power but large enough to

SET

limit the maximum LED current. R3 should also be used in parallel with the AD5252 to limit the LED current within an achievable range.

+5V

C2 10µF

is regulated around 0.1 V, depending on the

SET

13.5kΩ

PWM

100kΩ

390pF

ADP1610

/SD SW

COMP

SS RT GND

10nF

1.1kΩ

0.1µF

L1 10µF

+5V

V+

AD8591

V–

10kΩ

200Ω

10µF

AD5252

Figure 46. High Power Adjustable LED Driver

SET

0.25kΩ

100Ω

OUT

03823-0-046

Rev. 0 | Page 24 of 28

AD5251/AD5252

OUTLINE DIMENSIONS

5.10

5.00

4.90

1.05

1.00

0.80

4.50

4.40

4.30

PIN 1

0.65 BSC

0.15

0.05

COMPLIANT TO JEDEC STANDARDS MO-153AB-1

0.30

0.19

6.40 BSC

1.20 MAX

SEATING PLANE

0.20

0.09

COPLANARITY

0.10

8° 0°

0.75

0.60

0.45

Figure 47. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Model Step RAB (kΩ)

Range (°C)

Package Description

AD5251BRU1 64 1 −40 to +85 TSSOP RU-14 96 B1 AD5251BRU1-RL7 64 1 −40 to +85 TSSOP RU-14 1,000 B1 AD5251BRU10 64 10 −40 to +85 TSSOP RU-14 96 B10 AD5251BRU10-RL7 64 10 −40 to +85 TSSOP RU-14 1,000 B10 AD5251BRU50 64 50 −40 to +85 TSSOP RU-14 96 B50 AD5251BRU50-RL7 64 50 −40 to +85 TSSOP RU-14 1,000 B50 AD5251BRU100 64 100 −40 to +85 TSSOP RU-14 96 B100 AD5251BRU100-RL7 64 100 −40 to +85 TSSOP RU-14 1,000 B100 AD5251EVAL 64 10 Evaluation Board 1 AD5252BRU1 256 1 −40 to +85 TSSOP RU-14 96 B1 AD5252BRU1-RL7 256 1 −40 to +85 TSSOP RU-14 1,000 B1 AD5252BRU10 256 10 −40 to +85 TSSOP RU-14 96 B10 AD5252BRU10-RL7 256 10 −40 to +85 TSSOP RU-14 1,000 B10 AD5252BRU50 256 50 −40 to +85 TSSOP RU-14 96 B50 AD5252BRU50-RL7 256 50 −40 to +85 TSSOP RU-14 1,000 B50 AD5252BRU100 256 100 −40 to +85 TSSOP RU-14 96 B100 AD5252BRU100-RL7 256 100 −40 to +85 TSSOP RU-14 1,000 B100 AD5252EVAL 256 10 Evaluation Board 1

In the package marking, Line 1 shows the part number; Line 2 shows the branding information, such that B1 = 1 kΩ, B10 = 10 kΩ, B50 = 50 kΩ, and B100 = 100 kΩ;

Line 3 shows the date code in YYWW.

Package Option

Full Container Quantity

Branding

Rev.0 | Page 25 of 28

AD5251/AD5252

NOTES

Rev. 0 | Page 26 of 28

AD5251/AD5252

NOTES

Rev. 0 | Page 27 of 28

AD5251/AD5252

NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I

trademarks are the property of their respective owners.

C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

D03823-0-6/04(0)

Rev. 0 | Page 28 of 28

Datasheet AD5251 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNDAMENTAL BLOCK DIAGRAM

ELECTRICAL CHARACTERISTICS

INTERFACE TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTION

I2C INTERFACE TIMING DIAGRAM

I2C INTERFACE GENERAL DESCRIPTION

I2C INTERFACE DETAIL DESCRIPTION

RDAC/EEMEM WRITE

RDAC/EEMEM Read

RDAC/EEMEM Quick Commands

EEMEM Write-Acknowledge Polling

EEMEM Write Protection

I2C COMPATIBLE 2-WIRE SERIAL BUS

TYPICAL PERFORMANCE CHARACTERISTICS

OPERATIONAL OVERVIEW

LINEAR INCREMENT AND DECREMENT COMMANDS

±6 dB ADJUSTMENTS (DOUBLING/HALVING WIPER SETTING)

DIGITAL INPUT/OUTPUT CONFIGURATION

TERMINAL VOLTAGE OPERATION RANGE

MULTIPLE DEVICES ON ONE BUS

POWER-UP AND POWER-DOWN SEQUENCES

LAYOUT AND POWER SUPPLY BIASING

DIGITAL POTENTIOMETER OPERATION

PROGRAMMABLE RHEOSTAT OPERATION

PROGRAMMABLE POTENTIOMETER OPERATION

APPLICATIONS

CURRENT-SENSING AMPLIFIER

ADJUSTABLE HIGH POWER LED DRIVER

OUTLINE DIMENSIONS

ORDERING GUIDE