ANALOG DEVICES AD5251, AD5252 Service Manual

Dual 64-/256-Position I2C® Nonvolatile

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FEATURES

AD5251: Dual 64-position resolution AD5252: Dual 256-position resolution 1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Nonvolatile memory Power-on refreshed with EEMEM settings in 300 μs typ EEMEM rewrite time = 540 μs typ Resistance tolerance stored in nonvolatile memory 12 extra bytes in EEMEM for user-defined information

C-compatible serial interface

I Direct read/write access of RDAC Predefined linear increment/decrement commands Predefined ±6 dB step change commands Synchronous or asynchronous dual-channel update Wiper setting readback 4 MHz bandwidth—1 kΩ version Single supply 2.7 V to 5.5 V Dual supply ±2.25 V to ±2.75 V 2 slave address decoding bits allow operation of 4 devices 100-year typical data retention, T Operating temperature: –40°C to +85°C

APPLICATIONS

Mechanical potentiometer replacement General-purpose DAC replacement LCD panel V

COM

White LED brightness adjustment RF base station power amp bias control Programmable gain and offset control Programmable voltage-to-current conversion Programmable power supply Sensor calibrations

GENERAL DESCRIPTION

The AD5251/AD5252 are dual-channel, I2C, nonvolatile memory, digitally controlled potentiometers with 64/256 positions, respectively. These devices perform the same electronic adjustment functions as mechanical potentiometers, trimmers, and variable resistors. The parts’ versatile programmability allows multiple modes of operation, including read/write access in the RDAC and EEMEM registers, increment/decrement of resistance, resistance changes in ±6 dB scales, wiper setting readback, and extra EEMEM for storing user-defined information, such as memory data for other components, look-up table, or system identification information.

stores wiper setting w/write protection

and EEMEM registers

= 55°C

adjustment

Memory Digital Potentiometers

AD5251/AD5252

FUNCTIONAL BLOCK DIAGRAM

DGND

SCL SDA

AD0 AD1

I2C

SERIAL

INTERFACE

POWER-

ON RESET

The AD5251/AD5252 allow the host I any of the 64-/256-step wiper settings in the RDAC registers and store them in the EEMEM. Once the settings are stored, they are restored automatically to the RDAC registers at system power-on; the settings can also be restored dynamically.

The AD5251/AD5252 provide addi decrement, +6 dB step change, and –6 dB step change in synchronous or asynchronous channel update mode. The increment and decrement functions allow stepwise linear adjustments, with a ± 6 dB step change equivalent to doubling or halving the RDAC wiper setting. These functions are useful for steep-slope, nonlinear adjustments, such as white LED brightness and audio volume control.

The AD5251/AD5252 have a patented resistance-tolerance s

toring function that allows the user to access the EEMEM and obtain the absolute end-to-end resistance values of the RDACs for precision applications.

The AD5251/AD5252 are available in TSSOP-14 packages in 1 kΩ, 10 kΩ, 50 guaranteed to operate over the –40°C to +85°C extended industrial temperature range.

The terms nonvolatile memory and EEMEM are used interchangeably.

The terms digital potentiometer and RDAC are used interchangeably.

RDAC EEMEM

EEMEM

POWER-ON

REFRESH

DATA

CONTROL

RAB TOL

COMMAND

DECODE LOGIC

ADDRESS

DECODE LOGIC

CONTROL LOGIC

Figure 1.

RDAC1 REGIS-

TER

RDAC3 REGIS-

TER

AD5251/

AD5252

C controllers to write

tional increment,

kΩ, and 100 kΩ options. All parts are

RDAC1

RDAC3

A1 W1 B1

A3 W3 B3

03823-0-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5251/AD5252

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TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Electrical Characteristics ................................................................. 3

1 kΩ Version.................................................................................. 3

10 kΩ, 50 kΩ, 100 kΩ Versions .................................................. 5

Interface Timing Characteristics................................................ 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 10

C Interface..................................................................................... 14

C Interface General Description............................................ 14

C Interface Detail Description............................................... 15

C-Compatible 2-Wire Serial Bus ........................................... 20

Theory of Operation ...................................................................... 21

Linear Increment/Decrement Commands ............................. 21

±6 dB Adjustments (Doubling/Halving Wiper Setting) ....... 21

Digital Input/Output Configuration........................................ 22

Multiple Devices on One Bus................................................... 22

Terminal Voltage Operation Range......................................... 22

Power-Up and Power-Down Sequences.................................. 22

Layout and Power Supply Biasing............................................ 23

Digital Potentiometer Operation............................................. 23

Programmable Rheostat Operation......................................... 23

Programmable Potentiometer Operation ............................... 24

Applications..................................................................................... 25

LCD Panel V

Current-Sensing Amplifier ....................................................... 25

Adjustable High Power LED Driver ........................................ 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 27

Adjustment.................................................... 25

COM

REVISION HISTORY

9/05—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Change to Figure 6 ......................................................................... 10

Changes to Figure 28...................................................................... 15

Changes to Figure 29...................................................................... 17

Changes to RDAC/EEMEM Quick Commands Section .......... 18

Changes to EEMEM Write Protection Section........................... 18

Changes to Figure 37...................................................................... 22

Deleted Table 13 and Table 14 ......................................................23

Change to Figure 42 ....................................................................... 24

Change to Figure 46 ....................................................................... 25

Changes to Ordering Guide.......................................................... 27

6/04—Revision 0: Initial Version

Rev. A | Page 2 of 28

AD5251/AD5252

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ELECTRICAL CHARACTERISTICS

1 kΩ VERSION

VDD = 3 V ± 10% or 5 V ± 10%, VSS = 0 V or VDD/VSS = ±2.5 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ DC CHARACTERISTICS—

RHEOSTAT MODE Resolution N AD5251 6 Bits AD5252 8 Bits Resistor Differential Nonlinearity R R R Resistor Nonlinearity

R R R Nominal Resistor Tolerance ΔRAB/RAB T

R-DNL RWB, RWA = NC, VDD = 5.5 V, AD5251 –0.5 ±0.2 +0.5 LSB

, RWA = NC, VDD = 5.5 V, AD5252 –1.00 ±0.25 +1.00 LSB

, RWA = NC, VDD = 2.7 V, AD5251 –0.75 ±0.30 +0.75 LSB

, RWA = NC, VDD = 2.7 V, AD5252 –1.5 ±0.3 +1.5 LSB

R-INL RWB, RWA = NC, VDD = 5.5 V, AD5251 –0.5 ±0.2 +0.5 LSB

, RWA = NC, VDD = 5.5 V, AD5252 –2.0 ±0.5 +2.0 LSB

, RWA = NC, VDD = 2.7 V, AD5251 –1.0 +2.5 +4.0 LSB

, RWA = NC, VDD = 2.7 V, AD5252 –2 +9 +14 LSB

= 25°C –30 +30 %

Resistance Temperature Coefficient (ΔRAB/RAB) × 106/ΔT 650 ppm/°C Wiper Resistance RW I I Channel-Resistance Matching ΔR

DC CHARACTERISTICS—

/ΔR

AB1

0.15 %

AB3

= 1 V/R, VDD = 5 V 75 130 Ω

= 1 V/R, VDD = 3 V 200 300 Ω

POTENTIOMETER DIVIDER MODE Differential Nonlinearity

DNL AD5251 –0.5 ±0.1 +0.5 LSB AD5252 –1.00 ±0.25 +1.00 LSB Integral Nonlinearity

INL AD5251 –0.5 ±0.2 +0.5 LSB AD5252 –2.0 ±0.5 +2.0 LSB Voltage Divider Tempco (ΔVW/VW) × 106/ΔT Code = half scale 25 ppm/°C Full-Scale Error V

Code = full scale, VDD = 5.5 V, AD5251 –5 –3 0 LSB

WFSE

Code = full scale, VDD = 5.5 V, AD5252 –16 –11 0 LSB Code = full scale, VDD = 2.7 V, AD5251 −6 –4 0 LSB Code = full scale, VDD = 2.7 V, AD5252 –23 –16 0 LSB Zero-Scale Error V

Code = zero scale, VDD = 5.5 V, AD5251 0 3 5 LSB

WZSE

Code = zero scale, VDD = 5.5 V, AD5252 0 11 16 LSB Code = zero scale, VDD = 2.7 V, AD5251 0 4 6 LSB Code = zero scale, VDD = 2.7 V, AD5252 0 15 20 LSB

RESISTOR TERMINALS

Voltage Range Capacitance5 A, B CA, CB

Capacitance5 W CW

Common-Mode Leakage Current ICM V

VA, VB, VW V

f = 1 kHz, measured to GND,

ode = half scale

c f = 1 kHz, measured to GND,

ode = half scale

= VB = VDD/2 0.01 1 μA

VDD V

85 pF

95 pF

Max Unit

Rev. A | Page 3 of 28

AD5251/AD5252

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Parameter Symbol Conditions Min Typ

Max Unit

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V V Input Logic Low VIL V Output Logic High (SDA) VOH R Output Logic Low (SDA) VOL R

WP Leakage Current

= 5 V, VSS = 0 V 2.4 V

= 2.7 V/0 V or VDD/VSS = ± 2.5 V 2.1 V

DD/VSS

= 5 V, VSS = 0 V 0.8 V

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9 V

PULL-UP

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 0.4 V

PULL-UP

= VDD

5 μA A0 Leakage Current IA0 A0 = GND 3 μA Input Leakage Current

(Other than WP

Input Capacitance

and A0)

II V

CI 5 pF

= 0 V or VDD ±1 μA

POWER SUPPLIES

Single-Supply Power Range VDD V

= 0 V 2.7 5.5 V

Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V Positive Supply Current IDD V Negative Supply Current ISS

EEMEM Data Storing Mode Current I EEMEM Data Restoring Mode

Power Dissipation

Current

DD_STORE

DD_RESTORE

DISS

= VDD or VIL = GND 5 15 μA

= VDD or VIL = GND, VDD = 2.5 V,

= –2.5 V

= VDD or VIL = GND 35 mA

= VDD or VIL = GND 2.5 mA

= VDD = 5 V or VIL = GND 0.075 mW

–5 –15 μA

Power Supply Sensitivity PSS ΔVDD = 5 V ± 10% −0.025 +0.010 +0.025 %/% ΔVDD = 3 V ± 10% –0.04 +0.02 +0.04 %/%

DYNAMIC CHARACTERISTICS

5, 8

Bandwidth –3 dB BW RAB = 1 kΩ 4 MHz Total Harmonic Distortion THD VA = 1 V rms, VB = 0 V, f = 1 kHz 0.05 % VW Settling Time tS V Resistor Noise Voltage e

N_WB

= VDD, VB = 0 V 0.2 μs

= 500 Ω, f = 1 kHz

nV/√Hz

(thermal noise only)

Digital Crosstalk CT

= VDD, VB = 0 V, measure VW with

–80 dB

adjacent RDAC making full-scale change

Analog Coupling CAT

Typical values represent average readings at 25°C and VDD = 5 V.

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the

relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at V

2.7 V, IW = VDD/R for both VDD = 3 V and VDD = 5 V.

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.

Guaranteed by design and not subject to production test.

Command 0 NOP should be activated after Command 1 to minimize I

is calculated from IDD × VDD = 5 V.

DISS

All dynamic characteristics use VDD = 5 V.

Signal input at A1 and measure the output a

current consumption.

DD_READ

t W3, f = 1 kHz

–72 dB

Rev. A | Page 4 of 28

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10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = +3 V ± 10% or +5 V ± 10%, VSS = 0 V or VDD/VSS = ± 2.5 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +85°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ DC CHARACTERISTICS—

RHEOSTAT MODE Resolution N AD5251 6 Bits AD5252 8 Bits Resistor Differential

Nonlinearity

R Resistor Nonlinearity

R Nominal Resistor Tolerance ΔRAB/RAB T Resistance Temperature

R-DNL RWB, RWA = NC, AD5251 −0.75 ±0.10 +0.75 LSB

, RWA = NC, AD5252 −1.00 ±0.25 +1.00 LSB

R-INL RWB, RWA = NC, AD5251 −0.75 ±0.25 +0.75 LSB

, RWA = NC, AD5252 −2.5 ±1.0 +2.5 LSB

= 25°C −20 +20 %

(ΔR

) × 106/ΔT 650 ppm/°C

AB/RAB

Coefficient Wiper Resistance RW I I Channel-Resistance Matching ΔR

AB1

/ΔR

AB2

DC CHARACTERISTICS—

= 1 V/R, VDD = 5 V 75 130 Ω

= 1 V/R, VDD = 3 V 200 300 Ω

= 10 kΩ, 50 kΩ 0.15 %

= 100 kΩ 0.05 %

POTENTIOMETER DIVIDER MODE Differential Nonlinearity

DNL AD5251 −0.5 ±0.1 +0.5 LSB AD5252 −1.0 ±0.3 +1.0 LSB Integral Nonlinearity

INL AD5251 −0.50 ±0.15 +0.50 LSB AD5252 −1.5 ±0.5 +1.5 LSB Voltage Divider

(ΔV

) × 106/ΔT Code = half scale 15 ppm/°C

W/VW

Temperature Coefficient

Full-Scale Error V

Code = full scale, AD5251 −1.0 −0.3 0 LSB

WFSE

Code = full scale, AD5252 −3 −1 0 LSB Zero-Scale Error V

Code = zero scale, AD5251 0 0.3 1.0 LSB

WZSE

Code = zero scale, AD5252 0 1.2 3.0 LSB

RESISTOR TERMINALS

Voltage Range Capacitance5 A, B CA, CB

Capacitance5 W CW

Common-Mode Leakage Current ICM V

VA, VB, VW V

f = 1 kHz, measured to GND,

ode = half scale

c f = 1 kHz, measured to GND,

ode = half scale

= VB = VDD/2 0.01 1.00 μA

VDD V

85 pF

95 pF

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V V Input Logic Low VIL V V Output Logic High (SDA) VOH R Output Logic Low (SDA) VOL R

WP Leakage Current

= 5 V, VSS = 0 V 2.4 V

= +2.7 V/0 V or VDD/VSS = ±2.5 V 2.1 V

DD/VSS

= 5 V, VSS = 0 V 0.8 V

= +2.7 V/0 V or VDD/VSS = ±2.5 V 0.6 V

DD/VSS

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9 V

PULL-UP

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 0.4 V

PULL-UP

= VDD

5 μA A0 Leakage Current IA0 A0 = GND 3 μA Input Leakage Current

(Other than WP

and A0)

= 0 V or VDD ±1 μA

Input Capacitance5 CI 5 pF

Max Unit

Rev. A | Page 5 of 28

AD5251/AD5252

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Parameter Symbol Conditions Min Typ

Max Unit

POWER SUPPLIES

Single-Supply Power Range VDD V

= 0 V 2.7 5.5 V

Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V Positive Supply Current IDD V Negative Supply Current ISS

EEMEM Data Storing Mode

DD_STORE

= VDD or VIL = GND 5 15 μA

= VDD or VIL = GND, VDD = 2.5 V,

= −2.5 V

= VDD or VIL = GND, TA = 0°C to 85°C 35 mA

−5 −15 μA

Current

EEMEM Data Restoring Mode

Current

Power Dissipation7 P

DD_RESTORE

DISS

= VDD or VIL = GND, TA = 0°C to 85°C 2.5 mA

= VDD = 5 V or VIL = GND 0.075 mW

Power Supply Sensitivity PSS ΔVDD = 5 V ± 10% −0.005 +0.002 +0.005 %/% ΔVDD = 3 V ± 10% −0.010 +0.002 +0.010 %/%

DYNAMIC CHARACTERISTICS

5, 8

–3 dB Bandwidth BW RAB = 10 kΩ/50 kΩ/100 kΩ 400/80/40 kHz Total Harmonic Distortion THDW V VW Settling Time tS

Resistor Noise Voltage e

N_WB

= 1 V rms, VB = 0 V, f = 1 kHz 0.05 %

= VDD, VB = 0 V,

= 10 kΩ/50 kΩ/100 kΩ

= 10 kΩ/50 kΩ/100 kΩ,

1.5/7/14 μs

9/20/29

nV/√Hz code = midscale, f = 1 kHz (thermal noise only)

Digital Crosstalk CT

= VDD, VB = 0 V, measure VW with

−80 dB adjacent RDAC making full-scale change

Analog Coupling CAT

Typical values represent average readings at 25°C and VDD = 5 V.

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the

relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at VDD = 2.7 V, IW = VDD/R for both VDD = 3 V and VDD = 5 V.

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.

Guaranteed by design and not subject to production test.

Command 0 NOP should be activated after Command 1 to minimize I

is calculated from IDD × VDD = 5 V.

DISS

All dynamic characteristics use VDD = 5 V.

Signal input at A1 and measure output a

DD_READ

t W3, f = 1 kHz

current consumption.

−72 dB

Rev. A | Page 6 of 28

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INTERFACE TIMING CHARACTERISTICS

All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V

Table 3. Interface Timing and EEMEM Reliability Characteristics (All Parts)

Parameter Symbol Conditions Min Typ Max Unit

INTERFACE TIMING

SCL Clock Frequency f t

Bus-Free Time Between Stop and Start t1 1.3 μs

BUF

Hold Time (Repeated Start) t2

HD;STA

Low Period of SCL Clock t3 1.3

LOW

High Period of SCL Clock t4 0.6

HIGH

Set-up Time for Start Condition t5 0.6

SU;STA

Data Hold Time t6 0 0.9 μs

HD;DAT

Data Set-up Time t7 100

SU;DAT

tF Fall Time of Both SDA and SCL Signals t8 tR Rise Time of Both SDA and SCL Signals t9 t

Set-up Time for Stop Condition t10 0.6 μs

SU;STO

EEMEM Data Storing Time t EEMEM Data Restoring Time at Power-On

EEMEM Data Restoring Time upon Restore

Command or Reset Operation

EEMEM Data Rewritable Time (Delay Time

After Power-On or Reset Before EEMEM Can Be Written)

FLASH/EE MEMORY RELIABILITY

Endurance Data Retention

Guaranteed by design; not subject to production test. See Figure 23 for location of measured values.

During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM data restoring time, whereas RDAC3 has the longest.

Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.

Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates

with junction temperature in Flash/EE memory.

= 3 V and 5 V.

SCL

EEMEM_STORE

EEMEM_RESTORE1

EEMEM_RESTORE2

EEMEM_REWRITE

100 k cycles 100 Years

400 kHz

After this period, the first clock pulse is

ated.

gener

0.6

300 ns 300 ns

μs

μs μs μs

26 ms

rise time dependent. Measure

without decoupling capacitors at V and V

300 μs

VDD = 5 V. 300 μs

540 μs

Rev. A | Page 7 of 28

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V, +7 V VSS to GND +0.3 V, −7 V VDD to VSS 7 V VA, VB, VW to GND VSS, VDD Maximum Current

IWB, IWA Pulsed ±20 mA IWB Continuous (RWB ≤ 1 kΩ, A Open) IWA Continuous (RWA ≤ 1 kΩ, B Open)1 ±5 mA IAB Continuous

= 1 kΩ/10 kΩ/50 kΩ/100 kΩ)1

Digital Inputs and Output Voltage to GND 0 V, 7 V Operating Temperature Range −40°C to +85°C Maximum Junction Temperature (T Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C TSSOP-14 Thermal Resistance2 θJA 136°C/W

Maximum terminal current is bound by the maximum applied voltage across

any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. VDD = 5 V.

Package power dissipation = (T

− TA)/θJA.

JMAX

±5 mA

±5 mA/±500 μA/ ±100 μA/±50 μA

) 150°C

JMAX

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 8 of 28

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V AD0

WP W1

B1 A1

SDA

AD5251/

AD5252

TOP VIEW

(Not to Scale)

AD1

DGND

SCL

03823-0-002

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 VDD

Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply, where

VDD – VSS ≤ 5.5 V. VDD must be able to source 35 mA for 26 ms when storing data to EEMEM. 2 AD0 I2C Device Address 0. AD0 and AD1 allow four AD5251/AD5252 devices to be addressed. 3

WP 4 W1 Wiper Terminal of RDAC1. VSS ≤ VW1 ≤ VDD. 5 B1 B Terminal of RDAC1. VSS ≤ VB1 ≤ VDD. 6 A1 A Terminal of RDAC1. VSS ≤ VA1 ≤ VDD. 7 SDA

Write Protect, Active Low. VWP ≤ VDD + 0.3 V.

Serial Data Input/Output Pin. Shifts in one bit a

t a time upon positive clock edges. MSB loaded first.

Open-drain MOSFET requires pull-up resistor.

8 VSS

Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where V V

9 SCL

Serial Input Register Clock Pin. Shifts in one bit at a time upon positiv

is used in dual supply, VSS must be able to sink 35 mA for 26 ms when storing data to EEMEM.

e clock edges. V

– VSS ≤ +5.5 V. If

SCL

Pull-up resistor is recommended for SCL to ensure minimum power. 10 DGND Digital Ground. Connect to system analog ground at a single point. 11 AD1 I2C Device Address 1. AD0 and AD1 allow four AD5251/AD5252 devices to be addressed. 12 A3 A Terminal of RDAC3. VSS ≤ VA3 ≤ VDD. 13 B3 B Terminal of RDAC3. VSS ≤ VB3 ≤ VDD. 14 W3 Wiper Terminal of RDAC3. VSS ≤ VW3 ≤ VDD.

For quad-channel device software compatibility, the dual potentiometers in the parts are designated as RDAC1 and RDAC3.

≤ (VDD + 0.3 V).

Rev. A | Page 9 of 28

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TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

R-INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

TA= –40°C, +25°C, +85°C, +125°C

CODE (Decimal)

Figure 3. R-INL vs. Code

03823-0-015

1.0

0.8

0.6

0.4

0.2

–0.2

DNL (LSB)

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

= –40°C, +25°C, +85°C, +125°C

CODE (Decimal)

Figure 6. DNL vs. Code

03823-0-018

1.0

0.8

0.6

0.4

0.2

R-DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

TA = –40°C, +25°C, +85°C, +125°C

CODE (Decimal)

Figure 4. R-DNL vs. Code

1.0

0.8

0.6

0.4

0.2

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

= –40°C, +25°C, +85°C, +125°C

CODE (Decimal)

Figure 5. INL vs. Code

03823-0-016

03823-0-017

(μA)

–2

–4

–6

–8

–10

–40 –20 0 20 40 60 80 100 120

IDD @ VDD= 5.5V

IDD @ VDD= 2.7V

ISS @ VDD= 2.7V, VSS= –2.7V

TEMPERATURE (°C)

Figure 7. Supply Current vs. Temperature

0.1

(mA)

0.01

VDD= 2.7V

0.001

0.0001 0123456

DIGITAL INPUT VOLTAGE (V)

Figure 8. Supply Current vs. Digital Input Voltage, T

VDD= 5.5V

= 25°C

03823-0-019

03823-0-020

Rev. A | Page 10 of 28

AD5251/AD5252

www.BDTIC.com/ADI

240 220 200 180 160 140

(Ω)

120

100

80 60 40 20

10 23456

VDD= 2.7V

= 25°C

BIAS

(V)

Figure 9. Wiper Resistance vs. V

VDD= 5.5V

= 25°C

DATA = 0x00

BIAS

03823-0-021

VDD= 5V T

= –40°C/+85°C

POTENTIOMETER MODE TEMPCO (ppm/°C)

0 32 64 96 128 160 192 224 256

CODE (Decimal)

= V

VB= 0V

Figure 12. AD5252 Potentiometer Mode Tempco ∆V

/∆T vs. Code

03823-0-024

(%)

ΔR

–2

–4

–6

–40 –20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 10. Change of R

RHEOSTAT MODE TEMPCO (ppm/°C)

0 32 64 96 128 160 192 224 256

CODE (Decimal)

Figure 11. AD5252 Rheostat Mode Tempco ∆R

vs. Temperature

VDD= 5V T

= –40°C/+85°C

= V

VB= 0V

/∆T vs. Code

03823-0-022

03823-0-023

–6

–12

–18

–24

–30

0x08

GAIN (dB)

–36

–42

–48

–54

–60

0x04

0x02

1k 10k10 100 100k 1M 10M

FREQUENCY (Hz)

0x40 0x20

0x10

0x01

Figure 13. AD5252 Gain vs. Frequency vs. Code, R

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

0xFF

0x80

0x40 0x20 0x10

0x08 0x04

0x01 0x00

0x02

1k 10k10 100 100k 1M 10M

FREQUENCY (Hz)

Figure 14. AD5252 Gain vs. Frequency vs. Code, R

0xFF

0x80

0x00

= 1 kΩ, TA = 25°C

= 10 kΩ , TA = 25°C

03823-0-025

03823-0-026

Rev. A | Page 11 of 28

AD5251/AD5252

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–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

Figure 15. AD5252 Gain vs. Frequency vs. Code, R

0xFF 0x80

0x40 0x20

0x10

0x08 0x04

0x01 0x00

0x02

1k 10k10 100 100k 1M 10M

FREQUENCY (Hz)

= 50 kΩ , TA = 25°C

03823-0-026

1.2

1.0

0.8

0.6

(mA)

0.4

0.2

1 10010 1k 10k 100k 1M 10M

CLOCK FREQUENCY (Hz)

TA= 25°C

VDD= 5.5V

VDD= 2.7V

Figure 18. Supply Current vs. Digital Input Clock Frequency

03823-0-030

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

Figure 16. AD5252 Gain vs. Frequency vs. Code, R

100

(Ω)

–20

ΔR

–40

–60

–80

–100

0 32 64 96 128 160 192 224 256

Figure 17. AD5252 ΔR

0x80

0x40

0x20

0x10

0x08

0x04 0x02 0x01

1k 10k10 100 100k 1M 10M

FREQUENCY (Hz)

100kΩ

10kΩ

1kΩ

50kΩ

CODE (Decimal)

vs. Code, TA = 25°C

0xFF

0x00

= 100 kΩ , TA = 25°C

VDD = 5.5V

03823-0-028

03823-0-029

CLK

DIGITAL FEEDTHROUGH

400ns/DIV

Figure 19. Clock Feedthrough and Midscale Transition Glitch

(NO DECOUPLING CAPS)

WB1

(0x3F STORED IN EEMEM)

WB3

(0x3F STORED IN EEMEM)

MIDSCALE PRESET

Figure 20. t

RESTORE RDAC1 SETTING TO 0x3F

EEMEM_RESTORE

RESTORE RDAC3 SETTING TO 0x3F

VDD = VA1 = VA3 = 3.3V GND = VB1 = VB3

of RDAC0 and RDAC3

= 5V

03823-0-031

03823-0-032

Rev. A | Page 12 of 28

AD5251/AD5252

www.BDTIC.com/ADI

(mA)

WB_MAX

RAB= 10kΩ

RAB= 50kΩ

RAB= 100kΩ

0 8 16 24 32 40 48 56 64

THEORETICAL I

RAB= 1kΩ

CODE (Decimal)

Figure 21. AD5251 I

vs. Code Figure 22. AD5252 I

WB_MAX

VA= VB= OPEN T

=25°C

03823-0-033

(mA)

WB_MAX

THEORETICAL I

0 32 64 96 128 160 192 224 256

RAB= 10kΩ

RAB= 50kΩ

RAB= 100kΩ

RAB= 1kΩ

CODE (Decimal)

WB_MAX

VA= VB= OPEN T

=25°C

vs. Code

03823-0-034

Rev. A | Page 13 of 28

AD5251/AD5252

www.BDTIC.com/ADI

I2C INTERFACE

SCL

PS S

I2C INTERFACE GENERAL DESCRIPTION

FROM MASTER TO SLAVE FROM SLAVE TO MASTER

S = START CONDITION P = STOP CONDITION A = ACKNOWLEDGE (SDA LOW) A = NOT ACKNOWLEDGE (SDA HIGH) R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW

SLAVE ADDRESS

(7-BIT)

R/W A/AS

0 WRITE

Figure 23. I

Figure 24. I

C Interface Timing Diagram

INSTRUCTIONS

C—Master Writing Data to Slave

(8-BIT)

DATA TRANSFERRED

(N BYTES + ACKNOWLEDGE)

03823-0-004

03823-0-003

DATA

(8-BIT)

SLAVE ADDRESS

(7-BIT)

R/W AS

1 READ

Figure 25. I

DATA

(8-BIT)

(N BYTES + ACKNOWLEDGE)

C—Master Reading Data from Slave

DATA TRANSFERRED

DATA

(8-BIT)

03823-0-005

SLAVE ADDRESS

(7-BIT)

R/W R/WS

READ OR WRITE (N BYTES +

DATA

ACKNOWLEDGE)

Figure 26. I

A/A

SLAVE ADDRESS

REPEATED START READ

DIRECTION OF TRANSFER MAY

C—Combined Write/Read

OR WRITE

CHANGE AT THIS POINT

DATA

(N BYTES +

ACKNOWLEDGE)

A/A

03823-0-006

Rev. A | Page 14 of 28

AD5251/AD5252

www.BDTIC.com/ADI

I2C INTERFACE DETAIL DESCRIPTION

FROM MASTER TO SLAVE FROM SLAVE TO MASTER

S = START CONDITION P = STOP CONDITION A = ACKNOWLEDGE (SDA LOW) A = NOT ACKNOWLEDGE (SDA HIGH) R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW EE/RDAC = EEMEM REGISTER, LOGIC HIGH/RDAC REGISTER, LOGIC LOW A4, A3, A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES

S 0 1 0 1 1 A

0 A A4A3A2A1A0A PDATA0

CMD/

REG

EE/

RDAC

SLAVE ADDRESS INSTRUCTIONS

0 WRITE

0 REG

AND ADDRESS

(1 BYTE +

ACKNOWLEDGE)

03823-0-007

Figure 27. Single Write Mode

S 0 1 0 1 1 A

RDAC SLAVE ADDRESS RDAC INSTRUCTIONS

0 A A4A3A2A1A

0 WRITE

CMD/

REG

0 REG

EE/

RDAC

AND ADDRESS

Figure 28. Consecutive Write Mode

RDAC3

DATA

(N BYTES +

ACKNOWLEDGE)

DATA

PA ARDAC1

03823-0-008

Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/

A4 A3 A2 A1 A0

RDAC Data Byte Description

= 0, CMD/

REG

= 0, EE/

RDAC

= 0)

0 0 0 0 0 Reserved 0 0 0 0 1 RDAC1 6-/8-bit wiper setting (2 MSB of AD5251 are X) 0 0 0 1 0 Reserved 0 0 0 1 1 RDAC3 0 0 1 0 0 Reserved : : : : : : : : : : : :

6-/8-bit wiper setting (2 MSB of AD5251 are X)

0 1 1 1 1 Reserved

Rev. A | Page 15 of 28

AD5251/AD5252

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RDAC/EEMEM Write

Setting the wiper position requires an RDAC write operation. The single write operation is shown in Figure 27, and the co

nsecutive write operation is shown in Figure 28. In the nsecutive write operation, if the

co address starts at 00001, the first data byte goes to RDAC1 and

the second data byte goes to RDAC3. The RDAC address is shown in

While the RDAC wiper setting is controlled by a specific RDAC

egister, each RDAC register corresponds to a specific EEMEM

r location, which provides nonvolatile wiper storage functionality. The addresses are shown in wr

There are 12 nonvolatile memory locations: EEMEM4 to EEMEM15. U such as memory data for other components, look-up tables, or system identification information.

In a write operation to the EEMEM registers, the device disables th polling is required to determine the completion of the write cycle. See the

Tabl e 6.

Tabl e 7 . The single and consecutive

ite operations also apply to EEMEM write operations.

sers can store a total of 12 bytes of information,

C interface during the internal write cycle. Acknowledge

e I

EEMEM Write-Acknowledge Polling section.

RDAC/EEMEM Read

The AD5251/AD5252 provide two different RDAC or EEMEM read operations. For example, Figure 29 shows the method of

eading the RDAC0 to RDAC3 contents without specifying the

r address, assuming Address RDAC0 was already selected in the previous operation. If an RDAC_N address other than RDAC0 was previously selected, readback starts with Address N, followed by N + 1, and so on.

Figure 30 illustrates a random RDAC or EEMEM read

peration. This operation allows users to specify which RDAC

o or EEMEM register is read by issuing a dummy write command to change the RDAC address pointer and then proceeding with the RDAC read operation at the new address location.

is selected and the

RDAC

Table 7. Addresses for Writing (Storing) RDAC Settings

User-Defined Data to EEMEM Registers

and (R/

= 0, CMD/

A4 A3 A2 A1 A0

0 0 0 0 0 Reserved 0 0 0 0 1 Store RDAC1 setting to EEMEM1 0 0 0 1 0 Reserved 0 0 0 1 1 Store RDAC3 setting to EEMEM3 0 0 1 0 0 Store user data to EEMEM4 0 0 1 0 1 Store user data to EEMEM5 0 0 1 1 0 Store user data to EEMEM6 0 0 1 1 1 Store user data to EEMEM7 0 1 0 0 0 Store user data to EEMEM8 0 1 0 0 1 Store user data to EEMEM9 0 1 0 1 0 Store user data to EEMEM10 0 1 0 1 1 Store user data to EEMEM11 0 1 1 0 0 Store user data to EEMEM12 0 1 1 0 1 Store user data to EEMEM13 0 1 1 1 0 Store user data to EEMEM14 0 1 1 1 1 Store user data to EEMEM15

Table 8. Addresses for Reading (Restoring) RDAC Settings and User (R/

A4 A3 A2 A1 A0

0 0 0 0 0 Reserved 0 0 0 0 1 Read RDAC1 setting from EEMEM1 0 0 0 1 0 Reserved 0 0 0 1 1 Read RDAC3 setting from EEMEM3 0 0 1 0 0 Read user data from EEMEM4 0 0 1 0 1 Read user data from EEMEM5 0 0 1 1 0 Read user data from EEMEM6 0 0 1 1 1 Read user data from EEMEM7 0 1 0 0 0 Read user data from EEMEM8 0 1 0 0 1 Read user data from EEMEM9 0 1 0 1 0 Read user data from EEMEM10 0 1 0 1 1 Read user data from EEMEM11 0 1 1 0 0 Read user data from EEMEM12 0 1 1 0 1 Read user data from EEMEM13 0 1 1 1 0 Read user data from EEMEM14 0 1 1 1 1 Read user data from EEMEM15

Users can store any of the 64 RDAC settings directly to the EEMEM for AD5251,

or any of the 256 RDAC settings directly to the EEMEM for the AD5252. This is not limited to current RDAC wiper setting

Data from EEMEM

= 1, CMD/

REG

= 0, EE/

RDAC

Data Byte Description

RDAC

Data Byte Description

= 1)

Rev. A | Page 16 of 28

AD5251/AD5252

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S 0 1 0 1 1 A

SLAVE ADDRESS (N BYTES + ACKNOWLEDGE)

1 A PARDAC1

1 READ

EEMEM OR REGISTER DATA

Figure 29. RDAC Current Read (Restricted to Previo

DATA

RDAC3

EEMEM OR REGISTER DATA

usly Selected Address Stored in the Register)

03823-0-009

A0A

0 WRITE

ADDRESS

REPEATED START 1 READ

SLAVE ADDRESSINSTRUCTION AND

Figure 30. RDAC or EEMEM Random Read

A1S

RDAC OR

EEMEM DATA

(N BYTES + ACKNOWLEDGE)

A/A

PS SLAVE ADDRESS

03823-0-010

FROM MASTER TO SLAVE FROM SLAVE TO MASTER

S = START CONDITION P = STOP CONDITION A = ACKNOWLEDGE (SDA LOW) A = NOT ACKNOWLEDGE (SDA HIGH) AD1, AD0 = I R/W = READ ENABLE BIT, LOGIC HIGH/WRITE ENABLE BIT, LOGIC LOW CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW C3, C2, C1, C0 = COMMAND BITS A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES

S 0 1 0 1 1 A

C DEVICE ADDRESS BITS; MUST MATCH WITH THE LOGIC STATES AT PINS AD1, AD0

CMD/

0 A C3C2C1C0A2A1A0A P

REG

RDAC SLAVE ADDRESS

0 WRITE

1 CMD

03823-0-011

Figure 31. RDAC Quick Command Write (Dummy Write)

Rev. A | Page 17 of 28

AD5251/AD5252

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RDAC/EEMEM Quick Commands

The AD5251/AD5252 feature 12 quick commands that facilitate easy manipulation of RDAC wiper settings and provide RDACto-EEMEM storing and restoring functions. The command format is shown in

shown in Ta b le 9 .

are

Figure 31, and the command descriptions

When using a quick command, issuing a third byte is not

eded, but is allowed. The quick commands reset and store

ne RDAC to EEMEM require acknowledge polling to determine whether the command has finished executing.

RAB Tolerance Stored in Read-Only Memory

The AD5251/AD5252 feature patented RAB tolerances storage in the nonvolatile memory. The tolerance of each channel is stored in the memory during the factory production and can be read by users at any time. The knowledge of the stored tolerance, which is the average of R users to predict R

over all codes (see Figure 16), allows

accurately. This feature is valuable for precision, rheostat mode, and open-loop applications in which knowledge of absolute resistance is critical.

The stored tolerances reside in the read-only memory and are

xpressed as percentages. Each tolerance is stored in two memory

e locations (see Table 1 0 ). The tolerance data is expressed in sign ma

gnitude binary format stored in two bytes; an example is shown

Figure 32. For the first byte in Register N, the MSB is

esignated for the sign (0 = + and 1 = –) and the 7 LSB is

d designated for the integer portion of the tolerance. For the second byte in Register N + 1, all eight data bits are designated

Table 9. RDAC-to-EEMEM Interface and RDAC Op

C3 C2 C1 C0 Command Description

0 0 0 0 NOP 0 0 0 1 Restore EEMEM (A1, A0) to RDAC (A1, A0) 0 0 1 0 Store RDAC (A1, A0) to EEMEM (A1, A0) 0 0 1 1 Decrement RDAC (A1, A0) 6 dB 0 1 0 0 Decrement all RDACs 6 dB 0 1 0 1 Decrement RDAC (A1, A0) one step 0 1 1 0 Decrement all RDACs one step 0 1 1 1 Reset: restore EEMEMs to all RDACs 1 0 0 0 Increment RDACs (A1, A0) 6 dB 1 0 0 1 Increment all RDACs 6 dB 1 0 1 0 Increment RDACs (A1, A0) one step 1 0 1 1 Increment all RDACs one step 1 1 0 0 Reserved : : : : : : : : : : 1 1 1 1 Reserved

This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state.

eration Quick Command Bits (CMD/

for the decimal portion of tolerance. As shown in Figure 32, for example, if the rated R

is 10 kΩ and the data

readback from Address 11000 shows 0001 1100 and Address 11001 shows 0000 1111, then RDAC0 tolerance can be calculated as

MSB: 0 = +

ext 7 MSB: 001 1100 = 28

N 8 LSB: 0000 1111 = 15 × 2

–8

= 0.06 Tolerance = 28.06% and, therefore, R

AB_ACTUAL

= 12.806 kΩ

EEMEM Write-Acknowledge Polling

After each write operation to the EEMEM registers, an internal write cycle begins. The I

C interface of the device is disabled. To determine if the internal write cycle is complete and the I interface is enabled, interface polling can be executed. I interface polling can be conducted by sending a start condition, followed by the slave address and the write bit. If the I interface responds with an ACK, the write cycle is complete and the interface is ready to proceed with further operations. Other-

wise, I

C interface polling can be repeated until it succeeds.

Command 2 and Command 7 also require acknowledge polling.

EEMEM Write Protection

Setting the WP pin to logic low after EEMEM programming protects the memory and RDAC registers from future write

operations. In this mode, the EEMEM and RDAC read operations function as normal.

= 1, A2 = 0)

REG

Tabl e 10 and

Rev. A | Page 18 of 28

AD5251/AD5252

www.BDTIC.com/ADI

Table 10. Address Table for Reading Tolerance (CMD/

A4 A3 A2 A1 A0

Data Byte Description

0 0 0 0 0 Reserved : : : : : : : : : : : 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0

: Reserved Sign and 7-bit integer values of RDAC1 tolerance (read only) 8-bit decimal value of RDAC1 tolerance (read only) Reserved Reserved Sign and 7-bit integer values of RDAC3 tolerance (read only)

1 1 1 1 1 8-bit decimal value of RDAC3 tolerance (read only)

D7 D6 D5 D4 D3 D2 D1 D0

6252423222120

SIGN

REG

= 0, EE/

= 1, A4 = 1)

RDAC

D7 D6 D5 D4 D3 D2 D1 D0

2–12–22–32–42–52–62

–8

–7

SIGN

Figure 32. Format of Stored Tolerance in Sign Magnitude Format with Bi

7 BITS FOR INTEGER NUMBER

8 BITS FOR DECIMAL NUMBER

t Position Descriptions (Unit Is Percent, Only Data Bytes Are Shown)

03823-0-012

Rev. A | Page 19 of 28

AD5251/AD5252

XXXXXXX

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I2C-COMPATIBLE 2-WIRE SERIAL BUS

SCL

SLAVE ADDRESS BYTE

SCL SDA

FRAME 1

AD1

SLAVE ADDRESS BYTE

AD0

START B

MASTER

START BY

MASTER

The first byte of the AD5251/AD5252 is a slave address byte (see Figure 33 and Figure 34). It has a 7-bit slave address and an R/

bit. The 5 MSB of the slave address is 01011, and the next

W 2 LSB is determined by the states of the AD1 and AD0 pins. AD1 and AD0 allow the user to place up to four

AD5251/AD5252 devices on one bus.

AD5251/AD5252 can be controlled via an I bus and are connected to this bus as slave devices. The 2-wire

C serial bus protocol (see Figure 33 and Figure 34) follows:

1. The mast

er initiates a data transfer by establishing a start condition, such that SDA goes from high to low while SCL is high (see Figure 33). The following byte is the slave address

yte, which consists of the 5 MSB of a slave address defined

b as 01011. The next two bits are AD1 and AD0, I address bits. Depending on the states of their AD1 and AD0 bits, four AD5251/AD5252 devices can be addressed on the same bus. The last LSB, the R/

whether data is read from or written to the slave device.

The slave whose address corresponds to the transmitted

ess responds by pulling the SDA line low during the

addr ninth clock pulse (this is called an acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register.

2. I

n the write mode (except when restoring EEMEM to the RDAC register), there is an instruction byte that follows the slave address byte. The MSB of the instruction byte is labeled CMD/

. MSB = 1 enables CMD, the command

REG

instruction byte; MSB = 0 enables general register writing. The third MSB in the instruction byte, labeled EE/

is true when MSB = 0 or when the device is in general writing mode. EE enables the EEMEM register, and REG enables the RDAC register. The 5 LSB, A4 to A0, designates

R/W

ACK. BY

AD525x

Figure 33. General I

FRAME 1

C-compatible serial

AD0

AD1

Figure 34. General I

C device

bit, determines

RDAC

INSTRUCTION BYTE

D6 D5

ACK. BY

AD525x

FRAME 2

C Write Pattern

91 9

R/W

ACK. BY

AD525x

D7 D6 D5 D4 D3 D2

FRAME 2

RDAC REGISTER

C Read Pattern

D1 D0

the addresses of the EEMEM and RDAC registers (see Figure 27 and Figure 28). When MSB = 1 or when the de

vice is in CMD mode, the four bits following the MSB are C3 to C1, which correspond to 12 predefined EEMEM controls and quick commands; there are also four factoryreserved commands. The 3 LSB—A2, A1, and A0—are addresses, but only 001 and 011 are used for RDAC1 and RDAC3, respectively (see t

he instruction byte, the last byte in the write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see

n current read mode, the RDAC0 data byte immediately

3. I

follows the acknowledgment of the slave address byte. After an acknowledgement, RDAC1 follows, then RDAC2, and so on. (There is a slight difference in write mode, where the last eight data bits representing RDAC3 data are followed by a no acknowledge bit.) Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see re

4. W

Figure 34). Another reading method, random

ad method, is shown in Figure 30.

hen all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line that occurs while SCL is high. In write mode, the master pulls the SDA line high during the 10 stop condition (see Figure 33). In read mode, the master

sues a no acknowledge for the ninth clock pulse, that is,

is the SDA line remains high. The master brings the SDA line low before the 10 line high to establish a stop condition (see Figure 34).

D4 D3 D2 D1

FRAME 1

DATA BYTE

NO ACK. BY

MASTER

STOP BY MASTER

ACK. BY

AD525x

03823-0-014

STOP BY MASTER

03823-0-013

Figure 31). After acknowledging

Figure 33).

clock pulse to establish a

clock pulse and then brings the SDA

Rev. A | Page 20 of 28

AD5251/AD5252

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THEORY OF OPERATION

The AD5251/AD5252 are dual-channel digital potentiometers in 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ that allow 64/256 linear resistance step adjustments. The AD5251/AD5252 employ double-gate CMOS EEPROM technology, which allows resistance settings and user-defined data to be stored in the EEMEM registers. The EEMEM is nonvolatile, such that settings remain when power is removed. The RDAC wiper settings are restored from the nonvolatile memory settings during device power-up and can also be restored at any time during operation.

The AD5251/AD5252 resistor wiper positions are determined b

y the RDAC register contents. The RDAC register acts like a scratch-pad register, allowing unlimited changes of resistance settings. RDAC register contents can be changed using the device’s serial I the commands to program the RDAC registers are discussed in

C Interface Detail Description section.

the I

C interface. The format of the data-words and

Table 11. Quick Commands

Command Description

0 NOP. 1

2 Store RDAC register setting to EEMEM. 3 Decrement RDAC 6 dB (shift data bits right). 4 Decrement all RDACs 6 dB (shift all data bits right). 5 Decrement RDAC one step. 6 Decrement all RDACs one step. 7 Reset EEMEM contents to all RDACs. 8 Increment RDAC 6 dB (shift data bits left). 9 Increment all RDACs 6 dB (shift all data bits left). 10 Increment RDAC one step. 11 Increment all RDACs one step. 12 to 15 Reserved.

Restore EEMEM content to RDAC. Users should issue NOP imme conserve power.

diately after this command to

The four RDAC registers have corresponding EEMEM memory

cations that provide nonvolatile storage of resistor wiper

lo position settings. The AD5251/AD5252 provide commands to store the RDAC register contents to their respective EEMEM memory locations. During subsequent power-on sequences, the RDAC registers are automatically loaded with the stored value.

Whenever the EEMEM write operation is enabled, the device ac

tivates the internal charge pump and raises the EEMEM cell gate bias voltage to a high level; this essentially erases the current content in the EEMEM register and allows subsequent storage of the new content. Saving data to an EEMEM register consumes about 35 mA of current and lasts approximately 26 ms. Because of charge-pump operation, all RDAC channels may experience noise coupling during the EEMEM writing operation.

The EEMEM restore time in power-up or during operation is a

bout 300 μs. Note that the power-up EEMEM refresh time depends on how fast V supply voltage decoupling capacitors limits the EEMEM restore time during power-up. For example,

profile of the V

up the applied power is a digital signal. The device initially resets the measured RDACs to midscale before restoring the EEMEM contents. The omission of the decoupling capacitors should only be considered when the fast restoring time is absolutely needed in the application. In addition, users should issue a NOP Command 0 immediately after using Command 1 to restore the EEMEM setting to RDAC, thereby minimizing supply current dissipation. Reading user data directly from EEMEM does not require a similar NOP command execution.

In addition to the movement o EEMEM registers, the AD5251/AD5252 provide other shortcut commands that facilitate programming, as shown in Tabl e 11 .

reaches its final value. As a result, any

Figure 20 shows a power-

where there is no decoupling capacitor and

f data between RDAC and

LINEAR INCREMENT/DECREMENT COMMANDS

The increment and decrement commands (10, 11, 5, and 6) are useful for linear step-adjustment applications. These commands simplify microcontroller software coding by allowing the controller to send just an increment or decrement command to the AD5251/AD5252. The adjustments can be directed to a single RDAC or to all four RDACs.

±6 dB ADJUSTMENTS (DOUBLING/HALVING WIPER SETTING)

The AD5251/AD5252 accommodate ±6 dB adjustments of the RDAC wiper positions by shifting the register contents to left/right for increment/decrement operations, respectively. Command 3, Command 4, Command 8, and Command 9 can be used to increment or decrement the wiper positions in 6 dB steps synchronously or asynchronously.

Incrementing the wiper position by +6 dB essentially doubles t

he RDAC register value, whereas decrementing the wiper position by –6 dB halves the register content. Internally, the AD5251/AD5252 use shift registers to shift the bits left and right to achieve a ±6 dB increment or decrement. The maximum number of adjustments is nine and eight steps for incrementing from zero scale and decrementing from full scale, respectively. These functions are useful for various audio/video level adjustments, especially for white LED brightness settings in which human visual responses are more sensitive to large adjustments than to small adjustments.

Rev. A | Page 21 of 28

AD5251/AD5252

www.BDTIC.com/ADI

DIGITAL INPUT/OUTPUT CONFIGURATION

SDA is a digital input/output with an open-drain MOSFET that requires a pull-up resistor for proper communication. On the other hand, SCL and

resistors are recommended to minimize the MOSFET crossconduction current when the driving signals are lower than V

. SCL and WP have ESD protection diodes, as shown in

Figure 35 and Figure 36.

can be permanently tied to VDD without a pull-up resistor if

WP the write-protect feature is not used. If internal current source pulls it low to enable write protection. In applications in which the device is programmed infrequently, this allows the part to default to write-protection mode after any one-time factory programming or field calibration without using an on-board pull-down resistor. Because there are protection diodes on all inputs, the signal levels must not be greater than V

to prevent forward biasing of the diodes.

are digital inputs for which pull-up

is left floating, an

03823-0-035

GND

Figure 35. SCL Digital Input

Table 12. Multiple Devices Addressing

AD1 AD0 Device Addressed

0 0 U1 0 1 U2 1 0

1 1 U4

SCL

SDA

SCL

03823-0-037

MASTER

SDA SCL AD1

AD0

Figure 37. Multiple AD5251/AD5252 Devices on a Single Bus

SDA SCL AD1 AD0

5V 5V

SDA SCL AD1

AD0

SDA AD1 AD0

TERMINAL VOLTAGE OPERATION RANGE

The AD5251/AD5252 are designed with internal ESD diodes for protection; these diodes also set the boundaries for the terminal operating voltages. Positive signals present on Ter m in a l A , Ter min al B , or Ter m in a l W t hat exc ee d V clamped by the forward-biased diode. Similarly, negative signals on Te r mi n al A , Te r mi n al B , or Ter m ina l W t ha t are more negative than V users should not operate V the voltage across V

are also clamped (see Figure 38). In practice,

, VWA, and VWB to be higher than

to VSS, but VAB, VWA, and VWB have no

polarity constraint.

are

INPUTS

03823-0-036

GND

Figure 36. Equivalent

Digital Input

MULTIPLE DEVICES ON ONE BUS

The AD5251/AD5252 are equipped with two addressing pins, AD1 and AD0, that allow up to four AD5251/AD5252 devices to be operated on one I AD1 and AD0 on each device must first be defined. An example is shown in Tabl e 1 2 and Figure 37. In I device is issued a different slave address—01011(AD1)(AD0)— to complete the addressing.

C bus. To achieve this result, the states of

C programming, each

Rev. A | Page 22 of 28

03823-0-018

Figure 38. Maximum Terminal Voltages Set by V

and V

POWER-UP AND POWER-DOWN SEQUENCES

Because the ESD protection diodes limit the voltage compliance at Te r mi n al A , Te rm i na l B, a nd Te rm i na l W ( s ee Figure 38), it is

mportant to power on V

i these terminals. Otherwise, the diodes are forward biased such that V

are powered unintentionally and may affect the

DD/VSS

user’s circuit. Similarly, V The ideal power-up sequence is in the following order: GND, V

, VSS, digital inputs, and VA/VB/VW. The order of powering

, VB, VW, and the digital inputs is not important, as long as

they are powered after V

before applying any voltage to

DD/VSS

should be powered down last.

DD/VSS

AD5251/AD5252

www.BDTIC.com/ADI

LAYOUT AND POWER SUPPLY BIASING

It is always a good practice to employ a compact, minimum lead-length layout design. The leads to the input should be as direct as possible, with a minimum conductor length. Ground paths should have low resistance and low inductance.

Similarly, it is also good practice to bypass the power supplies wi

th quality capacitors. Low equivalent series resistance (ESR) 1 μF to 10 μF tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and filter low frequency ripple.

upply-bypassing configuration for the AD5251/AD5252.

10μF

Figure 39. Power Supply-Bypassing C

Figure 39 illustrates the basic

AD5251/AD5252

0.1μF

0.1μF V

GND

onfiguration

03823-0-039

The ground pin of the AD5251/AD5252 is used primarily as a digital ground reference. To minimize the digital ground bounce, the AD5251/AD5252 ground terminal should be joined remotely to the common ground (see Figure 39).

DIGITAL POTENTIOMETER OPERATION

The structure of the RDAC is designed to emulate the performance of a mechanical potentiometer. The RDAC contains a string of resistor segments with an array of analog switches that act as the wiper connection to the resistor array. The number of points is the resolution of the device. For example, the AD5251/AD5252 emulate 64/256 connection points with 64/256 equal resistance, R provide better than 1.5%/0.4% resolution.

Figure 40 provides an equivalent diagram of the connections

etween the three terminals that make up one channel of the

b RDAC. Switches SW switches SW(0) to SW(2

and SWB are always on, but only one of

N – 1

) can be on at a time (determined by the setting decoded from the data bit). Because the switches are nonideal, there is a 75 Ω wiper resistance, R is a function of supply voltage and temperature: Lower supply voltages and higher temperatures result in higher wiper resistances. Consideration of wiper resistance dynamics is important in applications in which accurate prediction of output resistance is required.

, allowing them to

. Wiper resistance

SW(2N– 1)

RDAC

WIPER

AND

DECODER

= RAB/2

DIGITAL

IRCUITRY

MITTED FOR

LARIT

SW(2N– 2)

SW(1)

SW(0)

03823-0-040

Figure 40. Equivalent RDAC Structure

PROGRAMMABLE RHEOSTAT OPERATION

If either the W-to-B or W-to-A terminal is used as a variable resistor, the unused terminal can be opened or shorted with W; such operation is called rheostat mode (see Figure 41). The r

esistance tolerance can range ±20%.

Figure 41. Rheostat Mode Configuration

The nominal resistance of the AD5251/AD5252 has 64/256 contact points accessed by the wiper terminal, plus the B terminal contact. The 6-/8-bit data-word in the RDAC register is decoded to select one of the 64/256 settings. The wiper’s first connection starts at the B terminal for Data 0x00. This B terminal connection has a wiper contact resistance, R nominal resistance. The second connection (the AD5251 10 kΩ part) is the first tap point where R R

= 156 Ω + 75 Ω) for Data 0x01, and so on. Each LSB data

value increase moves the wiper up the resistor ladder until the last tap point is reached at R simplified diagram of the equivalent RDAC circuit.

The general equation that determines the digitally programmed

utput resistance between W and B is

AD5251: RWB(D) = (D/64) × RAB + 75 Ω (1)

AD5252: R

(D) = (D/256) × RAB + 75 Ω (2)

where:

s the decimal equivalent of the data contained in the

D i RDAC latch.

is the nominal end-to-end resistance.

= 9893 Ω. See Figure 40 for a

03823-0-041

, of 75 Ω, regardless of the

= 231 Ω (RWB = RAB/64 +

Rev. A | Page 23 of 28

AD5251/AD5252

www.BDTIC.com/ADI

100

(%)

PROGRAMMABLE POTENTIOMETER OPERATION

If all three terminals are used, the operation is called potentiometer mode (see Figure 43); the most common configuration

he voltage divider operation.

is t

Figure 43. Potentiometer Mode Configuration

03823-0-043

Figure 42. AD5251 R

16 32 48 63

D (Code in Decimal)

(D) and RWB(D) vs. Decimal Code

03823-0-042

Since the digital potentiometer is not ideal, a 75 Ω finite wiper resistance is present that can easily be seen when the device is programmed at zero scale. Because of the fine geometric and interconnects employed by the device, care should be taken to limit the current conduction between W and B to no more than ±5 mA continuous for a total resistance of 1 kΩ or a pulse of ±20 mA to avoid degradation or possible destruction of the device. The maximum dc current for AD5251 and AD5252 are shown in

Figure 21and Figure 22, respectively.

Similar to the mechanical potentiometer, the resistance of the RDAC between Wiper W and Terminal A also produces a digitally controlled complementary resistance, R terminals are used, the B terminal can be opened. The R

. When these

starts at a maximum value and decreases as the data loaded into the latch increases in value (see

uation for this operation is

AD5251: R

AD5252: R

(D) = [(64 – D)/64] × RAB + 75 Ω (3)

(D) = [(256 – D)/256] × RAB + 75 Ω (4)

The typical distribution of R

Figure 42). The general

from channel-to-channel

matches is about ±0.15% within a given device. On the other hand, device-to-device matching is process-lot dependent with a ±20% tolerance.

If the wiper resistance is ignored, the transfer function is simply

AD5251:

AD5252:

V +×=

256

(5)

(6)

A more accurate calculation that includes the wiper resistance effect is

where 2

)(

is the number of steps.

(7)

Unlike in rheostat mode operation, where the tolerance is high, potentiometer mode operation yields an almost ratiometric

function of D/2

terms. Therefore, the tolerance effect is almost cancelled.

with a relatively small error contributed by the

Similarly, the ratiometric adjustment also reduces the temperature coefficient effect to 50 ppm/°C, except at low value codes where R

dominates.

Potentiometer mode operations include other applications, such as op amp input, feedback-resistor networks, and other voltagescaling applications. The A, W, and B terminals can, in fact, be input or output terminals, provided that |V not exceed V

to VSS.

|, |VW|, and |VB| do

Rev. A | Page 24 of 28

AD5251/AD5252

www.BDTIC.com/ADI

APPLICATIONS

LCD PANEL V

Large LCD panels usually require an adjustable V

ADJUSTMENT

COM

voltage centered around 6 V to 8 V with ±1 V swing and small steps adjustment. This example represents common DAC applications where the window of adjustments is small and centered at any level. High voltage and high resolution DACs can be used, but it is far more cost-effective to use low voltage digital potentiometers with level shifting, such as the AD5251 or AD5252, to achieve the objective.

Assume a V

voltage requirement of 6 V ± 1 V with a ±20 mV

COM

step adjustment, as shown in Figure 44. The AD5252 can be co

nfigured in voltage divider mode with an op amp gain. With ±20% tolerance accounted for by the AD5252, this circuit can still be adjusted from 5 V to 7 V with an 8 mV/step in the worst case.

+14.4V

±1%

350kΩ

+5V

AD5252

10kΩ

18.5kΩ

±20%

1kΩ

+14.4V

V+

V–

2.2pF

6kΩ

6V ± 1V

COM

03823-0-044

Figure 44. Apply 5 V Digital Potentiometer AD5251 in a 6 V ± 1 V Application

CURRENT-SENSING AMPLIFIER

The dual-channel, synchronous update, and channel-to-channel resistance matching characteristics make the AD5251/AD5252 suitable for current-sensing applications, such as LED brightness control. In the circuit shown in R

DAC1 and RDAC3 are programmed to the same settings, it

can be shown that

V +−

()

−

VVV

REF

As a result, the current through a sense resistor connected bet

ween V

and V2 can be determined.

The circuit can be programmed for use with systems that require dif

ferent sensitivities. If the op amp has very low offset and low bias current, the major source of error comes from the digital potentiometer channel-to-channel resistance mismatch, which is typically 0.15%. The circuit accuracy is about 9 bits, which is adequate for LED control and other general-purpose applications.

Figure 45, when

(8)

ADJUSTABLE HIGH POWER LED DRIVER

Figure 46 shows a circuit that can drive three or four high power LEDs. The ADP1610 is an adjustable boost regulator that provides adequate headroom and current for the LEDs. Because its FB pin voltage is 1.2 V, the digital potentiometer AD5252 and the op amp form an average gain of 12 feedback networks that servo the sensing and feedback voltages. As a result, the voltage across

is regulated around 0.1 V, depending on the AD5252’s

SET

setting. An adjustable LED current is

LED

should be small enough to conserve power, but large enough

SET

to limit the maximum LED current. R3 should be used in parallel with the AD5252 to limit the LED current to an achievable range.

+5V

RDAC1

SENSE

0.1kΩ

10kΩ

AD5252

RDAC3

10kΩ

AD8628

Figure 45. Current-Sensing Amplifier

SET

(9)

SET

ADP1610

SD SW

PWM

COMP

SS RT GND

100kΩ

390pF

10nF

1.1kΩ

0.1μF

AD8591

C2 10μF

Figure 46. High Power, Adjustable LED Driver

+5V

V+ V–

L1 10μF

10μF

+5V

V+

V–

AD5252

10kΩ

200Ω

VREF

0.25kΩ

100Ω

SET

03823-0-045

OUT

03823-0-046

Rev. A | Page 25 of 28

AD5251/AD5252

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

5.10

5.00

4.90

4.50

4.40

4.30

PIN 1

1.05

1.00

0.80

0.65

BSC

0.15

0.30

0.05

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AB-1

Figure 47. 14-Lead Thin Shrink S

Dimensions shown in millimeters

6.40 BSC

1.20 MAX

SEATING PLANE

0.20

0.09

COPLANARITY

0.10

8° 0°

mall Outline Package [TSSOP]

(RU-14)

0.75

0.60

0.45

Rev. A | Page 26 of 28

AD5251/AD5252

www.BDTIC.com/ADI

ORDERING GUIDE

Temperature R

ange (°C) Package Description

Model

Step RAB (kΩ)

AD5251BRU1 64 1 −40 to +85 14-Lead TSSOP RU-14 96 AD5251BRU1-RL7 64 1 −40 to +85 14-Lead TSSOP RU-14 1,000 AD5251BRUZ1

64 1 −40 to +85 14-Lead TSSOP RU-14 96 AD5251BRU10 64 10 −40 to +85 14-Lead TSSOP RU-14 96 AD5251BRU10-RL7 64 10 −40 to +85 14-Lead TSSOP RU-14 1,000 AD5251BRUZ10

64 10 −40 to +85 14-Lead TSSOP RU-14 96 AD5251BRU50 64 50 −40 to +85 14-Lead TSSOP RU-14 96 AD5251BRU50-RL7 64 50 −40 to +85 14-Lead TSSOP RU-14 1,000 AD5251BRUZ50

64 50 −40 to +85 14-Lead TSSOP RU-14 96 AD5251BRU100 64 100 −40 to +85 14-Lead TSSOP RU-14 96 AD5251BRU100-RL7 64 100 −40 to +85 14-Lead TSSOP RU-14 1,000 AD5251BRUZ100

64 100 −40 to +85 14-Lead TSSOP RU-14 96 AD5251EVAL 64 10 Evaluation Board 1 AD5252BRU1 256 1 −40 to +85 14-Lead TSSOP RU-14 96 AD5252BRU1-RL7 256 1 −40 to +85 14-Lead TSSOP RU-14 1,000 AD5252BRUZ1 AD5252BRUZ1-RL7

256 1 −40 to +85 14-Lead TSSOP RU-14 96

256 1 −40 to +85 14-Lead TSSOP RU-14 1,000 AD5252BRU10 256 10 −40 to +85 14-Lead TSSOP RU-14 96 AD5252BRU10-RL7 256 10 −40 to +85 14-Lead TSSOP RU-14 1,000 AD5252BRUZ10 AD5252BRUZ10-RL7

256 10 −40 to +85 14-Lead TSSOP RU-14 96

256 10 −40 to +85 14-Lead TSSOP RU-14 1,000 AD5252BRU50 256 50 −40 to +85 14-Lead TSSOP RU-14 96 AD5252BRU50-RL7 256 50 −40 to +85 14-Lead TSSOP RU-14 1,000 AD5252BRUZ50 AD5252BRUZ50-RL7

256 50 −40 to +85 14-Lead TSSOP RU-14 96

256 50 −40 to +85 14-Lead TSSOP RU-14 1,000 AD5252BRU100 256 100 −40 to +85 14-Lead TSSOP RU-14 96 AD5252BRU100-RL7 256 100 −40 to +85 14-Lead TSSOP RU-14 1,000 AD5252BRUZ100 AD5252BRUZ100-RL7

256 100 −40 to +85 14-Lead TSSOP RU-14 96

256 100 −40 to +85 14-Lead TSSOP RU-14 1,000 AD5252EVAL 256 10 Evaluation Board 1

In the package marking, Line 1 shows the part number. Line 2 shows the branding information, such that B1 = 1 kΩ, B10 = 10 kΩ, and so on. There is also a

“#” marking for the Pb-free part. Line 3 shows the date code in YYWW.

Z = Pb-free part.

Package Option

Ordering Quantity

Rev. A | Page 27 of 28

AD5251/AD5252

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NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

Rev. A | Page 28 of 28

ANALOG DEVICES AD5251, AD5252 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

REVISION HISTORY

ELECTRICAL CHARACTERISTICS

1 kΩ VERSION

10 kΩ, 50 kΩ, 100 kΩ VERSIONS

INTERFACE TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

I2C INTERFACE

I2C INTERFACE GENERAL DESCRIPTION

I2C INTERFACE DETAIL DESCRIPTION

RDAC/EEMEM Write

RDAC/EEMEM Read

RDAC/EEMEM Quick Commands

RAB Tolerance Stored in Read-Only Memory

EEMEM Write-Acknowledge Polling

EEMEM Write Protection

I2C-COMPATIBLE 2-WIRE SERIAL BUS

THEORY OF OPERATION

LINEAR INCREMENT/DECREMENT COMMANDS

±6 dB ADJUSTMENTS (DOUBLING/HALVING WIPER SETTING)

DIGITAL INPUT/OUTPUT CONFIGURATION

TERMINAL VOLTAGE OPERATION RANGE

MULTIPLE DEVICES ON ONE BUS

POWER-UP AND POWER-DOWN SEQUENCES

LAYOUT AND POWER SUPPLY BIASING

DIGITAL POTENTIOMETER OPERATION

PROGRAMMABLE RHEOSTAT OPERATION

PROGRAMMABLE POTENTIOMETER OPERATION

APPLICATIONS

CURRENT-SENSING AMPLIFIER

ADJUSTABLE HIGH POWER LED DRIVER

OUTLINE DIMENSIONS

ORDERING GUIDE