ANALOG DEVICES AD5241 Service Manual

I2C-Compatible,

A

A

FEATURES

256 positions
10 kΩ, 100 kΩ, 1 MΩ
Low temperature coefficient: 30 ppm/°C
Internal power on midscale preset
Single-supply 2.7 V to 5.5 V or dual-supply ±2.7 V for ac or

bipolar operation

2

I

C-compatible interface with readback capability
Extra programmable logic outputs
Self-contained shutdown feature
Extended temperature range: −40°C to +105°C

APPLICATIONS

Multimedia, video, and audio
Communications
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Line impedance matching

256-Position Digital Potentiometers

AD5241/AD5242

FUNCTIONAL BLOCK DIAGRAM

O1O

2

REGISTER 2

8

PWR-ON

RESET

A2W2B2O1O

REGISTER

00926-001

2

SHDN

1W1B1

SHDN

V

V

SDA
SCL
GND

DD

SS

DECODE

RDAC

REGIS TER 1

ADDR

AD5241

SERIAL INPUT REGIST ER

AD0

AD1

Figure 1. AD5241 Functional Block Diagram

1W1B1

GENERAL DESCRIPTION

The AD5241/AD5242 provide a single-/dual-channel, 256­position, digitally controlled variable resistor (VR) device. These
devices perform the same electronic adjustment function as a
potentiometer, trimmer, or variable resistor. Each VR offers a
completely programmable value of resistance between the A
terminal and the wiper, or the B terminal and the wiper. For the
AD5242, the fixed A-to-B terminal resistance of 10 kΩ, 100 kΩ,
or 1 MΩ has a 1% channel-to-channel matching tolerance. The
nominal temperature coefficient of both parts is 30 ppm/°C.

V

V

SDA

SCL

GND

DD

SS

DECODE

RDAC

REGISTER 1

ADDR

AD5242

1

SERIAL INPUT REGISTER

AD0 AD1

REGISTER 2

8

RDAC

PWR-ON

RESET

00926-002

Figure 2. AD5242 Functional Block Diagram

Wiper position programming defaults to midscale at system
power on. When powered, the VR wiper position is programmed

2

by an I

C®-compatible, 2-wire serial data interface. Both parts
have two extra programmable logic outputs available that
enable users to drive digital loads, logic gates, LED drivers, and
analog switches in their system.

The AD5241/AD5242 are available in surface-mount, 14-lead
SOIC and 16-lead SOIC packages and, for ultracompact solutions,
14-lead TSSOP and 16-lead TSSOP packages. All parts are
guaranteed to operate over the extended temperature range of

−40°C to +105°C.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2001–2009 Analog Devices, Inc. All rights reserved.

AD5241/AD5242

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

10 kΩ, 100 kΩ, 1 MΩ Version .................................................... 3

Timing Diagrams .......................................................................... 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

REVISION HISTORY

12/09—Rev. B to Rev. C

Changes to Features Section............................................................ 1

Changes to 10 kΩ, 100 kΩ, 1 MΩ Version Section ...................... 3

Changes to Table 3 ............................................................................ 6

Deleted Digital Potentiometer Selection Guide Section ........... 14

Changed Self-Contained Shutdown Function Section to

Shutdown Function Section .......................................................... 15

Changes to Shutdown Function Section ..................................... 15

Changes to Ordering Guide .......................................................... 18

8/02—Rev. A to Rev. B

Additions to Features ....................................................................... 1

Changes to General Description .................................................... 1

Changes to Specifications ................................................................ 2

Changes to Absolute Maximum Ratings ....................................... 4

Additions to Ordering Guide .......................................................... 4

Changes to TPC 8 and TPC 9 ......................................................... 8

Changes to Readback RDAC Value Section ................................ 11

Changes to Additional Programmable Logic Output Section .. 11

Added Self-Contained Shutdown Section ................................... 12

Added Figure 8 ................................................................................ 12

Changes to Digital Potentiometer Selection Guide ................... 14

Test Circuits ..................................................................................... 11

Theory of Operation ...................................................................... 12

Programming the Variable Resistor ......................................... 12

Programming the Potentiometer Divider ............................... 13

Digital Interface .......................................................................... 13

Readback RDAC Value .............................................................. 14

Multiple Devices on One Bus ................................................... 14

Level-Shift for Bidirectional Interface ..................................... 14

Additional Programmable Logic Output ................................ 15

Shutdown Function .................................................................... 15

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 18

2/02—Rev. 0 to Rev. A

Edits to Features ................................................................................. 1

Edits to Functional Block Diagrams ............................................... 1

Edits to Absolute Maximum Ratings .............................................. 4

Changes to Ordering Guide ............................................................. 4

Edits to Pin Function Descriptions ................................................. 5

Edits to Figures 1, 2, 3 ....................................................................... 6

Added Readback RDAC Value Section, Additional
Programmable Logic Output Section, and Figure 7;

Renumbered Sequentially ............................................................. 11

Changes to Digital Potentiometer Selection Guide ................... 14

Rev. C | Page 2 of 20

AD5241/AD5242

V

SPECIFICATIONS

10 kΩ, 100 kΩ, 1 MΩ VERSION

VDD = 2.7 V to 5.5 V, VA = VDD, VB = 0 V, −40°C < TA < +105°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS, RHEOSTAT MODE

(SPECIFICATIONS APPLY TO ALL VRs)
Resolution N 8 Bits

Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect −1 ±0.4 +1 LSB
Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect −2 ±0.5 +2 LSB
Nominal Resistor Tolerance ΔRAB/RAB T

Resistance Temperature Coefficient

Wiper Resistance RW I

DC CHARACTERISTICS, POTENTIOMETER DIVIDER

MODE (SPECIFICATIONS APPLY TO ALL VRs)
Resolution N 8 Bits

Differential Nonlinearity3 DNL −1 ±0.4 +1 LSB
Integral Nonlinearity3 INL −2 ±0.5 +2 LSB
Voltage Divider Temperature Coefficient (ΔVW/VW)/∆T × 106 Code = 0x80 5 ppm/°C
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range4 V
Capacitance (A, B)5 C

Capacitance (W)5 C

Common-Mode Leakage ICM V

DIGITAL INPUTS

Input Logic High (SDA and SCL) VIH 0.7 × VDD VDD + 0.5 V V
Input Logic Low (SDA and SCL) VIL −0.5 +0.3 × VDD V
Input Logic High (AD0 and AD1) VIH V
Input Logic Low (AD0 and AD1) VIL V
Input Logic High VIH V
Input Logic Low VIL V
Input Current IIL V
Input Capacitance5 C

DIGITAL OUTPUT

Output Logic Low (SDA) VOL I
Output Logic Low (O1 and O2) VOL I
Output Logic High (O1 and O2) VOH I
Three-State Leakage Current (SDA) IOZ V
Output Capacitance5 C

POWER SUPPLIES

Power Single-Supply Range V
Power Dual-Supply Range VDD/V
Positive Supply Current IDD V
Negative Supply Current ISS V
Power Dissipation6 P

Power Supply Sensitivity PSS −0.01 +0.002 +0.01 %/%

= 25°C, RAB = 10 kΩ −30 +30 %

A

−30 +50 %

30 ppm/°C

(ΔR

AB/RAB

ΔT × 10

= 25°C,

T

A

= 100 kΩ/1 MΩ

R

AB

)/

6

= VDD, wiper =

V

AB

no connect

= VDD/R 60 120 Ω

W

Code = 0xFF −1 −0.5 0 LSB

WFSE

Code = 0x00 0 0.5 1 LSB

WZSE

, VB, VW V

A

A

, CB

f = 1 MHz, measured

V

SS

V

DD

45 pF

to GND, code = 0x80

W

f = 1 MHz, measured

60 pF

to GND, code = 0x80

= VB = VW 1 nA

A

= 5 V 2.4 VDD V

DD

= 5 V 0 0.8 V

DD

= 3 V 2.1 VDD V

DD

= 3 V 0 0.6 V

DD

= 5 V or VIL = GND 1 μA

IH

3 pF

IL

OL

3 8 pF

OZ

V

DD RANGE

±2.3 ±2.7 V

SS RANGE

DISS

IOL= 3 mA 0.4 V

= 6 mA 0.6 V

OL

= 1.6 mA 0.4 V

SINK

= 40 μA 4 V

SOURCE

= 5 V or VIL = GND ±1 μA

IH

= 0 V 2.7 5.5 V

SS

= 5 V or VIL = GND 0.1 50 μA

IH

= −2.5 V, VDD = +2.5 V +0.1 −50 μA

SS

= 5 V or VIL = GND,

V

IH

V

= 5 V

DD

0.5 250
μW

Rev. C | Page 3 of 20

AD5241/AD5242

Parameter Symbol Conditions Min Typ1 Max Unit

DYNAMIC CHARACTERISTICS

−3 dB Bandwidth BW_10 kΩ RAB = 10 kΩ, code = 0x80 650 kHz
BW_100 kΩ RAB = 100 kΩ, code = 0x80 69 kHz
BW_1 MΩ RAB = 1 MΩ, code = 0x80 6 kHz
Total Harmonic Distortion THDW

VW Settling Time tS

Resistor Noise Voltage e

INTERFACE TIMING CHARACTERISTICS

(APPLIES TO ALL PARTS
SCL Clock Frequency f
Bus Free Time Between Stop and Start, t

5, 7 , 8

0.005 %

2 μs

5, 9

= 1 V rms + 2 V dc,

V

A

= 2 V dc, f = 1 kHz

V

B

= VDD, VB = 0 V, ± 1 LSB

V

A

error band, R

R

N_WB

= 5 kΩ, f = 1 kHz 14 nV√Hz

WB

= 10 kΩ

AB

)

0 400 kHz

SCL

t1 1.3 μs

BUF

Hold Time (Repeated Start), t

t

HD; STA

2

After this period, the first

600 ns

clock pulse is generated
Low Period of SCL Clock, t
High Period of SCL Clock, t
Setup Time for Repeated Start Condition, t
Data Hold Time, t
Data Setup Time, t

HD; DAT

SU; DAT

t

LOW

t

HIGH

SU; STA

t

t

1.3 μs

3

0.6 50 μs

4

t5 600 ns

900 ns

6

100 ns

7

Rise Time of Both SDA and SCL Signals, tR t8 300 ns

Fall Time of Both SDA and SCL Signals, tF t9 300 ns
Setup Time for Stop Condition, t

1

Typicals represent average readings at 25°C, VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits.

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL

specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 37.

4

Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.

5

Guaranteed by design, not subject to production test.

6

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

7

Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

8

All dynamic characteristics use VDD = 5 V.

9

See timing diagram in Figure 3 for location of measured values.

t

SU; STO

10

Rev. C | Page 4 of 20

AD5241/AD5242

SDA

S

TIMING DIAGRAMS

t

8

t

1

t

8

t

9

t

2

SCL

t

2

t

SP

3

t

t

4

6

t

7

t

5

S P

t

10

Figure 3. Detail Timing Diagram

Data of AD5241/AD5242 is accepted from the I

2

C bus in the following serial format.

Table 2.

S 0 1 0 1 1 AD1 AD0

Slave Address Byte Instruction Byte Data Byte

W

R/

A

/B

A

RS SD O

O2 X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P

1

where:
S = start condition
P = stop condition
A = acknowledge
X = don’t care
AD1, AD0 = Package pin programmable address bits. Must be matched with the logic states at Pins AD1 and AD0.

W

R/

= Read enable at high and output to SDA. Write enable at low.

A

/B = RDAC subaddress select; 0 for RDAC1 and 1 for RDAC2.
RS = Midscale reset, active high.
SD = Shutdown in active high. Same as
O

, O2 = Output logic pin latched values

1

SHDN

except inverse logic.

D7, D6, D5, D4, D3, D2, D1, D0 = data bits.

SCL

SDA

TART BY

MASTER

1 119 99

0

0

1

SLAVE ADDRESS BYT E

1

FRAME 1

1

AD1 AD0

R/W

A/B D0D4D5D6D7 D3 D2 D1

ACK BY
AD5241

SDRS

OO

21

FRAME 2

INSTRUCTIO N BYTE

XXX

ACK BY
AD5241

Figure 4. Writing to the RDAC Serial Register

SCL

SDA

START BY

MASTER

1

0

0

1

SLAVE ADDRESS BYTE

11

FRAME 1

AD1 AD0

R/W

D6 D5 D4 D3 D2 D1 D0

D7

ACK BY
AD5241

DATA BYTE FROM PREVIO USLY SELECTED

RDAC REGISTER I N WRITE MO DE

FRAME 2

Figure 5. Reading Data from a Previously Selected RDAC Register in Write Mode

FRAME 3

DATA BYTE

919

NO ACK BY

MASTER

STOP BY
MASTER

0926-005

ACK BY
AD5241

STOP BY
MASTER

0926-007

00926-006

Rev. C | Page 5 of 20

AD5241/AD5242

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND −0.3 V to +7 V
VSS to GND 0 V to −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS to VDD
IA, IB, IW

RAB = 10 kΩ in TSSOP-14 5.0 mA1
RAB = 100 kΩ in TSSOP-14 1.5 mA1

RAB = 1 MΩ in TSSOP-14 0.5 mA1
Digital Input Voltage to GND 0 V to VDD + 0.3 V
Operating Temperature Range −40°C to +105°C
Thermal Resistance θJA

14-Lead SOIC 158°C/W
16-Lead SOIC 73°C/W
14-Lead TSSOP 206°C/W

16-Lead TSSOP 180°C/W
Maximum Junction Temperature (TJ max) 150°C
Package Power Dissipation PD = (TJ max − TA)/θJA
Storage Temperature Range −65°C to +150°C
Lead Temperature

Vapor Phase, 60 sec 215°C

Infrared, 15 sec 220°C

1

Maximum current increases at lower resistance and different packages.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. C | Page 6 of 20