ANALOG DEVICES AD5235-EP Service Manual

Nonvolatile Memory, Dual

1024-Position Digital Potentiometer

Enhanced Product

FEATURES

Dual-channel, 1024-position resolution
25 kΩ nominal resistance
Low temperature coefficient: 35 ppm/°C
Nonvolatile memory stores wiper settings
Permanent memory write protection
Wiper setting readback
Resistance tolerance stored in EEMEM
Predefined linear increment/decrement instructions
Predefined ±6 dB/step log taper increment/decrement

instructions

SPI-compatible serial interface

2.7 V to 5 V single supply or ±2.5 V dual supply
26 bytes extra nonvolatile memory for user-defined

information
100-year typical data retention, T
Power-on refreshed with EEMEM settings
Enhanced Features

Supports defense and aerospace applications (AQEC)

Temperature range: −40°C to +125°C

Controlled manufacturing baseline

1 assembly/test site

1 fabrication site

Enhanced product change notification

Qualification data available on request

APPLICATIONS

DWDM laser diode driver, optical supervisory systems
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration

GENERAL DESCRIPTION

The AD5235-EP is a dual-channel, nonvolatile memory,1
digitally controlled potentiometer
The device performs the same electronic adjustment function as a
mechanical potentiometer with enhanced resolution, solid state
reliability, and superior low temperature coefficient performance.
The AD5235-EP’s versatile programming via an SPI®-compatible
serial interface allows 16 modes of operation and adjustment
including scratchpad programming, memory storing and restoring,
increment/decrement, ±6 dB/step log taper adjustment, wiper setting
readback, and extra EEMEM
memory data for other components, look-up tables, or system
identification information.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

1

= 55°C

A

2

with 1024-step resolution.

for user-defined information such as

AD5235-EP

FUNCTIONAL BLOCK DIAGRAM

ADDR

CS

CLK

SDI

SDO

PR

WP

RDY

*RAB TOLERANCE

DECODE

SERIAL

INTERFACE

POWER-ON

RESET

EEMEM

CONTROL

RTOL*

RDAC1

REGISTER

EEMEM1

RDAC2

REGISTER

EEMEM2

26 BYTES

USER EEMEM

Figure 1.

In scratchpad programming mode, a specific setting can be
programmed directly to the RDAC
between Terminal W and Terminal A, and Terminal W and
Terminal B. This setting can be stored into the EEMEM and
is restored automatically to the RDAC register during system
power-on.

The EEMEM content can be restored dynamically or through
external

PR

strobing, and a WP function protects EEMEM contents.
To simplify the programming, the independent or simultaneous
linear-step increment or decrement commands can be used to move
the RDAC wiper up or down, one step at a time. For logarithmic
±6 dB changes in the wiper setting, the left or right bit shift
command can be used to double or halve the RDAC wiper setting.

The AD5235-EP patterned resistance tolerance is stored in the
EEMEM. Therefore, in readback mode, the host processor can
know the actual end-to-end resistance. The host can execute the
appropriate resistance step through a software routine that simplifies
open-loop applications as well as precision calibration and
tolerance matching applications.

The AD5235-EP is available in a thin, 16-lead TSSOP package.
The part is guaranteed to operate over the extended industrial
temperature range of −40°C to +125°C.

Full details about this enhanced product, including theory of
operation, register details, and applications information, are
available in the AD5235 data sheet, which should be consulted
in conjunction with this data sheet.

1

The terms nonvolatile memory and EEMEM are used interchangeably.

2

The terms digital potentiometer and RDAC are used interchangeably.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010–2012 Analog Devices, Inc. All rights reserved.

AD5235-EP

RDAC1

RDAC2

2

register that sets the resistance

V

DD

A1

W1

B1

A2
W2

B2

V

SS

GND

09185-001

AD5235-EP Enhanced Product

TABLE OF CONTENTS

Features .............................................................................................. 1

Applicat ions ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics ............................................................. 3

Interface Timing and EEMEM Reliability Characteristics ..... 5

REVISION HISTORY

7/12—Rev. 0 to Rev. A

Change to Features Section .............................................................. 1

Changes to Electrical Characteristics Section and Table 1 .......... 3

Changes to Interface Timing and EEMEM Reliability

Characteristics Section and Table 2 ................................................ 5

Changes to Typical Performance Characteristics Section ............ 9

Added Figure 14 and Figure 16, Renumbered Sequentially ...... 10

Deleted Figure 21 ............................................................................. 11

Added Figure 23 ............................................................................... 12

7/10—Revision 0: Initial Version

Absolute Maximum Ratings ............................................................7

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions ..............................8

Typical Performance Characteristics ..............................................9

Test Circuits ..................................................................................... 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. A | Page 2 of 16

Enhanced Product AD5235-EP

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V, VA = VDD, VB = VSS, −40°C < TA < +125°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

(All RDACs)
Resistor Differential Nonlinearity2 R-DNL RWB −1 +1 LSB
Resistor Integral Nonlinearity2 R-INL RWB −2 +2 LSB
Nominal Resistor Tolerance ∆RAB/RAB Code = full scale −8 +8 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C
Wiper Resistance RW

Nominal Resistance Match R

DC CHARACTERISTICS—POTENTIOMETER

DIVIDER MODE (All RDACs)
Resolution N 10 Bits
Differential Nonlinearity3 DNL −1 +1 LSB
Integral Nonlinearity3 INL −1 +1 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T × 106 Code = half scale 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Terminal Voltage Range4 V
Capacitance Ax, Bx5 C

Capacitance Wx5 C

Common-Mode Leakage Current

5, 6

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH With respect to GND, VDD = 5 V 2.4 V
Input Logic Low VIL With respect to GND, VDD = 5 V 0.8 V
Input Logic High VIH With respect to GND, VDD = 3 V 2.1 V
Input Logic Low VIL With respect to GND, VDD = 3 V 0.6 V
Input Logic High VIH

Input Logic Low VIL

Output Logic High (SDO, RDY) VOH R
Output Logic Low VOL I
Input Current IIL V
Input Capacitance5 C

= 1 V/RWB, VDD = 5 V, code =

I

W

30 65 Ω

half scale

= 1 V/RWB, VDD = 3 V, code =

I

W

50 Ω

half scale

Code = full scale, TA = 25°C ±0.1 %

AB1/RAB2

Code = full scale −7 0 LSB

WFSE

Code = zero scale 0 5 LSB

WZSE

, VB, VW V

A

A

, CB

f = 1 MHz, measured to GND,

VDD V

SS

11 pF

code = half-scale

W

f = 1 MHz, measured to GND,

80 pF

code = half-scale

ICM V

5 pF

IL

= VDD/2 0.01 ±1 μA

W

With respect to GND, V

= −2.5 V

V

SS

With respect to GND, V

= −2.5 V

V

SS

= 2.2 kΩ to 5 V 4.9 V

PULL-UP

= 1.6 mA, V

OL

= 0 V or VDD ±2.25 μA

IN

LOGI C

= +2.5 V,

DD

= +2.5 V,

DD

= 5 V 0.4 V

2.0 V

0.5 V

Rev. A | Page 3 of 16

AD5235-EP Enhanced Product

Parameter Symbol Conditions Min Typ1 Max Unit

POWER SUPPLIES

Single-Supply Power Range VDD V
Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD V
Negative Supply Current ISS

EEMEM Store Mode Current IDD (store)

I
EEMEM Restore Mode Current7 I

I
Power Dissipation8 P
Power Supply Sensitivity5 P

DYNAMIC CHARACTERISTICS

5, 9

(store) VDD = +2.5 V, VSS = −2.5 V −2 mA

SS

(restore)

DD

(restore) VDD = +2.5 V, VSS = −2.5 V −320 μA

SS

V

DISS

ΔVDD = 5 V ± 10% 0.006 0.01 %/%

SS

Bandwidth BW −3 dB, VDD/VSS = ±2.5 V 125 kHz
Total Harmonic Distortion THDW V
VW Settling Time tS

Resistor Noise Density e

T

N_WB

Crosstalk (CW1/CW2) CT

Analog Crosstalk CTA

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. IW ~ 50 μA for VDD = 2.7 V and IW ~ 400 μA for VDD = 5 V (see Figure 25).

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of

±1 LSB maximum are guaranteed monotonic operating conditions (see Figure 26).

4

Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-

referenced bipolar signal adjustment.

5

Guaranteed by design and not subject to production test.

6

Common-mode leakage current is a measure of the dc leakage from any Terminal A, Terminal B, or Terminal W to a common-mode bias level of VDD/2.

7

EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 22). To

minimize power dissipation, a NOP, Instruction 0 (0x0) should be issued immediately after Instruction 1 (0x1).

8

P

is calculated from (IDD × VDD) + (ISS × VSS).

DISS

9

All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.

= 0 V 2.7 5.5 V

SS

= VDD or VIL = GND 2 7 μA

IH

= VDD or VIL = GND, VDD = +2.5 V,

V

IH

= −2.5 V

V

SS

= VDD or VIL = GND, VSS = GND,

V

IH

I

≈ 0

SS

= VDD or VIL = GND, VSS = GND,

V

IH

≈ 0

I

SS

= VDD or VIL = GND 10 40 μW

IH

= 1 V rms, VB = 0 V, f = 1 kHz 0.009 %

A

= VDD, VB = 0 V,

V

A

= 0.50% error band,

V

W

−6 −2 μA

2 mA

320 μA

4 μs

Code 0x000 to Code 0x200

= 25°C 20

A

= VDD, VB = 0 V, measured VW1

V

A

making full-scale change

with V

W2

= VA1 = +2.5 V,

V

DD

V

= VB1 = −2.5 V, measured

SS

with VW2 = 5 V p-p @ f = 1 kHz,

V

W1

30

−110

Code 1 = 0x200, Code 2 = 0x3FF

nV/√Hz
nV-s

dB

Rev. A | Page 4 of 16

Enhanced Product AD5235-EP

INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS

Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with t
measured using both V

= 2.7 V and VDD = 5 V.

DD

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

Clock Cycle Time (t

) t1 20 ns

CYC

CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulse Width t4, t5 Clock level high or low 10 ns

Data Setup Time t6 From positive CLK transition 5 ns
Data Hold Time t7 From positive CLK transition 5 ns
CS to SDO-SPI Line Acquire

CS to SDO-SPI Line Release
CLK to SDO Propagation Delay2 t
CLK to SDO Data Hold Time t11 R
CS High Pulse Width3
CS High to CS High3
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Store EEMEM Time

4, 5

Read EEMEM Time4 t
CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous)6 t
Preset Response Time to Wiper Setting6 t
Power-On EEMEM Restore Time6 t
FLASH/EE MEMORY RELIABILITY

Endurance7 T
100
Data Retention8 100

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Propagation delay depends on the value of VDD, R

3

Valid for commands that do not activate the RDY pin.

4

The RDY pin is low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 μs; CMD_9, CMD_10 ~ 7 μs;

CMD_2, CMD_3 ~ 15 ms; PR hardware pulse ~ 30 μs.

5

Store EEMEM time depends on the temperature and EEMEM writes cycles. Higher timing is expected at a lower temperature and higher write cycles.

6

Not shown in Figure 2 and Figure 3.

7

Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +125°C.

8

Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV

derates with junction temperature in the Flash/EE memory.

= tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are

R

t

10 ns

2

t

1 t

3

t

40 ns

8

t

50 ns

9

R

10

t

12

t

4 t

13

t

0 ns

14

t

0.15 0.3 ms

15

= 2.2 kΩ, CL < 20 pF 50 ns

P

= 2.2 kΩ, CL < 20 pF 0 ns

P

10 ns

CYC

CYC

t16 Applies to Instructions 0x2, 0x3 15 50 ms

Applies to Instructions 0x8, 0x9, 0x10 7 30 μs

16

t

10 ns

17

50 ns

PRW

PRESP

30 μs

EEMEM

, and CL.

PULL-UP

pulsed low to refresh wiper positions

PR

= 25°C 1

A

30 μs

MCycles
kCycles
Yea r s

Rev. A | Page 5 of 16