Analog Devices AD5235 b Datasheet

Nonvolatile Memory, Dual

FEATURES

Dual-channel, 1024-position resolution
25 kΩ, 250 kΩ nominal resistance
Low temperature coefficient: 35 ppm/°C
Nonvolatile memory stores wiper settings
Permanent memory write protection
Wiper setting readback
Resistance tolerance stored in EEMEM
Predefined linear increment/decrement instructions
Predefined ±6 dB/step log taper increment/decrement

instructions
SPI® compatible serial interface
3 V to 5 V single supply or ±2.5 V dual supply
26 bytes extra nonvolatile memory for user-defined

information
100-year typical data retention, T
Power-on refreshed with EEMEM settings

APPLICATIONS

DWDM laser diode driver, optical supervisory systems
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage to current conversion
Programmable filters, delays, time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration

GENERAL DESCRIPTION

The AD5235 is a dual-channel, nonvolatile memory,1 digitally
controlled potentiometer
performs the same electronic adjustment function as a
mechanical potentiometer with enhanced resolution, solid state
reliability, and superior low temperature coefficient perform­ance. The AD5235’s versatile programming via an SPI
compatible serial interface allows 16 modes of operation and
adjustment including scratchpad programming, memory
storing and restoring, increment/decrement, ±6 dB/step log
taper adjustment, wiper setting readback, and extra EEMEM for
user-defined information such as memory data for other
components, look-up table, or system identification
information.

2

with 1024-step resolution. The device

= 55°C

A

1024-Position Digital Potentiometer

AD5235

FUNCTIONAL BLOCK DIAGRAM

CS

CLK

SDI

SDO

PR

WP

RDY

ADDR

DECODE

SERIAL

INTERFACE

POWER-ON

RESET

EEMEM

CONTROL

RTOL

REGISTER

REGISTER

26 BYTES

3

USER EEMEM

Figure 1.

RDAC1

EEMEM1

RDAC2

EEMEM2

In the scratchpad programming mode, a specific setting can be
programmed directly to the RDAC
resistance between Terminals W–A and W–B. This setting can
be stored into the EEMEM and is restored automatically to the
RDAC register during system power-on.

The EEMEM content can be restored dynamically or through

PR

external

strobing, and a WP function protects EEMEM
contents. To simplif y the programming, the independent or
simultaneous linear-step increment or decrement commands
can be used to move the RDAC wiper up or down, one step at a
time. For logarithmic ±6 dB changes in wiper setting, the left or
right bit shift command can be used to double or half the
RDAC wiper setting.

AD5235 patterned resistance tolerance is stored in the EEMEM.
The actual end-to-end resistance can, therefore, be known by
the host processor in readback mode. The host can execute the
appropriate resistance step through a software routine that
simplifies open-loop applications as well as precision calibration
and tolerance matching applications.

The AD5235 is available in a thin TSSOP-16 package. The part
is guaranteed to operate over the extended industrial tempera­ture range of −40°C to +85°C.

1

The terms nonvolatile memory and EEMEM are used interchangeably.

2

The terms digital potentiometer and RDAC are used interchangeably.

3

RAB tolerance.

AD5235

RDAC1

RDAC2

2

register, which sets the

V

DD

A1
W1

B1

A2
W2

B2

V

SS

GND

02816-B-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD5235

TABLE OF CONTENTS

Specifications..................................................................................... 3

AD5235EVAL Evaluation Kit................................................... 21

Electrical Characteristics—25 kΩ, 250 kΩ Versions................ 3

Interface Timing Characteristics—25 kΩ, 250 kΩ Versions... 5

Timing Diagrams.......................................................................... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Test Circuits................................................................................. 12

Theory of Operation ...................................................................... 14

Scratchpad and EEMEM Programming.................................. 14

Basic Operation .......................................................................... 14

EEMEM Protection.................................................................... 15

Digital Input/Output Configuration........................................ 15

Serial Data Interface................................................................... 15

Daisy-Chain Operation .............................................................15

Terminal Voltage Operating Range.......................................... 16

Advanced Control Modes ......................................................... 18

RDAC Structure.......................................................................... 19

Programming the Variable Resistor .........................................20

Applications..................................................................................... 22

Bipolar Operation from Dual Supplies.................................... 22

Gain Control Compensation.................................................... 22

High Voltage Operation............................................................. 22

DAC.............................................................................................. 22

Bipolar Programmable Gain Amplifier ................................... 23

10-Bit Bipolar DAC.................................................................... 23

Programmable Voltage Source with Boosted Output............ 23

Programmable Current Source ................................................ 24

Programmable Bidirectional Current Source......................... 24

Programmable Low-Pass Filter ................................................ 24

Programmable Oscillator.......................................................... 25

Optical Transmitter Calibration with ADN2841................... 25

Resistance Scaling ...................................................................... 26

Resistance Tolerance, Drift, and Temperature Coefficient

Mismatch Considerations......................................................... 26

RDAC Circuit Simulation Model............................................. 27

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 28

Programming the Potentiometer Divider............................... 20

Programming Examples............................................................ 21

REVISION HISTORY

7/04—Data Sheet Changed from REV. A to REV. B

Updated Formatting........................................................... Universal

Edits to Features, General Description, and Block Diagram .......1

Changes to Specifications.................................................................3

Replaced Timing Diagrams..............................................................6

Changes to Absolute Maximum Ratings ........................................7

Changes to Pin Function Descriptions...........................................8

Changes to Typical Performance Characteristics..........................9

Additional Test Circuit (Figure 36).................................................9

Rev.B | Page 2 of 28

Edits to Theory of Operation.........................................................14

Edits to Applications .......................................................................23

Updated Outline Dimensions........................................................27

8/02—Data Sheet Changed from REV. 0 to REV. A

Change to Features and General Description................................ 1

Change to Specifications ..................................................................2

Change to Calculating Actual End-to-End Terminal

Resistance Section ..........................................................................14

AD5235

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—25 KΩ, 250 KΩ VERSIONS

VDD = 3 V to 5.5 V, VSS = 0 V, VA = VDD, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted.
The part can be operated at 2.7 V single supply, except from 0°C to −40°C, where a minimum of 3 V is needed.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS— RHEOSTAT MODE (All RDACs)

Resistor Differential Nonlinearity2 R-DNL RWB −2 +2 LSB
Resistor Integral Nonlinearity2 R-INL RWB −4 +4 LSB
Nominal Resistor Tolerance ∆RAB/RAB Dx = 0x3FF −30 +30 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C
Wiper Resistance RW

= 1 V/RWB, VDD = 5 V,

I

W

Code = 0x200

= 1 V/RWB, VDD = 3 V,

I

W

Code = 0x200

Channel Resistance Matching R

Ch 1 and 2 RWB, Dx = 0x3FF ±0.1 %

AB1/RAB2

DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE (All RDACs)

Resolution N 10 Bits
Differential Nonlinearity3 DNL −2 +2 LSB
Integral Nonlinearity3 INL −4 +4 LSB
Voltage Divider Temperature

(∆V

)/∆T × 106 Code = half-scale 15 ppm/°C

W/VW

Coefficient
Full-Scale Error V
Zero-Scale Error V

Code = full scale −6 0 LSB

WFSE

Code = zero scale 0 4 LSB

WZSE

RESISTOR TERMINALS

Terminal Voltage Range4 V
Capacitance5 Ax, Bx C

V

A, B, W

f = 1 MHz, measured to GND,

A, B

Code = half-scale

Capacitance5 Wx CW f = 1 MHz, measured to GND,

Code = half-scale

Common-Mode Leakage Current

5 , 6

ICM V

= VDD/2 0.01 ±2 µA

W

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH With respect to GND, VDD = 5 V 2.4 V
Input Logic Low VIL With respect to GND, VDD = 5 V 0.8 V
Input Logic High VIH With respect to GND, VDD = 3 V 2.1 V
Input Logic Low VIL With respect to GND, VDD = 3 V 0.6 V
Input Logic High VIH

Input Logic Low VIL

Output Logic High (SDO, RDY) VOH

With respect to GND, V
+2.5 V, V

= −2.5 V

SS

With respect to GND, V
+2.5 V, V

R

PULL-UP

= −2.5 V

SS

= 2.2 kΩ to 5 V

=

DD

=

DD

(see Figure 25)

Output Logic Low VOL

= 1.6 mA, V

I

OL

LOGIC

= 5 V

(see Figure 25)
Input Current IIL V
Input Capacitance5 C

5 pF

IL

= 0 V or VDD ±2.25 µA

IN

POWER SUPPLIES

Single-Supply Power Range VDD V

= 0 V 3.0 5.5 V

SS

Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD V
I

V

DD

Negative Supply Current ISS

= VDD or VIL = GND, TA = 25°C 2 4.5 µA

IH

= VDD or VIL = GND 3.5 6.0 µA

IH

= VDD or VIL = GND,

V

IH

V

= +2.5 V, VSS = −2.5 V

DD

50 100 Ω

200 Ω

VDD V

SS

11 pF

80 pF

2.0 V

0.5 V

4.9 V

0.4 V

3.5 6.0 µA

Rev. B | Page 3 of 28

AD5235

Parameter Symbol Conditions Min Typ1 Max Unit

EEMEM Store Mode Current IDD (store)

I
EEMEM Restore Mode Current7 I

I
Power Dissipation8 P
Power Supply Sensitivity5 P

DYNAMIC CHARACTERISTICS

5, 9

(store) VDD = +2.5 V, VSS = −2.5 V −35 mA

SS

(restore)

DD

(restore) VDD = +2.5 V, VSS = −2.5 V −0.3 −3 −9 mA

SS

V

DISS

∆VDD = 5 V ± 10% 0.002 0.01 %/%

SS

Bandwidth BW

Total Harmonic Distortion THDW V

VW Settling Time tS

= VDD or VIL = GND,

V

IH

V

= GND, ISS ≈ 0

SS

= VDD or VIL = GND,

V

IH

= GND, ISS ≈ 0

V

SS

= VDD or VIL = GND 18 50 µW

IH

−3 dB, V
= 25 kΩ/250 kΩ

R

AB

= 1 V rms, VB = 0 V, f = 1 kHz 0.05 %

A

= 1 V rms, VB = 0 V, f = 1 kHz,

V

A

= 50 kΩ, 100 kΩ

R

AB

= VDD, VB = 0 V,

V

A

V

= 0.50% error band,

W

DD/VSS

= ±2.5 V,

Code 0x000 to 0x200,
R

= 25 kΩ/250 kΩ

AB

Resistor Noise Density e
Crosstalk (CW1/CW2) CT

R

N_WB

= 25 kΩ/250 kΩ, TA = 25°C 20/64

AB

= VDD, VB = 0 V, measured VW1

V

A

with V

making full-scale

W2

change

Analog Crosstalk CTA

= VA1 = +2.5 V, VSS = VB1 =

V

DD

−2.5 V, measured V

W1

with VW2 =
5 V p-p @ f = 1 kHz, Code 1 =
0x200, Code 2 = 0x3FF,
R

= 25 kΩ/250 kΩ

AB

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from ideal between successive tap positions. I

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of

±1 LSB maximum are guaranteed monotonic operating conditions (see Figure 26).

4

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment.

5

Guaranteed by design and not subject to production test.

6

Common-mode leakage current is a measure of the dc leakage from any Terminal B–W to a common-mode bias level of VDD/2.

7

EEMEM restore mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 22). To minimize

power dissipation, a NOP, Instruction 0 (0x0) should be issued immediately after Instruction 1 (0x1).

8

P

is calculated from (IDD × VDD) + (ISS × VSS).

DISS

9

All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.

~ 50 µA for VDD = 2.7 V and IW ~ 400 µA for VDD = 5 V (see Figure 25).

W

35 mA

0.3 3 9 mA

125/12 kHz

0.045 %

4/36 µs

90/21

nV/√
nV-s

Hz

−81/−62 dB

Rev. B | Page 4 of 28

AD5235

INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 KΩ, 250 KΩ VERSIONS

Guaranteed by design and not subject to production test.

See the Timing Diagrams section for the location of measured values. All input control voltages are specified with t
90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V

= 3 V and 5 V.

DD

= tF = 2.5 ns (10% to

R

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

Clock Cycle Time (t
CS Setup Time
CLK Shutdown Time to CS Rise

) t1 20 ns

CYC

t

10 ns

2

t

1 t

3

CYC

Input Clock Pulse Width t4, t5 Clock level high or low 10 ns
Data Setup Time t6 From positive CLK transition 5 ns
Data Hold Time t7 From positive CLK transition 5 ns

t

CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay2 t
CLK to SDO Data Hold Time t11 R
CS High Pulse Width3
CS High to CS High3
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Store/Read EEMEM Time4 t
CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous) t
Preset Response Time to Wiper Setting t
Power-On EEMEM Restore Time t

40 ns

8

t

50 ns

9

R

10

t

12

t

4 t

13

t

0 ns

14

t

0.15 0.3 ms

15

Applies to instructions 0x2, 0x3, and 0x9 30 ms

16

t

10 ns

17

Not shown in timing diagram 50 ns

PRW

PRESP

140 µs

EEMEM1

= 2.2 kΩ, CL < 20 pF 50 ns

P

= 2.2 kΩ, CL < 20 pF 0 ns

P

pulsed low to refresh wiper positions

PR

10 ns

140 µs

CYC

FLASH/EE MEMORY RELIABILITY

Endurance5 100
Data Retention6 100

kCycles
Years

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Propagation delay depends on the value of VDD, R

3

Valid for commands that do not activate the RDY pin.

4

RDY pin low only for Instructions 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.1 ms; CMD_2, 3 ~ 20 ms. Device operation at TA = −40°C and

V

< 3 V extends the save time to 35 ms.

DD

5

Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.

6

Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV

derates with junction temperature in the Flash/EE memory.

PULL-UP

, and CL.

Rev. B | Page 5 of 28

AD5235

TIMING DIAGRAMS

CPHA = 1

CS

CLK

CPOL = 1

SDI

SDO

RDY

t

t

t

2

HIGH
OR LOW

t

8

B24* B23–MSB B0–LSB

t

14

*NOTE: EXTRA BIT THAT IS NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.

THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

1

t

B23 B0

5

t

4

t

7

t

6

B23–MSB

t

10

B0–LSB

t

11

3

t

12

t

13

t

17

HIGH
OR LOW

t

9

t

15

t

16

02816-B-002

Figure 2. CPHA = 1 Timing Diagram

CPHA = 0

CLK

CPOL = 0

SDI

CS

HIGH
OR LOW

t

2

B23–MSB IN

t

1

t

B23 B0

5

t

4

t

7

t

6

B0–LSB

t

3

t

12

t

13

t

17

HIGH
OR LOW

SDO

RDY

t

8

B23–MSB OUT B0–LSB

t

14

*NOTE: EXTRA BIT THAT IS NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.

THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

t

10

t

11

t

9

*

t

15

t

16

02816-B-003

Figure 3. CPHA = 0 Timing Diagram

Rev. B | Page 6 of 28

AD5235

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V, +7 V
VSS to GND +0.3 V, −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS − 0.3 V, VDD + 0.3 V
IA, IB, IW

Pulsed1 ±20 mA

Continuous ±2 mA
Digital Input and Output Voltage to GND −0.3 V, VDD + 0.3 V
Operating Temperature Range2 −40°C to +85°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature −65°C to +150°C
Lead Temperature, Soldering

Vapor Phase (60 s) 215°C

Infrared (15 s) 220°C
Thermal Resistance Junction-to-Ambient

θ

,TSSOP-16

JA

Thermal Resistance Junction-to-Case θJC,

TSSOP-16
Package Power Dissipation (TJ max − TA)/θJA

150°C/W

28°C/W

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Includes programming of nonvolatile memory.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 7 of 28

AD5235

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK

SDI

SDO

GND

V

W1

SS

A1

B1

1

2

3

AD5235BRU

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

RDY

15

CS

14

PR

13

WP
V

12

DD

A2

11

10

W2

9

B2

02816-B-005

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
2 SDI Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
3 SDO Serial Data Output. Serves readback and daisy-chain functions.

Commands 9 and 10 activate the SDO output for the readback function, delayed by 24 or 25 clock pulses,
depending on the clock polarity before and after the data-word (see Figure 2, Figure 3, and Table 7).

In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 24 or 25 clock pulses
depending on the clock polarity (see Figure 2 and Figure 3). This previously shifted-out SDI can be used for daisy­chaining multiple devices.

Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed.
4 GND Ground Pin, Logic Ground Reference.
5 VSS

Negative Supply. Connect to 0 V for single-supply applications. If V

is used in dual supply, it must be able to sink

SS

35 mA for 30 ms when storing data to EEMEM.
6 A1 Terminal A of RDAC1.
7 W1 Wiper terminal of RDAC1. ADDR(RDAC1) = 0x0.
8 B1 Terminal B of RDAC1.
9 B2 Terminal B of RDAC2.
10 W2 Wiper terminal of RDAC2. ADDR(RDAC2) = 0x1.
11 A2 Terminal A of RDAC2.
12 VDD Positive Power Supply.
13

Optional Write Protect. When active low, WP prevents any changes to the present contents, except PR strobe.

WP

CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Execute a NOP instruction before returning to WP

14

15

Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM

PR

Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.

CS

16 RDY

high. Tie WP

register. Factory default loads midscale 512

at the logic high transition. Tie PR

Ready. Active-high open-drain output. Identifies completion of Instructions 2, 3, 8, 9, 10, and PR

to VDD, if not used.

until EEMEM is loaded with a new value by the user. PR is activated

10

to VDD, if not used.

.

Rev. B | Page 8 of 28

AD5235

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 200 400 600 1000

Figure 5. INL vs. Code, T

1.0

0.8

0.6

0.4

0.2

0.0
–0.2
–0.4

DNL ERROR (LSB)

–0.6
–0.8
–1.0
–1.2
–1.4

0 200 400 600 1000

Figure 6. DNL vs. Code, T

1.0

0.8

0.6

0.4

0.2

0

R-INL ERROR (LSB)

–0.2

–0.4

–0.6

0 200 400 600 1000

Figure 7. R-INL vs. Code, T

DIGITAL CODE

= −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

A

DIGITAL CODE

= −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

A

DIGITAL CODE

= −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

A

800

800

800

+25°C
–40°C
+85°C

+25°C
–40°C
+85°C

+25°C
–40°C
+85°C

0.4

0.2

0.0

–0.2

R-DNL ERROR (LSB)

–0.4

–0.6

–0.8

0 200 400 600 1000

02816-B-006

Figure 8. R-DNL vs. Code, T

70

60

50

40

30

20

10

0

–10

–20

POTENTIOMETER MODE TEMPCO (ppm/°C)

–30

02816-B-007

0 128 256 512384 640 1023

25kΩ VERSION

250kΩ VERSION

Figure 9. (∆V

120

100

80

60

40

20

0

–20

–40

RHEOSTAT MODE TEMPCO (ppm/°C)

–60

–80

0 128 256 512384 640 1023

02816-B-008

25kΩ VERSION

250kΩ VERSION

Figure 10. (∆R

DIGITAL CODE

= −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

A

CODE (Decimal)

)/∆T × 106 Potentiometer Mode Tempco

W/VW

CODE (Decimal)

)/∆T × 106 Rheostat Mode Tempco

WB/RWB

+25°C
–40°C
+85°C

800

VDD/VSS = 5V/0V
T

= 25°C

A

768 896

VDD/VSS = 5V/0V
T

= 25°C

A

768 896

02816-B-009

02816-B-010

02816-B-011

Rev. B | Page 9 of 28