Datasheet AD5235 Datasheet (Analog Devices)

Nonvolatile Memory, Dual

FEATURES

Dual-channel, 1024-position resolution
25 kΩ, 250 kΩ nominal resistance
Low temperature coefficient: 35 ppm/°C
Nonvolatile memory stores wiper settings
Permanent memory write protection
Wiper setting readback
Resistance tolerance stored in EEMEM
Predefined linear increment/decrement instructions
Predefined ±6 dB/step log taper increment/decrement

instructions
SPI® compatible serial interface
3 V to 5 V single supply or ±2.5 V dual supply
26 bytes extra nonvolatile memory for user-defined

information
100-year typical data retention, T
Power-on refreshed with EEMEM settings

APPLICATIONS

DWDM laser diode driver, optical supervisory systems
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage to current conversion
Programmable filters, delays, time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration

GENERAL DESCRIPTION

The AD5235 is a dual-channel, nonvolatile memory,1 digitally
controlled potentiometer
performs the same electronic adjustment function as a
mechanical potentiometer with enhanced resolution, solid state
reliability, and superior low temperature coefficient perform­ance. The AD5235’s versatile programming via an SPI
compatible serial interface allows 16 modes of operation and
adjustment including scratchpad programming, memory
storing and restoring, increment/decrement, ±6 dB/step log
taper adjustment, wiper setting readback, and extra EEMEM for
user-defined information such as memory data for other
components, look-up table, or system identification
information.

2

with 1024-step resolution. The device

= 55°C

A

1024-Position Digital Potentiometer

AD5235

FUNCTIONAL BLOCK DIAGRAM

CS

CLK

SDI

SDO

PR

WP

RDY

ADDR

DECODE

SERIAL

INTERFACE

POWER-ON

RESET

EEMEM

CONTROL

RTOL

REGISTER

REGISTER

26 BYTES

3

USER EEMEM

Figure 1.

RDAC1

EEMEM1

RDAC2

EEMEM2

In the scratchpad programming mode, a specific setting can be
programmed directly to the RDAC
resistance between Terminals W–A and W–B. This setting can
be stored into the EEMEM and is restored automatically to the
RDAC register during system power-on.

The EEMEM content can be restored dynamically or through

PR

external

strobing, and a WP function protects EEMEM
contents. To simplif y the programming, the independent or
simultaneous linear-step increment or decrement commands
can be used to move the RDAC wiper up or down, one step at a
time. For logarithmic ±6 dB changes in wiper setting, the left or
right bit shift command can be used to double or half the
RDAC wiper setting.

AD5235 patterned resistance tolerance is stored in the EEMEM.
The actual end-to-end resistance can, therefore, be known by
the host processor in readback mode. The host can execute the
appropriate resistance step through a software routine that
simplifies open-loop applications as well as precision calibration
and tolerance matching applications.

The AD5235 is available in a thin TSSOP-16 package. The part
is guaranteed to operate over the extended industrial tempera­ture range of −40°C to +85°C.

1

The terms nonvolatile memory and EEMEM are used interchangeably.

2

The terms digital potentiometer and RDAC are used interchangeably.

3

RAB tolerance.

AD5235

RDAC1

RDAC2

2

register, which sets the

V

DD

A1
W1

B1

A2
W2

B2

V

SS

GND

02816-B-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD5235

TABLE OF CONTENTS

Specifications..................................................................................... 3

AD5235EVAL Evaluation Kit................................................... 21

Electrical Characteristics—25 kΩ, 250 kΩ Versions................ 3

Interface Timing Characteristics—25 kΩ, 250 kΩ Versions... 5

Timing Diagrams.......................................................................... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Test Circuits................................................................................. 12

Theory of Operation ...................................................................... 14

Scratchpad and EEMEM Programming.................................. 14

Basic Operation .......................................................................... 14

EEMEM Protection.................................................................... 15

Digital Input/Output Configuration........................................ 15

Serial Data Interface................................................................... 15

Daisy-Chain Operation .............................................................15

Terminal Voltage Operating Range.......................................... 16

Advanced Control Modes ......................................................... 18

RDAC Structure.......................................................................... 19

Programming the Variable Resistor .........................................20

Applications..................................................................................... 22

Bipolar Operation from Dual Supplies.................................... 22

Gain Control Compensation.................................................... 22

High Voltage Operation............................................................. 22

DAC.............................................................................................. 22

Bipolar Programmable Gain Amplifier ................................... 23

10-Bit Bipolar DAC.................................................................... 23

Programmable Voltage Source with Boosted Output............ 23

Programmable Current Source ................................................ 24

Programmable Bidirectional Current Source......................... 24

Programmable Low-Pass Filter ................................................ 24

Programmable Oscillator.......................................................... 25

Optical Transmitter Calibration with ADN2841................... 25

Resistance Scaling ...................................................................... 26

Resistance Tolerance, Drift, and Temperature Coefficient

Mismatch Considerations......................................................... 26

RDAC Circuit Simulation Model............................................. 27

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 28

Programming the Potentiometer Divider............................... 20

Programming Examples............................................................ 21

REVISION HISTORY

7/04—Data Sheet Changed from REV. A to REV. B

Updated Formatting........................................................... Universal

Edits to Features, General Description, and Block Diagram .......1

Changes to Specifications.................................................................3

Replaced Timing Diagrams..............................................................6

Changes to Absolute Maximum Ratings ........................................7

Changes to Pin Function Descriptions...........................................8

Changes to Typical Performance Characteristics..........................9

Additional Test Circuit (Figure 36).................................................9

Rev.B | Page 2 of 28

Edits to Theory of Operation.........................................................14

Edits to Applications .......................................................................23

Updated Outline Dimensions........................................................27

8/02—Data Sheet Changed from REV. 0 to REV. A

Change to Features and General Description................................ 1

Change to Specifications ..................................................................2

Change to Calculating Actual End-to-End Terminal

Resistance Section ..........................................................................14

AD5235

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—25 KΩ, 250 KΩ VERSIONS

VDD = 3 V to 5.5 V, VSS = 0 V, VA = VDD, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted.
The part can be operated at 2.7 V single supply, except from 0°C to −40°C, where a minimum of 3 V is needed.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS— RHEOSTAT MODE (All RDACs)

Resistor Differential Nonlinearity2 R-DNL RWB −2 +2 LSB
Resistor Integral Nonlinearity2 R-INL RWB −4 +4 LSB
Nominal Resistor Tolerance ∆RAB/RAB Dx = 0x3FF −30 +30 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C
Wiper Resistance RW

= 1 V/RWB, VDD = 5 V,

I

W

Code = 0x200

= 1 V/RWB, VDD = 3 V,

I

W

Code = 0x200

Channel Resistance Matching R

Ch 1 and 2 RWB, Dx = 0x3FF ±0.1 %

AB1/RAB2

DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE (All RDACs)

Resolution N 10 Bits
Differential Nonlinearity3 DNL −2 +2 LSB
Integral Nonlinearity3 INL −4 +4 LSB
Voltage Divider Temperature

(∆V

)/∆T × 106 Code = half-scale 15 ppm/°C

W/VW

Coefficient
Full-Scale Error V
Zero-Scale Error V

Code = full scale −6 0 LSB

WFSE

Code = zero scale 0 4 LSB

WZSE

RESISTOR TERMINALS

Terminal Voltage Range4 V
Capacitance5 Ax, Bx C

V

A, B, W

f = 1 MHz, measured to GND,

A, B

Code = half-scale

Capacitance5 Wx CW f = 1 MHz, measured to GND,

Code = half-scale

Common-Mode Leakage Current

5 , 6

ICM V

= VDD/2 0.01 ±2 µA

W

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH With respect to GND, VDD = 5 V 2.4 V
Input Logic Low VIL With respect to GND, VDD = 5 V 0.8 V
Input Logic High VIH With respect to GND, VDD = 3 V 2.1 V
Input Logic Low VIL With respect to GND, VDD = 3 V 0.6 V
Input Logic High VIH

Input Logic Low VIL

Output Logic High (SDO, RDY) VOH

With respect to GND, V
+2.5 V, V

= −2.5 V

SS

With respect to GND, V
+2.5 V, V

R

PULL-UP

= −2.5 V

SS

= 2.2 kΩ to 5 V

=

DD

=

DD

(see Figure 25)

Output Logic Low VOL

= 1.6 mA, V

I

OL

LOGIC

= 5 V

(see Figure 25)
Input Current IIL V
Input Capacitance5 C

5 pF

IL

= 0 V or VDD ±2.25 µA

IN

POWER SUPPLIES

Single-Supply Power Range VDD V

= 0 V 3.0 5.5 V

SS

Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD V
I

V

DD

Negative Supply Current ISS

= VDD or VIL = GND, TA = 25°C 2 4.5 µA

IH

= VDD or VIL = GND 3.5 6.0 µA

IH

= VDD or VIL = GND,

V

IH

V

= +2.5 V, VSS = −2.5 V

DD

50 100 Ω

200 Ω

VDD V

SS

11 pF

80 pF

2.0 V

0.5 V

4.9 V

0.4 V

3.5 6.0 µA

Rev. B | Page 3 of 28

AD5235

Parameter Symbol Conditions Min Typ1 Max Unit

EEMEM Store Mode Current IDD (store)

I
EEMEM Restore Mode Current7 I

I
Power Dissipation8 P
Power Supply Sensitivity5 P

DYNAMIC CHARACTERISTICS

5, 9

(store) VDD = +2.5 V, VSS = −2.5 V −35 mA

SS

(restore)

DD

(restore) VDD = +2.5 V, VSS = −2.5 V −0.3 −3 −9 mA

SS

V

DISS

∆VDD = 5 V ± 10% 0.002 0.01 %/%

SS

Bandwidth BW

Total Harmonic Distortion THDW V

VW Settling Time tS

= VDD or VIL = GND,

V

IH

V

= GND, ISS ≈ 0

SS

= VDD or VIL = GND,

V

IH

= GND, ISS ≈ 0

V

SS

= VDD or VIL = GND 18 50 µW

IH

−3 dB, V
= 25 kΩ/250 kΩ

R

AB

= 1 V rms, VB = 0 V, f = 1 kHz 0.05 %

A

= 1 V rms, VB = 0 V, f = 1 kHz,

V

A

= 50 kΩ, 100 kΩ

R

AB

= VDD, VB = 0 V,

V

A

V

= 0.50% error band,

W

DD/VSS

= ±2.5 V,

Code 0x000 to 0x200,
R

= 25 kΩ/250 kΩ

AB

Resistor Noise Density e
Crosstalk (CW1/CW2) CT

R

N_WB

= 25 kΩ/250 kΩ, TA = 25°C 20/64

AB

= VDD, VB = 0 V, measured VW1

V

A

with V

making full-scale

W2

change

Analog Crosstalk CTA

= VA1 = +2.5 V, VSS = VB1 =

V

DD

−2.5 V, measured V

W1

with VW2 =
5 V p-p @ f = 1 kHz, Code 1 =
0x200, Code 2 = 0x3FF,
R

= 25 kΩ/250 kΩ

AB

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from ideal between successive tap positions. I

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of

±1 LSB maximum are guaranteed monotonic operating conditions (see Figure 26).

4

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment.

5

Guaranteed by design and not subject to production test.

6

Common-mode leakage current is a measure of the dc leakage from any Terminal B–W to a common-mode bias level of VDD/2.

7

EEMEM restore mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 22). To minimize

power dissipation, a NOP, Instruction 0 (0x0) should be issued immediately after Instruction 1 (0x1).

8

P

is calculated from (IDD × VDD) + (ISS × VSS).

DISS

9

All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.

~ 50 µA for VDD = 2.7 V and IW ~ 400 µA for VDD = 5 V (see Figure 25).

W

35 mA

0.3 3 9 mA

125/12 kHz

0.045 %

4/36 µs

90/21

nV/√
nV-s

Hz

−81/−62 dB

Rev. B | Page 4 of 28

AD5235

INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 KΩ, 250 KΩ VERSIONS

Guaranteed by design and not subject to production test.

See the Timing Diagrams section for the location of measured values. All input control voltages are specified with t
90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V

= 3 V and 5 V.

DD

= tF = 2.5 ns (10% to

R

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

Clock Cycle Time (t
CS Setup Time
CLK Shutdown Time to CS Rise

) t1 20 ns

CYC

t

10 ns

2

t

1 t

3

CYC

Input Clock Pulse Width t4, t5 Clock level high or low 10 ns
Data Setup Time t6 From positive CLK transition 5 ns
Data Hold Time t7 From positive CLK transition 5 ns

t

CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay2 t
CLK to SDO Data Hold Time t11 R
CS High Pulse Width3
CS High to CS High3
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Store/Read EEMEM Time4 t
CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous) t
Preset Response Time to Wiper Setting t
Power-On EEMEM Restore Time t

40 ns

8

t

50 ns

9

R

10

t

12

t

4 t

13

t

0 ns

14

t

0.15 0.3 ms

15

Applies to instructions 0x2, 0x3, and 0x9 30 ms

16

t

10 ns

17

Not shown in timing diagram 50 ns

PRW

PRESP

140 µs

EEMEM1

= 2.2 kΩ, CL < 20 pF 50 ns

P

= 2.2 kΩ, CL < 20 pF 0 ns

P

pulsed low to refresh wiper positions

PR

10 ns

140 µs

CYC

FLASH/EE MEMORY RELIABILITY

Endurance5 100
Data Retention6 100

kCycles
Years

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Propagation delay depends on the value of VDD, R

3

Valid for commands that do not activate the RDY pin.

4

RDY pin low only for Instructions 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.1 ms; CMD_2, 3 ~ 20 ms. Device operation at TA = −40°C and

V

< 3 V extends the save time to 35 ms.

DD

5

Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.

6

Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV

derates with junction temperature in the Flash/EE memory.

PULL-UP

, and CL.

Rev. B | Page 5 of 28

AD5235

TIMING DIAGRAMS

CPHA = 1

CS

CLK

CPOL = 1

SDI

SDO

RDY

t

t

t

2

HIGH
OR LOW

t

8

B24* B23–MSB B0–LSB

t

14

*NOTE: EXTRA BIT THAT IS NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.

THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

1

t

B23 B0

5

t

4

t

7

t

6

B23–MSB

t

10

B0–LSB

t

11

3

t

12

t

13

t

17

HIGH
OR LOW

t

9

t

15

t

16

02816-B-002

Figure 2. CPHA = 1 Timing Diagram

CPHA = 0

CLK

CPOL = 0

SDI

CS

HIGH
OR LOW

t

2

B23–MSB IN

t

1

t

B23 B0

5

t

4

t

7

t

6

B0–LSB

t

3

t

12

t

13

t

17

HIGH
OR LOW

SDO

RDY

t

8

B23–MSB OUT B0–LSB

t

14

*NOTE: EXTRA BIT THAT IS NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.

THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

t

10

t

11

t

9

*

t

15

t

16

02816-B-003

Figure 3. CPHA = 0 Timing Diagram

Rev. B | Page 6 of 28

AD5235

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V, +7 V
VSS to GND +0.3 V, −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS − 0.3 V, VDD + 0.3 V
IA, IB, IW

Pulsed1 ±20 mA

Continuous ±2 mA
Digital Input and Output Voltage to GND −0.3 V, VDD + 0.3 V
Operating Temperature Range2 −40°C to +85°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature −65°C to +150°C
Lead Temperature, Soldering

Vapor Phase (60 s) 215°C

Infrared (15 s) 220°C
Thermal Resistance Junction-to-Ambient

θ

,TSSOP-16

JA

Thermal Resistance Junction-to-Case θJC,

TSSOP-16
Package Power Dissipation (TJ max − TA)/θJA

150°C/W

28°C/W

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Includes programming of nonvolatile memory.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 7 of 28

AD5235

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK

SDI

SDO

GND

V

W1

SS

A1

B1

1

2

3

AD5235BRU

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

RDY

15

CS

14

PR

13

WP
V

12

DD

A2

11

10

W2

9

B2

02816-B-005

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
2 SDI Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
3 SDO Serial Data Output. Serves readback and daisy-chain functions.

Commands 9 and 10 activate the SDO output for the readback function, delayed by 24 or 25 clock pulses,
depending on the clock polarity before and after the data-word (see Figure 2, Figure 3, and Table 7).

In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 24 or 25 clock pulses
depending on the clock polarity (see Figure 2 and Figure 3). This previously shifted-out SDI can be used for daisy­chaining multiple devices.

Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed.
4 GND Ground Pin, Logic Ground Reference.
5 VSS

Negative Supply. Connect to 0 V for single-supply applications. If V

is used in dual supply, it must be able to sink

SS

35 mA for 30 ms when storing data to EEMEM.
6 A1 Terminal A of RDAC1.
7 W1 Wiper terminal of RDAC1. ADDR(RDAC1) = 0x0.
8 B1 Terminal B of RDAC1.
9 B2 Terminal B of RDAC2.
10 W2 Wiper terminal of RDAC2. ADDR(RDAC2) = 0x1.
11 A2 Terminal A of RDAC2.
12 VDD Positive Power Supply.
13

Optional Write Protect. When active low, WP prevents any changes to the present contents, except PR strobe.

WP

CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Execute a NOP instruction before returning to WP

14

15

Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM

PR

Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.

CS

16 RDY

high. Tie WP

register. Factory default loads midscale 512

at the logic high transition. Tie PR

Ready. Active-high open-drain output. Identifies completion of Instructions 2, 3, 8, 9, 10, and PR

to VDD, if not used.

until EEMEM is loaded with a new value by the user. PR is activated

10

to VDD, if not used.

.

Rev. B | Page 8 of 28

AD5235

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 200 400 600 1000

Figure 5. INL vs. Code, T

1.0

0.8

0.6

0.4

0.2

0.0
–0.2
–0.4

DNL ERROR (LSB)

–0.6
–0.8
–1.0
–1.2
–1.4

0 200 400 600 1000

Figure 6. DNL vs. Code, T

1.0

0.8

0.6

0.4

0.2

0

R-INL ERROR (LSB)

–0.2

–0.4

–0.6

0 200 400 600 1000

Figure 7. R-INL vs. Code, T

DIGITAL CODE

= −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

A

DIGITAL CODE

= −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

A

DIGITAL CODE

= −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

A

800

800

800

+25°C
–40°C
+85°C

+25°C
–40°C
+85°C

+25°C
–40°C
+85°C

0.4

0.2

0.0

–0.2

R-DNL ERROR (LSB)

–0.4

–0.6

–0.8

0 200 400 600 1000

02816-B-006

Figure 8. R-DNL vs. Code, T

70

60

50

40

30

20

10

0

–10

–20

POTENTIOMETER MODE TEMPCO (ppm/°C)

–30

02816-B-007

0 128 256 512384 640 1023

25kΩ VERSION

250kΩ VERSION

Figure 9. (∆V

120

100

80

60

40

20

0

–20

–40

RHEOSTAT MODE TEMPCO (ppm/°C)

–60

–80

0 128 256 512384 640 1023

02816-B-008

25kΩ VERSION

250kΩ VERSION

Figure 10. (∆R

DIGITAL CODE

= −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

A

CODE (Decimal)

)/∆T × 106 Potentiometer Mode Tempco

W/VW

CODE (Decimal)

)/∆T × 106 Rheostat Mode Tempco

WB/RWB

+25°C
–40°C
+85°C

800

VDD/VSS = 5V/0V
T

= 25°C

A

768 896

VDD/VSS = 5V/0V
T

= 25°C

A

768 896

02816-B-009

02816-B-010

02816-B-011

Rev. B | Page 9 of 28

AD5235

36

VDD= 3V

34

= 0V

V

SS

= 25°C

T

A

32

30

28

26

Ω

24

22

20

18

16

0 200 400 800600 1000 1200

CODE (Decimal)

Figure 11. Wiper On Resistance vs. Code

4

0.28
V

= ±2.5V

DD/VSS

= 1V rms

V

0.24

A

0.20

0.16

0.12

THD + NOISE (%)

0.08

0.04

0.00

0.01k 0.1k 1k 10k 100k

02816-B-012

= 250kΩ

R

AB

FREQUENCY (Hz)

25kΩ

02816-B-015

Figure 14. Total Harmonic Distortion vs. Frequency

3

3

IDD@ VDD/VSS= 5V/0V

2

1

CURRENT ( µA)

0

I

@ VDD/VSS= 2.7V/0V

Figure 12. I

= 25kΩ

Figure 13. I

SS

DD

vs. Clock Frequency, RAB = 25 kΩ

DD

–1

–40 –20 0 4020 60 10080

0.25
VDD/VSS= 5V/0V
R

AR

0.20

0.15

(mA)

DD

I

0.10

0.05

0.00

0 2M 4M 6M 8M 10M 12M

I

@ VDD/VSS= 5V/0V

SS

I

@ VDD/VSS= 2.7V/0V

DD

CODE (Decimal)

vs. Temperature, RAB = 25 kΩ

FULL SCALE

MIDSCALE

ZERO SCALE

FREQUENCY (Hz)

0

–3

–6

GAIN (dB)

f

–3dB

–9

V

= ±2.5V

DD/VSS

= 1V rms

V

A

D = MIDSCALE

–12

1k 10k 100k 1M

02816-B-013

R

= 12kHz

FREQUENCY (Hz)

AB

= 250kΩ

f

–3dB

R

= 25kΩ

AB

= 125kHz

02816-B-016

Figure 15. −3 dB Bandwidth vs. Resistance ( Figure 31)

0

CODE 0x200

–10

0x100
0x080

–20

0x040

0x020

–30

GAIN (dB)

02816-B-014

0x010
0x008

–40

0x004
0x002

–50

0x001

–60

1k 10k 100k 1M

FREQUENCY (Hz)

Figure 16. Gain vs. Frequency vs. Code, R

= 25 kΩ ( Figure 31)

AB

02816-B-017

Rev. B | Page 10 of 28

AD5235

0

CODE 0x200

–10

0x100
0x080

–20

0x040

0x020

–30

GAIN (dB)

0x010

0x008

–40

0x004

–50

0x002
0x001

–60

1k 10k 100k 1M

FREQUENCY (Hz)

Figure 17. Gain vs. Frequency vs. Code, R

= 250 kΩ ( Figure 31)

AB

02816-B-018

2.64

2.62

2.60

2.58

2.56

2.54

2.52

2.50

AMPLITUDE (V)

2.48

2.46

2.44

2.42
0

10 20 30 5040

TIME (µS)

Figure 20. Midscale Glitch Energy, R

V

= VSS= 5V

DD

CODE = 0x200 TO 0x1FF

= 25 kΩ, Code 0x200 to 0x1FF

AB

02816-B-021

80

70

60

50

40

PSRR ( –dB)

30

20

= 5V ± 100mV AC

V

DD

V

= 0V, VA = 5V, VB = 0V

SS

10

MEASURED AT V
T

= 25°C

A

0

0.01k 0.1k 1k 10k 100k 10M1M

RAB= 250kΩ

WITH CODE = 0x200

W

FREQUENCY (Hz)

R

Figure 18. PSRR v s. Frequency

VDD= 5V

= 2.25V

V

A

= 0

V

B

= 25°C

T

A

0.5V/DIV

AB

VW(D)

= 25kΩ

V

A

0.5V/DIV

0.5/DIV

2.65

2.60

2.55

2.50

AMPLITUDE (V)

2.45

2.40
0

02816-B-019

Figure 21. Midscale Glitch Energy, R

5V/DIV

5V/DIV

10 20 30 5040

TIME (µS)

= 250 kΩ, Code 0x200 to 0x1FF

AB

CS

CLK

02816-B-022

MIDSCALE

Figure 19. Power-On Reset, V

Previously Stored Code = 0x2AA

50µS/DIV

= 2.25 V,

DD

02816-B-020

Rev. B | Page 11 of 28

5V/DIV

Figure 22. I

4ms/DIV

vs. Time when Storing Data to EEMEM

DD

SDI

I

DD

20mA/DIV

02816-B-023

AD5235

V

100

5V/DIV

5V/DIV

5V/DIV

4ms/DIV

* SUPPLY CURRENT RETURNS TO MINIMUM POWER

CONSUMPTION, IF INSTRUCTION 0 (NOP) IS EXECUTED
IIMMEDIATELY AFTER INSTRUCTION 1 (READ EEMEM).

Figure 23. I

vs. Time when Restoring Data from EEMEM

DD

TEST CIRCUITS

Figure 25 to Figure 35 define the test conditions used in the Specifications section.

NC

DUT
A

W

B

NC = NO CONNECT

Figure 25. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

DUT
A

V+

W

B

Figure 26. Potentiometer Divider Nonlinearity Error

(INL, DNL)

DUT
A

V

W

MS2

W

B

V

MS1

Figure 27. Wiper Resistance

I

W

V

MS

V+ =V
1LSB =V+/2

= VDD/R

I

W

R

W

=

DD

V

MS

[

V

02816-B-026

N

NOMINAL

–V

MS1

02816-B-027

MS2

CS

10

– mA)

CLK

WB_MAX

1

SDI

0.1

IDD*
2mA/DIV

02816-B-024

THEORECTICAL (I

0.01

V+

]

/I

W

02816-B-028

V

~

OFFSET

OFFSET

GND

R

= 25kΩ

AB

R

AB

CODE (Decimal)

Figure 24. I

V

A

A

DD

W

B

V

MS

vs. Code

WB_MAX

V+ = VDD±10%

PSRR (dB) = 20 LOG

PSS (%/%) =

Figure 28. Power Supply Sensitivity

(PSS, PSRR)

ABDUT

W

OP279

OFFSET BIAS

GND

V

IN

Figure 29. Inverting Gain

V

IN

ABDUT

OFFSET BIAS

OP279

W

Figure 30. Noninverting Gain

VA = VB = OPEN
T

= 250kΩ

5V

5V

= 25°C

A

∆V
∆V

896768640512384128 2560

1024

02816-B-025

V

∆

MS

)

(

∆V

DD

%

MS

%

DD

02816-B-029

V

OUT

02816-B-030

V

OUT

02816-B-031

Rev. B | Page 12 of 28

AD5235

RSW=

TO V

DD

0.1V
I

SW

+15V

OP42

–15V

V

W1

DD

A2

W2

V

OUT

B2

V

SS

B1

]

OUT/VIN

02816-B-035

A1

V

OUT

02816-B-032

V

IN

RDAC1 RDAC2

NC

CTA = 20 LOG [V
NC = NO CONNECT

Figure 34. Analog Crosstalk

+

0.1V

–

02816-B-033

TO OUTPUT

PIN

200µAI

C

L

50pF

200µAI

Figure 35. Load Circuit for Measuring V

circuit is equivalent to the application circuit with R

OL

VOH (MIN)
OR
V

(MAX)

OL

OH

and VOL (The diode bridge test

OH

PULL-UP

02816-B-036

of 2.2 kΩ.)

OFFSET

GND

A

V

IN

DUT

W

B

2.5V

Figure 31. Gain vs. Frequency

DUT

W

B

A = NC

CODE = 0x00

I

SW

V

SS

Figure 32. Incremental On Resistance

NC

GND

NC

A

B

NC = NO CONNECT

I

CM

W

V

CM

02816-B-034

V

DUT

V

DD

SS

Figure 33. Common-Mode Leakage Current

Rev. B | Page 13 of 28

AD5235

THEORY OF OPERATION

The AD5235 digital potentiometer is designed to operate as a
true variable resistor. The resistor wiper position is determined
by the RDAC register contents. The RDAC register acts as a
scratchpad register, allowing unlimited changes of resistance
settings. The scratchpad register can be programmed with any
position setting using the standard SPI serial interface by
loading the 24-bit data-word. In the format of the data-word,
the first four bits are commands, the following four bits are
addresses, and the last 16 bits are data. Once a specified value is
set, this value can be stored in a corresponding EEMEM
register. During subsequent power-up, the wiper setting is
automatically loaded to that value.

Storing data to EEMEM takes about 25 ms and consumes
approximately 35 mA. During this time, the shift register is
locked, preventing any changes from taking place. The RDY pin
pulses low to indicate the completion of this EEMEM storage.
There are also 13 addresses with two bytes each of user-defined
data that can be stored in EEMEM.

The following instructions facilitate the user’s programming
needs (see Table 7 for details):

0. Do nothing.

1. Restore EEMEM content to RDAC.

2. Store RDAC setting to EEMEM.

3. Store RDAC setting or user data to EEMEM.

4. Decrement 6 dB.

5. Decrement all 6 dB.

6. Decrement one step.

7. Decrement all one step.

8. Reset EEMEM content to RDAC.

9. Read EEMEM content from SDO.

10. Read RDAC wiper setting from SDO.

11. Write d ata t o RDAC.

12. Increment 6 dB.

13. Increment all 6 dB.

14. Increment one step.

15. Increment all one step.

SCRATCHPAD AND EEMEM PROGRAMMING

The scratchpad RDAC register directly controls the position of
the digital potentiometer wiper. For example, when the scratch­pad register is loaded with all zeros, the wiper is connected to
Terminal B of the variable resistor. The scratchpad register is a
standard logic register with no restriction on the number of
changes allowed, but the EEMEM registers have a program
erase/write cycle limitation.

BASIC OPERATION

The basic mode of setting the variable resistor wiper position
(programming the scratchpad register) is accomplished by
loading the serial data input register with Instruction 11 (0xB),
Address 0, and the desired wiper position data. When the
proper wiper position is determined, the user can load the serial
data input register with Instruction 2 (0x2), which stores the
wiper position data in the EEMEM register. After 25 ms, the
wiper position is permanently stored in nonvolatile memory.

Table 5 provides a programming example listing the sequence
of serial data input (SDI) words with the serial data output
appearing at the SDO pin in hexadecimal format.

Table 5. Write and Store RDAC Settings to EEMEM
Registers

SDI SDO Action

0xB00100 0xXXXXXX

0x20XXXX 0xB00100

0xB10200 0x20XXXX

0x21XXXX 0xB10200

At system power-on, the scratchpad register is automatically
refreshed with the value previously stored in the corresponding
EEMEM register. The factory-preset EEMEM value is midscale.
The scratchpad register can also be refreshed with the contents
of the EEMEM register in three different ways. First, executing
Instruction 1 (0x1) restores the corresponding EEMEM value.
Second, executing Instruction 8 (0x8) resets both channels’
EEMEM values. Finally, pulsing the
EEMEM settings. Operating the hardware control
requires a complete pulse signal. When
logic sets the wiper at midscale. The EEMEM value is not
loaded until

PR

returns high.

Writes data 0x100 to the RDAC1
register, Wiper W1 moves to 1/4 full­scale position.

Stores RDAC1 register content into
the EEMEM1 register.

Writes 0x200 data into the RDAC2
register, Wiper W2 moves to 1/2 full­scale position.

Stores RDAC2 register contents into
EEMEM2 register.

PR

pin refreshes both

PR

function

PR

goes low, the internal

Table 14 to Table 20 provide programming examples that use
some of these commands.

Rev. B | Page 14 of 28

AD5235

K

EEMEM PROTECTION

The write protect (WP) pin disables any changes to the
scratchpad register contents, except for the EEMEM setting,
which can still be restored using Instruction 1, Instruction 8,

PR

and the
hardware EEMEM protection feature. To disable

pulse. Therefore, WP can be used to provide a

WP

, it is
recommended to execute a NOP instruction before returning
WP

to logic high.

DIGITAL INPUT/OUTPUT CONFIGURATION

All digital inputs are ESD protected, high input impedance that
can be driven directly from most digital sources. Active at logic

PR

low,

and WP must be tied to VDD, if they are not used. No
internal pull-up resistors are present on any digital input pins.
To avoid floating digital pins that might cause false triggering in
a noisy environment, pull-up resistors should be added. This is
applicable when the device is detached from the driving source
once it is programmed.

The SDO and RDY pins are open-drain digital outputs that
need pull-up resistors only if these functions are used. To
optimize the speed and power trade-off, use 2.2 kΩ pull-up
resistors.

V

DD

INPUT

Ω

WP

Figure 38. Equivalent

300

GND

WP

Input Protection

02816-B-039

SERIAL DATA INTERFACE

The AD5235 contains a 4-wire SPI compatible digital interface

CS

(SDI, SDO,
loaded with MSB first. The format of the word is shown in
Table 6. The command bits (C0 to C3) control the operation of
the digital potentiometer according to the command shown in
Table 7. A0 to A3 are the address bits. A0 is used to address
RDAC1 or RDAC2. Addresses 2 to 14 are accessible by users for
extra EEMEM. Address 15 is reserved for factory usage. Table 9
provides an address map of the EEMEM locations. The data bits
(D0 to D9) are the values for the RDAC registers. The data bits
(D0 to D15) are the values for the EEMEM registers.

, and CLK). The 24-bit serial data-word must be

The equivalent serial data input and output logic is shown in
Figure 36. The open-drain output SDO is disabled whenever

CS

chip-select

is in logic high. ESD protection of the digital

inputs is shown in Figure 37 and Figure 38.

PR WP

VALID

COMMAND

COUNTER

CL

CS

SDI

Figure 36. Equivalent Digital Input-Output Logic

LOGIC

PINS

Figure 37. Equivalent ESD Digital Input Protection

COMMAND

PROCESSOR

AND ADDRESS

DECODE

SERIAL

REGISTER

AD5235

INPUTS

300

Ω

V

GND

5V

R

PULL-UP

(FOR DAISY
CHAIN ONLY)

SDO

GND

DD

02816-B-038

The AD5235 has an internal counter that counts a multiple of
24 bits (a frame) for proper operation. For example, AD5235
works with a 24-bit or 48-bit word, but it cannot work properly
with a 23-bit or 25-bit word. In addition, AD5235 has a subtle

CS

feature that, if

is pulsed without CLK and SDI, the part
repeats the previous command (except during power-up). As a
result, care must be taken to ensure that no excessive noise
exists in the CLK or

CS

line that might alter the effective
number-of-bits pattern. Also, to prevent data from mislocking
(due to noise, for example), the counter resets, if the count is not
a multiple of four when

CS

goes high.

The SPI interface can be used in two slave modes: CPHA = 1,
CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to
the control bits that dictate SPI timing in the following

02816-B-037

MicroConverters and microprocessors: ADuC812/ADuC824,
M68HC11, and MC68HC16R1/MC68HC 916R1.

DAISY-CHAIN OPERATION

The serial data output pin (SDO) serves two purposes. It can be
used to read the contents of the wiper setting and EEMEM
values using Instructions 10 and 9, respectively. The remaining
instructions (0 to 8, 11 to 15) are valid for daisy-chaining
multiple devices in simultaneous operations. Daisy-chaining
minimizes the number of port pins required from the
controlling IC (Figure 39). The SDO pin contains an open-drain
N-Ch FET that requires a pull-up resistor, if this function is
used. As shown in Figure 39, users need to tie the SDO pin of
one package to the SDI pin of the next package. Users might
need to increase the clock period, because the pull-up resistor

Rev. B | Page 15 of 28

AD5235

and the capacitive loading at the SDO–SDI interface might
require additional time delay between subsequent devices.

When two AD5235s are daisy-chained, 48 bits of data are
required. The first 24 bits (formatted 4-bit command, 4-bit
address, and 16-bit data) go to U2, and the second 24 bits with

CS

the same format go to U1. The
48 bits are clocked into their respective serial registers. The
is then pulled high to complete the operation.

AD5235 AD5235

MOSI

µC

SCLK SS

SDI SDO

U1 U2

CS

CLK CLK

Figure 39. Daisy-Chain Configuration Using SDO

TERMINAL VOLTAGE OPERATING RANGE

The AD5235’s positive VDD and negative VSS power supplies
define the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on Terminals A,
B, and W that exceed V
forward-biased diodes (see Figure 40).

or VSS are clamped by the internal

DD

should be kept low until all

V

DD

R

P

2.2k

Ω

SDI SDO

CS

V

DD

A

W

CS

02816-B-040

the common-mode voltage range of the three terminals extends
from V

to VDD, regardless of the digital input level.

SS

Power-Up Sequence

Because there are diodes to limit the voltage compliance at
Terminals A, B, and W (Figure 40), it is important to power

first before applying any voltage to Terminals A, B,

V

DD/VSS

and W. Otherwise, the diode is forward-biased such that V

DD/VSS

are powered unintentionally. For example, applying 5 V across
Terminals A and B prior to V

causes the VDD terminal to

DD

exhibit 4.3 V. It is not destructive to the device, but it might
affect the rest of the user’s system. The ideal power-up sequence
is GND, V
of powering V
long as they are powered after V

, digital inputs, and VA, VB, and VW. The order

DD/VSS

, VB, VW, and digital inputs is not important as

A

.

DD/VSS

Regardless of the power-up sequence and the ramp rates of the
power supplies, once V

are powered, the power-on preset

DD/VSS

activates, which restores the EEMEM values to the RDAC
registers.

Layout and Power Supply Bypassing

It is a good practice to employ compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.

Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 µF to 0.1 µF disk or chip
ceramic capacitors. Low ESR, 1 µF to 10 µF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance (see Figure 41).

B

V

02816-B-041

SS

Figure 40. Maximum Terminal Voltages Set by V

DD

and V

SS

The ground pin of the AD5235 device is primarily used as a
digital ground reference. To minimize the digital ground
bounce, the AD5235 ground terminal should be joined remotely
to the common ground (see Figure 41). The digital input
control signals to the AD5235 must be referenced to the device
ground pin (GND), and satisfy the logic level defined in the
Specifications section. An internal level-shift circuit ensures that

Rev. B | Page 16 of 28

AD5235

V

DD

10µF

10µFC20.1µF

V

SS

+

C1

C3

0.1µF

+

C4

V

DD

V

SS

GND

02816-B-042

Figure 41. Power Supply Bypassing

AD5235

In Table 6, command bits are C0 to C3, address bits are A0 to A3, data bits D0 to D9 are applicable to RDAC, and D0 to D15 are applicable
to EEMEM.

Table 6. 24-Bit Serial Data-Word

MSB Command Byte 0 Data Byte 1 Data Byte 0 LSB

RDAC C3 C2 C1 C0 0 0 0 A0 X X X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EEMEM C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Command instruction codes are defined in Table 7.

Table 7. Command Operation Truth Table

Command Byte 0 Data Byte 1 Data Byte 0

Command
Number

B23 B16 B15 B8 B7 B0

C3 C2 C1 C0 A3 A2 A1 A0 X … D9 D8 D7 … D0

0 0 0 0 0 X X X X X … X X X … X NOP: Do nothing. See Table 16.
1 0 0 0 1 0 0 0 A0 X … X X X … X Restore EEMEM(A0) contents to RDAC(A0)

2 0 0 1 0 0 0 0 A0 X … X X X … X Store Wiper Setting: Store RDAC(A0) setting to

34 0 0 1 1 A3 A2 A1 A0 D15 … D8 D7 … D0 Store contents of Serial Register Data Bytes 0

45 0 1 0 0 0 0 0 A0 X … X X X … X Decrement 6 dB: Right-shift contents of

55 0 1 0 1 X X X X X … X X X … X Decrement all 6 dB: Right-shift contents of all

65 0 1 1 0 0 0 0 A0 X … X X X … X Decrement contents of RDAC(A0) by 1, stop at

75 0 1 1 1 X X X X X … X X X … X Decrement contents of all RDAC registers by 1,

8 1 0 0 0 0 0 0 0 X … X X X … X Reset: Refresh all RDACs with their correspond-

9 1 0 0 1 A3 A2 A1 A0 X … X X X … X Read contents of EEMEM (ADDR) from SDO

10 1 0 1 0 0 0 0 A0 X … X X X … X Read RDAC wiper setting from SDO output in

11 1 0 1 1 0 0 0 A0 X … D9 D8 D7 … D0 Write contents of Serial Register Data Bytes 0

125 1 1 0 0 0 0 0 A0 X … X X X … X Increment 6 dB: Left-shift contents of

135 1 1 0 1 X X X X X … X X X … X Increment all 6 dB: Left-shift contents of all

145 1 1 1 0 0 0 0 A0 X … X X X … X Increment contents of RDAC(A0) by 1, stop at

155 1 1 1 1 X X X X X … X X X … X Increment contents of all RDAC registers by 1,

1

The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or 10,

the selected internal register data is present in Data Bytes 0 and 1. The instructions following Instructions 9 and 10 must also be a full 24-bit data-word to completely
clock out the contents of the serial register.

2

The RDAC register is a volatile scratchpad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register.

3

Execution of these operations takes place when the CS strobe returns to logic high.

4

Instruction 3 writes two data bytes (16 bits of data) to EEMEM. In the case of Addresses 0 and 1, only the last 10 bits are valid for wiper position setting.

5

The increment, decrement, and shift instructions ignore the contents of the shift register Data Bytes 0 and 1.

1, 2, 3

Operation

register. This command leaves the device in the
read program power state. To return the part to
the idle state, perform NOP instruction 0. See
Table 16.

EEMEM(A0). See Table 15.

and 1 (total 16 bits) to EEMEM(ADDR). See
Table 18.

RDAC(A0) register, stop at all 0s.

RDAC registers, stop at all 0s.

all 0s.

stop at all 0s.

ing EEMEM previously stored values.

output in the next frame. See Table 19.

the next frame. See Table 20.

and 1 (total 10 bits) to RDAC(A0). See Table 14.

RDAC(A0), stop at all 1s. See Table 17.

RDAC registers, stop at all 1s.

all 1s. See Table 15.

stop at all 1s.

Rev. B | Page 17 of 28

AD5235

ADVANCED CONTROL MODES

The AD5235 digital potentiometer includes a set of user
programming features to address the wide number of
applications for these universal adjustment devices.

Key programming features include:

• Scratchpad programming to any desirable values

• Nonvolatile memory storage of the scratchpad RDAC register

value in the EEMEM register

• Increment and decrement instructions for the RDAC wiper

register

• Left and right bit shift of the RDAC wiper register to achieve

±6 dB level changes

• 26 extra bytes of user-addressable nonvolatile memory

Linear Increment and Decrement Instructions

The increment and decrement instructions (14, 15, 6, and 7) are
useful for linear step-adjustment applications. These commands
simplify microcontroller software coding by allowing the
controller to send just an increment or decrement command to
the device. The adjustment can be individual or ganged control.

For an increment command, executing Instruction 14 automati­cally moves the wiper to the next resistance segment position.
The master increment command, Instruction 15, moves all
resistor wipers up by one position.

Logarithmic Taper Mode Adjustment

Four programming instructions produce logarithmic taper
increment and decrement of the wiper position control by
either individual or ganged control. The 6 dB increment is
activated by Instructions 12 and 13, and the 6 dB decrement is
activated by Instructions 4 and 5. For example, executing the
increment Instruction 12 eleven times moves the wiper in 6 dB
per step from 0% to full scale, R
near the maximum setting, the last 6 dB increment instruction
causes the wiper to go to the full-scale 1023 code position.
Further 6 dB per increment instructions do not change the
wiper position beyond its full scale (see Table 8).

. When the wiper position is

AB

data in the RDAC register is automatically set to full scale. This
makes the left-shift function as ideal a logarithmic adjustment
as possible.

The right-shift 4 and 5 instructions are ideal only if the LSB is 0
(ideal logarithmic = no error). If the LSB is a 1, the right-shift
function generates a linear half-LSB error, which translates to a
number-of-bits dependent logarithmic error, as shown in Figure

42. The plot shows the error of the odd numbers of bits for the
AD5235.

Table 8. Detail Left-Shift and Right-Shift Functions for 6 dB
Step Increment and Decrement

Left-Shift Right-Shift

00 0000 0000 11 1111 1111
00 0000 0001 01 1111 1111
00 0000 0010 00 1111 1111
00 0000 0100 00 0111 1111

Left-Shift
(+6 dB/Step)

00 0000 1000 00 0011 1111
00 0001 0000 00 0001 1111
00 0010 0000 00 0000 1111
00 0100 0000 00 0000 0111

Right-Shift

(–6 dB/Step)

00 1000 0000 00 0000 0011
01 0000 0000 00 0000 0001
10 0000 0000 00 0000 0000
11 1111 1111 00 0000 0000
11 1111 1111 00 0000 0000

Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
right-shift 4 and 5 command execution contains an error only
for odd numbers of bits. Even numbers of bits are ideal. The
graph in Figure 42 shows plots of Log_Error [20 × log

10

(error/code)] for the AD5235. For example, Code 3 Log_Error =
20 × log

(0.5/3) = −15.56 dB, which is the worst case. The plot

10

of Log_Error is more significant at the lower codes.

0

–20

–40

dB

The 6 dB step increments and 6 dB step decrements are
achieved by shifting the bit internally to the left or right,
respectively. The following information explains the nonideal
±6 dB step adjustment under certain conditions. Table 8
illustrates the operation of the shifting function on the RDAC
register data bits. Each table row represents a successive shift
operation. Note that the left-shift 12 and 13 instructions were
modified such that, if the data in the RDAC register is equal to
zero and the data is shifted left, the RDAC register is then set to
Code 1. Similarly, if the data in the RDAC register is greater
than or equal to midscale and the data is shifted left, then the

Rev. B | Page 18 of 28

–60

–80

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

0

CODE (From 1 to 1023 by 2.0 × 103)

Figure 42. Plot of Log_Error Conformance for Odd Numbers of Bits Only

(Even Numbers of Bits Are Ideal)

02816-B-043

AD5235

Using CS to Re-Execute a Previous Command

Another subtle feature of the AD5235 is that a subsequent CS
strobe, without clock and data, repeats a previous command.

Using Additional Internal Nonvolatile EEMEM

The AD5235 contains additional user EEMEM registers for
storing any 16-bit data such as memory data for other compo­nents, look-up tables, or system identification information.
Table 9 provides an address map of the internal storage registers
shown in the functional block diagram as EEMEM1, EEMEM2,
and 26 bytes (13 addresses × 2 bytes each) of USER EEMEM.

Table 9. EEMEM Address Map

EEMEM No. Address EEMEM Content for …

1 0000 RDAC1

1, 2

2 0001 RDAC2
3 0010 USER13
4 0011 USER2
… … …
15 1110 USER13
16 1111 R

1

RDAC data stored in EEMEM locations is transferred to the corresponding

RDAC register at power-on, or when Instruction 1, Instruction 8, and
executed.

2

Execution of Instruction 1 leaves the device in the read mode power

consumption state. After the last Instruction 1 is executed, the user should
perform a NOP, Instruction 0, to return the device to the low power idling
state.

3

USERx are internal nonvolatile EEMEM registers available to store and

retrieve constants and other 16-bit information using Instruction 3 and
Instruction 9, respectively.

4

Read only.

Tolerance4

AB1

PR

are

Calculating Actual End-to-End Terminal Resistance

The resistance tolerance is stored in the EEMEM register during
factory testing. The actual end-to-end resistance can, therefore,
be calculated, which is valuable for calibration, tolerance
matching, and precision applications. Note that this value is
read only and the R

matches with R

AB2

, typically 0.1%.

AB1

The resistance tolerance in percentage is contained in the last
16 bits of data in EEMEM Register 15. The format is the sign
magnitude binary format with the MSB designate for sign (0 =
negative and 1 = positive), the next 7 MSB designate the integer
number, and the 8 LSB designate the decimal number (see
Table 11).

For example, if R
shows XXXX XXXX 1001 1100 0000 1111, R

= 250 kΩ and the data in the SDO

AB_RATED

AB_ACTUAL

can be

Table 11. Calculating End-to-End Terminal Resistance

Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Sign
Mag Sign 2

7 Bits for Integer Number Decimal

6

25 24 23 22 21 20

calculated as follows:

MSB: 1 = Positive
Next 7 LSB: 001 1100 = 28

−8

8 LSB: 0000 1111 = 15 × 2

= 0.06
% Tolerance = 28.06%
Therefore, R

AB_ACTUAL

= 320.15 kΩ

RDAC STRUCTURE

The patent-pending RDAC contains multiple strings of equal
resistor segments with an array of analog switches that acts as
the wiper connection. The number of positions is the resolution
of the device. The AD5235 has 1024 connection points, allowing
it to provide better than 0.1% settability resolution. Figure 43
shows an equivalent structure of the connections among the
three terminals of the RDAC. The SW
while the switches SW(0) to SW(2
depending on the resistance position decoded from the data
bits. Because the switch is not ideal, there is a 50 Ω wiper
resistance, R

. Wiper resistance is a function of supply voltage

W

and temperature. The lower the supply voltage or the higher the
temperature, the higher the resulting wiper resistance. Users
should be aware of the wiper resistance dynamics, if accurate
prediction of the output resistance is needed.

R

RDAC

WIPER

REGISTER

AND

DECODER

R

= RAB/2

S

DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY

S

R

S

R

S

N

Figure 43. Equivalent RDAC Structure

Table 10. Nominal Individual Segment Resistor Values

Device Resolution 25 kΩ 250 kΩ

1024-Step 24.4 244

.

2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8

Point

8 Bits for Decimal Number

and SWB are always on,

A

N

−1) are on one at a time,

SW

A

A

N

SW(2

1)

–

W

N

SW(2

–

2)

SW

(1)

SW

(0)

SW

B

B

02816-B-044

Rev. B | Page 19 of 28

AD5235

−

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance of the RDAC between Terminals A
and B, R
1024 positions (10-bit resolution). The final digits of the part
number determine the nominal resistance value, for example,
25 kΩ = 25; 250 kΩ = 250.

The 10-bit data-word in the RDAC latch is decoded to select
one of the 1024 possible settings. The following discussion
describes the calculation of resistance R
25 kΩ part. The wiper’s first connection starts at Terminal B for
data 0x000. R
it is independent of the nominal resistance. The second
connection is the first tap point where R
50 Ω = 74.4 Ω for data 0x001. The third connection is the next
tap point representing R
0x002, and so on. Each LSB data value increase moves the wiper
up the resistor ladder until the last tap point is reached at
R

WB

the equivalent RDAC circuit. When R
be left floating or tied to the wiper.

The general equation that determines the programmed output
resistance between Wx and Bx is

where:

D is the decimal equivalent of the data contained in the RDAC

register.

R

AB

R

W

For example, the output resistance values in Table 12 are set for
the given RDAC latch codes (applies to R
potentiometers).

, is available with 25 kΩ and 250 kΩ with

AB

at different codes of a

WB

(0) is 50 Ω because of the wiper resistance, and

WB

(1) becomes 24.4 Ω +

WB

(2) = 48.8 Ω + 50 Ω = 98.8 Ω for data

WB

(1023) = 25026 Ω. See Figure 43 for a simplified diagram of

is used, Terminal A can

WB

100

75

)

WF

(D) (% R

50

WB

(D), R

WA

R

25

0

0 1023256

DR +×=

R

WA

Figure 44. R

D

)(

1024

512 768

CODE (Decimal)

(D) and RWB(D) vs. Decimal Code

WA

(1)

RR

W

ABWA

R

WB

is the nominal resistance between Terminals A and B.

is the wiper resistance.

= 25 kΩ digital

AB

02816-B-045

Table 12. RWB (D) at Selected Codes for RAB = 25 kΩ

D (DEC) RWB(D) (Ω) Output State

1023 25,026 Full scale
512 12,550 Midscale
1 74.4 1 LSB
0 50 Zero scale (wiper contact resistor)

Note that, in the zero-scale condition, a finite wiper resistance
of 50 Ω is present. Care should be taken to limit the current
flow between W and B in this state to no more than 20 mA to
avoid degradation or possible destruction of the internal
switches.

Like the mechanical potentiometer that the RDAC replaces, the
AD5235 part is totally symmetrical. The resistance between
Wiper W and Terminal A also produces a digitally controlled
complementary resistance, R

. Figure 44 shows the symmetri-

WA

cal programmability of the various terminal connections. When

is used, Terminal B can be left floating or tied to the wiper.

R

WA

Setting the resistance value for R

starts at a maximum value

WA

of resistance and decreases as the data loaded in the latch is
increased in value.

The general transfer equation for this operation is

1024

DR +×

=

)(

D

1024

ABWA

(2)

RR

W

For example, the output resistance values in Table 13 are set for
the given RDAC latch codes (applies to R

= 25 kΩ digital

AB

potentiometers).

Table 13. RWA(D) at Selected Codes for R

= 25 kΩ

AB

D (DEC) RWA(D) (Ω) Output State

1023 74.4 Full scale
512 12,550 Midscale
1 25,026 1 LSB
0 25,050 Zero scale (wiper contact resistance)

The typical distribution of RAB from channel to channel is
±0.2% within the same package. Device-to-device matching is
process lot dependent upon the worst case of ±30% variation.
However, the change in R

with temperature has a 35 ppm/°C

AB

temperature coefficient.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer can be configured to generate an
output voltage at the wiper terminal that is proportional to the
input voltages applied to Terminals A and B. For example,
connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the wiper that can be any value
from 0 V to 5 V. Each LSB of voltage is equal to the voltage
applied across Terminal AB divided by the 2
resolution of the potentiometer divider.

N

position

Rev. B | Page 20 of 28

AD5235

Because AD5235 can also be supplied by dual supplies, the
general equation defining the output voltage at V

with respect

W

to ground for any given input voltages applied to Terminals A
and B is

W

1024

D

DV +×=

)( (3)

Equation 3 assumes that V

VV

B

AB

is buffered so that the effect of

W

wiper resistance is minimized. Operation of the digital potenti­ometer in divider mode results in more accurate operation over
temperature. Here, the output voltage is dependent on the ratio
of the internal resistors and not the absolute value; therefore, the
drift improves to 15 ppm/°C. There is no voltage polarity
restriction between Terminals A, B, and W as long as the
terminal voltage (V

) stays within VSS < V

TERM

TERM

< VDD.

PROGRAMMING EXAMPLES

The following programming examples illustrate a typical
sequence of events for various features of the AD5235. See
Table 7 for the instructions and data-word format. The
instruction numbers, addresses, and data appearing at the SDI
and SDO pins are in hexadecimal format.

Table 14. Scratchpad Programming

SDI SDO Action

0xB00100 0xXXXXXX

0xB10200 0xB00100

Table 15. Incrementing RDAC Followed by Storing the
Wiper Setting to EEMEM

SDI SDO Action

0xB00100 0xXXXXXX

0xE0XXXX 0xB00100

0xE0XXXX 0xE0XXXX

0x20XXXX 0xXXXXXX

The EEMEM values for the RDACs can be restored by power­on, by strobing the
Table 16.

Writes data 0x100 into RDAC1 register,
Wiper W1 moves to 1/4 full-scale
position.

Loads data 0x200 into RDAC2 register,
Wiper W2 moves to 1/2 full-scale
position.

Writes data 0x100 into RDAC1
register, Wiper W1 moves to 1/4 full­scale position.

Increments RDAC1 register by one to
0x101.

Increments RDAC1 register by one to
0x102. Continue until desired wiper
position is reached.

Stores RDAC2 register data into
EEMEM1. Optionally tie WP
protect EEMEM values.

PR

pin, or by the two commands shown in

to GND to

Table 16. Restoring the EEMEM Values to RDAC Registers

SDI SDO Action

0x10XXXX 0xXXXXXX

0x00XXXX 0x10XXXX

Restores the EEMEM1 value to the
RDAC1 register.

NOP. Recommended step to minimize
power consumption.

Table 17. Using Left-Shift by One to Increment 6 dB Steps

SDI SDO Action

0xC0XXXX 0xXXXXXX

0xC1XXXX 0xC0XXXX

Moves Wiper 1 to double the
present data contained in the
RDAC1 register.

Moves Wiper 2 to double the
present data contained in the
RDAC2 register.

Table 18. Storing Additional User Data in EEMEM

SDI SDO Action

0x32AAAA 0xXXXXXX

0x335555 0x32AAAA

Stores data 0xAAAA in the extra
EEMEM location USER1. (Allowable to
address in 13 locations with a
maximum of 16 bits of data.)

Stores data 0x5555 in the extra
EEMEM location USER2. (Allowable to
address in 13 locations with a
maximum of 16 bits of data.)

Table 19. Reading Back Data from Memory Locations

SDI SDO Action

0x92XXXX 0xXXXXXX

0x00XXXX 0x92AAAA

Prepares data read from USER1
EEMEM location.

NOP Instruction 0 sends a 24-bit word
out of SDO, where the last 16 bits
contain the contents in USER1
EEMEM location. The NOP command
ensures that the device returns to the
idle power dissipation state.

Table 20. Reading Back Wiper Settings

SDI SDO Action

0xB00200 0xXXXXXX Writes RDAC1 to midscale.
0xC0XXXX 0xB00200

0xA0XXXX 0xC0XXXX

0xXXXXXX 0xA003FF Reads back full-scale value from SDO.

Doubles RDAC1 from midscale to full
scale.

Prepares reading wiper setting from
RDAC1 register.

AD5235EVAL EVALUATION KIT

Analog Devices offers a user-friendly AD5235EVAL evaluation
kit that can be controlled by a personal computer through a
printer port. The driving program is self-contained; no
programming languages or skills are needed.

Rev. B | Page 21 of 28

AD5235

APPLICATIONS

BIPOLAR OPERATION FROM DUAL SUPPLIES

The AD5235 can be operated from dual supplies ±2.5 V, which
enables control of ground referenced ac signals or bipolar
operation. AC signals as high as V
across Terminals A to B with output taken from Terminal W.
See Figure 45 for a typical circuit connection.

V

SS

DD

SCLK

µ

C

MOSI

GND

CS
CLK
SDI

GND

AD5235

Figure 45. Bipolar Operation from Dual Supplies

GAIN CONTROL COMPENSATION

A digital potentiometer is commonly used in gain control such
as the noninverting gain amplifier shown in Figure 46.

R1

47kΩ

C1

11pF

Vi

Figure 46. Typical Noninverting Gain Amplifier

When RDAC B terminal parasitic capacitance is connected to
the op amp noninverting node, it introduces a zero for the 1/ϐ
term with 20 dB/dec, while a typical op amp GBP has

−20 dB/dec characteristics. A large R2 and finite C1 can cause
this zero’s frequency to fall well below the crossover frequency.
Therefore, the rate of closure becomes 40 dB/dec, and the
system has a 0° phase margin at the crossover frequency. The
output can ring or oscillate, if an input is a rectangular pulse or
step function. Similarly, it is also likely to ring when switching
between two gain values; this is equivalent to a stop change at
the input.

Depending on the op amp GBP, reducing the feedback resistor
might extend the zero’s frequency far enough to overcome the
problem. A better approach is to include a compensation
capacitor, C2, to cancel the effect caused by C1. Optimum
compensation occurs when R1 × C1 = R2 × C2. This is not an
option because of the variation of R2. As a result, one can use
the relationship above and scale C2 as if R2 were at its maxi-

DD/VSS

C2

2.2pF

U1

can be applied directly

V

DD

A

±

1.25V p-p

W

B

V

SS

R2

250kΩ
BA

W

D = MIDSCALE

V

O

02816-B-047

+2.5V

±

2.5V p-p

–2.5V

mum value. Doing this might overcompensate and compromise
the performance when R2 is set at low values. On the other
hand, it avoids the ringing or oscillation at the worst case. For
critical applications, C2 should be found empirically to suit the
need. In general, C2 in the range of a few pF to no more than a
few tenths of pF is usually adequate for the compensation.

Similarly, W–A terminal capacitances are connected to the
output (not shown); their effect at this node is less significant
and the compensation can be avoided in most cases.

HIGH VOLTAGE OPERATION

The digital potentiometer can be placed directly in the feedback
or input path of an op amp for gain control, provided that the
voltage across Terminals A–B, W–A, or W–B does not exceed
|5 V|. When high voltage gain is needed, users should set a fixed
gain in an op amp and let the digital potentiometer control the

02816-B-046

adjustable input. Figure 47 shows a simple implementation.

C

2RR

15V

5V

A

AD5235

W

B

Figure 47. 15 V Voltage Span Control

V+

A1

V–

0V TO 15V

V

O

02816-A-048

Similarly, a compensation capacitor C might be needed to
dampen the potential ringing when the digital potentiometer
changes steps. This effect is prominent when stray capacitance
at the inverted node is augmented by a large feedback resistor.
Usually, a pF Capacitor C is adequate to combat the problem.

DAC

O

For DAC operation (Figure 48), it is common to buffer the
output of the digital potentiometer unless the load is much
larger than R

. The buffer serves the purpose of impedance

WB

conversion and can drive heavier loads.

5V

U11

V

GND

2

IN

V

OUT

AD1582

AD5235

3

A

B

5V

W

V+

AD8601

V–

A1

Figure 48. Unipolar 10-Bit DAC

V

O

02816-B-049

Rev. B | Page 22 of 28

AD5235

I

BIPOLAR PROGRAMMABLE GAIN AMPLIFIER

For applications requiring bipolar gain, Figure 49 shows one
implementation. Digital potentiometer U1 sets the adjustment
range; the wiper voltage V
between V

and −KVi at a given U2 setting. Configure A2 as a

i

can, therefore, be programmed

W2

noninverting amplifier that yields a transfer function:

V

O

V

2

R

⎛

1 (4)

+= KK

⎜

1

R

⎝

where K is the ratio of R

AD5235

U2

A2

Vi

A1

AD5235

U1

Figure 49. Bipolar Programmable Gain Amplifier

⎞
⎟
⎠

W

B2

B1

W1

2

D

⎛
⎜

1024

⎝

WB1/RWA 1

V

V+

OP2177

V–

A

V

DD

SS

⎞

)1(

−+××

⎟
⎠

set by U1.

OP2177

A2

–kVi

V

DD

V+

V–

R2

V

SS

R1

V

O

C

02816-B-050

In the simpler (and much more usual) case where K = 1, VO is
simplified to

2

D

2

R

⎛

1

V ×

⎜

O

⎝

⎛

⎞

+= 1

⎜

⎟

1024

1

R

⎠

⎝

⎞

2

−

V

(5)

⎟

i

⎠

Table 21 shows the result of adjusting D2, with A2 configured as
a unity gain, a gain of 2, and a gain of 10. The result is a bipolar
amplifier with linearly programmable gain and 1024-step
resolution.

Table 21. Result of Bipolar Gain Amplifier

D R1 = ∞, R2 = 0 R1 = R2 R2 = 9 R1

0 −1 −2 −10
256 −0.5 −1 −5
512 0 0 0
768 0.5 1 5
1023 0.992 1.984 9.92

10-BIT BIPOLAR DAC

If the circuit in Figure 49 is changed with the input taken from a
precision reference, U1 is set to midscale, and A2 is configured
as a buffer, a 10-bit bipolar DAC can be realized (Figure 48).
Compared to the conventional DAC, this circuit offers
comparable resolution, but not the precision because of the
wiper resistance effects. Degradation of the nonlinearity and
temperature coefficient is prominent near the low values of the
adjustment range. On the other hand, this circuit offers a unique

nonvolatile memory feature that in some cases outweighs any
shortfall in precision.

Without consideration of the wiper resistance, the output of this
circuit is approximately

2

D

⎛

V ×

⎜

O

⎝

Vi
26U3

VINV

OUT

+2.5V

5

TRIM

GND

ADR421

U1 = MIDSCALE

1024

REF

⎞

2

−= 1

V

(6)

⎟

REF

⎠

+2.5V

W2

U2

B2

A2

A1

B1

W1
U1

+2.5V

V+

AD8552

V–

A1

–2.5V

–2.5V

V+

AD8552

V–

A2

–2.5V

REF

U1 = U2 = AD5235

V

O

02816-B-051

Figure 50. 10-Bit Bipolar DAC

PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT

For applications that require high current adjustment, such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered (see Figure 51).

V

IN

AD5235

A

W

B

U2

AD8601

2N7002

SIGNAL

V+

V–

Figure 51. Programmable Booster Voltage Source

In this circuit, the inverting input of the op amp forces the V
to be equal to the wiper voltage set by the digital potentiometer.
The load current is then delivered by the supply via the N-Ch
FET N

. N1 power handling must be adequate to dissipate

1

(V

− VO) × IL power. This circuit can source a maximum of

i

100 mA with a 5 V supply.

For precision applications, a voltage reference such as ADR421,
ADR03, or ADR370 can be applied at Terminal A of the digital
potentiometer.

V

OUT

R

BIAS

C

C

I

L

LD

02816-B-052

OUT

Rev. B | Page 23 of 28

AD5235

A

5

+

V

PROGRAMMABLE CURRENT SOURCE

A programmable current source can be implemented with the
circuit shown in Figure 52.

+5V

U1

2

V

IN

3

SLEEP

REF191

GND

4

–2.048VTO V

AD5235

V

OUT

L

0 TO (2.048 + VL)

6

C1

1

µ

F

+5V

V+

OP1177

V–

–5V

B

W

A

–

U2

+

100

R

S

102

Ω

V

L

R

L

Ω

I

L

02861-B-053

Figure 52. Programmable Current Source

REF191 is a unique low supply headroom and high current
handling precision reference that can deliver 20 mA at 2.048 V.
The load current is simply the voltage across Terminals B–W of
the digital potentiometer divided by R

×

DV

REF

=

I (7)

L

1024×

R

S

:

S

The circuit is simple, but be aware that there are two issues.
First, dual-supply op amps are ideal, because the ground
potential of REF191 can swing from −2.048 V at zero scale to V

L

at full scale of the potentiometer setting. Although the circuit
works under single supply, the programmable resolution of the
system is reduced by half. Second, the voltage compliance at V

L

is limited to 2.5 V or equivalently a 125 Ω load. Should higher
voltage compliance be needed, users can consider digital
potentiometers AD5260, AD5280, and AD7376. Figure 53 shows
an alternate circuit for high voltage compliance.

To achieve higher current, such as when driving a high power
LED, the user can replace the U1 with an LDO, reduce R

, and

S

add a resistor in series with the digital potentiometer’s
A terminal. This limits the potentiometer’s current and
increases the current adjustment resolution.

PROGRAMMABLE BIDIRECTIONAL CURRENT SOURCE

For applications that require bidirectional current control or
higher voltage compliance, a Howland current pump can be a
solution (Figure 53). If the resistors are matched, the load
current is

BRAR

+

22

R

I ×

=

1

BR

2

(8)

V

WL

D523

+2.5V

A

B

–2.5V

+15V

+

V+

W

OP2177

–

A1

–15V

Figure 53. Programmable Bidirectional Current S ource

R2B, in theory, can be made as small as necessary to achieve the
current needed within the A2 output current-driving capability.
In this circuit, OP2177 delivers ±5 mA in either direction, and
the voltage compliance approaches 15 V. Without the additions
of C1 and C2, the output impedance (looking into V
shown as

=

Z

0

can be infinite, if resistors R1' and R2' match precisely with

Z

O

R1 and R2A + R2B,
hand, Z

can be negative, if the resistors are not matched and

O

cause oscillation. As a result, C1, in the range of a few pF, is
needed to prevent oscillation from the negative impedance.

PROGRAMMABLE LOW-PASS FILTER

In analog-to-digital conversions, it is common to include an
antialiasing filter to band limit the sampling signal. The dual­channel AD5235 can, therefore, be used to construct a second­order Sallen-Key low-pass filter, as shown in Figure 54.

R1

B

A

i

The design equations are

V

O

V

i

W

R

ADJUSTED

CONCURRENTLY

Figure 54. Sallen-Key Low-Pass Filter

ω

= (10)

ω

2

+

S

Q

R1

150k

Ω

V–

respectively, which is desirable. On the other

R1

150k

Ω

)(

R2AR1R2BR1'

)(

R2BR2AR1'R2'R1

+−

R2

15k

Ω

C1

+15V

10pF

–

V+

OP2177

V–

+

–15V

R2A

14.95k

R2B

A2

50

Ω

V

L

R

L

Ω

500

Ω

I

L

) can be

L

(9)

C1

+2.5V

R2

B

A

W

R

C2

2

f

f

2

ω+

S

f

V+

AD8601

V–

–2.5V

V

O

U1

02816-B-055

02816-B-054

Rev. B | Page 24 of 28

AD5235

2

C

C

=ω (11)

O

Q =

1

C2C1R2R1

1

1

+

C1R1

(12)

C2R2

Users can first select some convenient values for the capacitors.
To achieve maximally flat bandwidth, where Q = 0.707, let C1 be
twice the size of C2 and let R1 equal R2. As a result, the user can
adjust R1 and R2 concurrently to the same setting to achieve the
desirable bandwidth.

PROGRAMMABLE OSCILLATOR

In a classic Wien-bridge oscillator, shown in Figure 55, the Wien
network (R, R

R2 provide negative feedback.

At the resonant frequency, fO, the overall phase shift is zero, and
the positive feedback causes the circuit to oscillate. With R = R

', and R2 = R2A /(R2B + R

C = C
is

where R is equal to R

R

At resonance, setting

'C, C') provides positive feedback, while R1 and

FREQUENCY

ADJUSTMENT

C

25kΩ

.2nF

R = R' = AD5235
R2B = AD5231
D1 = D2 = 1N4148

VP

B

R

W

A

Figure 55. Programmable Oscillator with Amplitude Control

O

=

1

=ω

R

1024 −

1024

or

D

R

1

f

O

R

π=2

such that

WA

(14)

AB

R'

C'

25kΩ

B

A

2.2nF
W

+2.5V

U1

+

V+

OP1177

V–

–

R2A

2.1kΩ

–2.5V

R2B

10kΩ

BA

W

R1
1kΩ

AMPLITUDE

ADJUSTMENT

), the oscillation frequency

DIODE

V

O

D1

D2

02816-B-056

(13)

',

Once the frequency is set, the oscillation amplitude can be
turned by R2B, because

2

O

3

, ID, and VD are interdependent variables. With proper

V

O

selection of R2B, an equilibrium is reached such that V

(16)

VR2BIV +=

DD

WF

converges. R2B can be in series with a discrete resistor to
increase the amplitude, but the total resistance cannot be too
large to saturate the output.

In both circuits shown in Figure 54 and Figure 55, the frequency
tuning requires that both RDACs be adjusted concurrently to
the same settings. Because the two channels might be adjusted
one at a time, an intermediate state occurs that might not be
acceptable for some applications. Of course, the increment/
decrement instructions (5, 7, 13, and 15) can all be used.
Different devices can also be used in daisy-chain mode so that
parts can be programmed to the same settings simultaneously.

OPTICAL TRANSMITTER CALIBRATION WITH ADN2841

The AD5235, together with the multirate 2.7 Gbps laser diode
driver ADN2841, forms an optical supervisory system in which
the dual digital potentiometers can be used to set the laser
average optical power and extinction ratio (Figure 56). AD5235
is particularly suited for the optical parameter settings because
of its high resolution and superior temperature coefficient
characteristics.

CLK

SDI

CS

AD5235

CONTROL

ADN2841

DIN

DINQ

IDTONE

W1

B1
W2

B2

PSET

ERSET

DIN

DINQ

EEMEM

EEMEM

RDAC1

A1

RDAC2

A2

Figure 56. Optical Supervisory System

V

CC

IMPD

IMODP

IBIAS

IDTONE

V

CC

02816-B-057

R2

(15)

2=

R1

balances the bridge. In practice, R2/R1 should be set slightly
larger than 2 to ensure that the oscillation can start. On the
other hand, the alternate turn-on of the diodes D1 and D2
ensures that R2/R1 is smaller than 2, momentarily stabilizing
the oscillation.

Rev. B | Page 25 of 28

The ADN2841 is a 2.7 Gbps laser diode driver that uses a
unique control algorithm to manage the laser’s average power
and extinction ratio after the laser’s initial factory calibration.
The ADN2841 stabilizes the laser’s data transmission by
continuously monitoring its optical power and correcting the
variations caused by temperature and the laser’s degradation
over time. In the ADN2841, the I

monitors the laser diode

MPD

current. Through its dual loop power and extinction ratio

AD5235

A

+

×

control calibrated by the AD5235’s dual RDACs, the internal
driver controls the bias current, I
average power. It also regulates the modulation current, I

, and consequently the

BIAS

MODP

,
by changing the modulation current linearly with slope
efficiency. Any changes in the laser threshold current or slope
efficiency are, therefore, compensated. As a result, this optical
supervisory system minimizes the laser characterization efforts
and, therefore, enables designers to apply comparable lasers
from multiple sources.

RESISTANCE SCALING

The AD5235 offers 25 kΩ or 250 kΩ nominal resistance. For
users who need lower resistance but must still maintain the
number of adjustment steps, they can parallel multiple devices.
For example, Figure 57 shows a simple scheme of paralleling
two channels of RDACs. To adjust half the resistance linearly
per step, users need to program both RDACs concurrently with
the same settings.

A1

B1

Figure 57. Reduce Resistance by Half with Linear Adjustment Characteristics

In voltage divider mode, by paralleling a discrete resistor as
shown in Figure 58, a proportionately lower voltage appears at
Terminal A-to-B. This translates into a finer degree of precision,
because the step size at Terminal W is smaller. The voltage can
be found as follows:

W

+

RRR

AB

R2

Figure 58. Lowering the Nominal Resistance

)//(

RR

2

AB

)(

DV ××

=

Figure 57 and Figure 58 show that the digital potentiometers
change steps linearly. On the other hand, pseudolog taper
adjustment is usually preferred in applications such as audio
control. Figure 59 shows another type of resistance scaling. In
this configuration, the smaller the R2 with respect to R
more the pseudolog taper characteristic of the circuit behaves.

A2

W1

1024//

23

R3

R1

W2

B2

02816-B-058

D

A

B

(17)

V

DD

V

DD

W

02816-B-059

0

AB

, the

1

W1

B1

Figure 59. Resistor Scaling with Pseudo Log Adjustment Characteristics

R

02816-B-060

The equation is approximated as

RD

51200

AB

AB

(18)

RRD

×++×

102451200

R

=

eq

Users should also be aware of the need for tolerance matching
as well as for temperature coefficient matching of the
components.

RESISTANCE TOLERANCE, DRIFT, AND
TEMPERATURE COEFFICIENT MISMATCH
CONSIDERATIONS

In a rheostat mode operation such as gain control (see
Figure 60), the tolerance mismatch between the digital potenti­ometer and the discrete resistor can cause repeatability issues
among various systems. Because of the inherent matching of the
silicon process, it is practical to apply the dual-channel device in
this type of application. As such, R1 can be replaced by one of
the channels of the digital potentiometer and programmed to a
specific value. R2 can be used for the adjustable gain. Although
it adds cost, this approach minimizes the tolerance and
temperature coefficient mismatch between R1 and R2. This
approach also tracks the resistance drift over time. As a result,
these less than ideal parameters become less sensitive to system
variations.

R2

AB

W

R1*

*REPLACED WITH ANOTHER

CHANNEL OF RDAC

Figure 60. Linear Gain Control with Tracking Resistance Tolerance, Drift,

and Temperature Coefficient

Note that the circuit in Figure 61 can track tolerance,
temperature coefficient, and drift in this particular application.
The characteristic of the transfer function is, however, a pseudo­logarithmic rather than a linear gain function.

C1

–

AD8601

+

V

i

U1

V

O

02816-B-061

Rev. B | Page 26 of 28

AD5235

R

AB

C1

W

–

AD8601

+

V

i

U1

V

O

02816-B-062

Figure 61. Nonlinear Gain Control with Tracking Resistance Tolerance

and Drift

RDAC CIRCUIT SIMULATION MODEL

The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the −3 dB bandwidth of the AD5235
(25 kΩ resistor) measures 125 kHz at half-scale. Figure 14
provides the large signal BODE plot characteristics of the two
available resistor versions, 25 kΩ and 250 kΩ. A parasitic
simulation model is shown in Figure 62.

RDAC

Ω

A

11pF

C

25k

A

80pF

W

C

B

11pF

B

02816-B-063

Figure 62. RDAC Circuit Simulation Model (RDAC = 25 kΩ)

The following code provides a macro model net list for the
25 kΩ RDAC:

.PARAM D = 1024, RDAC = 25E3
*
.SUBCKT DPOT (A, W, B)
*
CA A 0 11E-12
RWA A W {(1-D/1024)* RDAC + 50}
CW W 0 80E-12
RWB W B {D/1024 * RDAC + 50}
CB B 0 11E-12
*
.ENDS DPOT

Rev. B | Page 27 of 28

AD5235

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40

BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 63. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

R

Model

WB_FS

(kΩ) RDNL RINL

AD5235BRU25 25 ±2 ±4 −40°C to +85°C TSSOP-16 RU-16 96 5235B25
AD5235BRU25-RL7 25 ±2 ±4 −40°C to +85°C TSSOP-16 RU-16 1,000 5235B25
AD5235BRUZ252 25 ±2 ±4 −40°C to +85°C TSSOP-16 RU-16 96 5235B25
AD5235BRUZ25-RL72 25 ±2 ±4 −40°C to +85°C TSSOP-16 RU-16 1,000 5235B25
AD5235BRU250 250 ±2 ±4 −40°C to +85°C TSSOP-16 RU-16 96 5235B250
AD5235BRU250-RL7 250 ±2 ±4 −40°C to +85°C TSSOP-16 RU-16 1,000 5235B250
AD5235BRUZ2502 250 ±2 ±4 −40°C to +85°C TSSOP-16 RU-16 96 5235B250
AD5235BRUZ250-RL72 250 ±2 ±4 −40°C to +85°C TSSOP-16 RU-16 1,000 5235B250
AD5235EVAL25 25 1
AD5235EVAL250 250 1

1

Line 1 contains the ADI logo followed by the date code, YYWW. Line 2 contains the model number followed by the end-to-end resistance value (note: D = 250 kΩ).
—OR—
Line 1 contains the model number. Line 2 contains the ADI logo followed by the end-to-end resistance value. Line 3 contains the date code, YYWW.

2

Z = Pb-free part.

Temperature
Range

Package
Description

Package
Option

Ordering
Quantity Branding

1

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C02816–0–7/04(B)

Rev. B | Page 28 of 28