ANALOG DEVICES AD5235 Service Manual

1024-Position Digital Potentiometer

AD5235

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Trademarks and registered trademarks are the property of their respective owners.

Fax: [phone] ©2004–2012 Analog Devices, Inc. All rights reserved.

ADDR

DECODE

AD5235

RDAC1

SERIAL

INTERFACE

CS

CLK

SDI

SDO

PR

WP

RD

Y

RDAC1

REGISTER

EEMEM1

RDAC2

REGISTER

EEMEM2

26 BYTES

RTOL*

USER EEMEM

POWER-ON

RESET

W1
B1

RDAC2

W2
B2

A1

V

DD

A2

V

SS

GND

02816-001

EEMEM

CONTROL

*RAB TOLERANCE

Data Sheet

FEATURES

Dual-channel, 1024-position resolution
25 kΩ, 250 kΩ nominal resistance
Maximum ±8% nominal resistor tolerance error
Low temperature coefficient: 35 ppm/°C

2.7 V to 5 V single supply or ±2.5 V dual supply
SPI-compatible serial interface
Nonvolatile memory stores wiper settings
Power-on refreshed with EEMEM settings
Permanent memory write protection
Resistance tolerance stored in EEMEM
26 bytes extra nonvolatile memory for user-defined

information
1M programming cycles
100-year typical data retention

APPLICATIONS

DWDM laser diode driver, optical supervisory systems
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration

GENERAL DESCRIPTION

The AD5235 is a dual-channel, nonvolatile memory,1 digitally
controlled potentiometer
guaranteed maximum low resistor tolerance error of ±8%.
The device performs the same electronic adjustment function
as a mechanical potentiometer with enhanced resolution, solid
state reliability, and superior low temperature coefficient per­formance. The versatile programming of the AD5235 via an
SPI®-compatible serial interface allows 16 modes of operation
and adjustment including scratchpad programming, memory
storing and restoring, increment/decrement, ±6 dB/step log taper
adjustment, wiper setting readback, and extra EEMEM
defined information such as memory data for other components,
look-up table, or system identification information.

1

The terms nonvolatile memory and EEMEM are used interchangeably.

2

The terms digital potentiometer and RDAC are used interchangeably.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

2

with 1024-step resolution, offering

1

for user-

Nonvolatile Memory, Dual

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

In the scratchpad programming mode, a specific setting can
be programmed directly to the RDAC
resistance between Terminal W and Terminal A and Te rm i na l W
and Terminal B. This setting can be stored into the EEMEM
and is restored automatically to the RDAC register during
system power-on.

The EEMEM content can be restored dynamically or through
external

PR

strobing, and a WP function protects EEMEM
contents. To simplify the programming, the independent or
simultaneous linear-step increment or decrement commands
can be used to move the RDAC wiper up or down, one step at
a time. For logarithmic ±6 dB changes in the wiper setting, the
left or right bit shift command can be used to double or halve the
RDAC wiper setting.

The AD5235 patterned resistance tolerance is stored in the
EEMEM. The actual end-to-end resistance can, therefore, be
known by the host processor in readback mode. The host can
execute the appropriate resistance step through a software
routine that simplifies open-loop applications as well as
precision calibration and tolerance matching applications.

The AD5235 is available in a thin, 16-lead TSSOP package.
The part is guaranteed to operate over the extended industrial
temperature range of −40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

2

register, which sets the

www.analog.com

AD5235 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications ..................................................................................... 4

Electrical Characteristics—25 kΩ, 250 kΩ Vers ions ............... 4

Interface Timing and EEMEM Reliability Characteristics—

25 kΩ, 250 kΩ Versions ............................................................... 6

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

Test Circuits ................................................................................. 14

Theory of Operation ...................................................................... 16

Scratchpad and EEMEM Programming .................................. 16

Basic Operation .......................................................................... 16

EEMEM Protection .................................................................... 17

Digital Input and Output Configuration................................. 17

Serial Data Interface ................................................................... 17

Daisy-Chain Operation ............................................................. 18

Terminal Voltage Operating Range .......................................... 18

Advanced Control Modes ......................................................... 20

RDAC Structure .......................................................................... 21

Programming the Variable Resistor ......................................... 22

Programming the Potentiometer Divider ............................... 22

Programming Examples ............................................................ 23

EVA L-AD5235SDZ Evaluation Kit .......................................... 23

Applications Information .............................................................. 24

Bipolar Operation from Dual Supplies.................................... 24

Gain Control Compensation .................................................... 24

High Voltage Operation ............................................................ 24

DAC .............................................................................................. 24

Bipolar Programmable Gain Amplifier ................................... 25

10-Bit Bipolar DAC .................................................................... 25

Programmable Voltage Source with Boosted Output ........... 25

Programmable Current Source ................................................ 26

Programmable Bidirectional Current Source ......................... 26

Programmable Low-Pass Filter ................................................ 27

Programmable Oscillator .......................................................... 27

Optical Transmitter Calibration with ADN2841 ................... 28

Resistance Scaling ...................................................................... 28

Resistance Tolerance, Drift, and Temperature Coefficient

Mismatch Considerations ......................................................... 29

RDAC Circuit Simulation Model ............................................. 29

Outline Dimensions ....................................................................... 30

Ordering Guide .......................................................................... 30

Rev. F | Page 2 of 32

Data Sheet AD5235

REVISION HISTORY

6/12—Rev. E to Rev. F

Changes to Table 1 Conditions ........................................................ 4

Removed Positive Supply Current RDY and/or SDO Floating
Parameters and Negative Supply Current RDY and/or SDO

Floating Parameters, Table 1 ............................................................ 5

Added Endnote 2 to Ordering Guide ........................................... 30

4/11—Rev. D to Rev. E

Changes to Figure 12 ...................................................................... 11

4/11—Rev. C to Rev. D

Changes to EEMEM Performance .............................. Throughout

Changes to Features and General Descriptions Sections ............. 1

Changes to Specifications Section ................................................... 4

Changes to Pin 5, Pin 13, Pin 14 Descriptions .............................. 9

Changes to Typical Performance Characteristics Section ......... 10

Changes to Table 7 .......................................................................... 19

Changes to Table 9 .......................................................................... 21

Changes to Rheostat Operation Section, Table 12, Table 13 ..... 22

Changes to Table 16, Table 19, and EVAL-AD5235SDZ

Evaluation Kit Section .................................................................... 23

Changes to RDAC Circuit Simulation Model Section ............... 29

Updated Outline Dimensions ........................................................ 30

Changes to Ordering Guide ........................................................... 30

4/09—Rev. B to Rev. C

Changes to Figure 1........................................................................... 1

Changes to Specifications ................................................................. 3

Changes to SDO, Description Column, Table 4 ............................ 8

Changes to Figure 18 ...................................................................... 11

Changes to Theory of Operation Section .................................... 14

Changes to Serial Data Interface Section ..................................... 15

Changes to Linear Increment and Decrement Instructions
Section, Logarithmic Taper Mode Adjustment Section, and

Figure 42 ........................................................................................... 18

Changes to Rheostat Operations Section ..................................... 20

Changes to Bipolar Programmable Gain Amplifier Section,

Figure 49, Table 21, and 10-Bit Bipolar DAC Section ................ 23

Changes to Programmable Oscillator Section and Figure 56 ... 25

Changes to Ordering Guide ........................................................... 28

7/04—Rev. A to Rev. B

Updated Formatting .......................................................... Universal

Edits to Features, General Description, and Block Diagram ...... 1

Changes to Specifications................................................................. 3

Replaced Timing Diagrams ............................................................. 6

Changes to Absolute Maximum Ratings........................................ 7

Changes to Pin Function Descriptions .......................................... 8

Changes to Typical Performance Characteristics ......................... 9

Additional Test Circuit (Figure 36)................................................. 9

Edits to Theory of Operation ........................................................ 14

Edits to Applications ....................................................................... 23

Updated Outline Dimensions........................................................ 27

8/02—Rev. 0 to Rev. A

Change to Features and General Description ............................... 1

Change to Specifications .................................................................. 2

Change to Calculating Actual End-to-End Terminal

Resistance Section ........................................................................... 14

Rev. F | Page 3 of 32

AD5235 Data Sheet

Resistor Differential Nonlinearity2

R-DNL

RWB

−1 +1

LSB

Output Logic Low

VOL

IOL = 1.6 mA, V

= 5 V (see

0.4

V

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS

VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V, VA = VDD, VB = VSS, −40°C < TA < +85°C, unless otherwise noted.

These specifications apply to versions with a date code 1209 or later.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT

MODE (All RDACs)

Resistor Integral Nonlinearity2 R-INL RWB −2 +2 LSB

Nominal Resistor Tolerance ∆RAB/RAB −8 +8 %

Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C

Wiper Resistance RW IW = 1 V/RWB, code = midscale

VDD = 5 V 30 60 Ω
VDD = 3 V 50 Ω

Nominal Resistance Match R
DC CHARACTERISTICS—

POTENTIOMETER DIVIDER MODE

(All RDACs)

Resolution N 10 Bits

Differential Nonlinearity3 DNL −1 +1 LSB

Integral Nonlinearity3 INL −1 +1 LSB

Voltage Divider Temperature

Coefficient
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Terminal Voltage Range4 VA, VB, VW VSS VDD V
Capacitance Ax, Bx5 CA, CB f = 1 MHz, measured to GND,

Capacitance Wx5 CW f = 1 MHz, measured to GND,

Common-Mode Leakage Current

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH With respect to GND, VDD = 5 V 2.4 V
Input Logic Low VIL With respect to GND, VDD = 5 V 0.8 V
Input Logic High VIH With respect to GND, VDD = 3 V 2.1 V
Input Logic Low VIL With respect to GND, VDD = 3 V 0.6 V
Input Logic High VIH With respect to GND, VDD = +2.5 V,

Input Logic Low VIL With respect to GND, VDD = +2.5 V,

Output Logic High (SDO, RDY) VOH R

Input Current IIL VIN = 0 V or VDD ±1 µA
Input Capacitance5 CIL 5 pF

±0.1 %

AB1/RAB2

(∆VW/VW)/∆T × 106 Code = midscale 15 ppm/°C

Code = full scale −6 0 LSB

WFSE

Code = zero scale 0 4 LSB

WZSE

11 pF

code = midscale

80 pF

code = midscale

5, 6

ICM VW = VDD/2 0.01 ±1 µA

2.0 V

V

= −2.5 V

SS

0.5 V

V

= −2.5 V

SS

= 2.2 kΩ to 5 V (see

PULL-UP

4.9 V

Figure 38)

Figure 38)

LOGIC

Rev. F | Page 4 of 32

Data Sheet AD5235

Negative Supply Current

ISS

VDD = +2.5 V, VSS = −2.5 V

f = 1 kHz, code = midscale

RAB = 25 kΩ

0.009

%

Resistor Noise Density

e

RAB = 25 kΩ/250 kΩ

20/64

nV/√Hz

Parameter Symbol Conditions Min Typ1 Max Unit

POWER SUPPLIES

Single-Supply Power Range VDD VSS = 0 V 2.7 5.5 V
Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD VIH = VDD or VIL = GND 2 5 µA

VIH = VDD or VIL = GND −4 −2 µA
EEMEM Store Mode Current IDD (store) VIH = VDD or VIL = GND,

V

= GND, ISS ≈ 0

SS

ISS (store) VDD = +2.5 V, VSS = −2.5 V −2 mA
EEMEM Restore Mode Current7 IDD (restore) VIH = VDD or VIL = GND,

V

= GND, ISS ≈ 0

SS

ISS (restore) VDD = +2.5 V, VSS = −2.5 V −320 µA
Power Dissipation8 P

VIH = VDD or VIL = GND 10 30 µW

DISS

Power Supply Sensitivity5 PSS ∆VDD = 5 V ± 10% 0.006 0.01 %/%

DYNAMIC CHARACTERISTICS

5, 9

Bandwidth BW −3 dB, RAB = 25 kΩ/250 kΩ 125/12 kHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V,

RAB = 250 kΩ 0.035 %

VW Settling Time tS VA = VDD, VB = 0 V, VW = 0.50% error

band, from zero scale to midscale
RAB = 25 kΩ 4 µs
RAB = 250 kΩ 36 µs

N_WB

Crosstalk (CW1/CW2) CT VA1 = VDD, VB1 = VSS , measured VW2

with VW1 making full-scale change,

= 25 kΩ/250 kΩ

R

AB

Analog Crosstalk CTA V

= 5 V p-p, f = 1 kHz, measured

AB2

VW1, Code 1 = midscale, Code 2 =

full scale, R

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. I

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of

±1 LSB maximum are guaranteed monotonic operating conditions (see Figure 28).

4

Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-

referenced bipolar signal adjustment.

5

Guaranteed by design and not subject to production test.

6

Common-mode leakage current is a measure of the dc leakage from any Terminal A, Terminal B, or Terminal W to a common-mode bias level of VDD/2.

7

EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register.

8

P

is calculated from (IDD × VDD) + (ISS × VSS).

DISS

9

All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.

= 25 kΩ/250 kΩ

AB

WB = (VDD − 1)/RWB (see Figure 27).

2 mA

320 µA

30/60

−110/−100

nV-s

dB

Rev. F | Page 5 of 32

AD5235 Data Sheet

Input Clock Pulse Width

t4, t5

Clock level high or low

10

ns

CLK to SDO Propagation Delay2

t10

RP = 2.2 kΩ, CL < 20 pF

50

ns

CLK to SDO Data Hold Time

t11

RP = 2.2 kΩ, CL < 20 pF

0

ns

Read EEMEM Time4

t16

Applies to Instructions 0x8, 0x9, 0x10

7 30

µs

Data Retention8

100 Years

INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS

Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with t
measured using both V

= 2.7 V and VDD = 5 V.

DD

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

Clock Cycle Time (t

Setup Time t2 10 ns

CS

) t1 20 ns

CYC

CLK Shutdown Time to CS Rise t3 1 t

Data Setup Time t6 From positive CLK transition 5 ns
Data Hold Time t7 From positive CLK transition 5 ns

to SDO-SPI Line Acquire t8 40 ns

CS

to SDO-SPI Line Release t9 50 ns

CS

= tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are

R

CYC

High Pulse Width3 t12

CS

High to CS High3 t13 4 t

CS

10 ns

CYC

RDY Rise to CS Fall t14 0 ns

Rise to RDY Fall Time t15 0.15 0.3 ms

CS
Store EEMEM Time

Rise to Clock Rise/Fall Setup t17 10 ns

CS
Preset Pulse Width (Asynchronous)6 t
Preset Response Time to Wiper Setting6 t
Power-On EEMEM Restore Time6 t

4, 5

t16 Applies to Instructions 0x2, 0x3 15 50 ms

50 ns

PRW

PRESP

30 µs

EEMEM

pulsed low to refresh wiper positions

PR

30 µs

FLASH/EE MEMORY RELIABILITY

Endurance7 TA = 25°C 1
100

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Propagation delay depends on the value of VDD, R

3

Valid for commands that do not activate the RDY pin.

4

The RDY pin is low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 µs; CMD_9, CMD_10 ~ 7 µs;

CMD_2, CMD_3 ~ 15 ms;

5

Store EEMEM time depends on the temperature and EEMEM writes cycles. Higher timing is expected at a lower temperature and higher write cycles.

6

Not shown in Figure 2 and Figure 3.

7

Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C.

8

Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV

derates with junction temperature in the Flash/EE memory.

PR

hardware pulse ~ 30 µs.

PULL-UP

, and CL.

MCycles
kCycles

Rev. F | Page 6 of 32

Data Sheet AD5235

CPOL = 1

t

12

t

13

t

3

t

17

t

9

t

11

t

5

t

4

t

2

t

1

CLK

t

8

B24*

B23 (MSB) B0 (LSB)

B23 (MSB)

HIGH
OR LOW

HIGH
OR LOW

B23 B0

B0 (LSB)

RDY

CPHA = 1

t

10

t

7

t

6

t

14

t

15

t

16

*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE LSB OF THE CHARACTE R P RE V IOUSLY TRANSMITTED.

THE CPOL = 1 MICROCONTROLLER COMM AND ALIGNS THE INCOMING DATATO THE POSITIVE EDGE OF THE CLOCK.

SDO

SDI

02816-002

CS

t

12

t

13

t

3

t

17

t

9

t

11

t

5

t

4

t

2

t

1

CLK

CPOL = 0

t

8

B23 (MSB OUT) B0 (LSB)

SDO

B23 (MSB IN)

B23 B0

HIGH
OR LOW

HIGH
OR LOW

B0 (LSB)

SDI

RDY

CPHA = 0

t

10

t

7

t

6

t

14

t

15

t

16

*THE EXT

RA BIT THAT IS NOT DEFINED IS NORMALLY THE MSB OF THE CHARAC

TER JUST RECEIVED.

THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

*

CS

02816-003

Timing Diagrams

Figure 2. CPHA = 1 Timing Diagram

Figure 3. CPHA = 0 Timing Diagram

Rev. F | Page 7 of 32

AD5235 Data Sheet

Vapor Phase (60 sec)

215°C

Package Power Dissipation

(TJ max − TA)/θJA

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7 V
VSS to GND +0.3 V to −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS − 0.3 V to VDD + 0.3 V
IA, IB, IW

Pulsed1 ±20 mA

Continuous ±2 mA
Digital Input and Output Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range2 −40°C to +85°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering

Infrared (15 sec) 220°C
Thermal Resistance

Junction-to-Ambient θJA,TSSOP-16 150°C/W

Junction-to-Case θJC, TSSOP-16 28°C/W

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Includes programming of nonvolatile memory.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. F | Page 8 of 32

Data Sheet AD5235

SDI
SDO
GND

A1

V

SS

W1

CLK

B1

CS
PR
WP
V

DD

A2

02816-005

W2
B2

RDY

1

2

3

4

5

6

7
8

16

15

14

13
12

11

10

9

AD5235

TOP VIEW

(Not to S cale)

4

GND

Ground Pin, Logic Ground Reference.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
2 SDI Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
3 SDO Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO

output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and
after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI
bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This
previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up
resistor in the range of 1 kΩ to 10 kΩ is needed.

5 VSS Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink

2 mA for 15 ms when storing data to EEMEM.
6 A1 Terminal A of RDAC1.
7 W1 Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0.
8 B1 Terminal B of RDAC1.
9 B2 Terminal B of RDAC2.
10 W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.
11 A2 Terminal A of RDAC2.
12 VDD Positive Power Supply.
13

Optional Write Protect. When active low, WP prevents any changes to the present contents, except PR strobe.

WP

CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie WP to VDD, if not used.
14

Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM

PR

register. Factory default loads midscale until EEMEM is loaded with a new value by the user.

is activated

PR

at the logic high transition. Tie PR to VDD, if not used.
15

Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.

CS

16 RDY Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,

Instruction 9, Instruction 10, and

PR

.

Rev. F | Page 9 of 32

AD5235 Data Sheet

DIGITAL CODE

0 200 400 600 1000

INL ERROR ( LSB)

800

0.20

–0.20

–0.15

–0.10

–0.05

0

0.05

0.10

0.15

–40°C

+25°C

+85°C

02816-006

DIGITAL CODE

0 200 400 600 1000

DNL ERROR (L S B)

800

0.16

–0.04

–0.02

0.02

0

0.04

0.06

0.08

0.10

0.12

0.14

02816-007

–40°C

+25°C

+85°C

DIGITAL CODE

0 200 400 600 1000

INL ERROR ( LSB)

800

0.20

–0.20

–0.15

–0.10

–0.05

0

0.05

0.10

0.15

–40°C

+25°C

+85°C

02816-008

DIGITAL CODE

0 200 400 600 1000

DNL ERROR (L S B)

800

0.20

–0.15

–0.10

–0.05

0

0.05

0.10

0.15

02816-009

–40°C

+25°C

+85°C

CODE (Decimal )

POTENTIOMETER MODE TEMPCO (ppm/°C)

200

180

160

140

120

100

80

60

40

20

0

0 1023768512256

25kΩ
250kΩ

02816-010

02816-011

CODE (Decimal )

RHEOSTAT MODE TEMPCO (ppm/°C)

200

180

160

140

120

100

80

60

40

20

0

0 1023768512256

25kΩ
250kΩ

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. INL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

Figure 6. DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

Figure 8. R-DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

Figure 9. (∆VW/VW)/∆T × 106 Potentiometer Mode Tempco

Figure 7. R-INL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

Figure 10. (∆RWB/RWB)/∆T × 106 Rheostat Mode Tempco

Rev. F | Page 10 of 32