Datasheet AD5235 Datasheet (ANALOG DEVICES)

1024-Position Digital Potentiometer

AD5235

Rev. F

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ADDR

DECODE

AD5235

RDAC1

SERIAL

INTERFACE

CS

CLK

SDI

SDO

PR

WP

RD

Y

RDAC1

REGISTER

EEMEM1

RDAC2

REGISTER

EEMEM2

26 BYTES

RTOL*

USER EEMEM

POWER-ON

RESET

W1
B1

RDAC2

W2
B2

A1

V

DD

A2

V

SS

GND

02816-001

EEMEM

CONTROL

*RAB TOLERANCE

Data Sheet

FEATURES

Dual-channel, 1024-position resolution
25 kΩ, 250 kΩ nominal resistance
Maximum ±8% nominal resistor tolerance error
Low temperature coefficient: 35 ppm/°C

2.7 V to 5 V single supply or ±2.5 V dual supply
SPI-compatible serial interface
Nonvolatile memory stores wiper settings
Power-on refreshed with EEMEM settings
Permanent memory write protection
Resistance tolerance stored in EEMEM
26 bytes extra nonvolatile memory for user-defined

information
1M programming cycles
100-year typical data retention

APPLICATIONS

DWDM laser diode driver, optical supervisory systems
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration

GENERAL DESCRIPTION

The AD5235 is a dual-channel, nonvolatile memory,1 digitally
controlled potentiometer
guaranteed maximum low resistor tolerance error of ±8%.
The device performs the same electronic adjustment function
as a mechanical potentiometer with enhanced resolution, solid
state reliability, and superior low temperature coefficient per­formance. The versatile programming of the AD5235 via an
SPI®-compatible serial interface allows 16 modes of operation
and adjustment including scratchpad programming, memory
storing and restoring, increment/decrement, ±6 dB/step log taper
adjustment, wiper setting readback, and extra EEMEM
defined information such as memory data for other components,
look-up table, or system identification information.

1

The terms nonvolatile memory and EEMEM are used interchangeably.

2

The terms digital potentiometer and RDAC are used interchangeably.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

2

with 1024-step resolution, offering

1

for user-

Nonvolatile Memory, Dual

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

In the scratchpad programming mode, a specific setting can
be programmed directly to the RDAC
resistance between Terminal W and Terminal A and Te rm i na l W
and Terminal B. This setting can be stored into the EEMEM
and is restored automatically to the RDAC register during
system power-on.

The EEMEM content can be restored dynamically or through
external

PR

strobing, and a WP function protects EEMEM
contents. To simplify the programming, the independent or
simultaneous linear-step increment or decrement commands
can be used to move the RDAC wiper up or down, one step at
a time. For logarithmic ±6 dB changes in the wiper setting, the
left or right bit shift command can be used to double or halve the
RDAC wiper setting.

The AD5235 patterned resistance tolerance is stored in the
EEMEM. The actual end-to-end resistance can, therefore, be
known by the host processor in readback mode. The host can
execute the appropriate resistance step through a software
routine that simplifies open-loop applications as well as
precision calibration and tolerance matching applications.

The AD5235 is available in a thin, 16-lead TSSOP package.
The part is guaranteed to operate over the extended industrial
temperature range of −40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

2

register, which sets the

www.analog.com

AD5235 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications ..................................................................................... 4

Electrical Characteristics—25 kΩ, 250 kΩ Vers ions ............... 4

Interface Timing and EEMEM Reliability Characteristics—

25 kΩ, 250 kΩ Versions ............................................................... 6

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

Test Circuits ................................................................................. 14

Theory of Operation ...................................................................... 16

Scratchpad and EEMEM Programming .................................. 16

Basic Operation .......................................................................... 16

EEMEM Protection .................................................................... 17

Digital Input and Output Configuration................................. 17

Serial Data Interface ................................................................... 17

Daisy-Chain Operation ............................................................. 18

Terminal Voltage Operating Range .......................................... 18

Advanced Control Modes ......................................................... 20

RDAC Structure .......................................................................... 21

Programming the Variable Resistor ......................................... 22

Programming the Potentiometer Divider ............................... 22

Programming Examples ............................................................ 23

EVA L-AD5235SDZ Evaluation Kit .......................................... 23

Applications Information .............................................................. 24

Bipolar Operation from Dual Supplies.................................... 24

Gain Control Compensation .................................................... 24

High Voltage Operation ............................................................ 24

DAC .............................................................................................. 24

Bipolar Programmable Gain Amplifier ................................... 25

10-Bit Bipolar DAC .................................................................... 25

Programmable Voltage Source with Boosted Output ........... 25

Programmable Current Source ................................................ 26

Programmable Bidirectional Current Source ......................... 26

Programmable Low-Pass Filter ................................................ 27

Programmable Oscillator .......................................................... 27

Optical Transmitter Calibration with ADN2841 ................... 28

Resistance Scaling ...................................................................... 28

Resistance Tolerance, Drift, and Temperature Coefficient

Mismatch Considerations ......................................................... 29

RDAC Circuit Simulation Model ............................................. 29

Outline Dimensions ....................................................................... 30

Ordering Guide .......................................................................... 30

Rev. F | Page 2 of 32

Data Sheet AD5235

REVISION HISTORY

6/12—Rev. E to Rev. F

Changes to Table 1 Conditions ........................................................ 4

Removed Positive Supply Current RDY and/or SDO Floating
Parameters and Negative Supply Current RDY and/or SDO

Floating Parameters, Table 1 ............................................................ 5

Added Endnote 2 to Ordering Guide ........................................... 30

4/11—Rev. D to Rev. E

Changes to Figure 12 ...................................................................... 11

4/11—Rev. C to Rev. D

Changes to EEMEM Performance .............................. Throughout

Changes to Features and General Descriptions Sections ............. 1

Changes to Specifications Section ................................................... 4

Changes to Pin 5, Pin 13, Pin 14 Descriptions .............................. 9

Changes to Typical Performance Characteristics Section ......... 10

Changes to Table 7 .......................................................................... 19

Changes to Table 9 .......................................................................... 21

Changes to Rheostat Operation Section, Table 12, Table 13 ..... 22

Changes to Table 16, Table 19, and EVAL-AD5235SDZ

Evaluation Kit Section .................................................................... 23

Changes to RDAC Circuit Simulation Model Section ............... 29

Updated Outline Dimensions ........................................................ 30

Changes to Ordering Guide ........................................................... 30

4/09—Rev. B to Rev. C

Changes to Figure 1........................................................................... 1

Changes to Specifications ................................................................. 3

Changes to SDO, Description Column, Table 4 ............................ 8

Changes to Figure 18 ...................................................................... 11

Changes to Theory of Operation Section .................................... 14

Changes to Serial Data Interface Section ..................................... 15

Changes to Linear Increment and Decrement Instructions
Section, Logarithmic Taper Mode Adjustment Section, and

Figure 42 ........................................................................................... 18

Changes to Rheostat Operations Section ..................................... 20

Changes to Bipolar Programmable Gain Amplifier Section,

Figure 49, Table 21, and 10-Bit Bipolar DAC Section ................ 23

Changes to Programmable Oscillator Section and Figure 56 ... 25

Changes to Ordering Guide ........................................................... 28

7/04—Rev. A to Rev. B

Updated Formatting .......................................................... Universal

Edits to Features, General Description, and Block Diagram ...... 1

Changes to Specifications................................................................. 3

Replaced Timing Diagrams ............................................................. 6

Changes to Absolute Maximum Ratings........................................ 7

Changes to Pin Function Descriptions .......................................... 8

Changes to Typical Performance Characteristics ......................... 9

Additional Test Circuit (Figure 36)................................................. 9

Edits to Theory of Operation ........................................................ 14

Edits to Applications ....................................................................... 23

Updated Outline Dimensions........................................................ 27

8/02—Rev. 0 to Rev. A

Change to Features and General Description ............................... 1

Change to Specifications .................................................................. 2

Change to Calculating Actual End-to-End Terminal

Resistance Section ........................................................................... 14

Rev. F | Page 3 of 32

AD5235 Data Sheet

Resistor Differential Nonlinearity2

R-DNL

RWB

−1 +1

LSB

Output Logic Low

VOL

IOL = 1.6 mA, V

= 5 V (see

0.4

V

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS

VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V, VA = VDD, VB = VSS, −40°C < TA < +85°C, unless otherwise noted.

These specifications apply to versions with a date code 1209 or later.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT

MODE (All RDACs)

Resistor Integral Nonlinearity2 R-INL RWB −2 +2 LSB

Nominal Resistor Tolerance ∆RAB/RAB −8 +8 %

Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C

Wiper Resistance RW IW = 1 V/RWB, code = midscale

VDD = 5 V 30 60 Ω
VDD = 3 V 50 Ω

Nominal Resistance Match R
DC CHARACTERISTICS—

POTENTIOMETER DIVIDER MODE

(All RDACs)

Resolution N 10 Bits

Differential Nonlinearity3 DNL −1 +1 LSB

Integral Nonlinearity3 INL −1 +1 LSB

Voltage Divider Temperature

Coefficient
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Terminal Voltage Range4 VA, VB, VW VSS VDD V
Capacitance Ax, Bx5 CA, CB f = 1 MHz, measured to GND,

Capacitance Wx5 CW f = 1 MHz, measured to GND,

Common-Mode Leakage Current

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH With respect to GND, VDD = 5 V 2.4 V
Input Logic Low VIL With respect to GND, VDD = 5 V 0.8 V
Input Logic High VIH With respect to GND, VDD = 3 V 2.1 V
Input Logic Low VIL With respect to GND, VDD = 3 V 0.6 V
Input Logic High VIH With respect to GND, VDD = +2.5 V,

Input Logic Low VIL With respect to GND, VDD = +2.5 V,

Output Logic High (SDO, RDY) VOH R

Input Current IIL VIN = 0 V or VDD ±1 µA
Input Capacitance5 CIL 5 pF

±0.1 %

AB1/RAB2

(∆VW/VW)/∆T × 106 Code = midscale 15 ppm/°C

Code = full scale −6 0 LSB

WFSE

Code = zero scale 0 4 LSB

WZSE

11 pF

code = midscale

80 pF

code = midscale

5, 6

ICM VW = VDD/2 0.01 ±1 µA

2.0 V

V

= −2.5 V

SS

0.5 V

V

= −2.5 V

SS

= 2.2 kΩ to 5 V (see

PULL-UP

4.9 V

Figure 38)

Figure 38)

LOGIC

Rev. F | Page 4 of 32

Data Sheet AD5235

Negative Supply Current

ISS

VDD = +2.5 V, VSS = −2.5 V

f = 1 kHz, code = midscale

RAB = 25 kΩ

0.009

%

Resistor Noise Density

e

RAB = 25 kΩ/250 kΩ

20/64

nV/√Hz

Parameter Symbol Conditions Min Typ1 Max Unit

POWER SUPPLIES

Single-Supply Power Range VDD VSS = 0 V 2.7 5.5 V
Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD VIH = VDD or VIL = GND 2 5 µA

VIH = VDD or VIL = GND −4 −2 µA
EEMEM Store Mode Current IDD (store) VIH = VDD or VIL = GND,

V

= GND, ISS ≈ 0

SS

ISS (store) VDD = +2.5 V, VSS = −2.5 V −2 mA
EEMEM Restore Mode Current7 IDD (restore) VIH = VDD or VIL = GND,

V

= GND, ISS ≈ 0

SS

ISS (restore) VDD = +2.5 V, VSS = −2.5 V −320 µA
Power Dissipation8 P

VIH = VDD or VIL = GND 10 30 µW

DISS

Power Supply Sensitivity5 PSS ∆VDD = 5 V ± 10% 0.006 0.01 %/%

DYNAMIC CHARACTERISTICS

5, 9

Bandwidth BW −3 dB, RAB = 25 kΩ/250 kΩ 125/12 kHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V,

RAB = 250 kΩ 0.035 %

VW Settling Time tS VA = VDD, VB = 0 V, VW = 0.50% error

band, from zero scale to midscale
RAB = 25 kΩ 4 µs
RAB = 250 kΩ 36 µs

N_WB

Crosstalk (CW1/CW2) CT VA1 = VDD, VB1 = VSS , measured VW2

with VW1 making full-scale change,

= 25 kΩ/250 kΩ

R

AB

Analog Crosstalk CTA V

= 5 V p-p, f = 1 kHz, measured

AB2

VW1, Code 1 = midscale, Code 2 =

full scale, R

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. I

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of

±1 LSB maximum are guaranteed monotonic operating conditions (see Figure 28).

4

Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-

referenced bipolar signal adjustment.

5

Guaranteed by design and not subject to production test.

6

Common-mode leakage current is a measure of the dc leakage from any Terminal A, Terminal B, or Terminal W to a common-mode bias level of VDD/2.

7

EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register.

8

P

is calculated from (IDD × VDD) + (ISS × VSS).

DISS

9

All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.

= 25 kΩ/250 kΩ

AB

WB = (VDD − 1)/RWB (see Figure 27).

2 mA

320 µA

30/60

−110/−100

nV-s

dB

Rev. F | Page 5 of 32

AD5235 Data Sheet

Input Clock Pulse Width

t4, t5

Clock level high or low

10

ns

CLK to SDO Propagation Delay2

t10

RP = 2.2 kΩ, CL < 20 pF

50

ns

CLK to SDO Data Hold Time

t11

RP = 2.2 kΩ, CL < 20 pF

0

ns

Read EEMEM Time4

t16

Applies to Instructions 0x8, 0x9, 0x10

7 30

µs

Data Retention8

100 Years

INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS

Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with t
measured using both V

= 2.7 V and VDD = 5 V.

DD

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

Clock Cycle Time (t

Setup Time t2 10 ns

CS

) t1 20 ns

CYC

CLK Shutdown Time to CS Rise t3 1 t

Data Setup Time t6 From positive CLK transition 5 ns
Data Hold Time t7 From positive CLK transition 5 ns

to SDO-SPI Line Acquire t8 40 ns

CS

to SDO-SPI Line Release t9 50 ns

CS

= tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are

R

CYC

High Pulse Width3 t12

CS

High to CS High3 t13 4 t

CS

10 ns

CYC

RDY Rise to CS Fall t14 0 ns

Rise to RDY Fall Time t15 0.15 0.3 ms

CS
Store EEMEM Time

Rise to Clock Rise/Fall Setup t17 10 ns

CS
Preset Pulse Width (Asynchronous)6 t
Preset Response Time to Wiper Setting6 t
Power-On EEMEM Restore Time6 t

4, 5

t16 Applies to Instructions 0x2, 0x3 15 50 ms

50 ns

PRW

PRESP

30 µs

EEMEM

pulsed low to refresh wiper positions

PR

30 µs

FLASH/EE MEMORY RELIABILITY

Endurance7 TA = 25°C 1
100

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Propagation delay depends on the value of VDD, R

3

Valid for commands that do not activate the RDY pin.

4

The RDY pin is low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 µs; CMD_9, CMD_10 ~ 7 µs;

CMD_2, CMD_3 ~ 15 ms;

5

Store EEMEM time depends on the temperature and EEMEM writes cycles. Higher timing is expected at a lower temperature and higher write cycles.

6

Not shown in Figure 2 and Figure 3.

7

Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C.

8

Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV

derates with junction temperature in the Flash/EE memory.

PR

hardware pulse ~ 30 µs.

PULL-UP

, and CL.

MCycles
kCycles

Rev. F | Page 6 of 32

Data Sheet AD5235

CPOL = 1

t

12

t

13

t

3

t

17

t

9

t

11

t

5

t

4

t

2

t

1

CLK

t

8

B24*

B23 (MSB) B0 (LSB)

B23 (MSB)

HIGH
OR LOW

HIGH
OR LOW

B23 B0

B0 (LSB)

RDY

CPHA = 1

t

10

t

7

t

6

t

14

t

15

t

16

*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE LSB OF THE CHARACTE R P RE V IOUSLY TRANSMITTED.

THE CPOL = 1 MICROCONTROLLER COMM AND ALIGNS THE INCOMING DATATO THE POSITIVE EDGE OF THE CLOCK.

SDO

SDI

02816-002

CS

t

12

t

13

t

3

t

17

t

9

t

11

t

5

t

4

t

2

t

1

CLK

CPOL = 0

t

8

B23 (MSB OUT) B0 (LSB)

SDO

B23 (MSB IN)

B23 B0

HIGH
OR LOW

HIGH
OR LOW

B0 (LSB)

SDI

RDY

CPHA = 0

t

10

t

7

t

6

t

14

t

15

t

16

*THE EXT

RA BIT THAT IS NOT DEFINED IS NORMALLY THE MSB OF THE CHARAC

TER JUST RECEIVED.

THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

*

CS

02816-003

Timing Diagrams

Figure 2. CPHA = 1 Timing Diagram

Figure 3. CPHA = 0 Timing Diagram

Rev. F | Page 7 of 32

AD5235 Data Sheet

Vapor Phase (60 sec)

215°C

Package Power Dissipation

(TJ max − TA)/θJA

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7 V
VSS to GND +0.3 V to −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS − 0.3 V to VDD + 0.3 V
IA, IB, IW

Pulsed1 ±20 mA

Continuous ±2 mA
Digital Input and Output Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range2 −40°C to +85°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering

Infrared (15 sec) 220°C
Thermal Resistance

Junction-to-Ambient θJA,TSSOP-16 150°C/W

Junction-to-Case θJC, TSSOP-16 28°C/W

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Includes programming of nonvolatile memory.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. F | Page 8 of 32

Data Sheet AD5235

SDI
SDO
GND

A1

V

SS

W1

CLK

B1

CS
PR
WP
V

DD

A2

02816-005

W2
B2

RDY

1

2

3

4

5

6

7
8

16

15

14

13
12

11

10

9

AD5235

TOP VIEW

(Not to S cale)

4

GND

Ground Pin, Logic Ground Reference.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
2 SDI Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
3 SDO Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO

output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and
after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI
bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This
previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up
resistor in the range of 1 kΩ to 10 kΩ is needed.

5 VSS Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink

2 mA for 15 ms when storing data to EEMEM.
6 A1 Terminal A of RDAC1.
7 W1 Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0.
8 B1 Terminal B of RDAC1.
9 B2 Terminal B of RDAC2.
10 W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.
11 A2 Terminal A of RDAC2.
12 VDD Positive Power Supply.
13

Optional Write Protect. When active low, WP prevents any changes to the present contents, except PR strobe.

WP

CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie WP to VDD, if not used.
14

Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM

PR

register. Factory default loads midscale until EEMEM is loaded with a new value by the user.

is activated

PR

at the logic high transition. Tie PR to VDD, if not used.
15

Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.

CS

16 RDY Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,

Instruction 9, Instruction 10, and

PR

.

Rev. F | Page 9 of 32

AD5235 Data Sheet

DIGITAL CODE

0 200 400 600 1000

INL ERROR ( LSB)

800

0.20

–0.20

–0.15

–0.10

–0.05

0

0.05

0.10

0.15

–40°C

+25°C

+85°C

02816-006

DIGITAL CODE

0 200 400 600 1000

DNL ERROR (L S B)

800

0.16

–0.04

–0.02

0.02

0

0.04

0.06

0.08

0.10

0.12

0.14

02816-007

–40°C

+25°C

+85°C

DIGITAL CODE

0 200 400 600 1000

INL ERROR ( LSB)

800

0.20

–0.20

–0.15

–0.10

–0.05

0

0.05

0.10

0.15

–40°C

+25°C

+85°C

02816-008

DIGITAL CODE

0 200 400 600 1000

DNL ERROR (L S B)

800

0.20

–0.15

–0.10

–0.05

0

0.05

0.10

0.15

02816-009

–40°C

+25°C

+85°C

CODE (Decimal )

POTENTIOMETER MODE TEMPCO (ppm/°C)

200

180

160

140

120

100

80

60

40

20

0

0 1023768512256

25kΩ
250kΩ

02816-010

02816-011

CODE (Decimal )

RHEOSTAT MODE TEMPCO (ppm/°C)

200

180

160

140

120

100

80

60

40

20

0

0 1023768512256

25kΩ
250kΩ

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. INL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

Figure 6. DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

Figure 8. R-DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

Figure 9. (∆VW/VW)/∆T × 106 Potentiometer Mode Tempco

Figure 7. R-INL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

Figure 10. (∆RWB/RWB)/∆T × 106 Rheostat Mode Tempco

Rev. F | Page 10 of 32

Data Sheet AD5235

CODE (Decimal )

0 200 400 800600 1000

WIPER ON RESISTANCE (Ω)

60

50

40

30

20

10

0

2.7V

3.0V

3.3V

5.0V

5.5V

02816-012

TEMPERATURE (°C)

–40 –20 0 20 40 60 8580

I

DD

/I

SS

(µA)

3

–3

–2

–1

0

1

2

I

DD

= 2.7V

I

DD

= 3.3V

I

DD

= 3.0V

I

DD

= 5.5V

I

DD

= 5.0V

I

SS

= 2.7V

I

SS

= 3.3V

I

SS

= 3.0V

I

SS

= 5.5V

I

SS

= 5.0V

02816-013

FREQUENCY (MHz)

1 1098765432

I

DD

(µA)

50

10

20

30

40

0

FULL SCALE
MIDSCALE
ZERO SCAL E

02816-014

0

100

200

300

400

I

DD

(µA)

VDIO (V)

2.7V

3.0V

3.3V

5.0V

5.5V

02816-015

0 1 2 3 4 5

0.12

0

0.02

0.04

0.06

0.08

0.10

10 100 1k 10k 100k

THD + N (%)

FREQUENCY ( Hz )

250kΩ

25kΩ

02816-115

10

0.001

0.01

0.1

1

0.0001 0.001 0.01 0.1 1 10

THD + N (%)

AMPLIT UDE ( V rms)

250kΩ

25kΩ

02816-116

Figure 11. Wiper On Resistance vs. Code

Figure 12. IDD vs. Temperature

Figure 14. IDD vs. Digital Input Voltage

Figure 15. THD + Noise vs. Frequency

Figure 13. IDD vs. Clock Frequency, RAB = 25 kΩ

Figure 16. THD + Noise vs. Amplitude

Rev. F | Page 11 of 32

AD5235 Data Sheet

FREQUENCY

(Hz)

02816-016

1k 10k 100k 1M

GAIN (dB)

3

–3

0

–6

–9

–12

V

DD

/V

SS

= ±2.5V

V

A

= 1V rms

D = MIDSCALE

f

–3dB

= 12kHz

R

AB

= 250kΩ

R

AB

= 25kΩ

f

–3dB

= 125kHz

FREQUENCY (Hz)

02816-017

1k 10k 100k 1M

GAIN (dB)

0

–20

–10

–30

–40

–50

–60

CODE 0x200

0x100
0x080
0x040

0x020
0x010
0x008

0x004
0x002

0x001

FREQUENCY (Hz)

02816-018

1k 10k 100k 1M

0

–20

–10

–30

–40

–50

–60

GAIN (dB)

CODE 0x200

0x100
0x080
0x040

0x020
0x010

0x008
0x004

0x002
0x001

FREQUENCY ( Hz )

10 100 1k 10k 100k 1M

PSRR (dB)

–80

–60

–70

–50

–40

–30

–20

–10

0

R

AB

= 250kΩ

V

DD

= 5V ± 10% AC

V

SS

= 0V, V

A

= 4V, V

B

= 0V

MEASURED AT V

W

WITH CO DE = 0x200

T

A

= 25°C

R

AB

= 25kΩ

02816-019

02816-020

VDD = 5V
V

A

= 5V

V

B

= 0V

T

A

= 25°C

1V/DIV

10µs/DIV

V

DD

VW (FULL SCALE)

TIME (µs)

0 20 40 60 80 100 120

144

AMPLITUDE (V)

2.5196

2.484

2.488

2.492

2.496

2.500

2.504

2.508

2.512

2.516

2.4796

V

DD

= V

SS

= 5V

CODE = 0x200 T O 0x1FF

02816-021

Figure 17. −3 dB Bandwidth vs. Resistance (See Figure 33)

Figure 18. Gain vs. Frequency vs. Code, RAB = 25 kΩ (See Figure 33)

Figure 20. PSRR vs. Frequency

Figure 21. Power-On Reset

Figure 19. Gain vs. Frequency vs. Code, RAB = 250 kΩ (See Figure 33)

Figure 22. Midscale Glitch Energy, RAB = 25 kΩ

Rev. F | Page 12 of 32

Data Sheet AD5235

TIME (µs)

AMPLITUDE (V)

0 20 40 60 80 100 120

144

2.3795

2.344

2.348

2.352

2.356

2.360

2.364

2.368

2.372

2.376

2.3399

02816-022

02816-023

CS (5V/DIV)

CLK (5V/DI V )

SDI (5V/DIV)

IDD (2mA/DIV)

VDD = 5V

T

A

= 25°C

2.60

2.55

2.50

2.45

2.40
0 0.5 1.0 1.5 2.0

WIPER VOLTAGE (V)

TIME (µs)

02816-126

CODE (Decimal )

02816-025

100

1

0.01
1023

THEORECT ICAL (I

WB_MAX

– mA)

0.1

10

896768640512384128 2560

VA = V

B

= OPEN

T

A

= 25°C

R

AB

= 25kΩ

R

AB

= 250kΩ

Figure 23. Midscale Glitch Energy, RAB = 250 kΩ

Figure 25. Digital Feedthrough

Figure 24. IDD vs. Time when Storing Data to EEMEM

Figure 26. I

WB_MAX

vs. Code

Rev. F | Page 13 of 32

AD5235 Data Sheet

A

W

B

NC

I

W

DUT

V

MS

NC = NO CONNECT

02816-026

A

W

B

DUT

V

MS

V+

02816-027

V+ = V

DD

1LSB = V+/2

N

A

W

B

DUT

I

W

= V

DD

/R

NOMINAL

V

MS1

V

MS2

V

W

02816-028

R

W

= [V

MS1

– V

MS2

]/I

W

A

W

B

V

MS

V+ = V

DD

±10%

PSRR (dB) = 20 L OG

V

MS

ΔV

DD

(

)

~

V

A

V

DD

ΔV

MS

%

ΔV

DD

%

PSS (%/%) =

V+

02816-029

Δ

OFFSET BIAS

OFFSET

GND

ABDUT

W

5V

V

IN

V

OUT

OP279

02816-030

OFFSET BIAS

OFFSET

GND

ABDUT

W

5V

V

IN

V

OUT

OP279

02816-031

OFFSET

GND

A

B

DUT

W

+15V

V

IN

V

OUT

OP42

–15V

2.5V

02816-032

+

–

DUT

CODE = 0x00

0.1V

V

SS

TO V

DD

RSW=

0.1V
I

SW

I

SW

W

B

A = NC

02816-033

TEST CIRCUITS

Figure 27 to Figure 37 define the test conditions used in the Specifications section.

Figure 27. Resistor Position Nonl inearity Error (Rheostat Operation; R-INL, R-DNL)

Figure 28. Potentiometer Divider Nonlinearity Error (INL, DNL)

Figure 29. Wiper Resistance

Figure 31. Inverting Gain

Figure 32. Noninverting Gain

Figure 33. Gain vs. Frequency

Figure 30. Power Supply Sensitivity (PSS, PSRR)

Figure 34. Incremental On Resistance

Rev. F | Page 14 of 32

Data Sheet AD5235

DUT

V

SS

I

CM

W

B

V

DD

NC

NC

V

CM

GND

A

NC = NO CONNECT

02816-034

02816-035

A1

RDAC1 RDAC2

W1

NC

B1

A2

W2

B2

C

TA

= 20 LOG[V

OUT

/V

IN

]

NC = NO CONNECT

V

IN

V

OUT

V

SS

V

DD

02816-036

200µA I

OL

200µA I

OH

V

OH

(MIN)
OR
V

OL

(MAX)

TO OUTPUT

PIN

C

L

50pF

Figure 35. Common-Mode Leakage Current

Figure 37. Load Circuit for Measuring VOH and VOL

(The diode bridge test circuit is equ ivalent to the

application circuit with R

PULL-UP

of 2.2 kΩ.)

Figure 36. Analog Crosstalk

Rev. F | Page 15 of 32

AD5235 Data Sheet

THEORY OF OPERATION

The AD5235 digital potentiometer is designed to operate as a
true variable resistor. The resistor wiper position is determined
by the RDAC register contents. The RDAC register acts as a
scratchpad register, allowing unlimited changes of resistance
settings. The scratchpad register can be programmed with any
position setting using the standard SPI serial interface by loading
the 24-bit data-word. In the format of the data-word, the first four
bits are commands, the following four bits are addresses, and the
last 16 bits are data. When a specified value is set, this value can
be stored in a corresponding EEMEM register. During subsequent
power-ups, the wiper setting is automatically loaded to that value.

Storing data to the EEMEM register takes about 15 ms and
consumes approximately 2 mA. During this time, the shift
register is locked, preventing any changes from taking place.
The RDY pin pulses low to indicate the completion of this
EEMEM storage. There are also 13 addresses with two bytes
each of user-defined data that can be stored in the EEMEM
register from Address 2 to Address 14.

The following instructions facilitate the programming needs
of the user (see Table 7 for details):

0. Do nothing.

1. Restore EEMEM content to RDAC.

2. Store RDAC setting to EEMEM.

3. Store RDAC setting or user data to EEMEM.

4. Decrement by 6 dB.

5. Decrement all by 6 dB.

6. Decrement by one step.

7. Decrement all by one step.

8. Reset EEMEM content to RDAC.

9. Read EEMEM content from SDO.

10. Read RDAC wiper setting from SDO.

11. Write data to RDAC.

12. Increment by 6 dB.

13. Increment all by 6 dB.

14. Increment by one step.

15. Increment all by one step.

Table 14 to Tabl e 20 provide programming examples that use
some of these commands.

SCRATCHPAD AND EEMEM PROGRAMMING

The scratchpad RDAC register directly controls the position of
the digital potentiometer wiper. For example, when the scratchpad
register is loaded with all 0s, the wiper is connected to Te rmi na l B
of the variable resistor. The scratchpad register is a standard
logic register with no restriction on the number of changes
allowed, but the EEMEM registers have a program erase/write
cycle limitation.

BASIC OPERATION

The basic mode of setting the variable resistor wiper position
(programming the scratchpad register) is accomplished by
loading the serial data input register with Instruction 11 (0xB),
Address 0, and the desired wiper position data. When the proper
wiper position is determined, the user can load the serial data
input register with Instruction 2 (0x2), which stores the wiper
position data in the EEMEM register. After 15 ms, the wiper
position is permanently stored in nonvolatile memory.

Table 5 provides a programming example listing the sequence
of the serial data input (SDI) words with the serial data output
appearing at the SDO pin in hexadecimal format.

Table 5. Write and Store RDAC Settings to EEMEM Registers

SDI SDO Action

0xB00100 0xXXXXXX Writes data 0x100 to the RDAC1 register,

Wiper W1 moves to 1/4 full-scale position.

0x20XXXX 0xB00100 Stores RDAC1 register content into the

EEMEM1 register.

0xB10200 0x20XXXX Writes Data 0x200 to the RDAC2 register,

Wiper W2 moves to 1/2 full-scale position.

0x21XXXX 0xB10200 Stores RDAC2 register contents into the

EEMEM2 register.

At system power-on, the scratchpad register is automatically
refreshed with the value previously stored in the corresponding
EEMEM register. The factory-preset EEMEM value is midscale.
The scratchpad register can also be refreshed with the contents
of the EEMEM register in three different ways. First, executing
Instruction 1 (0x1) restores the corresponding EEMEM value.
Second, executing Instruction 8 (0x8) resets the EEMEM values
of both channels. Finally, pulsing the
EEMEM settings. Operating the hardware control
requires a complete pulse signal. When
logic sets the wiper at midscale. The EEMEM value is not
loaded until

PR

returns high.

PR

pin refreshes both

PR

PR

goes low, the internal

function

Rev. F | Page 16 of 32

Data Sheet AD5235

VALID

COMMAND

COUNTER

COMMAND

PROCESSOR

AND ADDRESS

DECODE

(FOR DAIS Y
CHAIN ONLY)

SERIAL

REGISTER

CLK

SDI

5V

R

PULL-UP

SDO

GND

PR WP

AD5235

02816-037

CS

LOGIC

PINS

V

DD

GND

INPUTS

300

Ω

02816-038

V

DD

GND

INPUT

300

Ω

02816-039

WP

EEMEM PROTECTION

The write protect (WP) pin disables any changes to the
scratchpad register contents, except for the EEMEM setting,
which can still be restored using Instruction 1, Instruction 8,
and the
hardware EEMEM protection feature.

DIGITAL INPUT AND OUTPUT CONFIGURATION

All digital inputs are ESD protected, high input impedance that
can be driven directly from most digital sources. Active at logic
low,
internal pull-up resistors are present on any digital input pins.
To avoid floating digital pins that might cause false triggering
in a noisy environment, add pull-up resistors. This is applicable
when the device is detached from the driving source when it is
programmed.

The SDO and RDY pins are open-drain digital outputs that only
need pull-up resistors if these functions are used. To optimize
the speed and power trade-off, use 2.2 kΩ pull-up resistors.

The equivalent serial data input and output logic is shown in
Figure 38. The open-drain output SDO is disabled whenever
chip-select (
inputs is shown in Figure 39 and Figure 40.

PR

pulse. Therefore, WP can be used to provide a

PR

and WP must be tied to VDD, if they are not used. No

CS

) is in logic high. ESD protection of the digital

Figure 38. Equivalent Digital Input and Output Logic

Figure 40. Equivalent

WP

Input Protection

SERIAL DATA INTERFACE

The AD5235 contains a 4-wire SPI-compatible digital interface

CS

(SDI, SDO,
loaded with MSB first. The format of the word is shown in Table 6.
The command bits (C0 to C3) control the operation of the digital
potentiometer according to the command shown in Table 7. A0
to A3 are the address bits. A0 is used to address RDAC1 or RDAC2.
Address 2 to Address 14 are accessible by users for extra EEMEM.
Address 15 is reserved for factory usage. Tab l e 9 provides an
address map of the EEMEM locations. D0 to D9 are the values
for the RDAC registers. D0 to D15 are the values for the EEMEM
registers.

The AD5235 has an internal counter that counts a multiple of
24 bits (a frame) for proper operation. For example, AD5235
works with a 24-bit or 48-bit word, but it cannot work properly
with a 23-bit or 25-bit word. To prevent data from mislocking
(due to noise, for example), the counter resets, if the count is not a
multiple of four when
is multiple of four. In addition, the AD5235 has a subtle feature
that, if
previous command (except during power-up). As a result, care
must be taken to ensure that no excessive noise exists in the CLK or
CS

line that might alter the effective number-of-bits pattern.

The SPI interface can be used in two slave modes: CPHA = 1,
CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer
to the control bits that dictate SPI timing in the following
MicroConverters® and microprocessors: ADuC812, ADuC824,
M68HC11, MC68HC16R1, and MC68HC916R1.

, and CLK). The 24-bit serial data-word must be

CS

goes high but remains in the register if it

CS

is pulsed without CLK and SDI, the part repeats the

Figure 39. Equivalent ESD Digital Input Protection

Rev. F | Page 17 of 32

AD5235 Data Sheet

V

V

DAISY-CHAIN OPERATION

The serial data output pin (SDO) serves two purposes. It can be
used to read the contents of the wiper setting and EEMEM values
using Instruction 10 and Instruction 9, respectively. The remaining
instructions (Instruction 0 to Instruction 8, Instruction 11 to
Instruction 15) are valid for daisy-chaining multiple devices in
simultaneous operations. Daisy-chaining minimizes the number
of port pins required from the controlling IC (see Figure 41). The
SDO pin contains an open-drain N-Ch FET that requires a pull-up
resistor, if this function is used. As shown in Figure 41, users need
to tie the SDO pin of one package to the SDI pin of the next package.
Users may need to increase the clock period because the pull-up
resistor and the capacitive loading at the SDO-to-SDI interface may
require additional time delay between subsequent devices.

When two AD5235s are daisy-chained, 48 bits of data are
required. The first 24 bits (formatted 4-bit command, 4-bit
address, and 16-bit data) go to U2, and the second 24 bits with
the same format go to U1. Keep

clocked into their respective serial registers.

CS

low until all 48 bits are

CS

is then pulled

high to complete the operation.

DD

R

P

2.2k

Ω

AD5235

SDI SDO

U2

CLK

CS

02816-040

MOSI

MICRO-

CONTRO LLER

SCLK SS

Figure 41. Daisy-Chain Configuration Using SDO

AD5235

SDI SDO

U1

CLK

CS

TERMINAL VOLTAGE OPERATING RANGE

The positive VDD and negative VSS power supplies of the AD5235
define the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on Terminal A,
Ter mi na l B , an d Ter mi na l W th at e xc ee d V
the internal forward-biased diodes (see Figure 42).

or VSS are clamped by

DD

DD

The GND pin of the AD5235 is primarily used as a digital
ground reference. To minimize the digital ground bounce,
the AD5235 ground terminal should be joined remotely to
the common ground (see Figure 43). The digital input control
signals to the AD5235 must be referenced to the device ground
pin (GND) and must satisfy the logic level defined in the
Specifications section. An internal level-shift circuit ensures
that the common-mode voltage range of the three terminals
extends from V

to VDD, regardless of the digital input level.

SS

Power-Up Sequence

Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 42), it
is important to power V

and VSS first before applying any

DD

voltage to Terminal A, Terminal B, and Terminal W. Otherwise,
the diode is forward-biased such that V

and VSS are powered

DD

unintentionally. For example, applying 5 V across Terminal A
and Terminal B prior to V

causes the VDD terminal to exhibit

DD

4.3 V. It is not destructive to the device, but it might affect the
rest of the user’s system. The ideal power-up sequence is GND,
V

and VSS, digital inputs, and VA, VB, and VW. The order of

DD

powering V
long as they are powered after V

, VB, VW, and the digital inputs is not important as

A

and VSS.

DD

Regardless of the power-up sequence and the ramp rates of the
power supplies, when V

and VSS are powered, the power-on

DD

preset activates, which restores the EEMEM values to the RDAC
registers.

Layout and Power Supply Bypassing

It is a good practice to employ compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.

Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Bypass supply leads to
the device with 0.01 μF to 0.1 μF disk or chip ceramic capacitors.
Also, apply low ESR, 1 μF to 10 μF tantalum or electrolytic
capacitors at the supplies to minimize any transient disturbance
(see Figure 43).

A

W

B

V

02816-041

SS

Figure 42. Maximum Terminal Voltages Set by V

DD

and V

SS

V

DD

V

SS

+

C1

C3

0.1µF

10µF

+

C4

10µFC20.1µF

Figure 43. Power Supply Bypassing

V

DD

V

SS

AD5235

GND

02816-042

Rev. F | Page 18 of 32

Data Sheet AD5235

MSB

Command Byte 0

Data Byte 1

Data Byte 0

LSB

Restore EEMEM (A0) contents to RDAC (A0)

65 0 1 1 0 0 0 0 A0 X … X X X …

X

Decrement contents of RDAC (A0) by 1,

75 0 1 1 1 X X X X X … X X X …

X

Decrement contents of all RDAC registers by 1,

In Table 6, command bits are C0 to C3, address bits are A0 to A3, Data Bit D0 to Data Bit D9 are applicable to RDAC, and D0 to D15 are
applicable to EEMEM.

Table 6. 24-Bit Serial Data-Word

RDAC C3 C2 C1 C0 0 0 0 A0 X X X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EEMEM C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Command instruction codes are defined in Table 7.

1, 2, 3

Table 7. Command Operation Truth Table

Command Byte 0 Data Byte 1 Data Byte 0

Command
Number

0 0 0 0 0 X X X X X … X X X … X
1 0 0 0 1 0 0 0 A0 X … X X X … X

2 0 0 1 0 0 0 0 A0 X … X X X … X

34 0 0 1 1 A3 A2 A1 A0 D15 … D8 D7 … D0

45 0 1 0 0 0 0 0 A0 X … X X X … X

55 0 1 0 1 X X X X X … X X X … X

B23 B16 B15 B8 B7 B0

C3 C2 C1 C0 A3 A2 A1 A0 X … D9 D8 D7 … D0

Operation

NOP. Do nothing. See

register. See Table 16.
Store wiper setting. Store RDAC (A0) setting to

EEMEM (A0). See
Store contents of Serial Register Data Byte 0

and Serial Register Data Bytes 1 (total 16 bits)
to EEMEM (ADDR). See

Decrement by 6 dB. Right-shift contents of
RDAC (A0) register, stop at all 0s.

Decrement all by 6 dB. Right-shift contents of
all RDAC registers, stop at all 0s.

Table 19

Table 15.

Table 18.

stop at all 0s.

stop at all 0s.

8 1 0 0 0 0 0 0 0 X … X X X … X

9 1 0 0 1 A3 A2 A1 A0 X … X X X … X

10 1 0 1 0 0 0 0 A0 X … X X X … X

11 1 0 1 1 0 0 0 A0 X … D9 D8 D7 … D0

125 1 1 0 0 0 0 0 A0 X … X X X … X

135 1 1 0 1 X X X X X … X X X … X

145 1 1 1 0 0 0 0 A0 X … X X X … X

155 1 1 1 1 X X X X X … X X X … X

1

The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or

Instruction 10, the selected internal register data is present in Data Byte 0 and Data Byte 1. The instructions following Instruction 9 and Instruction 10 must also be a
full 24-bit data-word to completely clock out the contents of the serial register.

2

The RDAC register is a volatile scratchpad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register.

3

Execution of these operations takes place when the CS strobe returns to logic high.

4

Instruction 3 writes two data bytes (16 bits of data) to EEMEM. In the case of Address 0 and Address 1, only the last 10 bits are valid for wiper position setting.

5

The increment, decrement, and shift instructions ignore the contents of the shift register, Data Byte 0 and Data Byte 1.

Reset. Refresh all RDACs with their corresponding
EEMEM previously stored values.

Read contents of EEMEM (ADDR) from
SDO output in the next frame. See

Read RDAC wiper setting from SDO output
in the next frame. See

Write contents of Serial Register Data Byte 0
and Serial Register Data Byte 1 (total 10 bits)
to RDAC (A0). See

Increment by 6 dB: Left-shift contents of RDAC
(A0), stop at all 1s. See

Increment all by 6 dB. Left-shift contents of
all RDAC registers, stop at all 1s.

Increment contents of RDAC (A0) by 1,
stop at all 1s. See

Increment contents of all RDAC registers by 1,
stop at all 1s.

Table 20.

Table 14.

Table 17.

Table 15.

Table 19.

Rev. F | Page 19 of 32

AD5235 Data Sheet

00 0010 0000

00 0000 1111

11 1111 1111

00 0000 0000

CODE (Fro m 1 t o 1023 by 2.0 × 103)

0

GAIN (dB)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

02816-043

0

–40

–20

–60

–80

ADVANCED CONTROL MODES

The AD5235 digital potentiometer includes a set of user
programming features to address the wide number of
applications for these universal adjustment devices.

Key programming features include the following:

• Scratchpad programming to any desirable values

• Nonvolatile memory storage of the scratchpad RDAC

register value in the EEMEM register

• Increment and decrement instructions for the RDAC

wiper register

• Left and right bit shift of the RDAC wiper register to

achieve ±6 dB level changes

• 26 extra bytes of user-addressable nonvolatile memory

Linear Increment and Decrement Instructions

The increment and decrement instructions (Instruction 14,
Instruction 15, Instruction 6, and Instruction 7) are useful for
linear step adjustment applications. These commands simplify
microcontroller software coding by allowing the controller to
send just an increment or decrement command to the device.
The adjustment can be individual or in a ganged potentiometer
arrangement where both wiper positions are changed at the
same time.

For an increment command, executing Instruction 14
automatically moves the wiper to the next resistance segment
position. The master increment command, Instruction 15,
moves all resistor wipers up by one position.

Logarithmic Taper Mode Adjustment

Four programming instructions produce logarithmic taper
increment and decrement of the wiper position control by
an individual potentiometer or by a ganged potentiometer
arrangement where both wiper positions are changed at the
same time. The 6 dB increment is activated by Instruction 12
and Instruction 13, and the 6 dB decrement is activated by
Instruction 4 and Instruction 5. For example, starting with the
wiper connected to Terminal B, executing 11 increment
instructions (Command Instruction 12) moves the wiper in 6 dB
steps from 0% of the R
position of the AD5235 10-bit potentiometer. When the wiper
position is near the maximum setting, the last 6 dB increment
instruction causes the wiper to go to the full-scale 1023 code
position. Further 6 dB per increment instructions do not
change the wiper position beyond its full scale (see Tabl e 8).

The 6 dB step increments and 6 dB step decrements are achieved
by shifting the bit internally to the left or right, respectively. The
following information explains the nonideal ±6 dB step adjustment
under certain conditions. Table 8 illustrates the operation of the
shifting function on the RDAC register data bits. Each table row
represents a successive shift operation. Note that the left-shift
12 and 13 instructions were modified such that, if the data in
the RDAC register is equal to zero and the data is shifted left,

(Terminal B) position to 100% of the RAB

AB

Rev. F | Page 20 of 32

the RDAC register is then set to Code 1. Similarly, if the data in
the RDAC register is greater than or equal to midscale and the data
is shifted left, then the data in the RDAC register is automatically
set to full scale. This makes the left-shift function as ideal a
logarithmic adjustment as possible.

The Right-Shift 4 instruction and Right-Shift 5 instruction are
ideal only if the LSB is 0 (ideal logarithmic = no error). If the
LSB is 1, the right-shift function generates a linear half-LSB
error, which translates to a number-of-bits dependent logarithmic
error, as shown in Figure 44. Figure 44 shows the error of the odd
numbers of bits for the AD5235.

Table 8. Detail Left-Shift and Right-Shift Functions for 6 dB
Step Increment and Decrement

Left-Shift (+6 dB/Step) Right-Shift(–6 dB/Step)

00 0000 0000 11 1111 1111
00 0000 0001 01 1111 1111
00 0000 0010 00 1111 1111
00 0000 0100 00 0111 1111
00 0000 1000 00 0011 1111
00 0001 0000 00 0001 1111

00 0100 0000 00 0000 0111
00 1000 0000 00 0000 0011
01 0000 0000 00 0000 0001
10 0000 0000 00 0000 0000

11 1111 1111 00 0000 0000

Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
Right-Shift 4 command and Right-Shift 5 command execution
contains an error only for odd numbers of bits. Even numbers of
bits are ideal. Figure 44 shows plots of log error [20 × log

10

(error/code)] for the AD5235. For example, Code 3 log error = 20 ×
log

(0.5/3) = −15.56 dB, which is the worst case. The log error plot

10

is more significant at the lower codes (see Figure 44).

Figure 44. Log Error Conformance for Odd Numbers of Bits Only

(Even Numbers of Bits Are Ideal)

Data Sheet AD5235

SW

(1)

SW

(0)

SW

B

B

R

S

R

S

SW

A

SW(2

N

–

1)

A

W

SW(2

N

–

2)

RDAC

WIPER

REGISTER

AND

DECODER

R

S

= RAB/2

N

R

S

DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY

02816-044

Device Resolution

25 kΩ

250 kΩ

Using CS to Re-Execute a Previous Command

Another subtle feature of the AD5235 is that a subsequent CS
strobe, without clock and data, repeats a previous command.

Using Additional Internal Nonvolatile EEMEM

The AD5235 contains additional user EEMEM registers for
storing any 16-bit data such as memory data for other components,
look-up tables, or system identification information. Table 9 pro­vides an address map of the internal storage registers shown in the
functional block diagram (see Figure 1) as EEMEM1, EEMEM2,
and 26 bytes (13 addresses × 2 bytes each) of User EEMEM.

Table 9. EEMEM Address Map

EEMEM No. Address EEMEM Content for …

1 0000 RDAC11
2 0001 RDAC2
3 0010 USER12
4 0011 USER2
… … …
15 1110 USER13
16 1111 R

1

RDAC data stored in EEMEM locations is transferred to the corresponding

RDAC register at power-on, or when Instruction 1, Instruction 8, and
executed.

2

USERx are internal nonvolatile EEMEM registers available to store and

retrieve constants and other 16-bit information using Instruction 3 and
Instruction 9, respectively.

3

Read only.

tolerance3

AB1

PR

are

Calculating Actual End-to-End Terminal Resistance

The resistance tolerance is stored in the EEMEM register during
factory testing. The actual end-to-end resistance can, therefore,
be calculated, which is valuable for calibration, tolerance matching,
and precision applications. Note that this value is read only and
the R

matches with R

AB2

, typically 0.1%.

AB1

The resistance tolerance in percentage is contained in the last
16 bits of data in EEMEM Register 15. The format is the sign
magnitude binary format with the MSB designate for sign
(0 = negative and 1 = positive), the next 7 MSB designate the
integer number, and the 8 LSB designate the decimal number
(see Table 11).

For example, if R
shows XXXX XXXX 1001 1100 0000 1111, R
calculated as follows:

MSB: 1 = positive
Next 7 LSB: 001 1100 = 28
8 LSB: 0000 1111 = 15 × 2
% tolerance = 28.06%
Therefore, R

RDAC STRUCTURE

The patent-pending RDAC contains multiple strings of equal
resistor segments with an array of analog switches that acts as
the wiper connection. The number of positions is the resolution of
the device. The AD5235 has 1024 connection points, allowing it to
provide better than 0.1% setability resolution. Figure 45 shows
an equivalent structure of the connections among the three
terminals of the RDAC. The SW
the switches, SW(0) to SW(2
on the resistance position decoded from the data bits. Because
the switch is not ideal, there is a 50 Ω wiper resistance, R
Wiper resistance is a function of supply voltage and temperature.
The lower the supply voltage or the higher the temperature, the
higher the resulting wiper resistance. Users should be aware of
the wiper resistance dynamics, if accurate prediction of the
output resistance is needed.

= 250 kΩ and the data in the SDO

AB _RATE D

AB_ACTUAL

−8

= 0.06

AB_ACTUAL

= 320.15 kΩ

and SWB are always on, while

A

N

− 1), are on one at a time, depending

Figure 45. Equivalent RDAC Structure

can be

.

W

Table 11. Calculating End-to-End Terminal Resistance

Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Sign
Mag Sign 2

7 Bits for Integer Number

Table 10. Nominal Individual Segment Resistor Values

6

25 24 23 22 21 20

Rev. F | Page 21 of 32

1024-Step 24.4 244

.

2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8

Decimal

Point

8 Bits for Decimal Number

AD5235 Data Sheet

CODE (Decimal )

100

75

0

0 1023256

R

WA

(D), R

WB

(D) (% R

WF

)

512

768

50

25

R

WA

R

WB

02816-045

W

AB

WB

RR

D

DR +×=

1024

)(

W

ABWA

RR

D

DR +×

−

=

1024

1024

)(

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance of the RDAC between Terminal A
and Terminal B, R
1024 positions (10-bit resolution). The final digits of the part
number determine the nominal resistance value, for example,
25 kΩ = 24.4 Ω; 250 kΩ = 244 Ω.

The 10-bit data-word in the RDAC latch is decoded to select one
of the 1024 possible settings. The following description provides
the calculation of resistance, R
part. The first connection of the wiper starts at Terminal B for
Data 0x000. R
it is independent of the nominal resistance. The second connection
is the first tap point where R
for Data 0x001. The third connection is the next tap point
representing R
and so on. Each LSB data value increase moves the wiper up the
resistor ladder until the last tap point is reached at R
25006 Ω. See Figure 45 for a simplified diagram of the equivalent
RDAC circuit. When R
floating or tied to the wiper.

, is available with 25 kΩ and 250 kΩ with

AB

, at different codes of a 25 kΩ

WB

(0) is 30 Ω because of the wiper resistance, and

WB

(1) becomes 24.4 Ω + 30 Ω = 54.4 Ω

WB

(2) = 48.8 Ω + 30 Ω = 78.8 Ω for Data 0x002,

WB

(1023) =

WB

is used, Terminal A can be left

WB

Table 12. R

D (Dec) RWB(D) (Ω) Output State

1023 25,006 Full scale
512 12,530 Midscale
1 54.4 1 LSB
0 30 Zero scale (wiper contact resistor)

Note that, in the zero-scale condition, a finite wiper resistance
of 50 Ω is present. Care should be taken to limit the current
flow between W and B in this state to no more than 20 mA to
avoid degradation or possible destruction of the internal switches.

Like the mechanical potentiometer that the RDAC replaces, the
AD5235 part is symmetrical. The resistance between Wiper W
and Terminal A also produces a digitally controlled complementary
resistance, R
programmability of the various terminal connections. When R
is used, Terminal B can be left floating or tied to the wiper.
Setting the resistance value for R
of resistance and decreases as the data loaded in the latch is
increased in value.

The general transfer equation for this operation is

(D) at Selected Codes for RAB = 25 kΩ

WB

. Figure 46 shows the symmetrical

WA

starts at a maximum value

WA

(2)

WA

For example, the output resistance values in Table 13 are set for
the given RDAC latch codes (applies to R

= 25 kΩ digital

AB

potentiometers).

Table 13. R

(D) at Selected Codes for R

WA

= 25 kΩ

AB

D (Dec) RWA(D) (Ω) Output State

1023 54.4 Full scale
512 12,530 Midscale
1 25,006 1 LSB
0 25,030 Zero scale (wiper contact resistance)

The typical distribution of RAB from channel to channel is

Figure 46. R

(D) and RWB(D) vs. Decimal Code

WA

The general equation that determines the programmed output
resistance between Terminal Bx and Terminal Wx is

±0.2% within the same package. Device-to-device matching is
process lot dependent upon the worst case of ±30% variation.
However, the change in R

with temperature has a 35 ppm/°C

AB

temperature coefficient.

PROGRAMMING THE POTENTIOMETER DIVIDER

(1)

where:
D is the decimal equivalent of the data contained in the RDAC
register.

R

is the nominal resistance between Terminal A and Termi na l B.

AB

R

is the wiper resistance.

W

For example, the output resistance values in Table 12 are set for
the given RDAC latch codes (applies to R
potentiometers).

= 25 kΩ digital

AB

Rev. F | Page 22 of 32

Voltage Output Operation

The digital potentiometer can be configured to generate an output
voltage at the wiper terminal that is proportional to the input
voltages applied to Terminal A and Terminal B. For example,
connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the wiper that can be any value
from 0 V to 5 V. Each LSB of voltage is equal to the voltage
applied across Terminal A to Terminal B divided by the 2

N

position resolution of the potentiometer divider.

Data Sheet AD5235

B

AB

W

VV

D

DV +×=

1024

)(

0x92XXXX

0xXXXXXX

Prepares data read from USER1

0xB00200

0xXXXXXX

Writes RDAC1 to midscale.

0xXXXXXX

0xA003FF

Reads back full-scale value from SDO.

Because the AD5235 can also be supplied by dual supplies, the
general equation defining the output voltage at V

with respect

W

to ground for any given input voltages applied to Terminal A
and Terminal B is

(3)

Equation 3 assumes that V

is buffered so that the effect of wiper

W

resistance is minimized. Operation of the digital potentiometer in
divider mode results in more accurate operation over temperature.
Here, the output voltage is dependent on the ratio of the internal
resistors and not the absolute value; therefore, the drift improves
to 15 ppm/°C. There is no voltage polarity restriction between
Terminal A, Terminal B, and Terminal W as long as the
terminal voltage (V

) stays within VSS < V

TERM

TERM

< VDD.

PROGRAMMING EXAMPLES

The following programming examples illustrate a typical sequence
of events for various features of the AD5235. See Tab l e 7 for the
instructions and data-word format. The instruction numbers,
addresses, and data appearing at the SDI and SDO pins are in
hexadecimal format.

Table 14. Scratchpad Programming

SDI SDO Action

0xB00100 0xXXXXXX Writes Data 0x100 into RDAC1 register,

Wiper W1 moves to 1/4 full-scale
position.

0xB10200 0xB00100 Loads Data 0x200 into RDAC2 register,

Wiper W2 moves to 1/2 full-scale
position.

Table 15. Incrementing RDAC Followed by Storing the
Wiper Setting to EEMEM

SDI SDO Action

0xB00100 0xXXXXXX Writes Data 0x100 into RDAC1

register, Wiper W1 moves to 1/4 full­scale position.

0xE0XXXX 0xB00100 Increments RDAC1 register by one to

0x101.

0xE0XXXX 0xE0XXXX Increments RDAC1 register by one to

0x102. Continue until desired wiper
position is reached.

0x20XXXX 0xXXXXXX Stores RDAC2 register data into

EEMEM1. Optionally, tie
protect EEMEM values.

The EEMEM values for the RDACs can be restored by power­on, by strobing the

PR

pin, or by the two commands shown in

Table 16.

to GND to

WP

Table 16. Restoring the EEMEM Values to RDAC Registers

SDI SDO Action

0x10XXXX 0xXXXXXX Restores the EEMEM1 value to the

RDAC1 register.

Table 17. Using Left-Shift by One to Increment 6 dB Steps

SDI SDO Action

0xC0XXXX 0xXXXXXX Moves Wiper 1 to double the

present data contained in the
RDAC1 register.

0xC1XXXX 0xC0XXXX Moves Wiper 2 to double the

present data contained in the
RDAC2 register.

Table 18. Storing Additional User Data in EEMEM

SDI SDO Action

0x32AAAA 0xXXXXXX Stores Data 0xAAAA in the extra

EEMEM location USER1. (Allowable to
address in 13 locations with a
maximum of 16 bits of data.)

0x335555 0x32AAAA Stores Data 0x5555 in the extra

EEMEM location USER2. (Allowable to
address in 13 locations with a
maximum of 16 bits of data.)

Table 19. Reading Back Data from Memory Locations

SDI SDO Action

EEMEM location.

0x00XXXX 0x92AAAA NOP Instruction 0 sends a 24-bit word

out of SDO, where the last 16 bits
contain the contents in USER1 EEMEM
location.

Table 20. Reading Back Wiper Settings

SDI SDO Action

0xC0XXXX 0xB00200 Doubles RDAC1 from midscale to full

scale.

0xA0XXXX 0xC0XXXX Prepares reading wiper setting from

RDAC1 register.

EVAL-AD5235SDZ EVALUATION KIT

Analog Devices, Inc., offers a user-friendly EVA L-AD5235SDZ
evaluation kit that can be controlled by a PC in conjunction
with the SDP platform. The driving program is self-contained;
no programming languages or skills are needed.

Rev. F | Page 23 of 32

AD5235 Data Sheet

±2.5V p-p

AD5235

V

SS

GND

SDI

CLK

SS

SCLK

MOSI

GND

V

DD

MICRO-

CONTROLLER

±1.25V p-p

V

DD

+2.5V

–2.5V

CS

D = MIDSCALE

A

W

B

02816-046

U1

V

O

R2

02816-047

250kΩ

V

I

R1

47kΩ

C1

11pF

W

B A

C2

2.2pF

2RR

V

O

A1

V+

V–

15V

0V TO 15V

02816-048

C

A

B

W

AD5235

5V

AD8601

V+

V–

5V

V

O

A1

02816-049

AD1582

GND

V

IN

V

OUT

3

2

5V

U11

AD5235

A

B

W

APPLICATIONS INFORMATION

BIPOLAR OPERATION FROM DUAL SUPPLIES

The AD5235 can be operated from ±2.5 V dual supplies, which
enable control of ground referenced ac signals or bipolar operation.
AC signals as high as V

and VSS can be applied directly across

DD

Terminal A to Terminal B with the output taken from Termin al W.
See Figure 47 for a typical circuit connection.

Figure 47. Bipolar Operation from Dual Supplies

GAIN CONTROL COMPENSATION

A digital potentiometer is commonly used in gain control such
as the noninverting gain amplifier shown in Figure 48.

Alternatively, it avoids the ringing or oscillation at the worst
case. For critical applications, find C2 empirically to suit the
oscillation. In general, C2 in the range of a few picofarads to
no more than a few tenths of picofarads is usually adequate
for the compensation.

Similarly, W and A terminal capacitances are connected to the
output (not shown); their effect at this node is less significant
and the compensation can be avoided in most cases.

HIGH VOLTAGE OPERATION

The digital potentiometer can be placed directly in the feedback or
input path of an op amp for gain control, provided that the voltage
across Ter m in al A to Te rm in a l B, Terminal W to Terminal A or
Terminal W to Terminal B does not exceed |5 V|. When high
voltage gain is needed, set a fixed gain in the op amp and let the
digital potentiometer control the adjustable input. Figure 49
shows a simple implementation.

Figure 48. Typical Noninverting Gain Amplifier

When the RDAC B terminal parasitic capacitance is connected
to the op amp noninverting node, it introduces a zero for the 1/β
term with 20 dB/dec, whereas a typical op amp gain bandwidth
product (GBP) has −20 dB/dec characteristics. A large R2 and
finite C1 can cause the frequency of this zero to fall well below
the crossover frequency. Therefore, the rate of closure becomes
40 dB/dec, and the system has a 0° phase margin at the crossover
frequency. If an input is a rectangular pulse or step function, the
output can ring or oscillate. Similarly, it is also likely to ring when
switching between two gain values; this is equivalent to a stop
change at the input.

Depending on the op amp GBP, reducing the feedback resistor
might extend the frequency of the zero far enough to overcome
the problem. A better approach is to include a compensation
capacitor, C2, to cancel the effect caused by C1. Optimum
compensation occurs when R1 × C1 = R2 × C2. This is not
an option because of the variation of R2. As a result, one can
use the previous relationship and scale C2 as if R2 were at its
maximum value. Doing this might overcompensate and
compromise the performance when R2 is set at low values.

Similarly, a compensation capacitor, C, may be needed to dampen
the potential ringing when the digital potentiometer changes
steps. This effect is prominent when stray capacitance at the
inverted node is augmented by a large feedback resistor. Typically,
a picofarad Capacitor C is adequate to combat the problem.

O

DAC

For DAC operation (see Figure 50), it is common to buffer the
output of the digital potentiometer unless the load is much larger
than R
conversion and can drive heavier loads.

Rev. F | Page 24 of 32

Figure 49. 15 V Voltage Span Control

. The buffer serves the purpose of impedance

WB

Figure 50. Unipolar 10-Bit DAC

Data Sheet AD5235

I

V

V

BIPOLAR PROGRAMMABLE GAIN AMPLIFIER

For applications requiring bipolar gain, Figure 51 shows one
implementation. Digital Potentiometer U1 sets the adjustment
range; the wiper voltage (V
between V

and −KVI at a given U2 setting. Configure OP2177

I

) can, therefore, be programmed

W2

(A2) as a noninverting amplifier that yields a transfer function of

V

O

V

K is the ratio of R

where

AD5235

V

I

R2



 KK

1 (4)



R1



U2

A2

A1

AD5235

U1

Figure 51. Bipolar Programmable Gain Amplifier













W1

B2

B1

W1

OP2177

A1

D2

1024

WB1/RWA 1

V

DD

V+

V–

V

SS





)1(




set by U1.

OP2177

A2

–KV

I

DD

V+

V–

R2

V

SS

R1

V

O

C

02816-050

In the simpler (and much more usual) case where K = 1, VO is
simplified to

V 

 1

1 (5)



O

R1



R2



D

22









1024







V





I



Table 21 shows the result of adjusting D2, with OP2177 (A2)
configured as a unity gain, a gain of 2, and a gain of 10. The
result is a bipolar amplifier with linearly programmable gain
and 1024-step resolution.

Table 21. Result of Bipolar Gain Amplifier

D2 R1 = ∞, R2 = 0 R1 = R2 R2 = 9 × R1

0 −1 −2 −10
256 −0.5 −1 −5
512 0 0 0
768 0.5 1 5
1023 0.992 1.984 9.92

10-BIT BIPOLAR DAC

If the circuit in Figure 51 is changed with the input taken from a
precision reference, U1 is set to midscale, and AD8552 (A2) is
configured as a buffer, a 10-bit bipolar DAC can be realized (as
shown in Figure 52). Compared to the conventional DAC, this
circuit offers comparable resolution but not the precision because
of the wiper resistance effects. Degradation of the nonlinearity
and temperature coefficient is prominent near the low values
of the adjustment range. Alternatively, this circuit offers a unique
nonvolatile memory feature that, in some cases, outweighs any
shortfalls in precision.

Without consideration of the wiper resistance, the output of this
circuit is approximately

D

22

+2.5V

REF

 1



V

(6)



REF



+2.5

U2

W2

B2

A1

W1
U1

A2

B1

AD8552

A1

+2.5V

V+

V–

–2.5V

–2.5V

V+

AD8552

V–

A2

–2.5V

REF

U1 = U2 = AD5 2 35

V

O



V 



O

1024



V

I

26U3
VINV

OUT

5

TRIM

GND

ADR421

U1 = MIDSCALE

Figure 52. 10-Bit Bipolar DAC

PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT

For applications that require high current adjustment, such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered (see Figure 53).

V

I

AD5235

A

W

B

U2

AD8601

2N7002

SIGNAL

V+

V–

Figure 53. Programmable Booster Voltage Source

In this circuit, the inverting input of the op amp forces VO to be
equal to the wiper voltage set by the digital potentiometer. The
load current is then delivered by the supply via the N-Ch FET N
(see Figure 53). N

− VO) × IL power. This circuit can source a 100 mA maximum

(V

I

power handling must be adequate to dissipate

1

with a 5 V supply.

For precision applications, a voltage reference, such as ADR421,

ADR03, or ADR370, can be applied at Terminal A of the digital

potentiometer.

LD

V

O

R

BIAS

C

C

I

L

02816-052

1

02816-051

Rev. F | Page 25 of 32

AD5235 Data Sheet

V+

V–

OP1177

U2

V

S

SLEEP

REF191

GND

OUTPUT

3

2

4

6

U1

C1

1µF

AD5235

W

A

B

R

S

102Ω

R

L

100Ω

V

L

I

L

+5V

–2.048V TO V

L

–5V

0V TO (2. 048V + VL)

+5V

+

–

02861-053

1024×

×

=

S

REF

L

R

DV

I

R2B

R2BR2A

+

–15V

OP2177

V+

V–

+15V

+

–

C1

10pF

R2

15k

Ω

R1

150k

Ω

R2B
50

Ω

R

L

500

Ω

V

L

R2A

14.95k

Ω

R1

150k

Ω

I

L

OP2177

V+

V–

+15V

+

–

–15V

A1

AD5235

A

B

W

+2.5V

–2.5V

A2

02816-054

)(

)(

R2BR2AR1'R2'R1

R2AR1R2BR1'

+−

+

PROGRAMMABLE CURRENT SOURCE

A programmable current source can be implemented with the
circuit shown in Figure 54.

PROGRAMMABLE BIDIRECTIONAL CURRENT SOURCE

For applications that require bidirectional current control or
higher voltage compliance, a Howland current pump can be a
solution (see Figure 55). If the resistors are matched, the load
current is

Figure 54. Programmable Current Source

The REF191 is a unique low supply headroom and high current
handling precision reference that can deliver 20 mA at 2.048 V.
The load current is simply the voltage across Term i na l W to
Terminal B of the digital potentiometer divided by R

.

S

(7)

The circuit is simple but be aware that there are two issues.
First, dual-supply op amps are ideal because the ground potential
of REF191 can swing from −2.048 V at zero scale to V

at full

L

scale of the potentiometer setting. Although the circuit works
under single supply, the programmable resolution of the system
is reduced by half. Second, the voltage compliance at V

is

L

limited to 2.5 V, or equivalently, a 125 Ω load. When higher
voltage compliance is needed, consider digital potentiometers,
such as, AD5260, AD5280, and AD7376. Figure 55 shows an
alternate circuit for high voltage compliance.

To achieve higher current, such as when driving a high power
LED, replace U1 with an LDO, reduce R

, and add a resistor in

S

series with the A terminal of the digital potentiometer. This
limits the current of the potentiometer and increases the current
adjustment resolution.

I ×

R1

=

(8)

V

WL

Figure 55. Programmable Bidirectional Current Source

R2B, in theory, can be made as small as necessary to achieve the
current needed within the A2 output current driving capability.
In this circuit, OP2177 delivers ±5 mA in either direction, and
the voltage compliance approaches 15 V. Without the additions
of C1 and C2, the output impedance (looking into V

Z

=

O

Z

can be infinite, if Resistors R1' and R2' match precisely with

O

R1 and R2A + R2B,

respectively, which is desirable. On the other

hand, if the resistors do not match, Z

(9)

can be negative and cause

O

) can be

L

oscillation. As a result, C1, in the range of a few picofarad, is
needed to prevent oscillation from the negative impedance.

Rev. F | Page 26 of 32

Data Sheet AD5235

A

B

V

I

AD8601

+2.5V

V

O

ADJUSTED

CONCURRENTLY

–2.5V

V+

V–

W

R

R2

02816-055

R1

A

B

W

R

C1

C2

U1

ω

C2C1R2R1

O

1

=ω

C2R2

1

C1R1

+

1

D1

02816-056

D2

OP1177

V+

V–

+2.5V

+

–

–2.5V

V

O

U1

R2A

2.1kΩ

R2B

10kΩ

B A

W

R1
1kΩ

AMPLITUDE

ADJUSTMENT

R = R' = AD5235
R2B = AD5231
D1 = D2 = 1N4148

R'

25kΩ
A

B

W

C'

VP

R

25kΩ

A

B

W

C

2.2nF

FREQUENCY

ADJUSTMENT

2.2nF

RC

O

1

=ω

RC

f

O

π=2

1

W

ABWA

RR

D

DR +×

−

=

1024

1024

)(

DD

O

VR2BIV +=

3

2

PROGRAMMABLE LOW-PASS FILTER

In analog-to-digital conversions (ADCs), it is common to
include an antialiasing filter to band limit the sampling signal.
Therefore, the dual-channel AD5235 can be used to construct a
second-order Sallen-Key low-pass filter, as shown in Figure 56.

At the resonant frequency, f
the positive feedback causes the circuit to oscillate. With R = R

C = C

', and R2 = R2A /(R2B + R

or

, the overall phase shift is zero, and

O

), the oscillation frequency is

DIODE

(13)

',

Figure 56. Sallen-Key Low-Pass Filter

The design equations are

V

O

=

V

I

S

2

f

ω

f

2

S

+

Q

(10)

2

ω+

f

(11)

Q =

(12)

First, users should select convenient values for the capacitors.
To achieve maximally flat bandwidth, where Q = 0.707, let C1
be twice the size of C2 and let R1 equal R2. As a result, the user
can adjust R1 and R2 concurrently to the same setting to
achieve the desirable bandwidth.

PROGRAMMABLE OSCILLATOR

In a classic Wien bridge oscillator, the Wien network (R||C, R'C')
provides positive feedback, whereas R1 and R2 provide negative
feedback (see Figure 57).

where R is equal to R

such that :

WA

(14)

At resonance, setting R2/R1 = 2 balances the bridge. In practice,
R2/R1 should be set slightly larger than 2 to ensure that the
oscillation can start. On the other hand, the alternate turn-on
of the diodes, D1 and D2, ensures that R2/R1 is smaller than 2,
momentarily stabilizing the oscillation.

When the frequency is set, the oscillation amplitude can be
turned by R2B because

(15)

V

, ID, and VD are interdependent variables. With proper

O

selection of R2B, an equilibrium is reached such that V

O

converges. R2B can be in series with a discrete resistor to
increase the amplitude, but the total resistance cannot be too
large to saturate the output.

In Figure 56 and Figure 57, the frequency tuning requires that
both RDACs be adjusted concurrently to the same settings.
Because the two channels might be adjusted one at a time, an
intermediate state occurs that might not be acceptable for some
applications. Of course, the increment/decrement instructions
(Instruction 5, Instruction 7, Instruction 13, and Instruction 15)
can all be used. Different devices can also be used in daisy-chain
mode so that parts can be programmed to the same settings
simultaneously.

Figure 57. Programmable Oscillator with Amplitude Control

Rev. F | Page 27 of 32

AD5235 Data Sheet

CS

CLK

SDI

W1
B1

EEMEM

ADN2841

PSET

ERSET

IMODP

IBIAS

02816-057

IMPD

DATAP

DATAN

CLKP

CLKN

CLKN

CLKP
DATAP
DATAN

W2
B2

EEMEM

CONTROL

AD5235

V

CC

V

CC

A1

A2

RDAC1

RDAC2

A1

B1

W1

W2

A2

B2

02816-058

DD

AB

AB

W

V

D

R2RR3

R2R

DV ××

+

=

1024//

)//(

)(

R1

R2

A

B

W

0

02816-059

R3

V

DD

A1

B1

W1

R

02816-060

RRD

RD

R

AB

AB

QUIVALENT

×++×

+×

=

1024200,51

200,51

E

OPTICAL TRANSMITTER CALIBRATION WITH ADN2841

The AD5235, together with the multirate 2.7 Gbps laser diode
driver, ADN2841, forms an optical supervisory system in which
the dual digital potentiometers can be used to set the laser average
optical power and extinction ratio (see Figure 58). The AD5235
is particularly suited for the optical parameter settings because
of its high resolution and superior temperature coefficient
characteristics.

RESISTANCE SCALING

The AD5235 offers 25 kΩ or 250 kΩ nominal resistance. When
users need lower resistance but must maintain the number of
adjustment steps, they can parallel multiple devices. For example,
Figure 59 shows a simple scheme of paralleling two channels of
RDACs. To adjust half the resistance linearly per step, program
both RDACs concurrently with the same settings.

Figure 58. Optical Supervisory System

The ADN2841 is a 2.7 Gbps laser diode driver that uses a
unique control algorithm to manage the average power and
extinction ratio of the laser after its initial factory calibration.
The ADN2841 stabilizes the data transmission of the laser by
continuously monitoring its optical power and correcting the
variations caused by temperature and the degradation of the
laser over time. In the ADN2841, the IMPD monitors the laser
diode current. Through its dual-loop power and extinction
ratio control calibrated by the dual RDACs of the AD5235, the
internal driver controls the bias current, IBIAS, and consequently
the average power. It also regulates the modulation current,
IMODP, by changing the modulation current linearly with slope
efficiency. Therefore, any changes in the laser threshold current
or slope efficiency are compensated for. As a result, the optical
supervisory system minimizes the laser characterization efforts
and, therefore, enables designers to apply comparable lasers
from multiple sources.

Figure 59. Reduce Resistance by Half with Linear Adjustment Characteristics

In voltage divider mode, by paralleling a discrete resistor, as
shown in Figure 60, a proportionately lower voltage appears at
Terminal A to Terminal B. This translates into a finer degree of
precision because the step size at Terminal W is smaller. The
voltage can be found as

(16)

Figure 60. Lowering the Nominal Resistance

Figure 59 and Figure 60 show that the digital potentiometers
change steps linearly. Alternatively, pseudo log taper adjustment
is usually preferred in applications such as audio control. Figure 61
shows another type of resistance scaling. In this configuration,
the smaller the R2 with respect to R

, the more the pseudo log

AB

taper characteristic of the circuit behaves.

Figure 61. Resistor Scaling with Pseudo Log Adjustment Characteristics

The equation is approximated as

(17)

Rev. F | Page 28 of 32

Users should also be aware of the need for tolerance matching
as well as for temperature coefficient matching of the components.

Data Sheet AD5235

AD8601

+

–

V

i

U1

V

O

C1

AB

W

R2

R1*

*REPLACED WITH ANOTHER

CHANNEL OF RDAC

02816-061

AD8601

+

–

V

i

U1

02816-062

V

O

C1

A B

R

W

A

RDAC
25k

Ω

W

80pF

C

B

11pF

C

A

11pF

02816-063

B

RESISTANCE TOLERANCE, DRIFT, AND TEMPERATURE COEFFICIENT MISMATCH CONSIDERATIONS

In rheostat mode operation, such as gain control, the tolerance
mismatch between the digital potentiometer and the discrete
resistor can cause repeatability issues among various systems
(see Figure 62). Because of the inherent matching of the silicon
process, it is practical to apply the dual-channel device in this
type of application. As such, R1 can be replaced by one of the
channels of the digital potentiometer and programmed to a
specific value. R2 can be used for the adjustable gain. Although it
adds cost, this approach minimizes the tolerance and temperature
coefficient mismatch between R1 and R2. This approach also
tracks the resistance drift over time. As a result, these less than
ideal parameters become less sensitive to system variations.

Figure 62. Linear Gain Control with Tracking Resistance Tolerance,

Drift, and Temperature Coefficient

Note that the circuit in Figure 63 can track tolerance, temperature
coefficient, and drift in this particular application. The characteristic
of the transfer function is, however, a pseudo log rather than a
linear gain function.

RDAC CIRCUIT SIMULATION MODEL

The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the −3 dB bandwidth of the AD5235
(25 kΩ resistor) measures 125 kHz at half scale. Figure 17 provides
the large signal bode plot characteristics of the two available
resistor versions, 25 kΩ and 250 kΩ. A parasitic simulation model
is shown in Figure 64.

Figure 64. RDAC Circuit Simulation Model (RDAC = 25 kΩ)

The following code provides a macro model net list for the
25 kΩ RDAC:

.PARAM D = 1024, RDAC = 25E3
*
.SUBCKT DPOT (A, W, B)
*
CA A 0 11E-12
RWA A W {(1-D/1024)* RDAC + 30}
CW W 0 80E-12
RWB W B {D/1024 * RDAC + 30}
CB B 0 11E-12
*
.ENDS DPOT

Figure 63. Nonline ar Gain Control with Tracking Resistanc e Tolerance and Drif t

Rev. F | Page 29 of 32

AD5235 Data Sheet

16

9

81

PIN 1

SEATING
PLANE

8°
0°

4.50

4.40

4.30

6.40

BSC

5.10

5.00

4.90

0.65

BSC

0.15

0.05

1.20
MAX

0.20

0.09

0.75

0.60

0.45

0.30

0.19

COPLANARITY

0.10

COMPLI ANT TO JEDEC STANDARDS MO-153-AB

AD5235BRUZ250-R7

250

−40°C to +85°C

16-Lead TSSOP

RU-16

1,000

5235B250

EVAL-AD5235SDZ

Evaluation Board

1

OUTLINE DIMENSIONS

Figure 65. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature
Range

Model

1, 2

RAB (kΩ)

AD5235BRUZ25 25 −40°C to +85°C 16-Lead TSSOP RU-16 96 5235B25
AD5235BRUZ25-RL7 25 −40°C to +85°C 16-Lead TSSOP RU-16 1,000 5235B25
AD5235BRUZ250 250 −40°C to +85°C 16-Lead TSSOP RU-16 96 5235B250

1

Z = RoHS Compliant Part.

2

The evaluation board is shipped with the 25 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.

3

Line 1 contains the ADI logo followed by the date code, YYWW. Line 2 contains the model number followed by the end-to-end resistance value (note: D = 250 kΩ).

—OR—
Line 1 contains the model number. Line 2 contains the ADI logo followed by the end-to-end resistance value. Line 3 contains the date code, YYWW.

Package
Description

Package
Option

Ordering
Quantity Branding3

Rev. F | Page 30 of 32

Data Sheet AD5235

NOTES

Rev. F | Page 31 of 32

AD5235 Data Sheet

©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and

NOTES

registered trademarks are the property of their respective owners.
D02816-0-6/12(F)

Rev. F | Page 32 of 32