Datasheet AD5233 Datasheet (ANALOG DEVICES)

Nonvolatile Memory, Quad

FEATURES

Nonvolatile memory stores wiper setting
4-channel independent programmable
64-position resolution
Power-on refreshed with EEMEM settings
EEMEM restore time: 140 μs typical
Full monotonic operation
10 kΩ, 50 kΩ, and 100 kΩ terminal resistance
Permanent memory write protection
Wiper setting readback
Predefined linear increment/decrement instructions
Predefined ±6 dB/step log taper increment/decrement

instructions

SPI-compatible serial interface with readback function

2.7 V to 5.5 V single supply or ±2.5 V dual supply
11 bytes extra nonvolatile memory for user-defined data
100-year typical data retention, T

APPLICATIONS

Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Programmable power supply
Sensor calibration

= 55°C

A

64-Position Digital Potentiometer

AD5233

FUNCTIONAL BLOCK DIAGRAM

CS

CLK

SDI

SDO

WP

RDY

O1

O2

PR

GND

DECODE

SDI SERIAL
INTERFACE

SDO

EEMEM

CONTRO L

11 BYTES

USER EEMEM

DIGITAL
OUTPUT
BUFFER

2

DIGITAL 5

REGISTER

EEMEM5

ADDR

REGISTER

EEMEM1

REGISTER

EEMEM2

REGISTER

EEMEM3

REGISTER

EEMEM4

Figure 1.

RDAC1

RDAC2

RDAC3

RDAC4

AD5233

RDAC1

RDAC2

RDAC3

RDAC4

V

A1

W1

B1

A2

W2

B2

A3

W3

B3

A4

W4

B4

V

DD

SS

02794-001

GENERAL DESCRIPTION

The AD5233 is a quad-channel nonvolatile memory,1 digitally
controlled potentiometer
performs the same electronic adjustment function as a mechanical
potentiometer with enhanced resolution, solid-state reliability,
and remote controllability. The AD5233 has versatile program­ming using a serial peripheral interface (SPI) for 16 modes of
operation and adjustment, including scratchpad programming,
memory storing and restoring, increment/decrement, ±6 dB/step
log taper adjustment, wiper setting readback, and extra EEMEM
for user-defined information such as memory data for other
components, look-up tables, or system identification
information.

1

The terms nonvolatile memory and EEMEM are used interchangeably.

2

The terms digital potentiometer and RDAC are used interchangeably.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

2

with a 64-step resolution. The device

In the scratchpad programming mode, a specific setting can
be programmed directly to the RDAC register, which sets the
resistance between Terminal W to Terminal A and Terminal W
to Terminal B. This setting can be stored into the EEMEM and
is transferred automatically to the RDAC register during system
power-on.

The EEMEM content can be restored dynamically or through
external

PR

strobing. A WP function protects EEMEM contents.

To simplify the programming, independent or simultaneous
increment or decrement commands can be used to move the
RDAC wiper up or down, one step at a time. For logarithmic
±6 dB step changes in wiper settings, the left or right bit shift
command can be used to double or halve the RDAC wiper
setting.

The AD5233 is available in a thin 24-lead TSSOP package. The
part is guaranteed to operate over the extended industrial
temperature range of −40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2002–2008 Analog Devices, Inc. All rights reserved.

AD5233

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics—10 kΩ, 50 kΩ, and 100 kΩ

Versions .......................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ............................................. 9

Test Circuits ..................................................................................... 13

Theory of Operation ...................................................................... 15

Scratchpad and EEMEM Programming .................................. 15

Basic Operation .......................................................................... 15

EEMEM Protection .................................................................... 16

Digital Input/Output Configuration ........................................ 16

Serial Data Interface ................................................................... 16

Daisy-Chain Operation ............................................................. 17

Terminal Voltage Operation Range ......................................... 17

Power-Up Sequence ................................................................... 17

Latched Digital Outputs ............................................................ 17

Advanced Control Modes ......................................................... 19

REVISION HISTORY

5/08—Rev. A to Rev. B

Changes to Features ........................................................................... 1

Changes to Table 1 ............................................................................. 3

Changes Figure 3 ............................................................................... 6

Changes to Absolute Maximum Ratings Section .......................... 7

Changes to Figure 17 and Figure 18 .............................................. 11

Changes to Programmable Oscillator Section ............................. 26

Changes to Ordering Guide ........................................................... 29

RDAC Structure.......................................................................... 20

Programming the Variable Resistor ......................................... 20

Programming the Potentiometer Divider ............................... 21

Programming Examples ............................................................ 21

Flash/EEMEM Reliability .......................................................... 22

Applications Information .............................................................. 23

Bipolar Operation from Dual Supplies.................................... 23

Gain Control Compensation .................................................... 23

High Voltage Operation ............................................................ 23

DAC .............................................................................................. 23

Bipolar Programmable Gain Amplifier ................................... 24

Programmable Low-Pass Filter ................................................ 24

Programmable State-Variable Filter ......................................... 25

Programmable Oscillator .......................................................... 26

Programmable Voltage Source with Boosted Output ........... 26

Programmable Current Source ................................................ 27

Programmable Bidirectional Current Source ......................... 27

Resistance Scaling ...................................................................... 27

Doubling the Resolution ........................................................... 28

Re s is t an c e To ler anc e , Dr if t, a n d Te m pe r atu re Mi s mat ch

Considerations ............................................................................ 28

RDAC Circuit Simulation Model ............................................. 28

Outline Dimensions ....................................................................... 29

Ordering Guide .......................................................................... 29

7/04—Rev. 0 to Rev. A

Format updated .................................................................. Universal

Changes to Features, General Description, and Block

Diagram .............................................................................................. 1

Changes to Specifications ................................................................. 3

Replaced Timing Diagrams .............................................................. 6

Changes to Absolute Maximum Ratings ........................................ 7

Changes to Pin Function Descriptions ........................................... 8

Replaced Figure 11 ............................................................................ 9

Added Test Circuit (Figure 36) ...................................................... 13

Changes to Theory of Operation ................................................... 14

Changes to Applications ................................................................. 22

Updated Outline Dimensions ........................................................ 28

Changes to Ordering Guide ........................................................... 28

3/02—Revision 0: Initial Version

Rev. B | Page 2 of 32

AD5233

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS

VDD = 3 V ± 10% or 5 V ± 10%, VSS = 0 V, VA = VDD, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS,

1

Max Unit

RHEOSTAT MODE
Resistor Differential Nonlinearity
Resistor Integral Nonlinearity

2

2

R-INL R

R-DNL RWB, VA = NC, monotonic −0.5 ±0.1 +0.5 LSB

, VA = NC −0.5 ±0.1 +0.5 LSB

WB

Nominal Resistor Tolerance ∆RAB/RAB D = 0x3F −40 +20 %
Resistance Temperature Coefficient (∆RWB/RWB)/∆T × 106 600 ppm/°C
Wiper Resistance RW I

DC CHARACTERISTICS,

= 100 μA, code = half scale 15 100 Ω

W

POTENTIOMETER DIVIDER MODE
Resolution N 6 Bits
Differential Nonlinearity
Integral Nonlinearity
Voltage Divider Temperature

3

3

INL −0.5 +0.1 +0.5 LSB

DNL Monotonic −0.5 +0.1 +0.5 LSB

(∆V

)/∆T × 106 Code = half scale 15 ppm/°C

W/VW

Coefficient
Full-Scale Error V
Zero-Scale Error V

Code = full scale −1.5 0 % FS

WFSE

Code = zero scale 0 1.5 % FS

WZSE

RESISTOR TERMINALS

Terminal Voltage Range
Capacitance A, Capacitance B

4

5

VA, VB, VW V
CA, CB

f = 1 MHz, measured to GND,

VDD V

SS

35 pF

code = half scale

Capacitance W5 CW

f = 1 MHz, measured to GND,

35 pF

code = half scale

Common-Mode Leakage Current

5, 6

I

V

CM

= VDD/2 0.015 1 μA

W

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH With respect to GND, VDD = 5 V 2.4 V
With respect to GND, VDD = 3 V 2.1 V

With respect to GND,

= 2.5 V, VSS = −2.5 V

V

DD

2.0 V

Input Logic Low VIL With respect to GND, VDD = 5 V 0.8 V
With respect to GND, VDD = 3 V 0.6 V

Output Logic High (SDO, RDY) VOH

With respect to GND,

= 2.5 V, VSS = −2.5 V

V

DD

= 2.2 kΩ to 5 V

R

PULL-UP

0.5 V

4.9 V

(see Figure 35)

Output Logic Low VOL

= 1.6 mA, V

I

OL

LOGI C

= 5 V

0.4 V

(see Figure 35)
Input Current IIL V
Input Capacitance
Output Current

5

C

5

I

4 pF

IL

, IO2

O1

= 0 V or VDD ±2.5 μA

IN

= 5 V, VSS = 0 V, TA = 25°C,

V

DD

50 mA

sourcing only

= 2.5 V, VSS = 0 V, TA = 25°C,

V

DD

7 mA

sourcing only

Rev. B | Page 3 of 32

AD5233

Parameter Symbol Conditions Min Typ

1

Max Unit

POWER SUPPLIES

Single-Supply Power Range VDD V

= 0 V 2.7 5.5 V

SS

Dual-Supply Power Range VDD/VSS ±2.5 ±2.75 V
Positive Supply Current IDD V
Negative Supply Current ISS

EEMEM Store Mode Current IDD (store)

I
EEMEM Restore Mode Current

7

(store) VDD = 2.5 V, VSS = −2.5 V −40 mA

SS

IDD (restore)

= VDD or VIL = GND 3.5 10 μA

IH

= VDD or VIL = GND,

V

IH

= 2.5 V, VSS = −2.5 V

V

DD

= VDD or VIL = GND,

V

IH

= 0, ISS ≈ 0

V

SS

= VDD or VIL = GND,

V

IH

0.55 10 μA

40 mA

0.3 3 9 mA

VSS = GND, ISS ≈ 0
I
Power Dissipation
Power Supply Sensitivity

DYNAMIC CHARACTERISTICS

8

5

P

5, 9

(restore) VDD = 2.5 V, VSS = −2.5 V −0.3 −3 −9 mA

SS

P

V

DISS

∆VDD = 5 V ± 10% 0.002 0.01 %/%

SS

= VDD or VIL = GND 0.018 0.05 mW

IH

Bandwidth BW −3 dB, RAB = 10 kΩ/50 kΩ/100 kΩ 630/135/66 kHz
Total Harmonic Distortion THDW

VW Settling Time tS

= 1 V rms, VB = 0 V, f = 1 kHz,

V

A

= 10 kΩ

R

AB

= 1 V rms, VB = 0 V, f = 1 kHz,

V

A

R

= 50 kΩ, 100 kΩ

AB

= VDD, VB = 0 V,

V

A

= 0.50% error band,

V

W

0.04 %

0.015 %

0.6/2.2/3.8 μs

Code 0x000 to Code 0x200

for R

= 10 kΩ/50 kΩ/100 kΩ

AB

Resistor Noise Voltage e
Crosstalk (CW1/CW2) CT

R

N_WB

= 5 kΩ, f = 1 kHz 9

WB

= VDD, VB = 0 V, measure VW

V

A

−1

nV/√Hz

nV/sec
with adjacent RDAC making
the full-scale code change

Analog Crosstalk (CW1/CW2) CTA

= VA1 = +2.5 V,

V

DD

= VB1 = −2.5 V,

V

SS

measure V

with VW2 = 5 V p-p

W1

−86/−73/−68 dB

@ f = 10 kHz, Code 1 = 0x20,
Code 2 = 0x3F, RAB = 10 kΩ/
50 kΩ/100 kΩ

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. I
RAB = 50 kΩ, and IW > 25 μA for the RAB = 100 kΩ version (see Figure 25).

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output ADC. VA = VDD and VB = VSS. DNL specification limits of

−1 LSB minimum are guaranteed monotonic operating conditions (see Figure 26).

4

Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-

referenced bipolar signal adjustment.

5

Guaranteed by design and not subject to production test.

6

Common-mode leakage current is a measure of the dc leakage from Terminal B and Terminal W to a common-mode bias level of VDD/2.

7

EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 22). To

minimize power dissipation, a NOP instruction should be issued immediately after Instruction 1 (0x1).

8

Power dissipation is calculated by P

9

All dynamic characteristics use VDD = 2.5 V and VSS = −2.5 V.

= (IDD × VDD) + (ISS × VSS).

DISS

> 50 μA @ VDD = 2.7 V for the RAB = 10 kΩ version, IW > 50 μA for the

W

Rev. B | Page 4 of 32

AD5233

TIMING CHARACTERISTICS

VDD = 3 V to 5.5 V, VSS = 0 V, and −40°C < TA < +85°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

INTERFACE TIMING CHARACTERISTICS

Clock Cycle Time (t

) t1 20 ns

CYC

CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulse Width t4, t5 Clock level high or low 10 ns

Data Setup Time t6 From positive CLK transition 5 ns
Data Hold Time t7 From positive CLK transition 5 ns
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay4 t
CLK to SDO Data Hold Time t11 R
CS High Pulse Width5

CS High to CS High5
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Read/Store to Nonvolatile EEMEM6 t

CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous) t
Preset Response Time to Wiper Setting t
Power-On EEMEM Restore Time t

FLASH/EE MEMORY RELIABILITY

Endurance7 100
Data Retention8 100

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Guaranteed by design and not subject to production test.

3

See the timing diagrams (Figure 2 and Figure 3) for the location of the measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V)

and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 5 V.

4

Propagation delay depends on the value of VDD, R

5

Valid for commands that do not activate the RDY pin.

6

The RDY pin is low only for Command 2, Command 3, Command 8, Command 9, Command 10, and the PR hardware pulse: CMD_8 > 1 ms; CMD_9, CMD_10 > 0.12 ms;

CMD_2, CMD_3 > 20 ms. Device operation at T

7

Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, and +85°C; typical endurance at 25°C is 700,000 cycles.

8

Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV

derates with junction temperature, as shown in Figure 45 in the Flash/EEMEM Reliability section.

2, 3

t

10 ns

2

t

1 t

3

t

40 ns

8

t

50 ns

9

R

10

t

12

t

4 t

13

t

0 ns

14

t

0.1 0.15 ms

15

16

= 2.2 kΩ, CL < 20 pF 50 ns

PULL-UP

= 2.2 kΩ, CL < 20 pF 0 ns

P

Applies to Instruction 0x2, Instruction 0x3,

10 ns

25 ms

and Instruction 0x9

t

10 ns

17

Not shown in timing diagram 50 ns

PRW

PRESP

RAB = 10 kΩ 140 μs

EEMEM1

pulsed low to refresh wiper positions

PR

70 μs

, and CL.

PULL-UP

= −40°C and VDD < 3 V extends the save time to 35 ms.

A

CYC

CYC

kCycles
Yea r s

Rev. B | Page 5 of 32

AD5233

CPHA = 1

CS

t

12

t

t

5

B15

(MSB)

1

B15

B15

(MSB)

t

4

t

7

t

6

(LSB)

t

10

t

11

t

CLK

CPOL = 1

HIGH OR

LOW

SDI

t

SDO

t

14

RDY

*EXTRA BIT T HAT IS NOT DEFINED, BUT NORMALLY L SB OF CHARACTER PREVIOUSL Y TRANSMIT TED.
THE CPOL = 1 MICROCONTRO LLER COM MAND ALIGNS T HE INCOMING DATA TO T HE POSIT IVE EDGE O F THE CLO CK.

2

8

B16*

t

3

B0

B0

B0

(LSB)

t

t

13

t

17

HIGH OR LOW

t

9

15

t

16

02794-002

Figure 2. CPHA = 1 Timing Diagram

CS

CLK

CPOL = 0

t

1

t

2

B15 B0

t

5

t

4

CPHA = 0

t

12

t

3

t

13

t

17

SDI

SDO

RDY

t

HIGH
OR LOW

t

14

* NOT DEFINED, BUT NORMALL Y MSB OF CHARACTER PREVIOUSLY RECE IVED.

THE CPOL = 0 MICROCONT ROLLER CO MMAND ALIGNS THE INCOMI NG DATA TO THE POSI TIVE EDG E OF THE CLOCK.

t

8

B15

(MSB)

B15

(MSB OUT)

t

10

6

B0

(LSB)

t

11

B0

(LSB)

t

7

Figure 3. CPHA = 0 Timing Diagram

Rev. B | Page 6 of 32

HIGH
OR LOW

t

9

*

t

15

t

16

02794-003

AD5233

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7 V
VSS to GND +0.3 V to −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS − 0.3 V to VDD + 0.3 V
IA, IB, IW

Pulsed1 ±20 mA

Continuous ±2 mA
Digital Inputs and Output Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range2 −40°C to +85°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 20 sec to 40 sec
Thermal Resistance Junction-to-Ambient, θ
Package Power Dissipation (TJ max − TA)/θJA

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Includes programming of nonvolatile memory.

3

Thermal Resistance (JEDEC 4-layer (2S2P) board).

3

50°C/W

JA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 7 of 32

AD5233

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK

SDI

SDO

GND

V

W1

W2

O1

SS

A1

B1

A2

B2

1

2

3

4

AD5233

5

TOP VIEW

(Not to Scale)

6

7

8

9

10

11

12

24

O2

23

RDY

22

CS

21

PR

20

WP

19

V

DD

18

A4

17

W4

B4

16

15

A3

W3

14

B3

13

02794-005

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 O1 Nonvolatile Digital Output 1. Address (O1) = 0x4, the data bit position is D0; defaults to Logic 1 initially.
2 CLK Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges.
3 SDI Serial Data Input Pin. Shifts in one bit at a time on positive CLK edges. MSB loaded first.
4 SDO Serial Data Output Pin. Serves readback and daisy-chain functions.

Command 9 and Command 10 activate the SDO output for the readback function, delayed by 16 or 17 clock
pulses, depending on the clock polarity before and after the data-word (see Figure 2, Figure 3, and Table 7).

In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 16 or 17 clock pulses,
depending on the clock polarity (see Figure 2 and Figure 3). This previously shifted-out SDI can be used for daisy­chaining multiple devices.

Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed.
5 GND Ground Pin, Logic Ground Reference.
6 VSS

Negative Supply. Connect to 0 V for single-supply applications. If V

is used in dual supply, it must be able to sink

SS

40 mA for 25 ms when storing data to EEMEM.
7 A1 Terminal A of RDAC1.
8 W1 Wiper Terminal of RDAC1, Address (RDAC1) = 0x0.
9 B1 Terminal B of RDAC1.
10 A2 Terminal A of RDAC2.
11 W2 Wiper Terminal of RDAC2, Address (RDAC2) = 0x1.
12 B2 Terminal B of RDAC2.
13 B3 Terminal B of RDAC3.
14 W3 Wiper Terminal of RDAC3, Address (RDAC3) = 0x2.
15 A3 Terminal A of RDAC3.
16 B4 Terminal B of RDAC4.
17 W4 Wiper Terminal of RDAC4, Address (RDAC4) = 0x3.
18 A4 Terminal A of RDAC4.
19 VDD Positive Power Supply Pin.
20

Optional Write Protect Pin. When active low, WP prevents any changes to the present contents, except PR strobe

WP

and Instruction 1 and Instruction 8, and refreshes the RDAC register from EEMEM. Execute a NOP instruction

high. Tie WP to VDD if not used.

21

before returning to WP

Optional Hardware Override Preset Pin. Refreshes the scratchpad register with current contents of the EEMEM

PR

register. Factory default loads midscale 0x20 until EEMEM is loaded with a new value by the user. PR is activated at

.

22

Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to Logic 1.

CS

23 RDY

the Logic 1 transition. Tie PR

to VDD if not used.

Ready. Active-high open-drain output. Identifies completion of Software Instruction 2, Software Instruction 3,

Software Instruction 8, Software Instruction 9, Software Instruction 10, and Hardware Instruction PR
24 O2 Nonvolatile Digital Output 2. Address (O2) = 0x4, the data bit position is D1; defaults to Logic 1 initially.

Rev. B | Page 8 of 32

AD5233

TYPICAL PERFORMANCE CHARACTERISTICS

0.20

0.15

0.10

0.05

0

–0.05

INL ERROR (LSB)

–0.10

–0.15

–0.20

01632

CODE (Decimal)

TA =+25°C
T

A

T

A

48

=–40°C
=+85°C

64

02794-006

0.20

0.15

0.10

0.05

0

R-DNL (LSB)

–0.05

–0.10

–0.15

–0.20

01632

CODE (Decimal)

TA =+25°C
T

=–40°C

A

T

=+85°C

A

VDD = 5V, VSS = 0V

48

64

Figure 5. INL Error vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ Figure 8. R-DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

DNL ERROR (LSB)

0.20

0.15

0.10

0.05

–0.05

–0.10

–0.15

–0.20

TA =+25°C
T

=–40°C

A

T

=+85°C

A

0

0

16 32 64

CODE (Decimal)

48

02794-007

3000

2500

2000

1500

1000

500

RHEOSTAT MO DE TEMPCO (ppm/° C)

0

0

16 32 64

CODE (Decimal)

VDD = 5V, VSS = 0V
T

= –40°C TO + 85°C

A

48

Figure 9. (∆RWB/RWB)/∆T × 106 Figure 6. DNL Error vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

0.20

0.15

0.10

0.05

TA =+25°C
T

=–40°C

A

T

=+85°C

A

VDD = 5V, VSS = 0V

300

200

VDD = 5.5V, VSS = 0V
T

= –40°C TO +85°C

A

V

= 2V

A

V

= 0V

B

2794-009

2794-010

0

–0.05

R-INL ( LSB)

–0.10

–0.15

–0.20

01632

CODE (Decimal)

Figure 7. R-INL vs. Code, T

= −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

A

100

POTENTI OMETER MO DE TEMPCO (ppm/°C)

48

64

02794-008

0

01632

CODE (Decimal )

Figure 10. (∆VW/VW)/∆T × 106 vs. Code, R

48

= 10 kΩ

AB

64

02794-011

Rev. B | Page 9 of 32

AD5233

80

60

(Ω)

40

W

R

20

0

0

4

3

2

(µA)

DD

I

1

ISS @ VDD/VSS = 5V/0V

0

IDD @ VDD/VSS = 2.7V/0V

–1

–40 –20

0.30

0.25

0.20

0.15

(mA)

DD

I

0.10

0.05

VDD = 2.7V, VSS = 0V
T

= 25°C

A

16 32 64

CODE (Decimal)

48

Figure 11. Wiper On Resistance vs. Code

IDD @ VDD/VSS = 5V/0V

ISS @ VDD/VSS = 2.7V/0V

0 20 40 60 100

TEMPERATURE (° C)

Figure 12. IDD vs. Temperature, RAB = 10 kΩ

VDD = 5V
V

= 5V

SS

MIDSCALE

FULL SCALE

ZERO SCALE

3

VDD @ VSS = ±2.5V
V

= 1V rms

A

D = MIDSCALE

0

f

= 66kHz

–3

–6

GAIN (dB)

–9

–12

1k 1M

02794-012

–3dB

f

= 600kHz, RAB = 10kΩ

–3dB

f

= 132kHz, RAB = 50kΩ

–3dB

10k 100k

FREQUENCY (Hz)

02794-015

Figure 14. −3 dB Bandwidth vs. Resistance (Using the Circuit

Shown in Figure 31)

0.05

0.04

0.03

0.02

THD + NOISE ( %)

0.01

0

80

02794-013

10

RAB = 50kΩ

100 1k 10k

RAB = 10kΩ

RAB = 100kΩ

FREQUENCY (Hz)

V

DD/VSS

V

= 1V rms

A

= ±2.5V

100k

02794-016

Figure 15. Total Harmonic Distortion + Noise vs. Frequency

0

–6

–12

–18

–24

GAIN (dB)

–30

–36

CODE 0x20

0x10

0x08

0x04

0x02

0x01

0

024681012

CLOCK F REQUENCY (MHz)

Figure 13. IDD vs. Clock Frequency, RAB = 10 kΩ

Rev. B | Page 10 of 32

–42

100 10M

02794-014

1k 10k 100k

FREQUENCY (Hz)

1M

2794-017

Figure 16. Gain vs. Frequency vs. Code, RAB = 10 Ω ( Figure 31)

AD5233

0

CODE 0x20

–6

0x10

–12

0x08

–18

0x04

–24

GAIN (dB)

0x02

–30

0x01

–36

–42

100 1M

1k 10k 100k

FREQUENCY (Hz)

Figure 17. Gain vs. Frequency vs. Code, RAB = 50 kΩ (Figure 31)

2794-018

V

= 5V

DD

= 2.25V

V

A

= 0V

V

B

100µs/DIV

Figure 20. Power-On Reset, V

MIDSCALE

A

Code = 101010

EXPECTED

VALUE

= 2.25 V, VB = 0 V,

V

A

V

W

0.5V/
DIV

2794-021

0

CODE 0x20

–6

0x10

–12

0x08

–18

0x04

–24

GAIN (dB)

0x02

–30

0x01

–36

–42

100 1M

1k 10k 100k

FREQUENCY (Hz)

Figure 18. Gain vs. Frequency vs. Code, RAB = 100 kΩ ( Figure 31)

80

70

60

50

40

PSRR (dB)

30

R

AB

= 50kΩ

RAB= 10kΩ

R

AB

= 100kΩ

2.60

2.58

2.56

2.54

2.52

(V)

2.50

OUT

V

2.48

2.46

2.44

2.42

2.40
0 50 100 250 350 450200150 300 400 511

02794-019

TIME (µs)

VDD = VA= 5V
V

= VB= 0V

SS

CODE = 0x20 TO 0x1F

02794-022

Figure 21. Midscale Glitch Energy, Code 0x20 to Code 0x1F

5V/DIV

CS

5V/DIV

CLK

20

V

= 5V ±100mV AC

DD

10

V

= 0V, VA= 5V, VB= 0V

SS

MEASURED AT V

0

100 10M1M

1k 10k 100k

WITH CO DE = 0x200

W

FREQUENCY (Hz)

Figure 19. PSRR vs. Frequency

02794-020

Rev. B | Page 11 of 32

5V/DIV

4ms/DIV

Figure 22. IDD vs. Time When Storing Data to EEMEM

SDI

I

DD

20mA/
DIV

02794-023

AD5233

V

100

5V/DI

5V/DIV

5V/DIV

4ms/DIV

*SUPPLY CURRENT RET URNS TO MINIMUM POWE R
CONSUMPTION, IF INSTRUCTION 0 (NOP) IS EXECUTED
IMMEDIATE LY AFTE R INSTRUCTION 1 (READ EEMEM ).

CS

CLK

SDI

*

I

DD

2mA/DIV

10

(mA)

WB_MAX

1

0.1

THEORETI CAL, I

0.01

02794-024

= 100kΩ

R

AB

0 8 16 24 32 40 48 56 64

Figure 23. IDD vs. Time When Reading Data from EEMEM Figure 24. I

R

= 10kΩ

AB

CODE (Decimal)

vs. Code

WB_MAX

VA = VB = OPEN
T

A

= 50kΩ

R

AB

= 25°C

02794-025

Rev. B | Page 12 of 32

AD5233

V

V

V

A

V

V

V

TEST CIRCUITS

Figure 25 to Figure 35 define the test conditions used in the specifications.

NC

DUT
A

W

B

NC = NO CONNECT

I

W

V

MS

02794-026

Figure 25. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

OFFSET

GND

DUT B

V

IN

W

OP279

OFFSET BIAS

Figure 29. Inverting Gain

5V

V

OUT

02794-030

5

DUT

A

V+

W

B

+ = V

DD

1LSB = V+/2

V

MS

N

2794-027

Figure 26. Potentiometer Divider Nonlinearity Error (INL, DNL)

MS2

DUT

A

B

V

W

W

I

W

RW = [V

V

MS1

MS1

– V

MS2

]/I

W

2794-028

Figure 27. Wiper Resistance

A

V

A

DD

V+

W

B

V

MS

V+ = VDD±10%

PSRR (dB) = 20 l og

ΔV

PSS (%/%) =

ΔV

MS

DD

ΔV

MS

()

ΔV

DD

%

%

Figure 28. Power Supply Sensitivity (PSS, PSRR)

OFFSET

GND

V

IN

W

ABDUT

OFFSET BIAS

OP279

V

OUT

2794-031

Figure 30. Noninverting Gain

+15

OP42

–15V

V

OUT

02794-032

OFFSET

GND

A

V

IN

DUT

W

B

2.5V

Figure 31. Gain vs. Frequency

0.1

RSW=

DUT

W

B

I

SW

A = NC

02794-029

I

SW

CODE = 0x00

V

BIAS

+

0.1V

–

02794-033

Figure 32. Incremental On Resistance

Rev. B | Page 13 of 32

AD5233

V

NC

V

DD

DUT

V

SS

A

GND

B

NC

NC = NO CONNECT

I

CM

W

V

CM

Figure 33. Common-Mode Leakage Current

DD

A1

RDAC1

NC

W1

V

IN

NC = NO CONNECT

B1

V

SS

A2

RDAC2

W2

B2

CTA= 20 log

02794-034

V

OUT

V

OUT

()

V

IN

02794-035

TO OUTPUT

PIN

Figure 35. Load Circuit for Measuring VOH and VOL; the Diode Bridge Test

Circuit Is Equivalent to the Application Circuit with R

50pF

C

200µA I

L

200µA I

OL

VOH (MIN)
OR
V

(MAX)

OL

OH

PULL-UP

2794-036

of 2.2 kΩ

Figure 34. Analog Crosstalk

Rev. B | Page 14 of 32

AD5233

THEORY OF OPERATION

The AD5233 digital potentiometer is designed to operate as a
true variable resistor replacement device for analog signals that
remain within the terminal voltage range of V
The basic voltage range is limited to V

DD

SS

< V

TERM

< VDD.

− VSS < 5.5 V. The
digital potentiometer wiper position is determined by the
RDAC register contents.

The RDAC register acts as a scratchpad register, allowing as
many value changes as necessary to place the potentiometer
wiper in the correct position. The scratchpad register can be
programmed with any position value using the standard SPI
serial interface mode by loading the complete representative
data-word. Once a desirable position is found, this value can be
stored in an EEMEM register. Thereafter, the wiper position is
always restored to that position for subsequent power-up.

The EEMEM data storing process takes approximately 25 ms;
during this time, the shift register is locked, preventing any
changes from taking place. The RDY pin pulses low to indicate
the completion of this EEMEM storage.

The following instructions facilitate the user’s programming
needs (see Table 7 for details):

0 = Do nothing.

1 = Restore EEMEM contents to RDAC.

2 = Store RDAC setting to EEMEM.

3 = Store RDAC setting or user data to EEMEM.

4 = Decrement 6 dB.

5 = Decrement all 6 dB.

6 = Decrement one step.

7 = Decrement all one step.

8 = Reset EEMEM contents to RDACs.

9 = Read EEMEM contents from SDO.

10 = Read RDAC wiper setting from SDO.

11 = Write data to RDAC.

12 = Increment 6 dB.

13 = Increment all 6 dB.

14 = Increment one step.

15 = Increment all one step.

SCRATCHPAD AND EEMEM PROGRAMMING

The scratchpad RDAC register directly controls the position of
the digital potentiometer wiper. For example, when the scratchpad
register is loaded with all 0, the wiper is connected to Terminal
B of the variable resistor. The scratchpad register is a standard
logic register with no restriction on the number of changes
allowed, but the EEMEM registers have a program erase/write
cycle limitation (see the Flash/EEMEM Reliability section).

BASIC OPERATION

The basic mode of setting the variable resistor wiper position
(programming the scratchpad register) is accomplished by
loading the serial data input register with Instruction 11,
Address A1, Address A0, and the desired wiper position
data. When the proper wiper position is determined, the
user can load the serial data input register with Instruction 2,
which stores the wiper position data in the EEMEM register.
After 25 ms, the wiper position is permanently stored in the
nonvolatile memory location. Tab l e 5 provides a programming
example listing the sequence of serial data input (SDI) words
with the serial data output appearing at the SDO pin in
hexadecimal format.

Table 5. Set and Store RDAC Data to EEMEM Register

SDI SDO Action

0xB010 0xXXXX

0x20XX 0xB010

At system power-on, the scratchpad register is automatically
refreshed with the value previously stored in the EEMEM
register. The factory-preset EEMEM value is midscale, but it
can be changed by the user thereafter.

During operation, the scratchpad (RDAC) register can be
refreshed with the EEMEM register data with Instruction 1 or
Instruction 8. The RDAC register can also be refreshed with the
EEMEM register data under hardware control by pulsing the

pin. The

PR

pulse first sets the wiper at midscale when brought
to Logic 0, and then, on the positive transition to Logic 1, it
reloads the RDAC wiper register with the contents of EEMEM.

Many additional advanced programming commands are
available to simplify the variable resistor adjustment process
(see Tabl e 7). For example, the wiper position can be changed
one step at a time using the increment/decrement instruction or
by 6 dB with the shift left/right instruction. Once an increment,
decrement, or shift instruction has been loaded into the shift
register, subsequent

A serial data output SDO pin is available for daisy-chaining and
for readout of the internal register contents.

Writes Data 0x10 to the RDAC1 register,
Wiper W1 moves to ¼ full-scale position.

Stores RDAC1 register content into the
EEMEM1 register.

CS

strobes can repeat this command.

PR

Rev. B | Page 15 of 32

AD5233

V

V

EEMEM PROTECTION

The write protect (WP) pin disables any changes to the
scratchpad register contents, except for the EEMEM setting,
which can still be restored using Instruction 1, Instruction 8,
and the
hardware EEMEM protection feature. To disable

PR

pulse. Therefore, WP can be used to provide a

WP

, it is
recommended to execute a NOP instruction before returning
WP

to Logic 1.

DIGITAL INPUT/OUTPUT CONFIGURATION

All digital inputs are ESD-protected, high input impedance
that can be driven directly from most digital sources. Active at
Logic 0,
No internal pull-up resistors are present on any digital input
pins. Because the device can be detached from the driving
source once it is programmed, adding pull-up resistance on
the digital input pins is a good way to avoid falsely triggering
the floating pins in a noisy environment.

The SDO and RDY pins are open-drain digital outputs that
need pull-up resistors only if these functions are used. Use a
resistor in the range of 1 kΩ to 10 kΩ to balance the power
and switching speed trade-off.

PR

and WP must be tied to VDD if they are not used.

PR WP

CLK

CS

SDI

VALID

COMMAND

COUNTER

Figure 36. Equivalent Digital Input-Output Logic

COMMAND

PROCESSOR

AND ADDRESS

DECODE

SERIAL

REGISTER

AD5233

5V

R

PULL-UP

(FOR DAISY
CHAIN ONLY)

SDO

GND

The equivalent serial data input and output logic is shown in
Figure 36. The open-drain output SDO is disabled whenever
chip select (

CS

) is in Logic 1. The SPI interface can be used
in two slave modes: CPHA = 1, CPOL = 1 and CPHA = 0,
CPOL = 0. CPHA and CPOL refer to the control bits that
dictate SPI timing in the following MicroConverters® and
microprocessors: , , M68HC11, and

ADuC812 ADuC824

MC68HC16R1/MC68HC916R1. ESD protection of the
digital inputs is shown in and .

Figure 37 Figure 38

DD

02794-037

SERIAL DATA INTERFACE

The AD5233 contains a 4-wire SPI-compatible digital interface

CS

(SDI, SDO,
loaded MSB first. The format of the SPI-compatible word is
shown in . The chip-select Tabl e 6
the complete data-word is loaded into the SDI pin. When
returns high, the serial data-word is decoded according to the
instructions in . The command bits (Cx) control the
operation of the digital potentiometer. The address bits (Ax)
determine which register is activated. The data bits (Dx) are
the values that are loaded into the decoded register. To program
RDAC1 to RDAC4, only the 6 LSB data bits are used.

The AD5233 has an internal counter that counts a multiple
of 16 bits (a frame) for proper operation. For example, the
AD5233 works with a 32-bit word, but it cannot work properly
with a 15-bit or 17-bit word. In addition, the AD5233 has a
subtle feature that, if
part repeats the previous command (except during power-up).
As a result, care must be taken to ensure that no excessive noise
exists in the CLK or
of-bits pattern. Also, to prevent data from locking incorrectly
(due to noise, for example), the counter resets, if the count is
not a multiple of four when

, and CLK). It uses a 16-bit serial data-word

CS

pin must be held low until

Tabl e 7

CS

is pulsed without CLK and SDI, the

CS

line that might alter the effective number-

CS

goes high.

CS

INPUT

INPUT

300Ω

300Ω

WP

Input Protection

DD

GND

GND

02794-039

LOGIC

PINS

Figure 37. Equivalent ESD Digital Input Protection

WP

Figure 38. Equivalent

02794-038

Rev. B | Page 16 of 32

AD5233

V

V

DAISY-CHAIN OPERATION

The serial data output (SDO) pin serves two purposes. It can
be used to read the contents of the wiper setting and EEMEM
values using Instruction 10 and Instruction 9, respectively.
The remaining instructions (0 to 8, 11 to 15) are valid for
daisy-chaining multiple devices in simultaneous operations.
Daisy-chaining minimizes the number of port pins required
from the controlling IC (Figure 39). The SDO pin contains an
open-drain N-channel FET that requires a pull-up resistor, if
this function is used. As shown in Figure 39, users need to tie
the SDO pin of one package to the SDI pin of the next package.

Users might need to increase the clock period, because the
pull-up resistor and the capacitive loading at the SDO to SDI
interface might require an additional time delay between
subsequent packages. When two AD5233s are daisy-chained,
32 bits of data is required. The first 16 bits go to U2 and the
second 16 bits go to U1.

are clocked into their respective serial registers.
pulled high to complete the operation.

MICRO-

CONTROLL ER

CS

should be kept low until all 32 bits

+

AD5233 AD5233

SDI SDO

U1 U2

CS

CLK

R
2kΩ

P

SDI SDO

CS

CS

is then

CLK

The ground pin of the AD5233 device is used primarily as a
digital ground reference, which needs to be tied to the PCB’s
common ground. The digital input control signals to the
AD5233 must be referenced to the device ground pin (GND)
and satisfy the logic level defined in the Specifications section.
An internal level-shift circuit ensures that the common-mode
voltage range of the three terminals extends from V

to VDD,

SS

regardless of the digital input level.

POWER-UP SEQUENCE

Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 40), it is
important to power on V
to Te rm i na l A, Term ina l B, a nd Te rm i na l W. Ot her wi se, the
diode is forward-biased such that V
tentionally. For example, applying 5 V across the A and B
terminals prior to V

causes the VDD terminal to exhibit 4.3 V.

DD

It is not destructive to the device, but it might affect the rest of
the system. The ideal power-up sequence is GND, V
digital inputs, and V
V

, and digital inputs is not important as long as they are

W

powered after V

DD/VSS

A/VB/VW

.

Regardless of the power-up sequence and the ramp rates of the
power supplies, once V

DD/VSS

remains effective, which restores the EEMEM values to the
RDAC registers.

first before applying any voltage

DD/VSS

are powered unin-

DD/VSS

DD

. The order of powering VA, VB,

are powered, the power-on preset

, VSS,

2794-040

Figure 39. Daisy-Chain Configuration Using SDO

TERMINAL VOLTAGE OPERATION RANGE

The AD5233’s positive VDD and negative VSS power supplies
define the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on Terminal A,
Ter mi na l B, an d Ter mi na l W th at e xc ee d V
by the internal forward-biased diodes (see Figure 40).

Figure 40. Maximum Terminal Voltages Set by V

or VSS are clamped

DD

DD

A

W

B

V

SS

02794-041

and V

DD

SS

LATCHED DIGITAL OUTPUTS

A pair of digital outputs, O1 and O2, is available on the AD5233.
These outputs provide a nonvolatile Logic 0 or Logic 1 setting.
O1 and O2 are standard CMOS logic outputs, shown in Figure 41.
These outputs are ideal to replace the functions often provided
by DIP switches. In addition, they can be used to drive other
standard CMOS logic-controlled parts that need an occasional
setting change. Pin O1 and Pin O2 default to Logic 1, and they
can drive up to 50 mA of load at 5 V/25°C.

V

DD

OUTPUTS

O1 AND O2
PINS

GND

Figure 41. Logic Output O1 and Logic Output O2

02794-042

Rev. B | Page 17 of 32

AD5233

In Table 6, C0 to C3 are command bits, A3 to A0 are address bits, D0 to D5 are data bits that are applicable to the RDAC wiper register,
and D0 to D7 are applicable to the EEMEM register.

Table 6. 16-Bit Serial Data-Word

MSB Instruction Byte LSB Data Byte

RDAC C3 C2 C1 C0 0 0 A1 A0 X X D5 D4 D3 D2 D1 D0
EEMEM C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Command instruction codes are defined in Table 7.

1, 2, 3

Table 7. Instruction/Operation Truth Table

Instruction Byte 0 Data Byte 0

Inst.
No.

0 0 0 0 0 X X X X X X X X X X X X NOP: Do nothing. See Table 14 for

1 0 0 0 1 0 0 A1 A0 X X X X X X X X Restore EEMEM contents to the RDAC

2 0 0 1 0 0 0 A1 A0 X X X X X X X X Store wiper setting: Store RDAC (ADDR)

34 0 0 1 1 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Store contents of Serial Register Data

45 0 1 0 0 0 0 A1 A0 X X X X X X X X Decrement 6 dB: right-shift contents of

55

65

75

8 1 0 0 0 X X X X X X X X X X X X Reset: refresh all RDACs with their

9 1 0 0 1 A3 A2 A1 A0 X X X X X X X X Read content of EEMEM (ADDR) from

10 1 0 1 0 0 0 A1 A0 X X X X X X X X Read RDAC wiper setting from SDO

11 1 0 1 1 0 0 A1 A0 X X D5 D4 D3 D2 D1 D0 Write contents of Serial Register Data

125

135

145

155

1

2

3

4

5

B16 B8 B7 B6 B5 B4 B3 B2 B1 B0

C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 1 X X X X X X X X X X X X Decrement all 6 dB: right-shift contents

0 1 1 0 0 0 A1 A0 X X X X X X X X Decrement content of RDAC register

0 1 1 1 X X X X X X X X X X X X Decrement contents of all the RDAC

1 1 0 0 0 0 A1 A0 X X X X X X X X Increment 6 dB: Left-shift contents of

1 1 0 1 X X X X X X X X X X X X Increment all 6 dB: left-shift contents of

1 1 1 0 0 0 A1 A0 X X X X X X X X Increment contents of the RDAC

1 1 1 1 X X X X X X X X X X X X Increment contents of all RDAC

The SDO output shifts out the last 16 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or

Instruction 10, see details of these instructions for proper usage.
The RDAC register is a volatile scratchpad register that is automatically refreshed at power-on from the corresponding nonvolatile EEMEM register.
Execution of these operations takes place when the CS strobe returns to Logic 1.

Instruction 3 writes one data byte (eight bits of data) to EEMEM. In the case of Address 0, Address 1, Address 2, and Address 3, only the last six bits are valid for wiper

position setting.
The increment, decrement, and shift instructions ignore the contents of the Shift Register Data Byte 0.

Operation

programming example.

register. This command leaves the device
in read program power state. To return
the part to the idle state, perform NOP
instruction 0. See Table 14.

setting to EEMEM. See Table 13.

Byte 0 (total eight bits) to EEMEM
(ADDR). See Table 16.

RDAC register, stop at all 0s.

of all RDAC registers, stop at all 0s.

by 1, stop at all 0s.

registers by 1, stop at all 0s.

corresponding EEMEM previously
stored values.

SDO output in the next frame. See
Table 17.

output in the next frame. See Table 18.

Byte 0 (total six bits) to RDAC. See
Table 12.

RDAC register, stop at all 1s. See
Table 15.

RDAC registers, stop at all 1s.

register by 1, stop at all 1s. See
Table 13.

registers by 1, stop at all 1s.

Rev. B | Page 18 of 32

AD5233

ADVANCED CONTROL MODES

The AD5233 digital potentiometer includes a set of user
programming features to address the wide number of
applications for these universal adjustment devices.

Key programming features include

• Scratchpad programming to any desirable values

• Nonvolatile memory storage of the scratchpad RDAC

register value in the EEMEM register

• Increment and decrement instructions for the RDAC

wiper register

• Left- and right-bit shift of the RDAC wiper register to

achieve ±6 dB level changes

• Eleven extra bytes of user-addressable nonvolatile memory

Linear Increment and Decrement Instructions

The increment and decrement instructions (14, 15, 6, and 7)
are useful for linear step-adjustment applications. These com­mands simplify microcontroller software coding by allowing the
controller to send just an increment or decrement command to
the device.

For an increment command, executing Instruction 14 with
the proper address automatically moves the wiper to the next
resistance segment position. Instruction 15 performs the same
function, except that the address does not need to be specified.
All RDACs are changed at the same time.

Logarithmic Taper Mode Adjustment

Four programming instructions produce logarithmic taper
increment and decrement of the wiper. These settings are
activated by the 6 dB increment and 6 dB decrement instruc­tions (12, 13, 4, and 5). For example, starting at zero scale,
executing the increment Instruction 12 seven times moves
the wiper in 6 dB per step from 0% to full scale, R
increment instruction doubles the value of the RDAC register
contents each time the command is executed. When the wiper
position is near the maximum setting, the last 6 dB increment
instruction causes the wiper to go to the full-scale 63
position. Further 6 dB per increment instructions do not
change the wiper position beyond its full scale.

The 6 dB step increments and 6 dB step decrements are achieved
by shifting the bit internally to the left or right, respectively.
The following information explains the nonideal ±6 dB step
adjustment under certain conditions. Tab l e 8 illustrates the
operation of the shifting function on the RDAC register data
bits. Each table row represents a successive shift operation.
Note that the left-shift 12 and 13 instructions were modified
such that, if the data in the RDAC register is equal to zero and
the data is shifted left, the RDAC register is then set to Code 1.
Similarly, if the data in the RDAC register is greater than or
equal to midscale and the data is shifted left, then the

. The 6 dB

AB

code

10

data in the RDAC register is automatically set to full scale. This
makes the left-shift function as ideal a logarithmic adjustment
as possible.

The right-shift 4 and 5 instructions are ideal only if the LSB is
0 (ideal logarithmic = no error). If the LSB is a 1, the right-shift
function generates a linear half-LSB error, which translates to
a number-of-bits-dependent logarithmic error, as shown in
Figure 42. The plot shows the error of the odd numbers of bits
for the AD5233.

Table 8. Detail Left-Shift and Right-Shift Functions for
6 dB Step Increment and Decrement

Left-Shift
(+6 dB/Step)

Right-Shift
(–6 dB/Step)

00 0000 11 1111
00 0001 01 1111
00 0010 00 1111
00 0100 00 0111
00 1000 00 0011
01 0000 00 0001
10 0000 00 0000
11 1111 00 0000
11 1111 00 0000

Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
right-shift 4 and 5 command execution contains an error only
for odd numbers of bits. Even numbers of bits are ideal. The
graph in Figure 42 shows plots of log error [20 × log

(error/

10

code)] for the AD5233. For example, Code 3 log error = 20 ×
log

(0.5/3) = −15.56 dB, which is the worst-case scenario. The

10

plot of log error is more significant at the lower codes.

0

–10

–20

–15.56dB @ CODE 3

–30

ERROR (dB)

–40

–50

0

5 101520253035404550556065

CODE (Decimal)

Figure 42. Plot of Log Error Conformance for Odd Numbers of Bits Only (Even

Numbers of Bits are Ideal)

02794-043

Rev. B | Page 19 of 32

AD5233

C

O

C

R

Using Additional Internal Nonvolatile EEMEM

The AD5233 contains additional user EEMEM registers for
storing any 8-bit data. Tab l e 9 provides an address map of the
internal storage registers shown in the functional block diagram
as EEMEM1, EEMEM2, and 11 bytes of user EEMEM.

Table 9. EEMEM Address Map

EEMEM Number Address EEMEM Content

1 0000 RDAC1
2 0001 RDAC2
3 0010 RDAC3
4 0011 RDAC4

1, 2

1, 2

1, 2

1, 2

5 0100 O1 and O23
6 0101 USER14
7 0110 USER2
… … …
15 1110 USER10
16 1111 USER11

1

RDAC data stored in the EEMEM location is transferred to the RDAC register

at power-on, or when Instruction 1, Instruction 8, and PR are executed.

2

Execution of Instruction 1 leaves the device in the read mode power

consumption state. After the last Instruction 1 is executed, the user

should perform a NOP, Instruction 0, to return the device to the low

power idling state.

3

O1 and O2 data stored in EEMEM locations is transferred to the corresponding

digital register at power-on, or when Instruction 1 and Instruction 8 are

executed.

4

USERx are internal nonvolatile EEMEM registers available to store and

retrieve constants and other 8-bit information using Instruction 3 and

Instruction 9, respectively.

RDAC STRUCTURE

The patent-pending RDAC contains multiple strings of equal
resistor segments, with an array of analog switches that act as
the wiper connection. The number of positions is the resolution
of the device. The AD5233 has 64 connection points, allowing it
to provide better than 1.5% set ability resolution. Figure 43
shows an equivalent structure of the connections between the
three terminals of the RDAC. The SW
while the switches, SW(0) to SW(2
depending on the resistance position decoded from the data
bits. Because the switch is not ideal, there is a 15 Ω wiper
resistance, R

. Wiper resistance is a function of supply voltage

W

and temperature. The lower the supply voltage or the higher the
temperature, the higher the resulting wiper resistance. Users
should be aware of the wiper resistance dynamics if an accurate
prediction of the output resistance is needed.

and SWB are always on,

A

N

−1), are on, one at a time,

SW

A

A

SW(2N – 1)

RDAC

WIPER

REGISTER

AND

DECODER

R

= RAB/2

S

DIGITAL

IRCUITRY

MITTED FOR

LARITY

R

S

SW(2

SW

R

S

R

SW

S

N

SW

N

– 2)

(1)

(0)

B

W

B

2794-044

Figure 43. Equivalent RDAC Structure

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance of the RDAC between Terminal A
and Terminal B, R
with 64 positions (6-bit resolution). The final digit(s) of the part
number determine the nominal resistance value, for example,
10 = 10 kΩ; 50 = 50 kΩ; 100 = 100 kΩ.

The 6-bit data-word in the RDAC latch is decoded to select
one of the 64 possible settings. The following discussion
describes the calculation of resistance (R
of a 10 kΩ part. For V
starts at Terminal B for Data 0x00. R
the wiper resistance and because it is independent of the nominal
resistance. The second connection is the first tap point, where
R

(1) becomes 156 Ω + 15 Ω = 171 Ω for Data 0x01. The third

WB

connection is the next tap point, representing R
15 Ω = 327 Ω for Data 0x02, and so on. Each LSB data value
increase moves the wiper up the resistor ladder until the last
tap point is reached at R
simplified diagram of the equivalent RDAC circuit. When R
is used, Terminal A can be left floating or tied to the wiper.

100

)

AB

75

50

(D) (% of Full-Scale R

WB

25

(D),

WA

R

, is available with 10 kΩ, 50 kΩ, and 100 kΩ

AB

) at different codes

WB

= 5 V, the wiper’s first connection

DD

(0) is 15 Ω because of

WB

(2) = 321 Ω +

WB

(63) = 9858 Ω. See Figure 43 for a

WB

R

WA

R

WB

WB

0

0616

Figure 44. R

(D) and RWB(D) vs. Decimal Code

WA

32 48

CODE (Decimal)

4

2794-045

Rev. B | Page 20 of 32

AD5233

The general equation that determines the programmed output
resistance between W and B is

WB

D

DR +×=64)(

AB

(1)

RR

W

where:

D is the decimal equivalent of the data contained in the RDAC

register.

R

is the nominal resistance between Terminal A and Terminal B.

AB

R

is the wiper resistance.

W

For example, the output resistance values in Tab l e 1 0 are set for
the given RDAC latch codes with V

= 5 V (applies to RAB =

DD

10 kΩ digital potentiometers).

Table 10. RWB(D) at Selected Codes for RAB = 10 kΩ

D (Decimal) RWB(D) (Ω) Output State

63 9858 Full scale
32 5015 Midscale
1 171 1 LSB
0 15 Zero scale (wiper contact resistor)

Note that in the zero-scale condition a finite wiper resistance of
15 Ω is present. Care should be taken to limit the current flow
between W and B in this state to no more than 20 mA to avoid
degradation or possible destruction of the internal switches.

Like the mechanical potentiometer that the RDAC replaces, the
AD5233 part is totally symmetrical. The resistance between
Wiper W and Terminal A also produces a digitally controlled
complementary resistance, R

. Figure 44 shows the symmetrical

WA

programmability of the various terminal connections. When
R

is used, Terminal B can be left floating or tied to the wiper.

WA

Setting the resistance value for R

starts at a maximum value

WA

of resistance and decreases as the data loaded in the latch is
increased in value.

The general transfer equation for this operation is

D

−

64

DR +×

=

)(

64

ABWA

(2)

RR

W

For example, the output resistance values in Tab l e 1 1 are set for
the RDAC latch codes with V

= 5 V (applies to RAB = 10 kΩ

DD

digital potentiometers).

Table 11. RWA(D) at Selected Codes for R

= 10 kΩ

AB

D (Decimal) RWA(D) (Ω) Output State

63 171 Full scale
32 5015 Midscale
1 9858 1 LSB
0 10015 Zero scale

Channel-to-channel RAB matching is better than 1%. The
change in R

with temperature has a 600 ppm/°C temperature

AB

coefficient.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer can be configured to generate an
output voltage at the wiper terminal that is proportional to
the input voltages applied to Terminal A and Terminal B. For
ex a mpl e, c onn e ct in g Ter mi nal A to 5 V a nd Te rm i na l B t o
ground produces an output voltage at the wiper that can be
any value from 0 V to 5 V. Each LSB of voltage is equal to the
voltage applied across Terminal A and Terminal B divided

N

by the 2

position resolution of the potentiometer divider.

Because AD5233 can also be supplied by dual supplies, the
general equation defining the output voltage at V

with respect

W

to ground for any given input voltages applied to the A and B
terminals is

D

DV +×=64)(

W

Equation 3 assumes that V

(3)

VV

B

AB

is buffered so that the effect of

W

wiper resistance is minimized. Operation of the digital potenti­ometer in divider mode results in more accurate operation over
temperature. Here, the output voltage is dependent on the ratio
of the internal resistors and not the absolute value; therefore,
the drift improves to 15 ppm/°C. There is no voltage polarity
restriction among the A, B, and W terminals as long as the
terminal voltage (V

) stays within VSS < V

TERM

TERM

< VDD.

PROGRAMMING EXAMPLES

The following programming examples illustrate a typical
sequence of events for various features of the AD5233. See
Tabl e 7 for the instructions and data-word format. The
instruction numbers, addresses, and data appearing at the
SDI and SDO pins are in hexadecimal format.

Table 12. Scratchpad Programming

SDI SDO Action

0xB010 0xXXXX

Table 13. Incrementing RDAC1 Followed by Storing the
Wiper Setting to EEMEM1

SDI SDO Action

0xB010 0xXXXX

0xE0XX 0xB010

0xE0XX 0xE0XX

0x20XX 0xXXXX

Writes Data 0x10 into RDAC register,
Wiper W1 moves to ¼ full-scale position.

Writes Data 0x10 into RDAC register,
Wiper W1 moves to ¼ full-scale
position.

Increments the RDAC register by one
to 0x11.

Increments the RDAC register by one
to 0x12. Continues until desired wiper
position is reached.

Stores the RDAC register data into
EEMEM1. Optionally tie WP

to GND to

protect EEMEM values.

Rev. B | Page 21 of 32

AD5233

The EEMEM1 value for RDAC1 can be restored by power-on,

PR

by strobing the

pin, or by programming, as shown in . Tabl e 14

Table 14. Restoring the EEMEM1 Value to the
RDAC1 Register

SDI

0x10XX

SDO Action

0xXXXX

Restores the EEMEM1 value to the
RDAC1 register.

0x00XX

0x10XX

NOP. Recommended step to minimize
power consumption.

Table 15. Using Left-Shift by One to Increment 6 dB Step

SDI SDO Action

0xC0XX

0xXXXX

Moves the wiper to double the present
data contained in the RDAC1 register.

Table 16. Storing Additional User Data in EEMEM

SDI SDO Action

0x35AA 0xXXXX

Stores Data 0xAA in the extra EEMEM6
location, USER1. (Allowable to address
in 11 locations with a maximum of
eight bits of data.)

0x3655

0x35AA

Stores Data 0x55 in the extra EEMEM7
location USER2. (Allowable to address
in 11 locations with a maximum of
eight bits of data.)

Table 17. Reading Back Data from Memory Locations

SDI SDO Action

0x95XX 0xXXXX

Prepares data read from USER1 EEMEM
location.

0x00XX 0x95AA

NOP Instruction 0 sends a 16-bit word
out of SDO, where the last eight bits
contain the contents of the USER1
location. The NOP command ensures
that the device returns to the idle
power dissipation state.

Table 18. Reading Back Wiper Settings

SDI SDO Action

0xB020 0xXXXX Writes RDAC1 to midscale.
0xC0XX 0xB020

Doubles RDAC1 from midscale to full scale
(left-shift instruction).

0xA0XX

0xC0XX

Prepares reading the wiper setting from the
RDAC1 register.

0xXXXX 0xA03F Reads back full-scale value from SDO.

Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. In real
terms, a single endurance cycle is composed of the following
four independent, sequential events:

•

Initial page erase sequence

•

Read/verify sequence
Byte program sequence

•

•

Second read/verify sequence

During reliability qualification, Flash/EE memory is cycled
from 0x00 to 0x3F until a first fail is recorded, signifying the
endurance limit of the on-chip Flash/EE memory.

As indicated in the Specifications section, the AD5233
Flash/EE memory endurance qualification has been carried
out in accordance with JEDEC Specification A117 over the
industrial temperature range of −40°C to +85°C. The results
allow the specification of a minimum endurance figure over
supply and temperature of 100,000 cycles, with an endurance
figure of 700,000 cycles being typical of operation at 25°C.

Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the AD5233 has
been qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature

= 55°C). As part of this qualification procedure, the

(T

J

Flash/EE memory is cycled to its specified endurance limit,
described previously, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for its full specified retention lifetime every time the
Flash/EE memory is reprogrammed. It should also be noted
that retention lifetime, based on an activation energy of 0.6 eV,
derates with T

as shown in Figure 45. For example, the data is

J

retained for 100 years at 55°C operation, but reduces to 15 years
at 85°C operation. Beyond these limits, the part must be
reprogrammed so that the data can be restored.

300

250

200

150

100

RETENTIO N (Years)

ANALOG DEVICES
TYPICAL PERF ORMANCE
AT T

= 55°C

J

FLASH/EEMEM RELIABILITY

The Flash/EE memory array on the AD5233 is fully qualified
for two key Flash/EE memory characteristics, Flash/EE memory
cycling endurance, and Flash/EE memory data retention.

Rev. B | Page 22 of 32

50

0

50 60 70 80 90 100 110

40

TJ JUNCTION TE MPERATURE (°C)

Figure 45. Flash/EE Memory Data Retention

02794-046

AD5233

V

A

V

APPLICATIONS INFORMATION

BIPOLAR OPERATION FROM DUAL SUPPLIES

The AD5233 can be operated from dual supplies ±2.5 V, which
enables control of ground-referenced ac signals or bipolar opera­tion. AC signals as high as V

can be applied directly

DD/VSS

ac r os s Ter mi nal A an d Ter mi n al B w ith o utp ut t ake n f r om
Ter min al W. S ee Figure 46 for a typical circuit connection.

+2.5

V

DD

MICRO-

CONVERTER

GND

SS

SCLK

MOSI

CS
CLK

SDI

GND

AD5233

Figure 46. Bipolar Operation from Dual Supplies

V

V

DD

SS

A

W

B

±1.25V p-p

D = MIDSCALE

±

2.5V p-p

–2.5V

02794-047

GAIN CONTROL COMPENSATION

A digital potentiometer is commonly used in gain control such
as the noninverting gain amplifier shown in Figure 47.

C2

10pF

R2

100kΩ

R1

33.2kΩ

C1

35pF

V

i

Figure 47. Typical Noninverting Gain Amplifier

When RDAC B terminal parasitic capacitance is connected
to the op amp noninverting node, it introduces a 0 for the

term with 20 dB/dec, while a typical op amp GBP has

1/b

O

−20 dB/dec characteristics. A large R2 and finite C1 can cause
this zero’s frequency to fall well below the crossover frequency.
Therefore, the rate of closure becomes 40 dB/dec, and the
system as a 0° phase margin at the crossover frequency. The
output can ring or oscillate if an input is a rectangular pulse or
step function. Similarly, it is also likely to ring when switching
between two gain values; this is equivalent to a stop change at
the input.

Depending on the op amp GBP, reducing the feedback
resistor might extend the zero’s frequency far enough to
overcome the problem. A better approach is to include a
compensation capacitor, C2, to cancel the effect caused by
C1. Optimum compensation occurs when R1 × C1 = R2 ×
C2. This is not an option because of the variation of R2.

BA

U1

W

V

O

02794-048

As a result, one can use the previous relationship and scale C2
as if R2 were at its maximum value. Doing this might over­compensate and compromise the performance when R2 is
set at low values. On the other hand, it avoids the ringing or
oscillation at the worst case. For critical applications, C2 should
be found empirically to suit the need. In general, C2 in the
range of picofarads is usually adequate for the compensation.

Similarly, W and A terminal capacitances are connected to the
output (not shown); their effect at this node is less significant
and the compensation can be avoided in most cases.

HIGH VOLTAGE OPERATION

The digital potentiometer can be placed directly in the feedback
or input path of an op amp for gain control, provided that the
voltage across Terminal A and Terminal B, Terminal W and
Ter min al A , o r Ter mi n al W an d Ter mi n al B d oes not ex c ee d
|5 V|. When high voltage gain is needed, users should set a
fixed gain in an op amp operated at high voltage and let the
digital potentiometer control the adjustable input. Figure 48
shows a simple implementation.

C

R2R

15V

D5233

5V

A

W

B

–

V+

A2

V–

+

0 TO 15V

V

O

2794-049

Figure 48. 5 V Voltage Span Control

Similarly, a compensation capacitor, C, might be needed to
dampen the potential ringing when the digital potentiometer
changes steps. This effect is prominent when stray capacitance
at the inverted node is augmented by a large feedback resistor.
Usually, a capacitor (C) of a few picofarads, is adequate to combat
the problem.

DAC

Figure 49 shows a unipolar 8-bit DAC using the AD5233. The
buffer is needed to drive various loads.

5

AD5233

U1

1

VINV

GND

2

3

OUT

AD1582

A

W

B

Figure 49. Unipolar 8-Bit DAC

5V

V+

AD8601

V–

A1

V

O

02794-050

Rev. B | Page 23 of 32

AD5233

V

BIPOLAR PROGRAMMABLE GAIN AMPLIFIER

There are several ways to achieve bipolar gain. Figure 50 shows
one versatile implementation. Digital potentiometer, U1, sets
the adjustment range; therefore, the wiper voltage, V
programmed between V

U2

AD5233

V

i

A2

A1

U1

AD5233

Figure 50. Bipolar Programmable Gain Amplifier

and −KVi at a given U2 setting.

i

DD

–KV

OP2177

A2

i

V+

V–

V

SS

W2

B2

B1

W1

A1

V+

OP2177

V–

V

DD

V

SS

Configuring A2 as a noninverting amplifier yields a linear
transfer function:

V

⎛

O

+= KK

1 (4)

⎜

V

⎝

i

R2

R1

D2

⎞

⎛

⎟

⎜

64

⎠

⎝

⎞

−+××

)1(

⎟
⎠

where:
K is the ratio of R

that is set by U1.

WB/RWA

D is the decimal equivalent of the input code.

In the simpler (and much more usual) case where K is 1, a
pair of matched resistors can replace U1. Equation 4 can be
simplified to

V

⎛

O

+= 1

1

⎜

V

⎝

i

R2
R1

2

D

64

⎞

2

(5)

−×

⎟
⎠

⎛

⎞

⎜

⎟
⎠

⎝

Tabl e 19 shows the result of adjusting D with A2 configured as a
unity gain, a gain of 2, and a gain of 10. The result is a bipolar
amplifier with linearly programmable gain and 64-step resolution.

, can be

W2

V

O

R2

R1

C

02794-051

PROGRAMMABLE LOW-PASS FILTER

The AD5233 digital potentiometer can be used to construct a
second-order Sallen-Key low-pass filter, as shown in Figure 51.

C1

+2.5V

R2R1

ω

O

O

S

+

and R

B

A

W

R

C2

2

(6)

2

ω+

O

1

1

×

(7)

C2C1R2R1

×××

(8)

C2R2

, respectively.

WB2

V+

AD8601

V–

–2.5V

V

O

U1

2794-052

i

W

R

GANGED

TOGETHER

Figure 51. Sallen-Key Low-Pass Filter

B

A

V

The design equations are

V

O

=

ω

2

V

i

S

+

Q

=ω

O

1

Q

=

C1R1

×

where:
Q is the Q factor.

is the resonant frequency.

V

O

R1 and R2 are R

WB1

To achieve maximal flat bandwidth where Q is 0.707, let C1
be twice the size of C2 and let R1 equal R2. Users can first
select convenient values for the capacitors and then gang and
move R1 and R2 together to adjust the −3 dB corner frequency.
Instruction 5, Instruction 7, Instruction 13, and Instruction 15
of the AD5233 make these changes simple to implement.

Table 19. Result of Bipolar Gain Amplifier

D R1 = ∞, R2 = 0 R1 = R2 R2 = 9 × R1

0 −1 −2 −10
16 −0.5 −1 −5
32 0 0 0
48 0.5 1 5
63 0.968 1.937 9.680

Rev. B | Page 24 of 32

AD5233

V

PROGRAMMABLE STATE-VARIABLE FILTER

One of the standard circuits used to generate a low-pass, high­pass, or band-pass filter is the state-variable active filter. The
AD5233 digital potentiometer allows full programmability
of the frequency, the gain, and the Q of the filter outputs.
Figure 52 shows a filter circuit using a 2.5 V virtual ground,
which allows a ±2.5 V peak input and output swing. RDAC2
and RDAC3 set the low-pass, high-pass, and band-pass cutoff
and center frequencies, respectively. RDAC2 and RDAC3
should be programmed with the same data (as with ganged
potentiometers) to maintain the best Circuit Q.

RDAC4

IN

RDAC1

B

B

A1

2.5V

R1

10kΩ

A2

R2

10kΩ

RDAC2

0.01µF

B

A3

B

RDAC3

0.01µF

A3

LOW-PASS

Figure 53 shows the measured filter response at the band-pass
output as a function of the RDAC2 and RDAC3 settings, which
produce a range of center frequencies from 2 kHz to 20 kHz.
The filter gain response at the band-pass output is shown in
Figure 54. At a center frequency of 2 kHz, the gain is adjusted
over the −20 dB to +20 dB range, determined by RDAC1.
Circuit Q is adjusted by RDAC4 and RDAC1. Suitable op amps
for this application are OP4177, AD8604, OP279, and AD824.

40

20

0

–20

AMPLITUDE (dB)

–40

20k–16

*

OP279 × 2

Figure 52. Programmable Stable-Variable Filter

The transfer function of the band-pass filter is

ω

O

S

A

V

V

where A

For R

WB2(D2)

A =

Q

BP

i

is the gain.

O

=ω (10)

O

O

R

R

O

= (9)

S

= R

Q

ω

2

+

Q

WB3(D3)

O

2

S

ω+

O

, R1 = R2, and C1 = C2:

1

C1R

WB2

R

WB1

(11)

R

WA1

R

WB1

WA4

×= (12)

R1

WB4

BAND-PASS

HIGH-PASS

–60

2794-053

–80

20 100 1k 10k 100k 200k

FREQUENCY (Hz)

02794-054

Figure 53. Programmed Center Frequency Band-Pass Response

40

20

0

–20

AMPLITUDE (dB)

–40

–60

–80

20 100 1k 10k 100k 200k

FREQUENCY ( Hz)

2.0k–19.01

02794-055

Figure 54. Programmed Amplitude Band-Pass Response

Rev. B | Page 25 of 32

AD5233

C

C

PROGRAMMABLE OSCILLATOR

In a classic Wien-bridge oscillator, shown in Figure 55, the
Wien network (R, R´, C, C´) provides positive feedback, while
R1 and R2 provide negative feedback. At the resonant frequency,

, the overall phase shift is zero, and the positive feedback

f

O

causes the circuit to oscillate. If the op amp is chosen with a
relatively high gain bandwidth product, the frequency response
of the op amp can be neglected.

FREQUENCY

ADJUSTMENT

10kΩ

B

R

A

C

2.2nF

R = R' = R2B = 1/4 AD5233
D1 = D2 = 1N4148

Figure 55. Programmable Oscillator with Amplitude Control

With R = R´, C = C´, and R2 = R2A||(R2B + R
oscillation frequency is

1

or

=

f

O

such that

WA

(14)

R

AB

where

R

=ω

O

R

R is equal to R

−

64

D

=

64

At resonance, setting

R2

(15)

2=

R1

balances the bridge. In practice, R2/R1 should be set slightly
larger than 2 to ensure that the oscillation can start. On the
other hand, the alternate turn-on of the diodes, D1 and D2,
ensures that R1/R2 is smaller than 2 momentarily and,
therefore, stabilizes the oscillation.

Once the frequency is set, the oscillation amplitude can be
turned on by R2B, because

where

2

O

3

V

, ID, and VD are interdependent variables.

O

VR2BIV +=

DD

With proper selection of R2B, an equilibrium is reached such
that V

converges. R2B can be in series with a discrete resistor

O

to increase the amplitude, but the total resistance cannot be too
large or it saturates the output. In this configuration, R2B can be
adjusted from minimum to full scale with amplitude varied
from ±0.6 V to ±0.9 V. Using 2.2 nF for C and C´, 10 kΩ dual

C'

R'

2.2nF

+2.5V

OP1177

–2.5V

R2B

W

10kΩ

AB

W

V+

U1

V–

R2A

2.1kΩ

AB

AMPLITUDE

ADJUSTMENT

V

O

D1

D2

02794-056

), the

DIODE

VP

W

VN

10kΩ

R1

1kΩ

1

(13)

R

π

2

(16)

digital potentiometer, with R and R´ set to 8.06 kΩ, 4.05 kΩ,
and 670 Ω, oscillation occurs at 8.8 kHz, 17.6 kHz, and
102 kHz, respectively (see Figure 56).

1V/DIV

R = 8.06kΩ
f = 8.8kHz

1V/DIV

R = 4.05kΩ
f = 17.6kHz

1V/DIV

R = 670Ω
f = 102kHz

Figure 56. Programmable Oscillation

In both circuits (shown in Figure 51 and Figure 55), the
frequency tuning requires that both RDACs be adjusted to
the same settings. Because the two channels might be adjusted
one at a time, an intermediate state occurs that might not be
acceptable for some applications. Of course, the increment/
decrement all instructions (5, 7, 13, and 15) can be used.
Different devices can also be used in daisy-chain mode so that
parts can be programmed to the same setting simultaneously.

PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT

For applications that require high current adjustment, such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered (see Figure 57).

V

IN

AD5233

A

W

B

U2

AD8601

2N7002

SIGNAL

V+

V–

Figure 57. Programmable Boosted Voltage Source

In this circuit, the inverting input of the op amp forces the V
to be equal to the wiper voltage set by the digital potentiometer.
The load current is then delivered by the supply via the N­channel FET N
dissipate (V

. N1 power handling must be adequate to

1

− VO) × IL power. This circuit can source a

i

maximum of 100 mA with a 5 V supply.

For precision applications, a voltage reference such as ADR421,
ADR03, or ADR370 can be applied at Terminal A of the digital
potentiometer.

LD

V

OUT

R

BIAS

C

C

I

L

02794-058

OUT

02794-057

Rev. B | Page 26 of 32

AD5233

V

A

(

+

V

PROGRAMMABLE CURRENT SOURCE

A programmable current source can be implemented with the
circuit shown in Figure 58.

+5

2

U1

V

S

3

SLEEP

GND

4

OUTPUT

REF191

AD5233

–2.048V TO V

Figure 58. Programmable Current Source

REF191 is a unique low supply headroom precision reference
that can deliver the 20 mA needed at 2.048 V. The load current
is simply the voltage across Terminal B to Terminal W of the
digital potentiometer divided by R

The circuit is simple, but be aware that there are two issues.
First, dual-supply op amps are ideal, because the ground
potential of REF191 can swing from −2.048 V at zero scale

at full scale of the potentiometer setting. Although the

to V

L

circuit works under single supply, the programmable resolution
of the system is reduced. Second, the voltage compliance at V
is limited to 2.5 V or equivalently a 125 Ω load. If higher voltage
compliance is needed, users can consider digital potentiometers
AD5260, AD5280, and AD7376. Figure 58 shows an alternative
circuit for high voltage compliance.

To achieve higher current, such as when driving a high power
LED, the user can replace the U1 with an LDO, reduce R
add a resistor in series with the AD5233’s A terminal. This
limits the potentiometer’s current and enhances the current
adjustment resolution.

L

0 TO (2.048 + VL)

6

C1
1µF

+5V

V+

OP1177

U2

V–

–5V

B

W

A

–

+

.

S

100Ω

R

S

102Ω

V

R

L

L

I

L

2794-059

L

, and

S

PROGRAMMABLE BIDIRECTIONAL CURRENT SOURCE

For applications that require bidirectional current control or
higher voltage compliance, a Howland current pump can be
used (see Figure 59).

R1

150kΩ

D5233

+2.5V

A

BW

–2.5V

+15V

+

OP2177

–

A1

–15V

V+

V–

R1

150kΩ

Figure 59. Programmable Bidirectional Current Source

15kΩ

+15V

–

V+

OP2177

V–

+

–15V

14.95kΩ

R2

A2

R2A

C1

10pF

R2B
50Ω

R

L

500Ω

V

L

I

L

02794-060

If the resistors are matched, the load current is

)

R2BR2A

I ×

R1

=

R2B

(17)

V

WL

R2B, in theory, can be made as small as necessary to achieve the
current needed within the A2 output current-driving capability.
In this circuit, OP2177 delivers ±5 mA in both directions, and
the voltage compliance approaches 15 V. Without C1, it can be
shown that the output impedance is

)('

R2AR1R2BR1

Z

=

O

can be infinite if the R1´ and R2´ resistors match precisely

Z

O

R1 and R2A + R2B,

with

+×

respectively. On the other hand, ZO can

(18)

)(''

R2BR2AR1R2R1

+−×

be negative if the resistors are not matched. As a result, C1 in
the range of 1 pF to 10 pF is needed to prevent oscillation from
the negative impedance.

RESISTANCE SCALING

AD5233 offers 10 kΩ, 50 kΩ, and 100 kΩ nominal resistance.
Users who need lower resistance but want to maintain the
number of adjustment steps can parallel multiple devices. For
example, Figure 60 shows a simple scheme of paralleling two
AD5233 channels. To adjust half the resistance linearly per step,
users need to program both devices concurrently with the same
settings.

DD

W1

A2

W2

B2

02794-061

A1

B1

LD

Figure 60. Reduce Resistance by Half with Linear Adjustment Characteristics

Rev. B | Page 27 of 32

AD5233

V

V

A

V

In voltage divider mode, by paralleling a discrete resistor as
shown in Figure 61, a proportionately lower voltage appears at
Terminal A to Terminal B. This translates into a finer degree of
precision because the step size at Terminal W is smaller.

DD

R3

A

R2

W

R1

B

0

02794-062

Figure 61. Lowering the Nominal Resistance

The voltage can be found as follows:

RR

)||(

D

2

DV ××

W

AB

=

)(

+

AB

RRR

64||

23

(19)

V

DD

Figure 60 and Figure 61 show that the digital potentiometer
steps change linearly. On the other hand, log taper adjustment
is usually preferred in applications such as audio control.
Figure 62 shows another type of resistance scaling. In this
configuration, the smaller the R2 with respect to R1, the
more the pseudo log taper characteristic of the circuit behaves.

i

A

R1

W

B

V

O

R2

2794-063

Figure 62. Resistor Scaling with Pseudo Log Adjustment Characteristics

DOUBLING THE RESOLUTION

Borrowing from Analog Devices’ patented RDAC segmentation
technique, the user can configure three channels of AD5233, as
shown in Figure 63. By paralleling a discrete resistor, R

R

/64), with RDAC3, the user can double the resolution of

AB

AD5233 from 6 bits to 12 bits. One might think that moving
RDAC1 and RDAC2 together would form the coarse 6-bit
resolution, and then moving RDAC3 would form the finer
6-bit resolution. As a result, the effective resolution would
become 12 bits. However, the precision of this circuit remains
only 6-bit accurate and the programming can be complicated.

A

A1

RDAC1

B1

R

P

A2

RDAC2

B2

Figure 63. Doubling AD5233 from 6 Bits to 12 Bits

A3

RDAC3

B3

W3

02794-064

(RP =

P

RESISTANCE TOLERANCE, DRIFT, AND TEMPERATURE MISMATCH CONSIDERATIONS

In a rheostat mode operation such as gain control (see Figure 64),
the tolerance mismatch between the digital potentiometer and
the discrete resistor can cause repeatability issues among various
systems. Because of the inherent matching of the silicon process,
it is practical to apply the dual- or multiple-channel device in
this type of application. As such, R1 can be replaced by one of
the channels of the digital potentiometer and programmed to a
specific value. R2 can be used for the adjustable gain. Although
it adds cost, this approach minimizes the tolerance and
temperature coefficient mismatch between R1 and R2. This
approach also tracks the resistance drift over time. As a result,
all nonideal parameters become less sensitive to the system
variations.

R2

AB

W

R1*

V

*REPLACED WIT H ANOTHER
CHANNEL OF RDAC

Figure 64. Linear Gain Control with Tracking Resistance Tolerance

and Temperature Coefficient

C1

–

AD8601

+

i

U1

V

O

2794-065

RDAC CIRCUIT SIMULATION MODEL

The internal parasitic capacitances and the external load
dominate the ac characteristics of the RDACs. Configured as
a potentiometer divider, the −3 dB bandwidth of the AD5233
(10 kΩ resistor) measures 370 kHz at half scale. Figure 14
provides the large signal bode plot characteristics. A parasitic
simulation model is shown in Figure 65.

RDAC

10kΩ

C

A

35pF

C

W

35pF

W

Figure 65. RDAC Circuit Simulation Model for RDAC = 10 kΩ

The following code provides a macromodel net list for the
10 kΩ RDAC:

Listing I. spice model net list
.PARAM D = 64, RDAC = 10E3
*
.SUBCKT DPOT (A, W, B)
*
CA A 0 35E-12
RWA A W {(1-D/64)* RDAC + 15}
CW W 0 35-12
RWB W B {D/64 * RDAC + 15}
CB B 0 35E-12
*
.ENDS DPOT

C

B

35pF

B

02794-066

Rev. B | Page 28 of 32

AD5233

OUTLINE DIMENSIONS

7.90

7.80

7.70

24

PIN 1

0.15

0.05

0.10 COPLANARITY

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AD

13

121

1.20
MAX

SEATING
PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09

8°
0°

0.75

0.60

0.45

Figure 66. 24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

ORDERING GUIDE

R

AB

(kΩ)

Temperature
Range

Model

No. of
Channels

AD5233BRU10 4 10 −40°C to +85°C 24-Lead TSSOP RU-24 96 5233B10
AD5233BRU10-REEL7 4 10 −40°C to +85°C 24-Lead TSSOP RU-24 1,000 5233B10
AD5233BRUZ10
AD5233BRUZ10-R7

2

2

4 10 −40°C to +85°C 24-Lead TSSOP RU-24 1,000 5233B10

4 10 −40°C to +85°C 24-Lead TSSOP RU-24 96 5233B10

AD5233BRU50 4 50 −40°C to +85°C 24-Lead TSSOP RU-24 96 5233B50
AD5233BRU50-REEL7 4 50 −40°C to +85°C 24-Lead TSSOP RU-24 1,000 5233B50
AD5233BRUZ50
AD5233BRUZ50-R7

2

4 50 −40°C to +85°C 24-Lead TSSOP RU-24 96 5233B50

2

4 50 −40°C to +85°C 24-Lead TSSOP RU-24 1,000 5233B50

AD5233BRU100 4 100 −40°C to +85°C 24-Lead TSSOP RU-24 96 5233B100
AD5233BRU100-REEL7 4 100 −40°C to +85°C 24-Lead TSSOP RU-24 1,000 5233B100
AD5233BRUZ100
AD5233BRUZ100-R7

1

Line 1 contains the model number. Line 2 contains the Analog Devices logo followed by the end-to-end resistance value. Line 3 contains the date code, YWW or

#YWW, for RoHS compliant parts.

2

Z = RoHS Compliant Part.

2

4 100 −40°C to +85°C 24-Lead TSSOP RU-24 96 5233B100

2

4 100 −40°C to +85°C 24-Lead TSSOP RU-24 1,000 5233B100

Package
Description

Package
Option

Ordering
Quantity

Branding

1

Rev. B | Page 29 of 32

AD5233

NOTES

Rev. B | Page 30 of 32

AD5233

NOTES

Rev. B | Page 31 of 32

AD5233

NOTES

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent
Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02794-0-5/08(B)

Rev. B | Page 32 of 32