ANALOG DEVICES AD5233 Service Manual

Nonvolatile Memory, Quad

FEATURES

Nonvolatile memory stores wiper setting
4-channel independent programmable
64-position resolution
Power-on refreshed with EEMEM settings
EEMEM restore time: 140 μs typical
Full monotonic operation
10 kΩ, 50 kΩ, and 100 kΩ terminal resistance
Permanent memory write protection
Wiper setting readback
Predefined linear increment/decrement instructions
Predefined ±6 dB/step log taper increment/decrement

instructions

SPI-compatible serial interface with readback function

2.7 V to 5.5 V single supply or ±2.5 V dual supply
11 bytes extra nonvolatile memory for user-defined data
100-year typical data retention, T

APPLICATIONS

Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Programmable power supply
Sensor calibration

= 55°C

A

64-Position Digital Potentiometer

AD5233

FUNCTIONAL BLOCK DIAGRAM

CS

CLK

SDI

SDO

WP

RDY

O1

O2

PR

GND

DECODE

SDI SERIAL
INTERFACE

SDO

EEMEM

CONTRO L

11 BYTES

USER EEMEM

DIGITAL
OUTPUT
BUFFER

2

DIGITAL 5

REGISTER

EEMEM5

ADDR

REGISTER

EEMEM1

REGISTER

EEMEM2

REGISTER

EEMEM3

REGISTER

EEMEM4

Figure 1.

RDAC1

RDAC2

RDAC3

RDAC4

AD5233

RDAC1

RDAC2

RDAC3

RDAC4

V

A1

W1

B1

A2

W2

B2

A3

W3

B3

A4

W4

B4

V

DD

SS

02794-001

GENERAL DESCRIPTION

The AD5233 is a quad-channel nonvolatile memory,1 digitally
controlled potentiometer
performs the same electronic adjustment function as a mechanical
potentiometer with enhanced resolution, solid-state reliability,
and remote controllability. The AD5233 has versatile program­ming using a serial peripheral interface (SPI) for 16 modes of
operation and adjustment, including scratchpad programming,
memory storing and restoring, increment/decrement, ±6 dB/step
log taper adjustment, wiper setting readback, and extra EEMEM
for user-defined information such as memory data for other
components, look-up tables, or system identification
information.

1

The terms nonvolatile memory and EEMEM are used interchangeably.

2

The terms digital potentiometer and RDAC are used interchangeably.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

2

with a 64-step resolution. The device

In the scratchpad programming mode, a specific setting can
be programmed directly to the RDAC register, which sets the
resistance between Terminal W to Terminal A and Terminal W
to Terminal B. This setting can be stored into the EEMEM and
is transferred automatically to the RDAC register during system
power-on.

The EEMEM content can be restored dynamically or through
external

PR

strobing. A WP function protects EEMEM contents.

To simplify the programming, independent or simultaneous
increment or decrement commands can be used to move the
RDAC wiper up or down, one step at a time. For logarithmic
±6 dB step changes in wiper settings, the left or right bit shift
command can be used to double or halve the RDAC wiper
setting.

The AD5233 is available in a thin 24-lead TSSOP package. The
part is guaranteed to operate over the extended industrial
temperature range of −40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2002–2008 Analog Devices, Inc. All rights reserved.

AD5233

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics—10 kΩ, 50 kΩ, and 100 kΩ

Versions .......................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ............................................. 9

Test Circuits ..................................................................................... 13

Theory of Operation ...................................................................... 15

Scratchpad and EEMEM Programming .................................. 15

Basic Operation .......................................................................... 15

EEMEM Protection .................................................................... 16

Digital Input/Output Configuration ........................................ 16

Serial Data Interface ................................................................... 16

Daisy-Chain Operation ............................................................. 17

Terminal Voltage Operation Range ......................................... 17

Power-Up Sequence ................................................................... 17

Latched Digital Outputs ............................................................ 17

Advanced Control Modes ......................................................... 19

REVISION HISTORY

5/08—Rev. A to Rev. B

Changes to Features ........................................................................... 1

Changes to Table 1 ............................................................................. 3

Changes Figure 3 ............................................................................... 6

Changes to Absolute Maximum Ratings Section .......................... 7

Changes to Figure 17 and Figure 18 .............................................. 11

Changes to Programmable Oscillator Section ............................. 26

Changes to Ordering Guide ........................................................... 29

RDAC Structure.......................................................................... 20

Programming the Variable Resistor ......................................... 20

Programming the Potentiometer Divider ............................... 21

Programming Examples ............................................................ 21

Flash/EEMEM Reliability .......................................................... 22

Applications Information .............................................................. 23

Bipolar Operation from Dual Supplies.................................... 23

Gain Control Compensation .................................................... 23

High Voltage Operation ............................................................ 23

DAC .............................................................................................. 23

Bipolar Programmable Gain Amplifier ................................... 24

Programmable Low-Pass Filter ................................................ 24

Programmable State-Variable Filter ......................................... 25

Programmable Oscillator .......................................................... 26

Programmable Voltage Source with Boosted Output ........... 26

Programmable Current Source ................................................ 27

Programmable Bidirectional Current Source ......................... 27

Resistance Scaling ...................................................................... 27

Doubling the Resolution ........................................................... 28

Re s is t an c e To ler anc e , Dr if t, a n d Te m pe r atu re Mi s mat ch

Considerations ............................................................................ 28

RDAC Circuit Simulation Model ............................................. 28

Outline Dimensions ....................................................................... 29

Ordering Guide .......................................................................... 29

7/04—Rev. 0 to Rev. A

Format updated .................................................................. Universal

Changes to Features, General Description, and Block

Diagram .............................................................................................. 1

Changes to Specifications ................................................................. 3

Replaced Timing Diagrams .............................................................. 6

Changes to Absolute Maximum Ratings ........................................ 7

Changes to Pin Function Descriptions ........................................... 8

Replaced Figure 11 ............................................................................ 9

Added Test Circuit (Figure 36) ...................................................... 13

Changes to Theory of Operation ................................................... 14

Changes to Applications ................................................................. 22

Updated Outline Dimensions ........................................................ 28

Changes to Ordering Guide ........................................................... 28

3/02—Revision 0: Initial Version

Rev. B | Page 2 of 32

AD5233

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS

VDD = 3 V ± 10% or 5 V ± 10%, VSS = 0 V, VA = VDD, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS,

1

Max Unit

RHEOSTAT MODE
Resistor Differential Nonlinearity
Resistor Integral Nonlinearity

2

2

R-INL R

R-DNL RWB, VA = NC, monotonic −0.5 ±0.1 +0.5 LSB

, VA = NC −0.5 ±0.1 +0.5 LSB

WB

Nominal Resistor Tolerance ∆RAB/RAB D = 0x3F −40 +20 %
Resistance Temperature Coefficient (∆RWB/RWB)/∆T × 106 600 ppm/°C
Wiper Resistance RW I

DC CHARACTERISTICS,

= 100 μA, code = half scale 15 100 Ω

W

POTENTIOMETER DIVIDER MODE
Resolution N 6 Bits
Differential Nonlinearity
Integral Nonlinearity
Voltage Divider Temperature

3

3

INL −0.5 +0.1 +0.5 LSB

DNL Monotonic −0.5 +0.1 +0.5 LSB

(∆V

)/∆T × 106 Code = half scale 15 ppm/°C

W/VW

Coefficient
Full-Scale Error V
Zero-Scale Error V

Code = full scale −1.5 0 % FS

WFSE

Code = zero scale 0 1.5 % FS

WZSE

RESISTOR TERMINALS

Terminal Voltage Range
Capacitance A, Capacitance B

4

5

VA, VB, VW V
CA, CB

f = 1 MHz, measured to GND,

VDD V

SS

35 pF

code = half scale

Capacitance W5 CW

f = 1 MHz, measured to GND,

35 pF

code = half scale

Common-Mode Leakage Current

5, 6

I

V

CM

= VDD/2 0.015 1 μA

W

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH With respect to GND, VDD = 5 V 2.4 V
With respect to GND, VDD = 3 V 2.1 V

With respect to GND,

= 2.5 V, VSS = −2.5 V

V

DD

2.0 V

Input Logic Low VIL With respect to GND, VDD = 5 V 0.8 V
With respect to GND, VDD = 3 V 0.6 V

Output Logic High (SDO, RDY) VOH

With respect to GND,

= 2.5 V, VSS = −2.5 V

V

DD

= 2.2 kΩ to 5 V

R

PULL-UP

0.5 V

4.9 V

(see Figure 35)

Output Logic Low VOL

= 1.6 mA, V

I

OL

LOGI C

= 5 V

0.4 V

(see Figure 35)
Input Current IIL V
Input Capacitance
Output Current

5

C

5

I

4 pF

IL

, IO2

O1

= 0 V or VDD ±2.5 μA

IN

= 5 V, VSS = 0 V, TA = 25°C,

V

DD

50 mA

sourcing only

= 2.5 V, VSS = 0 V, TA = 25°C,

V

DD

7 mA

sourcing only

Rev. B | Page 3 of 32

AD5233

Parameter Symbol Conditions Min Typ

1

Max Unit

POWER SUPPLIES

Single-Supply Power Range VDD V

= 0 V 2.7 5.5 V

SS

Dual-Supply Power Range VDD/VSS ±2.5 ±2.75 V
Positive Supply Current IDD V
Negative Supply Current ISS

EEMEM Store Mode Current IDD (store)

I
EEMEM Restore Mode Current

7

(store) VDD = 2.5 V, VSS = −2.5 V −40 mA

SS

IDD (restore)

= VDD or VIL = GND 3.5 10 μA

IH

= VDD or VIL = GND,

V

IH

= 2.5 V, VSS = −2.5 V

V

DD

= VDD or VIL = GND,

V

IH

= 0, ISS ≈ 0

V

SS

= VDD or VIL = GND,

V

IH

0.55 10 μA

40 mA

0.3 3 9 mA

VSS = GND, ISS ≈ 0
I
Power Dissipation
Power Supply Sensitivity

DYNAMIC CHARACTERISTICS

8

5

P

5, 9

(restore) VDD = 2.5 V, VSS = −2.5 V −0.3 −3 −9 mA

SS

P

V

DISS

∆VDD = 5 V ± 10% 0.002 0.01 %/%

SS

= VDD or VIL = GND 0.018 0.05 mW

IH

Bandwidth BW −3 dB, RAB = 10 kΩ/50 kΩ/100 kΩ 630/135/66 kHz
Total Harmonic Distortion THDW

VW Settling Time tS

= 1 V rms, VB = 0 V, f = 1 kHz,

V

A

= 10 kΩ

R

AB

= 1 V rms, VB = 0 V, f = 1 kHz,

V

A

R

= 50 kΩ, 100 kΩ

AB

= VDD, VB = 0 V,

V

A

= 0.50% error band,

V

W

0.04 %

0.015 %

0.6/2.2/3.8 μs

Code 0x000 to Code 0x200

for R

= 10 kΩ/50 kΩ/100 kΩ

AB

Resistor Noise Voltage e
Crosstalk (CW1/CW2) CT

R

N_WB

= 5 kΩ, f = 1 kHz 9

WB

= VDD, VB = 0 V, measure VW

V

A

−1

nV/√Hz

nV/sec
with adjacent RDAC making
the full-scale code change

Analog Crosstalk (CW1/CW2) CTA

= VA1 = +2.5 V,

V

DD

= VB1 = −2.5 V,

V

SS

measure V

with VW2 = 5 V p-p

W1

−86/−73/−68 dB

@ f = 10 kHz, Code 1 = 0x20,
Code 2 = 0x3F, RAB = 10 kΩ/
50 kΩ/100 kΩ

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. I
RAB = 50 kΩ, and IW > 25 μA for the RAB = 100 kΩ version (see Figure 25).

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output ADC. VA = VDD and VB = VSS. DNL specification limits of

−1 LSB minimum are guaranteed monotonic operating conditions (see Figure 26).

4

Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-

referenced bipolar signal adjustment.

5

Guaranteed by design and not subject to production test.

6

Common-mode leakage current is a measure of the dc leakage from Terminal B and Terminal W to a common-mode bias level of VDD/2.

7

EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 22). To

minimize power dissipation, a NOP instruction should be issued immediately after Instruction 1 (0x1).

8

Power dissipation is calculated by P

9

All dynamic characteristics use VDD = 2.5 V and VSS = −2.5 V.

= (IDD × VDD) + (ISS × VSS).

DISS

> 50 μA @ VDD = 2.7 V for the RAB = 10 kΩ version, IW > 50 μA for the

W

Rev. B | Page 4 of 32

AD5233

TIMING CHARACTERISTICS

VDD = 3 V to 5.5 V, VSS = 0 V, and −40°C < TA < +85°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

INTERFACE TIMING CHARACTERISTICS

Clock Cycle Time (t

) t1 20 ns

CYC

CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulse Width t4, t5 Clock level high or low 10 ns

Data Setup Time t6 From positive CLK transition 5 ns
Data Hold Time t7 From positive CLK transition 5 ns
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay4 t
CLK to SDO Data Hold Time t11 R
CS High Pulse Width5

CS High to CS High5
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Read/Store to Nonvolatile EEMEM6 t

CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous) t
Preset Response Time to Wiper Setting t
Power-On EEMEM Restore Time t

FLASH/EE MEMORY RELIABILITY

Endurance7 100
Data Retention8 100

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Guaranteed by design and not subject to production test.

3

See the timing diagrams (Figure 2 and Figure 3) for the location of the measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V)

and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 5 V.

4

Propagation delay depends on the value of VDD, R

5

Valid for commands that do not activate the RDY pin.

6

The RDY pin is low only for Command 2, Command 3, Command 8, Command 9, Command 10, and the PR hardware pulse: CMD_8 > 1 ms; CMD_9, CMD_10 > 0.12 ms;

CMD_2, CMD_3 > 20 ms. Device operation at T

7

Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, and +85°C; typical endurance at 25°C is 700,000 cycles.

8

Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV

derates with junction temperature, as shown in Figure 45 in the Flash/EEMEM Reliability section.

2, 3

t

10 ns

2

t

1 t

3

t

40 ns

8

t

50 ns

9

R

10

t

12

t

4 t

13

t

0 ns

14

t

0.1 0.15 ms

15

16

= 2.2 kΩ, CL < 20 pF 50 ns

PULL-UP

= 2.2 kΩ, CL < 20 pF 0 ns

P

Applies to Instruction 0x2, Instruction 0x3,

10 ns

25 ms

and Instruction 0x9

t

10 ns

17

Not shown in timing diagram 50 ns

PRW

PRESP

RAB = 10 kΩ 140 μs

EEMEM1

pulsed low to refresh wiper positions

PR

70 μs

, and CL.

PULL-UP

= −40°C and VDD < 3 V extends the save time to 35 ms.

A

CYC

CYC

kCycles
Yea r s

Rev. B | Page 5 of 32

AD5233

CPHA = 1

CS

t

12

t

t

5

B15

(MSB)

1

B15

B15

(MSB)

t

4

t

7

t

6

(LSB)

t

10

t

11

t

CLK

CPOL = 1

HIGH OR

LOW

SDI

t

SDO

t

14

RDY

*EXTRA BIT T HAT IS NOT DEFINED, BUT NORMALLY L SB OF CHARACTER PREVIOUSL Y TRANSMIT TED.
THE CPOL = 1 MICROCONTRO LLER COM MAND ALIGNS T HE INCOMING DATA TO T HE POSIT IVE EDGE O F THE CLO CK.

2

8

B16*

t

3

B0

B0

B0

(LSB)

t

t

13

t

17

HIGH OR LOW

t

9

15

t

16

02794-002

Figure 2. CPHA = 1 Timing Diagram

CS

CLK

CPOL = 0

t

1

t

2

B15 B0

t

5

t

4

CPHA = 0

t

12

t

3

t

13

t

17

SDI

SDO

RDY

t

HIGH
OR LOW

t

14

* NOT DEFINED, BUT NORMALL Y MSB OF CHARACTER PREVIOUSLY RECE IVED.

THE CPOL = 0 MICROCONT ROLLER CO MMAND ALIGNS THE INCOMI NG DATA TO THE POSI TIVE EDG E OF THE CLOCK.

t

8

B15

(MSB)

B15

(MSB OUT)

t

10

6

B0

(LSB)

t

11

B0

(LSB)

t

7

Figure 3. CPHA = 0 Timing Diagram

Rev. B | Page 6 of 32

HIGH
OR LOW

t

9

*

t

15

t

16

02794-003

AD5233

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7 V
VSS to GND +0.3 V to −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS − 0.3 V to VDD + 0.3 V
IA, IB, IW

Pulsed1 ±20 mA

Continuous ±2 mA
Digital Inputs and Output Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range2 −40°C to +85°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 20 sec to 40 sec
Thermal Resistance Junction-to-Ambient, θ
Package Power Dissipation (TJ max − TA)/θJA

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Includes programming of nonvolatile memory.

3

Thermal Resistance (JEDEC 4-layer (2S2P) board).

3

50°C/W

JA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 7 of 32

AD5233

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK

SDI

SDO

GND

V

W1

W2

O1

SS

A1

B1

A2

B2

1

2

3

4

AD5233

5

TOP VIEW

(Not to Scale)

6

7

8

9

10

11

12

24

O2

23

RDY

22

CS

21

PR

20

WP

19

V

DD

18

A4

17

W4

B4

16

15

A3

W3

14

B3

13

02794-005

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 O1 Nonvolatile Digital Output 1. Address (O1) = 0x4, the data bit position is D0; defaults to Logic 1 initially.
2 CLK Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges.
3 SDI Serial Data Input Pin. Shifts in one bit at a time on positive CLK edges. MSB loaded first.
4 SDO Serial Data Output Pin. Serves readback and daisy-chain functions.

Command 9 and Command 10 activate the SDO output for the readback function, delayed by 16 or 17 clock
pulses, depending on the clock polarity before and after the data-word (see Figure 2, Figure 3, and Table 7).

In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 16 or 17 clock pulses,
depending on the clock polarity (see Figure 2 and Figure 3). This previously shifted-out SDI can be used for daisy­chaining multiple devices.

Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed.
5 GND Ground Pin, Logic Ground Reference.
6 VSS

Negative Supply. Connect to 0 V for single-supply applications. If V

is used in dual supply, it must be able to sink

SS

40 mA for 25 ms when storing data to EEMEM.
7 A1 Terminal A of RDAC1.
8 W1 Wiper Terminal of RDAC1, Address (RDAC1) = 0x0.
9 B1 Terminal B of RDAC1.
10 A2 Terminal A of RDAC2.
11 W2 Wiper Terminal of RDAC2, Address (RDAC2) = 0x1.
12 B2 Terminal B of RDAC2.
13 B3 Terminal B of RDAC3.
14 W3 Wiper Terminal of RDAC3, Address (RDAC3) = 0x2.
15 A3 Terminal A of RDAC3.
16 B4 Terminal B of RDAC4.
17 W4 Wiper Terminal of RDAC4, Address (RDAC4) = 0x3.
18 A4 Terminal A of RDAC4.
19 VDD Positive Power Supply Pin.
20

Optional Write Protect Pin. When active low, WP prevents any changes to the present contents, except PR strobe

WP

and Instruction 1 and Instruction 8, and refreshes the RDAC register from EEMEM. Execute a NOP instruction

high. Tie WP to VDD if not used.

21

before returning to WP

Optional Hardware Override Preset Pin. Refreshes the scratchpad register with current contents of the EEMEM

PR

register. Factory default loads midscale 0x20 until EEMEM is loaded with a new value by the user. PR is activated at

.

22

Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to Logic 1.

CS

23 RDY

the Logic 1 transition. Tie PR

to VDD if not used.

Ready. Active-high open-drain output. Identifies completion of Software Instruction 2, Software Instruction 3,

Software Instruction 8, Software Instruction 9, Software Instruction 10, and Hardware Instruction PR
24 O2 Nonvolatile Digital Output 2. Address (O2) = 0x4, the data bit position is D1; defaults to Logic 1 initially.

Rev. B | Page 8 of 32

AD5233

TYPICAL PERFORMANCE CHARACTERISTICS

0.20

0.15

0.10

0.05

0

–0.05

INL ERROR (LSB)

–0.10

–0.15

–0.20

01632

CODE (Decimal)

TA =+25°C
T

A

T

A

48

=–40°C
=+85°C

64

02794-006

0.20

0.15

0.10

0.05

0

R-DNL (LSB)

–0.05

–0.10

–0.15

–0.20

01632

CODE (Decimal)

TA =+25°C
T

=–40°C

A

T

=+85°C

A

VDD = 5V, VSS = 0V

48

64

Figure 5. INL Error vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ Figure 8. R-DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

DNL ERROR (LSB)

0.20

0.15

0.10

0.05

–0.05

–0.10

–0.15

–0.20

TA =+25°C
T

=–40°C

A

T

=+85°C

A

0

0

16 32 64

CODE (Decimal)

48

02794-007

3000

2500

2000

1500

1000

500

RHEOSTAT MO DE TEMPCO (ppm/° C)

0

0

16 32 64

CODE (Decimal)

VDD = 5V, VSS = 0V
T

= –40°C TO + 85°C

A

48

Figure 9. (∆RWB/RWB)/∆T × 106 Figure 6. DNL Error vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

0.20

0.15

0.10

0.05

TA =+25°C
T

=–40°C

A

T

=+85°C

A

VDD = 5V, VSS = 0V

300

200

VDD = 5.5V, VSS = 0V
T

= –40°C TO +85°C

A

V

= 2V

A

V

= 0V

B

2794-009

2794-010

0

–0.05

R-INL ( LSB)

–0.10

–0.15

–0.20

01632

CODE (Decimal)

Figure 7. R-INL vs. Code, T

= −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

A

100

POTENTI OMETER MO DE TEMPCO (ppm/°C)

48

64

02794-008

0

01632

CODE (Decimal )

Figure 10. (∆VW/VW)/∆T × 106 vs. Code, R

48

= 10 kΩ

AB

64

02794-011

Rev. B | Page 9 of 32

AD5233

80

60

(Ω)

40

W

R

20

0

0

4

3

2

(µA)

DD

I

1

ISS @ VDD/VSS = 5V/0V

0

IDD @ VDD/VSS = 2.7V/0V

–1

–40 –20

0.30

0.25

0.20

0.15

(mA)

DD

I

0.10

0.05

VDD = 2.7V, VSS = 0V
T

= 25°C

A

16 32 64

CODE (Decimal)

48

Figure 11. Wiper On Resistance vs. Code

IDD @ VDD/VSS = 5V/0V

ISS @ VDD/VSS = 2.7V/0V

0 20 40 60 100

TEMPERATURE (° C)

Figure 12. IDD vs. Temperature, RAB = 10 kΩ

VDD = 5V
V

= 5V

SS

MIDSCALE

FULL SCALE

ZERO SCALE

3

VDD @ VSS = ±2.5V
V

= 1V rms

A

D = MIDSCALE

0

f

= 66kHz

–3

–6

GAIN (dB)

–9

–12

1k 1M

02794-012

–3dB

f

= 600kHz, RAB = 10kΩ

–3dB

f

= 132kHz, RAB = 50kΩ

–3dB

10k 100k

FREQUENCY (Hz)

02794-015

Figure 14. −3 dB Bandwidth vs. Resistance (Using the Circuit

Shown in Figure 31)

0.05

0.04

0.03

0.02

THD + NOISE ( %)

0.01

0

80

02794-013

10

RAB = 50kΩ

100 1k 10k

RAB = 10kΩ

RAB = 100kΩ

FREQUENCY (Hz)

V

DD/VSS

V

= 1V rms

A

= ±2.5V

100k

02794-016

Figure 15. Total Harmonic Distortion + Noise vs. Frequency

0

–6

–12

–18

–24

GAIN (dB)

–30

–36

CODE 0x20

0x10

0x08

0x04

0x02

0x01

0

024681012

CLOCK F REQUENCY (MHz)

Figure 13. IDD vs. Clock Frequency, RAB = 10 kΩ

Rev. B | Page 10 of 32

–42

100 10M

02794-014

1k 10k 100k

FREQUENCY (Hz)

1M

2794-017

Figure 16. Gain vs. Frequency vs. Code, RAB = 10 Ω ( Figure 31)