ANALOG DEVICES AD5232 Service Manual

Nonvolatile Memory,

V

S

Dual 256-Position Digital Potentiometer

Data Sheet

FEATURES

Dual-channel, 256-position resolution
10 kΩ, 50 kΩ, and 100 kΩ nominal terminal resistance
Nonvolatile memory maintenance of wiper settings
Predefined linear increment/decrement instructions
Predefined ±6 dB step log taper increment/decrement

instructions
SPI-compatible serial interface
Wiper settings and EEMEM readback
3 V to 5 V single-supply operation
±2.5 V dual-supply operation
14 bytes of general-purpose user EEMEM
Permanent memory write protection
100-year typical data retention (T

APPLICATIONS

Mechanical potentiometer replacement
Instrumentation: gain and offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, and time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration

= 55°C)

A

CS

CLK

SDI

DO

PR

WP

RDY

FUNCTIONAL BLOCK DIAGRAM

DD

V

SS

AD5232

ADDR

DECODE

SERIAL

INTERFACE

POWER-ON

RESET

EEMEM

CONTROL

GND

RDAC1

REGISTER

EEMEM1

RDAC2

REGISTER

EEMEM2

14 BYTES

USER

EEMEM

Figure 1.

AD5232

A1

W1

RDAC1

RDAC2

B1

A2

W2

B2

02618-001

GENERAL DESCRIPTION

The AD5232 device provides a nonvolatile, dual-channel,
digitally controlled variable resistor (VR) with 256-position
resolution. This device performs the same electronic adjustment
function as a mechanical potentiometer with enhanced resolution,
solid state reliability, and superior low temperature coefficient
performance. The versatile programming of the AD5232, per­ormed via a microcontroller, allows multiple modes of operation
and adjustment.

In the direct program mode, a predetermined setting of the RDAC
registers (RDAC1 and RDAC2) can be loaded directly from the
microcontroller. Another important mode of operation allows
the RDACx register to be refreshed with the setting previously
stored in the corresponding EEMEM register (EEMEM1 and
EEMEM2). When changes are made to the RDACx register to
establish a new wiper position, the value of the setting can be
saved into the EEMEMx register by executing an EEMEM save
operation. After the settings are saved in the EEMEMx register,
these values are automatically transferred to the RDACx register
to set the wiper position at system power-on. Such operation is
enabled by the internal preset strobe. The preset strobe can also
be accessed externally.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the proper ty of their respec tive owners.

All internal register contents can be read via the serial data
output (SDO). This includes the RDAC1 and RDAC2 registers,
the corresponding nonvolatile EEMEM1 and EEMEM2 registers,
and the 14 spare USER EEMEM registers that are available for
constant storage.

The basic mode of adjustment is the increment and decrement
command instructions that control the wiper position setting
register (RDACx). An internal scratch pad RDACx register can
be moved up or down one step of the nominal resistance between
Terminal A and Terminal B. This step adjustment linearly changes
the wiper to Terminal B resistance (R
of the device’s end-to-end resistance (R

) by one position segment

WB

). For exponential/

AB

logarithmic changes in wiper setting, a left/right shift command
instruction adjusts the levels in ±6 dB steps, which can be useful
for audio and light alarm applications.

The AD5232 is available in a thin, 16-lead TSSOP package.
All parts are guaranteed to operate over the extended industrial
temperature range of −40°C to +85°C. An evaluation board, the
EVAL-AD5232-10EBZ, is available.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2001–2011 Analog Devices, Inc. All rights reserved.

AD5232 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions .. 3

Interface Timing Characteristics................................................ 5

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Test Circuits..................................................................................... 12

Theory of Operation ...................................................................... 14

Scratch Pad and EEMEM Programming................................. 14

Basic Operation .......................................................................... 14

EEMEM Protection.................................................................... 14

Digital Input/Output Configuration........................................ 14

Serial Data Interface................................................................... 15

Daisy-Chaining Operation........................................................ 15

Advanced Control Modes ......................................................... 17

Using Additional Internal, Nonvolatile EEMEM................... 18

Terminal Voltage Operating Range ......................................... 18

Detailed Potentiometer Operation .......................................... 18

Programming the Variable Resistor......................................... 19

Programming the Potentiometer Divider............................... 20

Operation from Dual Supplies ................................................. 20

Application Programming Examples ...................................... 20

Equipment Customer Start-up Sequence

for a PCB Calibrated Unit with Protected Settings................ 21

Flash/EEMEM Reliability.......................................................... 21

Evaluation Board........................................................................ 21

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 22



REVISION HISTORY

09/11—Rev. A to Rev. B

Change to Resistor Noise Voltage Parameter in Table 1.............. 4

10/09—Rev. 0 to Rev. A

Updated Format ..................................................................Universal

Changes to Data Sheet Title............................................................ 1

Changes to Features Section............................................................ 1

Changes to Applications Section .................................................... 1

Change to Wiper Resistance Parameter, Table 1 .......................... 3

Changes to

Changes to Figure 2 and Figure 3....................................................6

Changes to Figure 24...................................................................... 12

Added Figure 32 ............................................................................. 13

Changes to Serial Data Interface Section .................................... 15

Changes to Programming the Variable Resistor Section .......... 19

Changes to Ordering Guide.......................................................... 22

10/01—Revision 0: Initial Version

CS

Rise to RDY Fall Time Parameter, Table 2 ..........5

Rev. B | Page 2 of 24

Data Sheet AD5232

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = 3 V ± 10% or 5 V ± 10% and VSS = 0 V, VA = +VDD, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS,

RHEOSTAT MODE

Resistor Differential Nonlinearity2 R-DNL RWB, VA = NC −1 ±1/2 +1 LSB

Resistor Nonlinearity2 R-INL RWB, VA = NC −0.4 +0.4 % FS

Nominal Resistor Tolerance ∆RAB −40 +20 %

Resistance Temperature Coefficient ∆RAB/∆T 600 ppm/°C

Wiper Resistance RW IW = 100 μA, VDD = 5.5 V, code = 0x1E 50 100 Ω

I
POTENTIOMETER DIVIDER MODES

Resolution N 8 Bits

Differential Nonlinearity3 DNL −1 ±1/2 +1 LSB

Integral Nonlinearity3 INL −0.4 +0.4 % FS

Voltage Divider Temperature

Coefficient
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Terminal Voltage Range4 VA, VB, VW VSS VDD V
Capacitance Ax, Bx5 C
Capacitance Wx5 C
Common-Mode Leakage Current

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH With respect to GND, VDD = 5 V 2.4 V
Input Logic Low VIL With respect to GND, VDD = 5 V 0.8 V
Input Logic High VIH With respect to GND, VDD= 3 V 2.1 V
Input Logic Low VIL With respect to GND, VDD = 3 V 0.6 V
Input Logic High VIH With respect to GND, VDD = +2.5 V, VSS = −2.5 V 2.0 V
Input Logic Low VIL With respect to GND, VDD = +2.5 V, VSS = −2.5 V 0.5 V
Output Logic High (SDO and RDY) VOH R
Output Logic Low VOL IOL = 1.6 mA, V
Input Current IIL VIN = 0 V or VDD ±2.5 μA
Input Capacitance5 CIL 4 pF

POWER SUPPLIES

Single-Supply Power Range VDD V
Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD VIH = VDD or VIL = GND 3.5 10 μA
Programming Mode Current I
Read Mode Current7 I
Negative Supply Current ISS VIH = VDD or VIL = GND,
V
Power Dissipation8 P
Power Supply Sensitivity5 PSS ∆VDD = 5 V ± 10% 0.002 0.01 %/%

Specifications apply to all VRs

= 100 μA, VDD = 3 V, code = 0x1E 200 Ω

W

∆V

/ΔT Code = half scale 15 ppm/°C

W

Code = full scale −3 0 % FS

WFSE

Code = zero scale 0 3 % FS

WZSE

, CB f = 1 MHz, measured to GND, code = half-scale 45 pF

A

f = 1 MHz, measured to GND, code = half scale 60 pF

5, 6

W

ICM VW = VDD/2 0.01 1 μA

= 2.2 kΩ to 5 V 4.9 V

PULL-UP

= 5 V 0.4 V

LOGI C

= 0 V 2.7 5.5 V

SS

VIH = VDD or VIL = GND 35 mA

DD(PG)

VIH = VDD or VIL = GND 0.9 3 9 mA

DD(XFR)

= +2.5 V, VSS = −2.5 V 3.5 10 μA

DD

VIH = VDD or VIL = GND 0.018 0.05 mW

DISS

Rev. B | Page 3 of 24

AD5232 Data Sheet

Parameter Symbol Conditions Min Typ1 Max Unit

DYNAMIC CHARACTERISTICS

Bandwidth −3 dB, BW_10kΩ, R = 10 kΩ 500 kHz
Total Harmonic Distortion THDw VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ 0.022 %
V
VW Settling Time tS V
V
for RAB = 10 kΩ/50 kΩ/100 kΩ
Resistor Noise Voltage e
Crosstalk (CW1/CW2) CT V
adjacent VR making full-scale code change
Analog Crosstalk (CW1/CW2) CTA V
5 V p-p @ f = 10 kHz; Code1 = 0x80; Code2 = 0xFF

FLASH/EE MEMORY RELIABILITY

Endurance10 100
Data Retention11 100

1

Typical parameters represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW ~ 50 μA @ VDD = 2.7 V and IW ~
400 μA @ VDD = 5 V for the RAB = 10 kΩ version, IW ~ 50 μA for the RAB = 50 kΩ version, and IW ~ 25 μA for the RAB = 100 kΩ version (see Figure 22).

3

INL and DNL are measured at VW with the RDACx configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = VSS.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions (see Figure 23).

4

The A, B, and W resistor terminals have no limitations on polarity with respect to each other. Dual supply operation enables ground-referenced bipolar signal

adjustment.

5

Guaranteed by design; not subject to production test.

6

Common-mode leakage current is a measure of the dc leakage from any A, B, or W terminal to a common-mode bias level of VDD/2.

7

Transfer (XFR) mode current is not continuous. Current is consumed while the EEMEMx locations are read and transferred to the RDACx register (see Figure 13).

8

P

is calculated from (IDD × VDD) + (ISS × VSS).

DISS

9

All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V, unless otherwise noted.

10

Endurance is qualified to 100,000 cycles per JEDEC Std. 22, Method A117 and measured at −40°C, +25°C, and +85°C. Typical endurance at +25°C is 700,000 cycles.

11

The retention lifetime equivalent at junction temperature (T

derates with junction temperature as shown in Figure 44 in the Flash/EEMEM Reliability section. The AD5232 contains 9,646 transistors. Die size = 69 mil × 115 mil,
7,993 sq. mil.

5, 9

= 1 V rms, VB = 0 V, f = 1 kHz, RAB = 50 kΩ, 100 kΩ 0.045 %

A

= 5 V, VSS = 0 V, VA = VDD, VB = 0 V, 0.65/3/6 μs

DD

= 0.50% error band, Code 0x00 to Code 0x80

W

RWB = 5 kΩ, f= 1 kHz 9 nV/√Hz

N_WB

= VDD, VB = 0 V, measure VW with −5 nV-sec

A

= VDD, VB1 = 0 V, measure VW1 with VW2 = −70 dB

A1

) = 55°C, as per JEDEC Std. 22, Method A117. Retention lifetime, based on an activation energy of 0.6 eV,

J

kCycles
Yea r s

Rev. B | Page 4 of 24

Data Sheet AD5232

INTERFACE TIMING CHARACTERISTICS

All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and are timed from a voltage level of 1.5 V. Switching
characteristics are measured using both V

= 3 V and VDD = 5 V.

DD

Table 2.

Parameter

Clock Cycle Time (t
CS Setup Time
CLK Shutdown Time to CS Rise

1, 2

Symbol Conditions Min Typ3 Max Unit

) t1 20 ns

CYC

t

10 ns

2

t

1 t

3

CYC

Input Clock Pulse Width t4, t5 Clock level high or low 10 ns
Data Setup Time t6 From positive CLK transition 5 ns
Data Hold Time t7 From positive CLK transition 5 ns

t

CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay4 t

CLK to SDO Data Hold Time t11 R
CS High Pulse Width5
CS High to CS High5
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Store/Read EEMEM Time6 t

40 ns

8

t

50 ns

9

R

10

t

12

t

4 t

13

t

0 ns

14

t

0.15 0.3 ms

15

16

= 2.2 kΩ, CL < 20 pF 50 ns

P

= 2.2 kΩ, CL < 20 pF 0 ns

P

Applies to Command Instruction 2, Command

10 ns

25 ms

CYC

Instruction 3, and Command Instruction 9

t

CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous) t
Preset Response Time to RDY High t

1

Guaranteed by design; not subject to production test.

2

See the Timing Diagrams section for the location of measured values.

3

Typicals represent average readings at 25°C and VDD = 5 V.

4

Propagation delay depends on the value of VDD, R

5

Valid for commands that do not activate the RDY pin.

6

RDY pin low only for Command Instruction 2, Command Instruction 3, Command Instruction 8, Command Instruction 9, Command Instruction 10, and the PR hardware pulse:

CMD_8 ~ 1 ms, CMD_9 = CMD_10 ~ 0.12 ms, and CMD_2 = CMD_3 ~ 20 ms. Device operation at TA = −40°C and VDD < 3 V extends the save time to 35 ms.

10 ns

17

Not shown in timing diagram 50 ns

PRW

PRESP

PULL-UP

, and CL.

pulsed low to refresh wiper positions

PR

70 μs

Rev. B | Page 5 of 24

AD5232 Data Sheet

Timing Diagrams

CPHA = 1

CS

t

B0

(LSB)

3

B0

(LSB)

t

t

CLK

CPOL = 1

HIGH
OR LOW

SDI

SDO

t

14

RDY

NOTES

1. B24 IS AN EXT RA BIT THAT IS NOT DEF INED, BUT I T IS USUAL LY THE LSB OF THE CHARACT ER THAT WAS PREVIOUSL Y TRANSMIT TED.

2. THE CPOL = 1 MICROCO NTROLL ER COMMAND ALI GNS THE I NCOMING DAT A TO THE POSITI VE EDGE O F THE CLOCK.

2

t

8

B16*

1

t

B15 B0

5

t

4

t

7

t

6

B15

(MSB)

t

10

B15

(MSB)

t

11

t

12

t

13

t

17

HIGH
OR LOW

t

9

t

15

t

16

02618-002

Figure 2. CPHA = 1

CPHA = 0

CLK

CPOL = 0

SDI

CS

HIGH
OR LOW

B15

(MSB)

t

2

B15

(MSB IN)

t

1

t

B15 B0

5

t

4

t

7

t

6

B0

(LSB)

B0

(LSB)

t

3

t

12

t

13

t

17

HIGH
OR LOW

t

8

SDO

t

14

RDY

NOTES

1. THIS EXTRA BIT IS NOT DEFI NED, BUT IT IS USUALL Y THE MSB OF THE CHARACTER T HAT WAS JUST RECEIVED.

2. THE CPOL = 0 MICROCO NTROLL ER COMMAND ALI GNS THE I NCOMING DAT A TO THE POSITI VE EDGE O F THE CLOCK.

B15

(MSB OUT)

t

10

t

11

B0

(LSB)

*

Figure 3. CPHA = 0

Rev. B | Page 6 of 24

t

9

t

15

t

16

02618-003

Data Sheet AD5232

ABSOLUTE MAXIMUM RATINGS

= 25°C, unless otherwise noted.

A

Table 3.

Parameter Rating

VDD to GND −0.3 V, +7 V
VSS to GND +0.3 V, −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS − 0.3 V, VDD + 0.3 V
AX − BX, AX − WX, BX − WX

Intermittent

1

±20 mA

Continuous ±2 mA
Digital Inputs and Output Voltage to GND −0.3 V, VDD + 0.3 V
Operating Temperature Range2 −40°C to +85°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C
Package Power Dissipation (TJ max − TA)/θJA

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Includes programming of nonvolatile memory.

T

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA θ

Unit

JC

16-Lead TSSOP (RU-16) 150 28 °C/W

ESD CAUTION

Rev. B | Page 7 of 24

AD5232 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK

SDI

SDO

GND

V

W1

SS

A1

B1

1

2

3

AD5232

TOP VIEW

4

(Not to Scal e)

5

6

7

8

16

RDY

15

CS

14

PR

13

WP

12

V

DD

11

A2

10

W2

9

B2

02618-004

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin
No. Mnemonic Description

1 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
2 SDI Serial Data Input. The MSB is loaded first.
3 SDO

Serial Data Output. This open-drain output requires an external pull-up resistor. Command Instruction 9 and Command
Instruction 10 activate the SDO output (see Table 8). Other commands shift out the previously loaded SDI bit pattern

delayed by 16 clock pulses, allowing daisy-chain operation of multiple packages.
4 GND Ground, Logic Ground Reference.
5 VSS Negative Power Supply. Connect to 0 V for single-supply applications.
6 A1 Terminal A of RDAC1.
7 W1 Wiper Terminal W of RDAC1, ADDR (RDAC1) = 0x0.
8 B1 Terminal B of RDAC1.
9 B2 Terminal B of RDAC2.
10 W2 Wiper Terminal W of RDAC2, ADDR (RDAC2) = 0x1.
11 A2 Terminal A of RDAC2.
12 VDD Positive Power Supply.
13

Write Protect. When active low, WP prevents any changes to the present register contents, except PR, Command

WP

Instruction 1, and Command Instruction 8, which refresh the RDACx register from EEMEM. Execute an NOP instruction

14

(Command Instruction 0) before returning WP

Hardware Override Preset. Refreshes the scratch pad register with current contents of the EEMEMx register. Factory

PR

to logic high.

default loads Midscale 0x80 until EEMEMx is loaded with a new value by the user (PR

transition).
15

16 RDY

Serial Register Chip Select, Active Low. Serial register operation takes place when CS returns to logic high.

CS

Ready. This active-high, open-drain output requires a pull-up resistor. Identifies completion of Command Instruction 2,

Command Instruction 3, Command Instruction 8, Command Instruction 9, Command Instruction 10, and PR

is activated at the logic high

.

Rev. B | Page 8 of 24