ANALOG DEVICES AD5175 Service Manual

Single-Channel, 1024-Position, Digital Rheostat

V

W

with I

2

C Interface and 50-TP Memory

FEATURES

Single-channel, 1024-position resolution
10 kΩ nominal resistance
50-times programmable (50-TP) wiper memory
Rheostat mode temperature coefficient: 35 ppm/°C

2.7 V to 5.5 V single-supply operation
±2.5 V to ±2.75 V dual-supply operation for ac or bipolar

operations

2

I

C-compatible interface
Wiper setting and memory readback
Power on refreshed from memory
Resistor tolerance stored in memory
Thin LFCSP, 10-lead, 3 mm × 3 mm × 0.8 mm package
Compact MSOP, 10-lead 3 mm × 4.9 mm × 1.1 mm package

APPLICATIONS

Mechanical rheostat replacements
Op-amp: variable gain control
Instrumentation: gain, offset adjustment
Programmable voltage to current conversions
Programmable filters, delays, time constants
Programmable power supply
Sensor calibration

SCL

SDA

ADDR

RESET

AD5175

FUNCTIONAL BLOCK DIAGRAM

DD

POWER-ON

RESET

I2C

SERIAL

INTERFACE

V

SS

REGISTER

10

50-TP

MEMORY

BLOCK

EXT_CAP GND

Figure 1.

AD5175

RDAC

A

08719-001

GENERAL DESCRIPTION

The AD5175 is a single-channel, 1024-position digital rheostat
that combines industry leading variable resistor performance
with nonvolatile memory (NVM) in a compact package.

This device supports both dual-supply operation at ±2.5 V to
±2.75 V and single-supply operation at 2.7 V to 5.5 V, and offers
50-times programmable (50-TP) memory.

The AD5175 device wiper settings are controllable through the

2

I

C–compatible digital interface. Unlimited adjustments are
allowed before programming the resistance value into the
50-TP memory. The AD5175 does not require any external

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

voltage supply to facilitate fuse blow and there are 50 oppor­tunities for permanent programming. During 50-TP activation,
a permanent blow fuse command freezes the resistance position
(analogous to placing epoxy on a mechanical rheostat).

The AD5175 is available in a 3 mm × 3mm 10-lead LFCSP
package and in a 10-lead MSOP package. The part is guaranteed
to operate over the extended industrial temperature range of

−40°C to +125°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

AD5175

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics ............................................................. 3

Interface Timing Specifications .................................................. 4

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Test Circuits ..................................................................................... 11

Theory of Operation ...................................................................... 12

Serial Data Interface ................................................................... 12

Shift Register ............................................................................... 12

Write Operation.......................................................................... 13

Read Operation........................................................................... 15

RDAC Register ............................................................................ 16

50-TP Memory Block ................................................................ 16

Write Protection ......................................................................... 16

50-TP Memory Write-Acknowledge Polling .......................... 18

Reset ............................................................................................. 18

Shutdown Mode ......................................................................... 18

RDAC Architecture .................................................................... 18

Programming the Variable Resistor ......................................... 18

EXT_CAP Capacitor .................................................................. 19

Terminal Voltage Operating Range ......................................... 19

Power-Up Sequence ................................................................... 19

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

7/10—Rev. 0 to Rev. A

Changes to Ordering Guide .......................................................... 20

3/10—Revision 0: Initial Version

Rev. A | Page 2 of 20

AD5175

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution 10 Bits
Resistor Integral Nonlinearity

|VDD − VSS| = 3.3 V to 3.6 V −1 +1.5 LSB

|VDD − VSS| = 2.7 V to 3.3 V −2.5 +2.5 LSB
Resistor Differential Nonlinearity2 R-DNL
Nominal Resistor Tolerance ±15 %
Resistance Temperature Coefficient
Wiper Resistance Code = zero scale 35 70 Ω

RESISTOR TERMINALS

Terminal Voltage Range
Capacitance A4 f = 1 MHz, measured to GND, code = half scale 90 pF
Capacitance W4 f = 1 MHz, measured to GND, code = half scale 40 pF
Common-Mode Leakage Current4 V

DIGITAL INPUTS

Input Logic4

High V

Low V
Input Current IIN ±1 µA
Input Capacitance4 C

DIGITAL OUTPUT

Output Voltage4

High VOH R

Low VOL R
V
V
Tristate Leakage Current −1 +1 µA
Output Capacitance4 5 pF

POWER SUPPLIES

Single-Supply Power Range VSS = 0 V 2.7 5.5 V
Dual-Supply Power Range ±2.5 ±2.75 V
Supply Current

Positive IDD 1 µA

Negative ISS −1 µA
50-TP Store Current

4, 7

Positive I

Negative I
50-TP Read Current

4, 8

Positive I

Negative I
Power Dissipation9 P
Power Supply Rejection Ratio4 PSRR ∆VDD/∆VSS = ±5 V ± 10% −50 −55 dB

2, 3

R-INL |VDD − VSS| = 3.6 V to 5.5 V −1 +1 LSB

−1 +1 LSB

V

SS

− 0.1 V

DD

V

DD

4, 5

Code = full scale 35 ppm/°C

4, 6

V

V

TERM

2.0 V

INH

0.8 V

INL

5 pF

IN

= VW 50 nA

A

= 2.2 kΩ to VDD V

PULL_UP

= 2.2 kΩ to VDD

PULL_UP

= 2.7 V to 5.5 V, VSS = 0 V 0.4 V

DD

= 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V 0.6 V

DD

DD_OTP_STORE

SS_OTP_STORE

4 mA

−4 mA

DD_OTP_READ

SS_OTP_READ

DISS

500 µA

−500 µA

V

= VDD or VIL = GND 5.5 µW

IH

Rev. A | Page 3 of 20

AD5175

Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit

DYNAMIC CHARACTERISTICS

Bandwidth −3 dB, RAW = 5 kΩ, Terminal W, see Figure 23 700 kHz
Total Harmonic Distortion VA = 1 V rms, f = 1 kHz, RAW = 5 kΩ −90 dB
Resistor Noise Density RWB = 5 kΩ, TA = 25°C, f = 10 kHz 13 nV/√Hz

1

Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from the ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions.

3

The maximum current in each code is defined by IAW = (VDD − 1)/RAW.

4

Guaranteed by design and not subject to production test.

5

See Figure 8 for more details.

6

Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar

signal adjustment.

7

Different from operating current; the supply current for the fuse program lasts approximately 55 ms.

8

Different from operating current; the supply current for the fuse read lasts approximately 500 ns.

9

P

is calculated from (IDD × VDD) + (ISS × VSS).

DISS

10

All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V.

INTERFACE TIMING SPECIFICATIONS

VDD = 2.7 V to 5.5 V; all specifications T

Table 2.

Limit at T
Parameter Conditions1 Min Max Unit Description

2

f

Standard mode 100 kHz Serial clock frequency

SCL

Fast mode 400 kHz Serial clock frequency
t1 Standard mode 4 µs t
Fast mode 0.6 µs t
t2 Standard mode 4.7 µs t
Fast mode 1.3 µs t
t3 Standard mode 250 ns t
Fast mode 100 ns t
t4 Standard mode 0 3.45 µs t
Fast mode 0 0.9 µs t
t5 Standard mode 4.7 µs t
Fast mode 0.6 µs t
t6 Standard mode 4 µs t
Fast mode 0.6 µs t
High speed mode 160 ns t
t7 Standard mode 4.7 µs t
Fast mode 1.3 µs t
t8 Standard mode 4 µs t
Fast mode 0.6 µs t
t9 Standard mode 1000 ns t
Fast mode 300 ns t
t10 Standard mode 300 ns t
Fast mode 300 ns t
t11 Standard mode 1000 ns t
Fast mode 300 ns t
t

Standard mode 1000 ns

11A

Fast mode 300 ns

t12 Standard mode 300 ns t
Fast mode 300 ns t
t13

3

t

Fast mode 0 50 ns Pulse width of the spike is suppressed

SP

4, 5

t

500 ns Command execute time

EXEC

RESET

4, 10

MIN

to T

, unless otherwise noted.

MAX

, T

MIN

MAX

, SCL high time

HIGH

, SCL high time

HIGH

, SCL low time

LOW

, SCL low time

LOW

, data setup time

SU;DAT

, data setup time

SU;DAT

, data hold time

HD;DAT

, data hold time

HD;DAT

, set-up time for a repeated start condition

SU;STA

set-up time for a repeated start condition

SU;STA,

, hold time (repeated) start condition

HD;STA

, hold time (repeated) start condition

HD;STA

, hold time (repeated) start condition

HD;STA

, bus free time between a stop and a start condition

BUF

, bus free time between a stop and a start condition

BUF

, setup time for a stop condition

SU;STO

, setup time for a stop condition

SU;STO

, rise time of the SDA signal

RDA

, rise time of the SDA signal

RDA

, fall time of the SDA signal

FDA

, fall time of the SDA signal

FDA

, rise time of the SCL signal

RCL

, rise time of the SCL signal

RCL

, rise time of the SCL signal after a repeated start condition

t

RCL1

and after an acknowledge bit

, rise time of the SCL signal after a repeated start condition

t

RCL1

and after an acknowledge bit

, fall time of the SCL signal

FCL

, fall time of the SCL signal

FCL

pulse time

20 ns

Rev. A | Page 4 of 20

Minimum RESET low time

AD5175

Limit at T
Parameter Conditions1 Min Max Unit Description

t

RDAC_R-PERF

t

RDAC_NORMAL

t

MEMORY_READ

t

MEMORY_PROGRAM

t

RESET

t

POWER-UP

1

Maximum bus capacitance is limited to 400 pF.

2

The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior

of the part.

3

Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.

4

Refer to t

5

Refer to t

6

Maximum time after VDD − VSS is equal to 2.5 V.

2 µs RDAC register write command execute time (R-Perf mode)

600 ns RDAC register write command execute time (normal mode)

6 µs Memory readback execute time

350 ms Memory program time

600 µs Reset 50-TP restore time

6

2 ms Power-on 50-TP restore time

RDAC_R-PERF

MEMORY_READ

and t

and

for RDAC register write operations.

RDAC_NORMAL

t

MEMORY_PROGRAM

for memory commands operations.

Shift Register and Timing Diagrams

, T

MIN

MAX

DB9 (MSB) DB0 (LSB)

C3

0 0

C2

CONTROL BI T S

D9

C0 C1

D7

D8

D6 D5

DATA BITS

D4

D3

D2 D1

D0

8719-003

Figure 2. Shift Register Content

SCL

SDA

RESET

t

11

t

2

t

6

t

7

PS S P

t

4

t

12

t

1

t

3

Figure 3. 2-Wire I

t

6

t

5

2

C Timing Diagram

t

8

t

10

t

1

3

t

9

8719-002

Rev. A | Page 5 of 20

AD5175

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7.0 V
VSS to GND +0.3 V to −7.0 V
VDD to VSS 7 V
VA, VW to GND VSS − 0.3 V, VDD + 0.3 V
Digital Input and Output Voltage to GND −0.3 V to VDD + 0.3 V
EXT_CAP to VSS 7 V
IA, IW

Pulsed1

Frequency > 10 kHz ±6 mA/d2
Frequency ≤ 10 kHz ±6 mA/√d2

Continuous ±6 mA
Operating Temperature Range3 −40°C to +125°C
Maximum Junction Temperature

(T

Maximum)

J

150°C

Storage Temperature Range −65°C to +150°C
Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 20 sec to 40 sec
Package Power Dissipation (TJ max − TA)/θJA

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A and W terminals at a given
resistance.

2

Pulse duty factor.

3

Includes programming of 50-TP memory.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is defined by JEDEC specification JESD-51 and the value is
dependent on the test board and test environment.

Table 4. Thermal Resistance

Package Type θJA θ

10-Lead LFCSP 50 3 °C/W
10-Lead MSOP 1351 N/A °C/W

1

JEDEC 2S2P test board, still air (0 m/sec airflow).

ESD CAUTION

Unit

JC

Rev. A | Page 6 of 20

AD5175

1

2

3

4

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

10

VDD1

2

V

V

EXT_CAP

DD

A
W

SS

1

AD5175

2
3

TOP VIEW

4

(Not toScale)

5

10

9
8
7
6

ADDR

SCL
SDA
RESET
GND

A

W

V

SS

EXT_CAP

08719-004

*LEAVE FLOATING OR CONNECTED TO VSS.

AD5175

3

(EXPOSED

4
5

PAD)*

Figure 4. MSOP Pin Configuration Figure 5. LFCSP Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 VDD Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
2 A Terminal A of RDAC. VSS ≤ VA ≤ VDD.
3 W Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD.
4 VSS

Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 F ceramic capacitors
and 10 F capacitors.

5 EXT_CAP

External Capacitor. Connect a 1 µF capacitor between EXT_CAP and V

. This capacitor must have a voltage

SS

rating of ≥7 V.
6 GND Ground Pin, Logic Ground Reference.
7

Hardware Reset Pin. Refreshes the RDAC register with the contents of the 50-TP memory register. Factory

RESET

default loads midscale until the first 50-TP wiper memory location is programmed. RESET

to V

if not used.

DD

8 SDA

Serial Data Line. This pin is used in conjunction with the SCL line to clock data into or out of the 16-bit input

registers. It is a bidirectional, open-drain data line that should be pulled to the supply with an external

pull-up resistor.
9 SCL

Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 16-bit

input registers.
10 ADDR Tristate Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 6).
EPAD Exposed Pad Leave floating or connected to VSS

ADDR

9

SCL

8

SDA

7

RESET

6

GND

08719-103

is active low. Tie RESET

Rev. A | Page 7 of 20

AD5175

TYPICAL PERFORMANCE CHARACTERISTICS

0.8

0.6

0.4

0.2

INL (LSB)

–0.2

–0.4

+25°C
–40°C
+125°C

0

0.7

0.6

0.5

0.4

0.3

0.2

CURRENT (mA)

0.1

0

VDD/VSS = 5V/0V

–0.6

0 128 256 384 512 640 768 896 1023

CODE (Decimal )

Figure 6. R-INL in Normal Mode vs. Code vs. Temperature

0.4

0.3

0.2

0.1

DNL (LSB)

–0.1

–0.2

–0.3

+25°C
–40°C
+125°C

0

0 128 256 384 512 640 768 896 1023

CODE (Decimal)

Figure 7. R-DNL in Normal Mode vs. Code vs. Temperature

700

600

VDD/VSS = 5V/0V

–0.1

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

08719-014

VOLTAGE (V)

8719-038

Figure 9. Supply Current (IDD) vs. Digital Input Voltage

500

400

300

200

100

0

–100

CURRENT (nA)

–200

–300

–400

–500

–40 –30 –20 –10 0 20 30 40 50 60 70 80 90 100 11010

08719-015

ISS = 3V

TEMPERATURE (°C)

IDD = 5V

IDD = 3V

ISS = 5V

8719-018

Figure 10. Supply Current (IDD, ISS) vs. Temperature

7

6

VDD/VSS = 5V/0V

500

400

300

200

100

RHEOSTAT MO DE T E M PCO (ppm/ ° C)

0

0 128 256 384 512 640 768 896 1023

CODE (Decimal)

Figure 8. Tempco ΔRWA/ΔT vs. Code

08719-019

Rev. A | Page 8 of 20

5

(mA)

4

WA_MAX

3

2

THEORETI CAL l

1

0

0 1023850765 935680510 595340 425170 25585

CODE (Decimal )

08719-028

Figure 11. Theoretical Maximum Current vs. Code

AD5175

–

0

–5

–10

–15

–20

–25

GAIN (dB)

–30

–35

–40

–45

–50

1 10M1M100k10k1k10010

0

V

DD/VSS

CODE = HALF SCALE
f

IN

–20

NOISE BW = 22kHz

–40

–60

THD + N (dB)

–80

–100

0x200

0x100

0x080

0x040

0x020

0x010
0x008

0x004
0x002

0x001

FREQUENCY (Hz)

VDD/VSS = 5V/0V

Figure 12. Bandwidth vs. Frequency vs. Code

= ±2.5V

= 1V rms

20

VDD/VSS = 5V/0V

–25

CODE = HALF SCALE

–30

–35

–40

PSRR (dB)

–45

–50

–55

–60

10 100 1M100k10k1k

08719-031

FREQUENCY (Hz)

08719-024

Figure 15. PSRR vs. Frequency

8

7

6

VOLTAGE (V)

5

–120

10 100 1k 10k

FREQUENCY (Hz)

Figure 13. THD + N vs. Frequency

0

–20

–40

–60

THD + N (dB)

–80

–100

0.001 0.01 0.1 1

= ±2.5V

V

DD/VSS

CODE = HALF SCALE

f

= 1kHz

IN

NOISE BW = 22 kHz

AMPLITUDE ( V rms)

Figure 14. THD + N vs. Amplitude

100k

10kΩ

1M

4

0.07 0.09 0.11 0.13 0.15 0.17

08719-039

Figure 16. V

20

10

0

–10

–20

–30

–40

GLITCH AMPLITUDE (mV)

–50

–60

–70

–2 420

08719-026

TIME (Seco nds)

Waveform While Writing Fuse

EXT_CAP

TIME (µs)

VDD/VSS = ±2.5V
I

= 200µA

AW

08719-029

08719-102

Figure 17. Maximum Glitch Energy

Rev. A | Page 9 of 20

AD5175

R

1.0

0.5

0.006

0.005

0.004

VDD/VSS = 5V/0V
I

= 10µA

AW

CODE = HALF S CAL E

0.003

0.002

RESISTANCE (%)

0.001

AW

Δ

–0.001

–0.002

0

0 1000900800700600500400300200100

OPERATION AT 150°C (Hours)

08719-101

–0.5

VOLTAGE (mV)

–1.0

–1.5

0

–10 6050403020100

TIME (µs)

VDD/VSS = ±2.5V
I

= 200µA

AW

08719-100

Figure 18. Digital Feedthrough Figure 19. Long-Term Drift Accelerated Average by Burn-In

Rev. A | Page 10 of 20

AD5175

V

V

%

TEST CIRCUITS

Figure 20 to Figure 24 define the test conditions used in the Specifications section.

DUT

W

A

I

W

V

MS

08719-033

Figure 20. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

DUT

W

A

1GΩ

V

V

MS

Figure 23. Gain vs. Frequency

08719-036

CODE = 0x00

DUT

W

A

I

V

MS

Figure 21. Wiper Resistance

W

RWA=

RW =

MS

I

W

R

WA

2

08719-034

DUT

W

A

NC

+2.75V –2.75V

GND

I

CM

Figure 24. Common Leakage Current

GND

GND

NC = NO CONNECT

+2.75V
–2.75V

08719-037

+ = VDD ±10

PSRR (dB) = 20 log

I

W

V

DD

V+

W

A

V

PSS (%/%) =

MS

ΔVMS%
ΔV

DD

V

MS

V

DD

%

08719-035

Figure 22. Power Supply Sensitivity (PSS, PSRR)

Rev. A | Page 11 of 20

AD5175

THEORY OF OPERATION

The AD5175 is designed to operate as a true variable resistor for
analog signals within the terminal voltage range of V
< V

. The RDAC register contents determine the resistor wiper

DD

position. The RDAC register acts as a scratchpad register, which
allows unlimited changes of resistance settings. The RDAC
register can be programmed with any position setting using

2

the I

C interface. When a desirable wiper position is found, this
value can be stored in a 50-TP memory register. Thereafter, the
wiper position is always restored to that position for subsequent
power-up. The storing of 50-TP data takes approximately 350 ms;
during this time, the AD5175 is locked and does not acknowl­edge any new command thereby preventing any changes from
taking place. The acknowledge bit can be polled to verify that
the fuse program command is complete.

SERIAL DATA INTERFACE

The AD5175 has a 2-wire I2C-compatible serial interface.
It can be connected to an I
control of a master device; see Figure 3 for a timing diagram
of a typical write sequence.

The AD5175 supports standard (100 kHz) and fast (400 kHz)
data transfer modes. Support is not provided for 10-bit
addressing and general call addressing.

The AD5175 has a 7-bit slave address. The five MSBs are 01011
and the two LSBs are determined by the state of the ADDR pin.
The facility to make hardwired changes to ADDR allows the
user to incorporate up to three of these devices on one bus, as
outlined in Tab l e 6 .

2

C bus as a slave device under the

SS

< V

TERM

The 2-wire serial bus protocol operates as follows: The master
initiates a data transfer by establishing a start condition, which
is when a high-to-low transition on the SDA line occurs while
SCL is high. The next byte is the address byte, which consists
of the 7-bit slave address and a R/

W

bit. The slave device
corresponding to the transmitted address responds by pulling
SDA low during the ninth clock pulse (this is termed the acknowl­edge bit). At this stage, all other devices on the bus remain idle
while the selected device waits for data to be written to, or read
from, its shift register.

Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.

When all data bits have been read or written, a stop condition is
established. In write mode, the master pulls the SDA line high
during the 10

th

clock pulse to establish a stop condition. In read
mode, the master issues a no acknowledge for the ninth clock
pulse, that is, the SDA line remains high. The master then
brings the SDA line low before the 10

th

high during the 10

clock pulse to establish a stop condition.

th

clock pulse, and then

SHIFT REGISTER

For the AD5175, the shift register is 16 bits wide, as shown in
Figure 2. The 16-bit word consists of two unused bits, which
should be set to 0, followed by four control bits and 10 RDAC data
bits, and data is loaded MSB first (Bit D9). The four control bits
determine the function of the software command (Tabl e 7 ).
Figure 25 shows a timing diagram of a typical AD5175 write
sequence.

The command bits (Cx) control the operation of the digital
potentiometer and the internal 50-TP memory. The data bits
(Dx) are the values that are loaded into the decoded register.

Table 6. Device Address Selection

ADDR Pin A1 A0 7-Bit I2C Device Address

GND 1 1 0101111
VDD 0 0 0101100
NC (No Connection)1 1 0 0101110

1

Not available in bipolar mode. VSS < 0 V.

Rev. A | Page 12 of 20

AD5175

WRITE OPERATION

It is possible to write data for the RDAC register or the control
register. When writing to the AD5175, the user must begin with
a start command followed by an address byte (R/
which the AD5175 acknowledges that it is prepared to receive
data by pulling SDA low.

W

= 0), after

Two bytes of data are then written to the RDAC, the most
significant byte followed by the least significant byte; both
of these data bytes are acknowledged by the AD5175. A stop
condition follows. The write operations for the AD5175 are
shown in Figure 25.

A repeated write function gives the user flexibility to update the
device a number of times after addressing the part only once, as
shown in Figure 26.

SCL

SDA

START BY

MASTER

19

1

0

011A1A0 00C3C2

FRAME 1

SERIAL BUS ADDRESS BYTE

SCL (CONTINUED)

SDA (CONTINUED)

R/W

ACK. BY
AD5175

MOST SI GNIFICANT DATA BYTE

99

1

D7 D6 D5 D4 D3 D2 D1 D0

LEAST SIGNIFICANT DATA BYTE

C1 C0

FRAME 2

FRAME 3

D9 D8

ACK. BY

AD5175

Figure 25. Write Command

91

ACK. BY

AD5175

STOP BY
MASTER

8719-005

Rev. A | Page 13 of 20

AD5175

SDA

SCL

START BY

MASTER

19

1

0

0 1 1 A1 A0 R/W 0 0 C3 C2 C1 C0 D9 D8

ACK. BY

FRAME 1

SERIAL BUS ADDRESS BYTE

SCL (CONTINUED)

SDA (CONTINUED)

SCL (CONTINUED)

SDA (CONTINUED)

SCL (CONTINUED)

AD5175

MOST SIGNIFICANT DATA BYTE

99

1

D7 D6 D5 D4 D3 D2 D1 D0

LEAST SIGNIFICANT DATA BYTE

199

0 0 C3 C2 C1 C0 D9 D8

MOST SI GNIFICANT DATA BYTE

199

FRAME 2

FRAME 3

FRAME 4

ACK. BY

AD5175

ACK. BY

AD5175

91

ACK. BY

AD5175

SDA (CONTINUED)

D7 D6 D5 D4 D3 D2 D1 D0

LEAST SIGNIFICANT DATA BYTE

FRAME 5

ACK. BY

AD5175

STOP BY
MASTER

08719-006

Figure 26. Multiple Write

Rev. A | Page 14 of 20

AD5175

A

A

READ OPERATION

When reading data back from the AD5175, the user must first
issue a readback command to the device, this begins with a start
command followed by an address byte (R/

W

= 0), after which
the AD5175 acknowledges that it is prepared to receive data by
pulling SDA low.

Two bytes of data are then written to the AD5175, the most
significant byte followed by the least significant byte; both
of these data bytes are acknowledged by the AD5175. A stop
condition follows. These bytes contain the read instruction,

19

SCL

which enables readback of the RDAC register, 50-TP memory,
or the control register. The user can then read back the data
beginning with a start command followed by an address byte

W

(R/

= 1), after which the device acknowledges that it is
prepared to transmit data by pulling SDA low. Two bytes of
data are then read from the device, as shown in . A

Figure 27
stop condition follows. If the master does not acknowledge the
first byte, the second byte is not transmitted by the AD5175.

91

SD

START BY

MASTER

SCL

SD

START BY

MASTER

1

0

19

0

0 1 1 A1 A0 R/W 0 0 C3 C2 C1 C0 D9 D8

ACK. BY

FRAME 1

SERIAL BUS ADDRESS BY TE

SCL (CONTINUED)

SDA (CONTINUED)

1

0 1 1 A1 A0 R/W 0 0 X X X X D9 D8

FRAME 1

SERIAL BUS ADDRESS BYTE

SCL (CONTINUED)

SDA (CONTINUED)

AD5175

MOST SI GNIFICANT DATA BYTE

1

99

D7 D6 D5 D4 D3 D2 D1 D0

LEAST SIGNIFICANT DATA BYTE

ACK. BY

AD5175

MOST SI GNIFICANT DATA BYTE

99

1

D7 D6 D5 D4 D3 D2 D1 D0

LEAST SIGNIFICANT DATA BYTE

FRAME 2

FRAME 3

FRAME 2

FRAME 3

ACK. BY

AD5175

NO ACK. BY

MASTER

Figure 27. Read Command

ACK. BY
AD5175

STOP BY
MASTER

91

ACK. BY
MASTER

STOP BY
MASTER

08719-007

Rev. A | Page 15 of 20

AD5175

RDAC REGISTER

The RDAC register directly controls the position of the digital
rheostat wiper. For example, when the RDAC register is loaded
with all 0s, the wiper is connected to Terminal A of the variable
resistor. It is possible to both write to and read from the RDAC
register using the I
logic register; there is no restriction on the number of changes
allowed.

50-TP MEMORY BLOCK

The AD5175 contains an array of 50-TP programmable
memory registers, which allow the wiper position to be pro­grammed up to 50 times. Tab l e 1 1 shows the memory map.
Command 3 in Tab l e 7 programs the contents of the RDAC
register to memory. The first address to be programmed is
Location 0x01, see Tab l e 1 1 , and the AD5175 increments the
50-TP memory address for each subsequent program until
the memory is full. Programming data to 50-TP consumes
approximately 4 mA for 55 ms, and takes approximately
350 ms to complete, during which time the shift register is
locked preventing any changes from taking place. Bit C2 of
the control register in Ta b le 1 0 can be polled to verify that the
fuse program command was successful. No change in supply
voltage is required to program the 50-TP memory; however, a
1 μF capacitor on the EXT_CAP pin is required as shown in
Figure 29.

2

C interface. The RDAC register is a standard

Prior to 50-TP activation, the AD5175 presets to midscale on
power-up. It is possible to read back the contents of any of the
50-TP memory registers through the I

2

C interface by using
Command 5 in Tab l e 7 . The lower six LSB bits, D0 to D5 of
the data byte, select which memory location is to be read back.
A binary encoded version address of the most recently pro­grammed wiper memory location can be read back using
Command 6 in Tab l e 7 . This can be used to monitor the
spare memory status of the 50-TP memory block.

WRITE PROTECTION

On power-up, serial data input register write commands for
both the RDAC register and the 50-TP memory registers are
disabled. The RDAC write protect bit (Bit C1) of the control
register (see Ta b le 9 and Tabl e 10 ), is set to 0 by default. This
disables any change of the RDAC register content regardless
of the software commands, except that the RDAC register can
be refreshed from the 50-TP memory using the software reset,
Command 4, or through the hardware by the
enable programming of the variable resistor wiper position
(programming the RDAC register), the write protect bit
(Bit C1) of the control register must first be programmed.
This is accomplished by loading the serial data input register
with Command 7 (see ). To enable programming of the

Table 7
50-TP memory block, Bit C0 of the control register, which is set
to 0 by default, must first be set to 1.

RESET

pin. To

Table 7. Command Operation Truth Table

1

Command
Number

0 0 0 0 0 X X X X X X X X X X NOP: do nothing.
1 0 0 0 1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D

2 0 0 1 0 X X X X X X X X X X Read contents of RDAC wiper register.
3 0 0 1 1 X X X X X X X X X X

4 0 1 0 0 X X X X X X X X X X

52 0 1 0 1 X X X X D5 D4 D3 D2 D1 D0

6 0 1 1 0 X X X X X X X X X X

73 0 1 1 1 X X X X X X X X D1 D0

8 1 0 0 0 X X X X X X X X X X Read contents of the control register.
9 1 0 0 1 X X X X X X X X X D0 Software shutdown.
D0 = 0; normal mode.
D0 = 1; shutdown mode.

1

X is don’t care.

2

See Table 11 for the 50-TP memory map.

3

See Table 10 for bit details.

Command[DB13:DB10] Data[DB9:DB0]

C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Operation

Write contents of serial register data
to RDAC.

Store wiper setting: store RDAC setting
to 50-TP.

Software reset: refresh RDAC with the
last 50-TP memory stored value.

Read contents of 50-TP from the SDO
output in the next frame.

Read address of the last 50-TP
programmed memory location.

Write contents of the serial register data
to the control register.

Rev. A | Page 16 of 20

AD5175

Table 8. Write and Read to RDAC and 50-TP Memory

DIN SDO1 Action

0x1C03 0xXXXX Enable update of wiper position and 50-TP memory contents through digital interface.
0x0500 0x1C03 Write 0x100 to the RDAC register, wiper moves to ¼ full-scale position.
0x0800 0x0500 Prepare data read from RDAC register.
0x0C00 0x100

0x1800 0x0C00 Prepare data read of the last programmed 50-TP memory monitor location.
0x0000 0xXX19

0x1419 0x0000 Prepares data read from Memory Location 0x19.
0x2000 0x0100

0x0000 0xXXXX

1

X is don’t care.

Table 9. Control Register Bit Map

DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 C2 0 C1 C0

Table 10. Control Register Description

Bit Name Description

C0 50-TP program enable
0 = 50-TP program disabled (default)
1 = enable device for 50-TP program
C1 RDAC register write protect
0 = wiper position frozen to value in OTP memory (default)1
1 = allow update of wiper position through a digital interface
C2 50-TP memory program success bit
0 = fuse program command unsuccessful (default)
1 = fuse program command successful

1

Wiper position is frozen to the last value programmed in the 50-TP memory. Wiper freezes to midscale if 50-TP memory has not been previously programmed.

Table 11. Memory Map

Command Number

5 X X X 0 0 0 0 0 0 0 Reserved

1

X is don’t care.

Stores RDAC register content into 50-TP memory. 16-bit word appears out of SDO, where the last 10-bits contain the
contents of the RDAC Register 0x100.

NOP Instruction 0 sends a 16-bit word out of SDO, where the six LSBs (that is, the last 6 bits) contain the binary address
of the last programmed 50-TP memory location, for example, 0x19 (see Table 11).

Prepare data read from the control register. Sends a 16-bit word out of SDO, where the last 10-bits contain the contents
of Memory Location 0x19.

NOP Instruction 0 sends a 16-bit word out of SDO, where the last four bits contain the contents of the control register.
If Bit C2 = 1, fuse program command successful.

Data Byte[DB9:DB0]

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1

Register Contents

X X X 0 0 0 0 0 0 1 1st programmed wiper location (0x01)
X X X 0 0 0 0 0 1 0 2nd programmed wiper location (0x02)
X X X 0 0 0 0 0 1 1 3rd programmed wiper location (0x03)
X X X 0 0 0 0 1 0 0 4th programmed wiper location (0x04)
… … … … … … … … … … …
X X X 0 0 0 1 0 1 0 10th programmed wiper location (0xA)
… … … … … … … … … … …
X X X 0 0 1 0 1 0 0 20th programmed wiper location (0x14)
… … … … … … … … … … …
X X X 0 0 1 1 1 1 0 30th programmed wiper location (0x1E)
… … … … … … … … … … …
X X X 0 1 0 1 0 0 0 40th programmed wiper location (0x28)
… … … … … … … … … … …
X X X 0 1 1 0 0 1 0 50th programmed wiper location (0x32)
… … … … … … … … … … …
X X X 0 1 1 1 0 0 1 MSB resistance tolerance (0x39)
X X X 0 1 1 1 0 1 0 LSB resistance tolerance (0x3A)

Rev. A | Page 17 of 20

AD5175

A

50-TP MEMORY WRITE-ACKNOWLEDGE POLLING

After each write operation to the 50-TP registers, an internal
write cycle begins. The I
To determine if the internal write cycle is complete and the

2

I

C interface is enabled, interface polling can be executed. I2C
interface polling can be conducted by sending a start condition
followed by the slave address and the write bit. If the I
face responds with an acknowledge (ACK), the write cycle is
complete and the interface is ready to proceed with further
operations. Otherwise, I
until it completes.

2

C interface of the device is disabled.

2

C inter-

2

C interface polling can be repeated

RDAC ARCHITECTURE

To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the
digital potentiometers. In particular, the AD5175 employs a
three-stage segmentation approach, as shown in Figure 28.
The AD5175 wiper switch is designed with the transmission
gate CMOS topology.

R

L

RESET

The AD5175 can be reset through software by executing
Command 4 (see Tabl e 7) or through hardware on the low
pulse of the

RESET

pin. The reset command loads the RDAC
register with the contents of the most recently programmed
50-TP memory location. The RDAC register loads with
midscale if no 50-TP memory location has been previously
programmed. Tie

RESET

to VDD if the

RESET

pin is not used.

SHUTDOWN MODE

The AD5175 can be shut down by executing the software
shutdown command, Command 9 (see Tabl e 7), and setting
the LSB to 1. This feature places the RDAC in a zero-power­consumption state where Terminal A is disconnected from the
wiper terminal. It is possible to execute any command from
Tabl e 7 while the AD5175 is in shutdown mode. The part can
be taken out of shutdown mode by executing Command 9 and
setting the LSB to 0, or by issuing a software or hardware reset.

10-BIT
ADDRESS
DECODER

R

L

Figure 28. Simplified RDAC Circuit

R

M

S

W

R

M

R

W

W

R

W

08719-008

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance between Terminal W and Terminal A,
R

, is available in 10 kΩ and has 1024-tap points accessed by

WA

the wiper terminal. The 10-bit data in the RDAC latch is decoded
to select one of the 1024 possible wiper settings. As a result, the
general equation for determining the digitally programmed
output resistance between the W terminal and A terminal is

D

DR ×=

)(

1024

where:

D is the decimal equivalent of the binary code loaded in the

10-bit RDAC register.

R

is the end-to-end resistance.

WA

In the zero-scale condition, a finite total wiper resistance of
120 Ω is present. Regardless of which setting the part is oper­ating in, take care to limit the current between the A terminal
to W terminal, and W terminal to B terminal, to the maximum
continuous current of ±6 mA, or the pulse current specified in
Tabl e 3. Otherwise, degradation or possible destruction of the
internal switch contact can occur.

(1)

R

WAWA

Rev. A | Page 18 of 20

AD5175

V

Calculate the Actual End-to-End Resistance

The resistance tolerance is stored in the internal memory
during factory testing. The actual end-to-end resistance
can, therefore, be calculated (which is valuable for calibration,
tolerance matching, and precision applications).

The resistance tolerance in percentage is stored in fixed-point
format, using a 16-bit sign magnitude binary. The sign bit(0 =
negative and 1 = positive) and the integer part is located in
Address 0x39, as shown in Tab l e 1 1. Address 0x3A contains
the fractional part, as shown in Tabl e 12 .

That is, if the data readback from Address 0x39 is 0000001010
and data from Address 0x3A is 0010110000, then the end-to-end
resistance can be calculated as follows.

For Memory Location 0x39,

DB[9:8]: XX = don’t care



DB[7]: 0 = negative

DB[6:0]: 0001010 = 10

For Memory Location 0x3A,

DB[9:8]: XX = don’t care

−8

DB[7:0]: 10110000 = 176 × 2

Therefore, tolerance = −10.6875% and R

= 0.6875

(1023)= 8.931 kΩ.

WA

EXT_CAP CAPACITOR

A 1 μF capacitor to VSS must be connected to the EXT_CAP pin
(see Figure 29) on power-up and throughout the operation of
the AD5175.

AD5175

50-TP

EXT_CAP

C1

1µF

Figure 29. EXT_CAP Hardware Setup

MEMORY

BLOCK

V

SS

V

SS

8719-009

TERMINAL VOLTAGE OPERATING RANGE

The positive V
define the boundary conditions for proper 2-terminal digital
resistor operation. Supply signals present on Terminal A and
Terminal W that exceed V
forward-biased diodes (see Figure 30).

Figure 30. Maximum Terminal Voltages Set by V

The ground pin of the AD5175 is primarily used as a digital
ground reference. To minimize the digital ground bounce, join
the AD5175 ground terminal remotely to the common ground.
The digital input control signals to the AD5175 must be refe­renced to the device ground pin (GND) and satisfy the logic
level defined in the Specifications section. An internal level
shift circuit ensures that the common-mode voltage range of
the three terminals extends from V
digital input level.

and negative VSS power supplies of the AD5175

DD

or VSS are clamped by the internal

DD

DD

A

W

V

SS

8719-109

and V

DD

SS

to VDD, regardless of the

SS

POWER-UP SEQUENCE

Because there are diodes to limit the voltage compliance at
Ter mi n al A a n d Te rm i na l W (s e e Figure 30), it is important to
power V
and Terminal W; otherwise, the diode is forward-biased such
that V

DD/VSS

sequence is V
order of powering V
as long as they are powered after V

As soon as V
which first sets the RDAC to midscale and then restores the
last programmed 50-TP value to the RDAC register.

first before applying any voltage to Terminal A

DD/VSS

are powered unintentionally. The ideal power-up

, GND, VDD, digital inputs, VA, and VW. The

SS

, VW, and digital inputs is not important

A

.

DD/VSS

is powered, the power-on preset activates,

DD

Table 12. End-to-End Resistance Tolerance Bytes

Data Byte1

Memory Map Address DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0x39 X X Sign 26 2
0x3A X X 2−1 2

1

X is don’t care.

−2

2

5

2

−3

2−4 2

4

2

3

2

−5

2

2

2

−6

2

1

2

−7

2

0

−8

Rev. A | Page 19 of 20

AD5175

OUTLINE DIMENSIONS

3.10

3.00 SQ

2.90

2.48

2.38

2.23

0.50 BSC

PIN 1 INDEX

AREA

0.80

0.75

0.70

SEATING

PLANE

TOP VIEW

0.30

0.25

0.20

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

6

EXPOSED

PAD

5

BOTTOM VIEW

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

10

1.74

1.64

1.49

1

P

N

I

1

A

O

R

T

N

I

D

C

I

)

5

1

.

R

0

(

121009-A

Figure 31. 10-Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

3.10

3.00

2.90

10

6

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

1

0.50 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

5.15

4.90

4.65

5

15° MAX

6°
0°

0.23

0.13

0.70

0.55

0.40

091709-A

0.30

0.15

1.10 MAX

Figure 32. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 R

AD5175BRMZ-10 10 1,024 −40°C to +125°C 10-Lead MSOP RM-10 DDR
AD5175BRMZ-10-RL7 10 1,024 −40°C to +125°C 10-Lead MSOP RM-10 DDR
AD5175BCPZ-10-RL7 10 1,024 −40°C to +125°C 10-Lead LFCSP_WD CP-10-9 DEG

1

Z = RoHS Compliant Part.

2

C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

I

©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08719-0-7/10(A)

(kΩ) Resolution Temperature Range Package Description Package Option Branding

AB

Rev. A | Page 20 of 20