ANALOG DEVICES AD5175 Service Manual

Single-Channel, 1024-Position, Digital Rheostat

V

W

with I

2

C Interface and 50-TP Memory

FEATURES

Single-channel, 1024-position resolution
10 kΩ nominal resistance
50-times programmable (50-TP) wiper memory
Rheostat mode temperature coefficient: 35 ppm/°C

2.7 V to 5.5 V single-supply operation
±2.5 V to ±2.75 V dual-supply operation for ac or bipolar

operations

2

I

C-compatible interface
Wiper setting and memory readback
Power on refreshed from memory
Resistor tolerance stored in memory
Thin LFCSP, 10-lead, 3 mm × 3 mm × 0.8 mm package
Compact MSOP, 10-lead 3 mm × 4.9 mm × 1.1 mm package

APPLICATIONS

Mechanical rheostat replacements
Op-amp: variable gain control
Instrumentation: gain, offset adjustment
Programmable voltage to current conversions
Programmable filters, delays, time constants
Programmable power supply
Sensor calibration

SCL

SDA

ADDR

RESET

AD5175

FUNCTIONAL BLOCK DIAGRAM

DD

POWER-ON

RESET

I2C

SERIAL

INTERFACE

V

SS

REGISTER

10

50-TP

MEMORY

BLOCK

EXT_CAP GND

Figure 1.

AD5175

RDAC

A

08719-001

GENERAL DESCRIPTION

The AD5175 is a single-channel, 1024-position digital rheostat
that combines industry leading variable resistor performance
with nonvolatile memory (NVM) in a compact package.

This device supports both dual-supply operation at ±2.5 V to
±2.75 V and single-supply operation at 2.7 V to 5.5 V, and offers
50-times programmable (50-TP) memory.

The AD5175 device wiper settings are controllable through the

2

I

C–compatible digital interface. Unlimited adjustments are
allowed before programming the resistance value into the
50-TP memory. The AD5175 does not require any external

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

voltage supply to facilitate fuse blow and there are 50 oppor­tunities for permanent programming. During 50-TP activation,
a permanent blow fuse command freezes the resistance position
(analogous to placing epoxy on a mechanical rheostat).

The AD5175 is available in a 3 mm × 3mm 10-lead LFCSP
package and in a 10-lead MSOP package. The part is guaranteed
to operate over the extended industrial temperature range of

−40°C to +125°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

AD5175

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics ............................................................. 3

Interface Timing Specifications .................................................. 4

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Test Circuits ..................................................................................... 11

Theory of Operation ...................................................................... 12

Serial Data Interface ................................................................... 12

Shift Register ............................................................................... 12

Write Operation.......................................................................... 13

Read Operation........................................................................... 15

RDAC Register ............................................................................ 16

50-TP Memory Block ................................................................ 16

Write Protection ......................................................................... 16

50-TP Memory Write-Acknowledge Polling .......................... 18

Reset ............................................................................................. 18

Shutdown Mode ......................................................................... 18

RDAC Architecture .................................................................... 18

Programming the Variable Resistor ......................................... 18

EXT_CAP Capacitor .................................................................. 19

Terminal Voltage Operating Range ......................................... 19

Power-Up Sequence ................................................................... 19

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

7/10—Rev. 0 to Rev. A

Changes to Ordering Guide .......................................................... 20

3/10—Revision 0: Initial Version

Rev. A | Page 2 of 20

AD5175

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution 10 Bits
Resistor Integral Nonlinearity

|VDD − VSS| = 3.3 V to 3.6 V −1 +1.5 LSB

|VDD − VSS| = 2.7 V to 3.3 V −2.5 +2.5 LSB
Resistor Differential Nonlinearity2 R-DNL
Nominal Resistor Tolerance ±15 %
Resistance Temperature Coefficient
Wiper Resistance Code = zero scale 35 70 Ω

RESISTOR TERMINALS

Terminal Voltage Range
Capacitance A4 f = 1 MHz, measured to GND, code = half scale 90 pF
Capacitance W4 f = 1 MHz, measured to GND, code = half scale 40 pF
Common-Mode Leakage Current4 V

DIGITAL INPUTS

Input Logic4

High V

Low V
Input Current IIN ±1 µA
Input Capacitance4 C

DIGITAL OUTPUT

Output Voltage4

High VOH R

Low VOL R
V
V
Tristate Leakage Current −1 +1 µA
Output Capacitance4 5 pF

POWER SUPPLIES

Single-Supply Power Range VSS = 0 V 2.7 5.5 V
Dual-Supply Power Range ±2.5 ±2.75 V
Supply Current

Positive IDD 1 µA

Negative ISS −1 µA
50-TP Store Current

4, 7

Positive I

Negative I
50-TP Read Current

4, 8

Positive I

Negative I
Power Dissipation9 P
Power Supply Rejection Ratio4 PSRR ∆VDD/∆VSS = ±5 V ± 10% −50 −55 dB

2, 3

R-INL |VDD − VSS| = 3.6 V to 5.5 V −1 +1 LSB

−1 +1 LSB

V

SS

− 0.1 V

DD

V

DD

4, 5

Code = full scale 35 ppm/°C

4, 6

V

V

TERM

2.0 V

INH

0.8 V

INL

5 pF

IN

= VW 50 nA

A

= 2.2 kΩ to VDD V

PULL_UP

= 2.2 kΩ to VDD

PULL_UP

= 2.7 V to 5.5 V, VSS = 0 V 0.4 V

DD

= 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V 0.6 V

DD

DD_OTP_STORE

SS_OTP_STORE

4 mA

−4 mA

DD_OTP_READ

SS_OTP_READ

DISS

500 µA

−500 µA

V

= VDD or VIL = GND 5.5 µW

IH

Rev. A | Page 3 of 20

AD5175

Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit

DYNAMIC CHARACTERISTICS

Bandwidth −3 dB, RAW = 5 kΩ, Terminal W, see Figure 23 700 kHz
Total Harmonic Distortion VA = 1 V rms, f = 1 kHz, RAW = 5 kΩ −90 dB
Resistor Noise Density RWB = 5 kΩ, TA = 25°C, f = 10 kHz 13 nV/√Hz

1

Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from the ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions.

3

The maximum current in each code is defined by IAW = (VDD − 1)/RAW.

4

Guaranteed by design and not subject to production test.

5

See Figure 8 for more details.

6

Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar

signal adjustment.

7

Different from operating current; the supply current for the fuse program lasts approximately 55 ms.

8

Different from operating current; the supply current for the fuse read lasts approximately 500 ns.

9

P

is calculated from (IDD × VDD) + (ISS × VSS).

DISS

10

All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V.

INTERFACE TIMING SPECIFICATIONS

VDD = 2.7 V to 5.5 V; all specifications T

Table 2.

Limit at T
Parameter Conditions1 Min Max Unit Description

2

f

Standard mode 100 kHz Serial clock frequency

SCL

Fast mode 400 kHz Serial clock frequency
t1 Standard mode 4 µs t
Fast mode 0.6 µs t
t2 Standard mode 4.7 µs t
Fast mode 1.3 µs t
t3 Standard mode 250 ns t
Fast mode 100 ns t
t4 Standard mode 0 3.45 µs t
Fast mode 0 0.9 µs t
t5 Standard mode 4.7 µs t
Fast mode 0.6 µs t
t6 Standard mode 4 µs t
Fast mode 0.6 µs t
High speed mode 160 ns t
t7 Standard mode 4.7 µs t
Fast mode 1.3 µs t
t8 Standard mode 4 µs t
Fast mode 0.6 µs t
t9 Standard mode 1000 ns t
Fast mode 300 ns t
t10 Standard mode 300 ns t
Fast mode 300 ns t
t11 Standard mode 1000 ns t
Fast mode 300 ns t
t

Standard mode 1000 ns

11A

Fast mode 300 ns

t12 Standard mode 300 ns t
Fast mode 300 ns t
t13

3

t

Fast mode 0 50 ns Pulse width of the spike is suppressed

SP

4, 5

t

500 ns Command execute time

EXEC

RESET

4, 10

MIN

to T

, unless otherwise noted.

MAX

, T

MIN

MAX

, SCL high time

HIGH

, SCL high time

HIGH

, SCL low time

LOW

, SCL low time

LOW

, data setup time

SU;DAT

, data setup time

SU;DAT

, data hold time

HD;DAT

, data hold time

HD;DAT

, set-up time for a repeated start condition

SU;STA

set-up time for a repeated start condition

SU;STA,

, hold time (repeated) start condition

HD;STA

, hold time (repeated) start condition

HD;STA

, hold time (repeated) start condition

HD;STA

, bus free time between a stop and a start condition

BUF

, bus free time between a stop and a start condition

BUF

, setup time for a stop condition

SU;STO

, setup time for a stop condition

SU;STO

, rise time of the SDA signal

RDA

, rise time of the SDA signal

RDA

, fall time of the SDA signal

FDA

, fall time of the SDA signal

FDA

, rise time of the SCL signal

RCL

, rise time of the SCL signal

RCL

, rise time of the SCL signal after a repeated start condition

t

RCL1

and after an acknowledge bit

, rise time of the SCL signal after a repeated start condition

t

RCL1

and after an acknowledge bit

, fall time of the SCL signal

FCL

, fall time of the SCL signal

FCL

pulse time

20 ns

Rev. A | Page 4 of 20

Minimum RESET low time

AD5175

Limit at T
Parameter Conditions1 Min Max Unit Description

t

RDAC_R-PERF

t

RDAC_NORMAL

t

MEMORY_READ

t

MEMORY_PROGRAM

t

RESET

t

POWER-UP

1

Maximum bus capacitance is limited to 400 pF.

2

The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior

of the part.

3

Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.

4

Refer to t

5

Refer to t

6

Maximum time after VDD − VSS is equal to 2.5 V.

2 µs RDAC register write command execute time (R-Perf mode)

600 ns RDAC register write command execute time (normal mode)

6 µs Memory readback execute time

350 ms Memory program time

600 µs Reset 50-TP restore time

6

2 ms Power-on 50-TP restore time

RDAC_R-PERF

MEMORY_READ

and t

and

for RDAC register write operations.

RDAC_NORMAL

t

MEMORY_PROGRAM

for memory commands operations.

Shift Register and Timing Diagrams

, T

MIN

MAX

DB9 (MSB) DB0 (LSB)

C3

0 0

C2

CONTROL BI T S

D9

C0 C1

D7

D8

D6 D5

DATA BITS

D4

D3

D2 D1

D0

8719-003

Figure 2. Shift Register Content

SCL

SDA

RESET

t

11

t

2

t

6

t

7

PS S P

t

4

t

12

t

1

t

3

Figure 3. 2-Wire I

t

6

t

5

2

C Timing Diagram

t

8

t

10

t

1

3

t

9

8719-002

Rev. A | Page 5 of 20

AD5175

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7.0 V
VSS to GND +0.3 V to −7.0 V
VDD to VSS 7 V
VA, VW to GND VSS − 0.3 V, VDD + 0.3 V
Digital Input and Output Voltage to GND −0.3 V to VDD + 0.3 V
EXT_CAP to VSS 7 V
IA, IW

Pulsed1

Frequency > 10 kHz ±6 mA/d2
Frequency ≤ 10 kHz ±6 mA/√d2

Continuous ±6 mA
Operating Temperature Range3 −40°C to +125°C
Maximum Junction Temperature

(T

Maximum)

J

150°C

Storage Temperature Range −65°C to +150°C
Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 20 sec to 40 sec
Package Power Dissipation (TJ max − TA)/θJA

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A and W terminals at a given
resistance.

2

Pulse duty factor.

3

Includes programming of 50-TP memory.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is defined by JEDEC specification JESD-51 and the value is
dependent on the test board and test environment.

Table 4. Thermal Resistance

Package Type θJA θ

10-Lead LFCSP 50 3 °C/W
10-Lead MSOP 1351 N/A °C/W

1

JEDEC 2S2P test board, still air (0 m/sec airflow).

ESD CAUTION

Unit

JC

Rev. A | Page 6 of 20