ANALOG DEVICES AD5173 Service Manual

256-Position, One-Time Programmable,

A

Dual-Channel, I2C Digital Potentiometers

FEATURES

2-channel, 256-position potentiometers
One-time programmable (OTP) set-and-forget resistance

setting provides a low cost alternative to EEMEM
Unlimited adjustments prior to OTP activation
OTP overwrite allows dynamic adjustments with user-

defined preset
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ
Compact 10-lead MSOP: 3 mm × 4.9 mm
Fast settling time: t
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins: AD0 and AD1 (AD5173)
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: I
Wide operating temperature: −40°C to +125°C

APPLICATIONS

Systems calibration
Electronics level setting
Mechanical trimmers replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment

= 5 μs typical on power-up

S

= 6 μA maximum

DD

AD5172/AD5173

FUNCTIONAL BLOCK DIAGRAMS

W1

RDAC

SERIAL INPUT

W1

RDAC

SERIAL INPUT

B1 A2 W2

FUSE

LINKS

RDAC

REGISTER 2

/

8

REGISTER

B1 W2

FUSE

LINKS

RDAC

REGISTER 2

/

8

REGISTER

1

V

GND

SDA

SCL

V

GND

AD0

AD1

SDA

SCL

DD

DD

12

REGISTER 1

Figure 1. AD5172 Functional Block Diagram

12

REGISTER 1

ADDRESS

DECODE

Figure 2. AD5173 Functional Block Diagram

B2

4103-001

B2

04103-002

GENERAL DESCRIPTION

The AD5172/AD5173 are dual-channel, 256-position, one-time
programmable (OTP) digital potentiometers

1

that employ fuse
link technology to achieve memory retention of resistance
settings. OTP is a cost-effective alternative to EEMEM for users
who do not need to program the digital potentiometer setting
in memory more than once. These devices perform the same
electronic adjustment function as mechanical potentiometers or
variable resistors but with enhanced resolution, solid-state reliabil­ity, and superior low temperature coefficient performance.

The AD5172/AD5173 are programmed using a 2-wire, I

2

C®-

compatible digital interface. Unlimited adjustments are allowed

1

The terms digital potentiometer, VR, and RDAC are used interchangeably.

Rev. H

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

before permanently setting the resistance value. During OTP
activation, a permanent blow fuse command freezes the wiper
position (analogous to placing epoxy on a mechanical trimmer).

Unlike traditional OTP digital potentiometers, the AD5172/
AD5173 have a unique temporary OTP overwrite feature that
allows for new adjustments even after a fuse is blown. However,
the OTP setting is restored during subsequent power-up condi­tions. This allows users to treat these digital potentiometers as
volatile potentiometers with a programmable preset.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2003–2009 Analog Devices, Inc. All rights reserved.

AD5172/AD5173

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagrams ............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics: 2.5 kΩ ............................................... 3

Electrical Characteristics: 10 kΩ, 50 kΩ, and 100 kΩ ............. 4

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings ............................................................ 7

ESD Caution .................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ............................................. 9

Test Circuits ..................................................................................... 14

Theory of Operation ...................................................................... 15

One-Time Programming (OTP) .............................................. 15

REVISION HISTORY

4/09—Rev. G to Rev. H

Changes to DC Characteristics—Rheostat Mode Parameter and
to DC Characteristics—Potentiometer Divider Mode Parameter,

Table 1 ................................................................................................ 3

12/08—Rev. F to Rev. G

Changes to OTP Supply Voltage Parameter, Table 1.................... 3

Changes to OTP Supply Voltage Parameter, Table 2.................... 5

Changes to Table 5 and Table 6 ....................................................... 8

Changes to One-Time Programming (OTP) Section ................ 15

Changes to Power Supply Considerations Section, Figure 46,

and Figure 46 Caption .................................................................... 17

Changes to Ordering Guide .......................................................... 23

7/08—Rev. E to Rev. F

Changes to Power Supplies Parameter in Table 1 and Table 2 ... 3

Updated Fuse Blow Condition to 400 ms Throughout ............... 5

1/08—Rev. D to Rev. E

Changes to Features .......................................................................... 1

Changes to General Description .................................................... 1

Changes to OTP Supply Voltage and OTP Supply Current in

Table 1 ................................................................................................ 3

Changes to OTP Supply Voltage and OTP Supply Current in

Table 2 ................................................................................................ 5

Added OTP Program Time in Table 3 ........................................... 6

Changes to Table 4 ............................................................................ 7

Changes to Table 5 and Table 6 ....................................................... 8

Inserted Figure 30 ........................................................................... 13

Replaced One-Time Programming (OTP) Section ................... 15

Replaced Power Supply Considerations Section ........................ 17

Deleted Device Programming Software Section ........................ 20

Programming the Variable Resistor and Voltage ................... 15

Programming the Potentiometer Divider ............................... 16

ESD Protection ........................................................................... 17

Terminal Voltage Operating Range ......................................... 17

Power-Up Sequence ................................................................... 17

Power Supply Considerations ................................................... 17

Layout Considerations ............................................................... 18

I2C Interface .................................................................................... 19

Write Mode ................................................................................. 19

Read Mode .................................................................................. 19

I2C Controller Programming .................................................... 20

I2C-Compatible, 2-Wire Serial Bus .......................................... 21

Level Shifting for Different Voltage Operation ...................... 22

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 23

Replaced I

2

C-Compatible, 2-Wire Serial Bus Section ............... 21

Changes to Ordering Guide .......................................................... 23

6/06—Rev. C to Rev. D

Changes to Features .......................................................................... 1

Changes to One-Time Programming (OTP) Section................ 15

Changes to Figure 44 and Figure 45............................................. 17

Changes to Power Supply Considerations Section .................... 18

Changes to Figure 46 and Figure 47............................................. 18

Changes to Device Programming Software Section .................. 19

Updated Outline Dimensions ....................................................... 24

6/05—Rev. B to Rev. C

Added Footnote 8, Footnote 9, and Footnote 10 to Table 1 ........ 3

Added Footnote 8 to Table 2 ............................................................ 5

Changes to Table 5 and Table 6 ....................................................... 9

Changes to Power Supply Considerations Section .................... 17

Changes to I

2

C-Compatible 2-Wire Serial Bus Section ............ 23

Added Level Shifting for Different Voltage Operation Section ...... 24

Updated Outline Dimensions ....................................................... 25

Changes to Ordering Guide .......................................................... 25

10/04—Rev. A to Rev. B

Updated Format ................................................................. Universal

Changes to Specifications ................................................................. 3

Changes to One-Time Programming (OTP) Section................ 13

Changes to Power Supply Considerations Section .................... 15

Changes to Figure 44 and Figure 45............................................. 15

Changes to Figure 46 and Figure 47............................................. 16

11/03—Rev. 0 to Rev. A

Changes to Electrical Characteristics—2.5 kΩ .............................. 3

11/03—Revision 0: Initial Version

Rev. H | Page 2 of 24

AD5172/AD5173

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS: 2.5 kΩ

VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance
Resistance Temperature Coefficient (∆RAB/RAB)/∆T 35 ppm/°C
Wiper Resistance RWB Code = 0x00, VDD = 5 V 160 200 Ω

DC CHARACTERISTICS—POTENTIOMETER DIVIDER

4

MODE
Differential Nonlinearity
Integral Nonlinearity

5

INL −2 ±0.6 +2 LSB

5

Voltage Divider Temperature Coefficient (ΔVW/VW)/ΔT Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance A, B

Capacitance W

6

7

7

C

Shutdown Supply Current
Common-Mode Leakage ICM V

DIGITAL INPUTS AND OUTPUTS

SDA and SCL

Input Logic High
Input Logic Low

9

9

V

AD0 and AD1

Input Logic High VIH V

Input Logic Low VIL V
Input Current IIL V
Input Capacitance

7

C

POWER SUPPLIES

Power Supply Range V
OTP Supply Voltage

9, 10

V

Supply Current IDD V
OTP Supply Current
Power Dissipation

9, 11 , 12

13

Power Supply Sensitivity PSS

DYNAMIC CHARACTERISTICS

Bandwidth, −3 dB BW Code = 0x80 4.8 MHz
Total Harmonic Distortion THDW

2

2

R-INL R

3

R-DNL RWB, VA = no connect −2 ±0.1 +2 LSB

∆RAB T

DNL −1.5 ±0.1 +1.5 LSB

Code = 0xFF −14 −5.5 0 LSB

WFSE

Code = 0x00 0 4.5 12 LSB

WZSE

VA, VB, VW GND VDD V
CA, CB

W

8

I

V

A_SD

VIH V

V

IL

5 pF

IL

DD_RANGE

T

DD_OTP

I

14

V

DD_OTP

P

V

DISS

, VA = no connect −14 ±2 +14 LSB

WB

= 25°C −20 +55 %

A

f = 1 MHz, measured to

45 pF

GND, code = 0x80
f = 1 MHz, measured to

60 pF

GND, code = 0x80

= 5.5 V 0.01 1 μA

DD

= VB = VDD/2 1 nA

A

= 5 V 0.7 VDD VDD + 0.5 V

DD

= 5 V −0.5 +0.3 VDD V

DD

= 3 V 2.1 V

DD

= 3 V 0.6 V

DD

= 0 V or 5 V ±1 μA

IN

2.7 5.5 V
= 25°C 5.6 5.7 5.8 V

A

= 5 V or VIL = 0 V 3.5 6 μA

IH

= 5.0 V, TA = 25°C 100 mA

DD_OTP

= 5 V or VIL = 0 V, VDD = 5 V 33 μW

IH

= 5 V ± 10%,

V

DD

±0.02 ±0.08 %/%

code = midscale

= 1 V rms, VB = 0 V,

V

A

0.1 %

f = 1 kHz

Rev. H | Page 3 of 24

AD5172/AD5173

Parameter Symbol Conditions Min Typ1Max Unit

VW Settling Time tS

= 5 V, VB = 0 V, ±1 LSB

V

A

error band

Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.

3

VA = VDD, VB = 0 V, wiper (VW) = no connect.

4

Specifications apply to all VRs.

5

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

6

Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.

7

Guaranteed by design, but not subject to production test.

8

Measured at Terminal A. Terminal A is open circuited in shutdown mode.

9

The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD.

However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.

10

Different from the operating power supply; the power supply for OTP is used one time only.

11

Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.

12

See Figure 30 for an energy plot during an OTP program.

13

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

14

All dynamic characteristics use VDD = 5 V.

R

N_WB

WB

= 1.25 kΩ, RS = 0 Ω 3.2 nV/√Hz

ELECTRICAL CHARACTERISTICS: 10 kΩ, 50 kΩ, AND 100 kΩ

VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.

1 μs

Table 2.

Parameter Symbol Conditions Min Typ

1

Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance

2

2

R-INL R

3

R-DNL RWB, VA = no connect −1 ±0.1 +1 LSB

ΔRAB T

, VA = no connect −2.5 ±0.25 +2.5 LSB

WB

= 25°C −20 +20 %

A

Resistance Temperature Coefficient (ΔRAB/RAB)/ΔT 35 ppm/°C
Wiper Resistance RWB Code = 0x00, VDD = 5 V 160 200 Ω

DC CHARACTERISTICS—POTENTIOMETER DIVIDER

4

MODE
Differential Nonlinearity
Integral Nonlinearity

5

INL −1 ±0.3 +1 LSB

5

DNL −1 ±0.1 +1 LSB

Voltage Divider Temperature Coefficient (ΔVW/VW)/ΔT Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

Code = 0xFF −2.5 −1 0 LSB

WFSE

Code = 0x00 0 1 2.5 LSB

WZSE

RESISTOR TERMINALS

Voltage Range
Capacitance A, B

6

7

VA, VB, VW GND VDD V
CA, CB

f = 1 MHz, measured to

45 pF

GND, code = 0x80

Capacitance W

7

C

W

f = 1 MHz, measured to

60 pF

GND, code = 0x80
Shutdown Supply Current
Common-Mode Leakage ICM V

8

I

V

A_SD

DD

= VB = VDD/2 1 nA

A

= 5.5 V 0.01 1 μA

DIGITAL INPUTS AND OUTPUTS

SDA and SCL

Input Logic High
Input Logic Low

9

9

V

VIH V

V

IL

= 5 V 0.7 VDD VDD + 0.5 V

DD

= 5 V −0.5 +0.3 VDD V

DD

AD0 and AD1

Input Logic High VIH V

Input Logic Low VIL V
Input Current IIL V
Input Capacitance

7

C

5 pF

IL

= 3 V 2.1 V

DD

= 3 V 0.6 V

DD

= 0 V or 5 V ±1 μA

IN

Rev. H | Page 4 of 24

AD5172/AD5173

Parameter Symbol Conditions Min Typ

1

Max Unit

POWER SUPPLIES

Power Supply Range V
OTP Supply Voltage

9, 10

V

Supply Current IDD V
OTP Supply Current
Power Dissipation

13

9, 11 , 12

I
P

Power Supply Sensitivity PSS

2.7 5.5 V

DD_RANGE

T

DD_OTP

V

DD_OTP

DISS

= 25°C 5.6 5.7 5.8 V

A

= 5 V or VIL = 0 V 3.5 6 μA

IH

= 5.0 V, TA = 25°C 100 mA

DD_OTP

= 5 V or VIL = 0 V,

V

IH

= 5 V

V

DD

= 5 V ± 10%,

V

DD

33 μW

±0.02 ±0.08 %/%

code = midscale

DYNAMIC CHARACTERISTICS

14

Bandwidth, −3 dB BW RAB = 10 kΩ, code = 0x80 600 kHz
R
R
Total Harmonic Distortion THDW

VW Settling Time tS

= 50 kΩ, code = 0x80 100 kHz

AB

= 100 kΩ, code = 0x80 40 kHz

AB

= 1 V rms, VB = 0 V,

V

A

f = 1 kHz, R

= 5 V, VB = 0 V, ±1 LSB

V

A

= 10 kΩ

AB

0.1 %

2 μs

error band

Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.

3

VA = VDD, VB = 0 V, wiper (VW) = no connect.

4

Specifications apply to all VRs.

5

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

6

Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.

7

Guaranteed by design, but not subject to production test.

8

Measured at Terminal A. Terminal A is open circuited in shutdown mode.

9

The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD.

However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.

10

Different from the operating power supply; the power supply for OTP is used one time only.

11

Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.

12

See Figure 30 for an energy plot during an OTP program.

13

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

14

All dynamic characteristics use VDD = 5 V.

R

N_WB

WB

= 5 kΩ, RS = 0 Ω 9 nV/√Hz

Rev. H | Page 5 of 24

AD5172/AD5173

TIMING CHARACTERISTICS

VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.

Table 3.

Parameter Symbol Conditions Min Typ Max Unit

I2C INTERFACE TIMING CHARACTERISTICS

SCL Clock Frequency f
Bus-Free Time Between Stop and Start, t
Hold Time (Repeated Start), t

Low Period of SCL Clock, t
High Period of SCL Clock, t

HD;STA

t

LOW

t

HIGH

Setup Time for Repeated Start Condition, t
Data Hold Time, t
Data Setup Time, t

2

HD;DAT

t

SU;DAT

Fall Time of Both SDA and SCL Signals, tF t
Rise Time of Both SDA and SCL Signals, tR t
Setup Time for Stop Condition, t
OTP Program Time t11 400 ms

1

See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 48 to Figure 51).

2

The maximum t

has to be met only if the device does not stretch the low period (t

HD;DAT

Timing Diagram

1

t

BUF

t

400 kHz

SCL

1.3 μs

1

2

After this period, the first clock
pulse is generated.

1.3 μs

3

0.6 μs

4

t

SU;STA

0.6 μs

5

t6 0.9 μs

100 ns

7

300 ns

8

300 ns

9

t

SU;STO

t

8

0.6 μs

10

) of the SCL signal.

LOW

t

t

6

9

0.6 μs

t

2

SCL

SDA

t

2

t

1

PS

t

3

t

9

t

8

Figure 3. I

t

4

2

C Interface Detailed Timing Diagram

t

7

t

5

S

t

10

04103-0-039

P

Rev. H | Page 6 of 24

AD5172/AD5173

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7 V

VA, VB, VW to GND VDD

Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx1

Pulsed ±20 mA

Continuous ±5 mA
Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range −40°C to +125°C
Maximum Junction Temperature (T

) 150°C

JMAX

Storage Temperature Range −65°C to +150°C
Reflow Soldering

Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
Thermal Resistance

2

θJA for 10-Lead MSOP 200°C/W

1

The maximum terminal current is bound by the maximum current handling

of the switches, the maximum power dissipation of the package, and the
maximum applied voltage across any two of the A, B, and W terminals at a
given resistance.

2

The package power dissipation is (T

− TA)/θJA.

JMAX

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. H | Page 7 of 24

AD5172/AD5173

G

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

B1

2

A1

AD5172

3

W2

TOP VIEW

(Not to Scale)

ND

4

V

5

DD

Figure 4. AD5172 Pin Configuration

10

W1

9

B2

8

A2

SDA

7

SCL

6

4103-045

B1

AD0

W2

GND

V

DD

1

2

AD5173

3

TOP VIEW

(Not to Scale)

4

5

W1

10

B2

9

AD1

8

SDA

7

SCL

6

04103-046

Figure 5. AD5173 Pin Configuration

Table 5. AD5172 Pin Function Descriptions

Pin
No. Mnemonic Description

1 B1 B1 Terminal. GND ≤ VB1 ≤ VDD.
2 A1 A1 Terminal. GND ≤ VA1 ≤ VDD.
3 W2 W2 Terminal. GND ≤ VW2 ≤ VDD.
4 GND Digital Ground.
5 VDD

Positive Power Supply. Specified for
operation from 2.7 V to 5.5 V. For OTP
programming, V

needs to be a minimum

DD

of 5.6 V but no more than 5.8 V and to be
capable of driving 100 mA.

6 SCL

Serial Clock Input. Positive-edge triggered.
Requires a pull-up resistor. If this pin is driven
directly from a logic controller without a
pull-up resistor, ensure that the VIH minimum

.

DD

7 SDA

is 0.7 V × V
Serial Data Input/Output. Requires a pull-up

resistor. If this pin is driven directly from a
logic controller without a pull-up resistor,
ensure that the V

minimum is 0.7 V × VDD.

IH

8 A2 A2 Terminal. GND ≤ VA2 ≤ VDD.
9 B2 B2 Terminal. GND ≤ VB2 ≤ VDD.
10 W1 W1 Terminal. GND ≤ VW1 ≤ VDD.

Table 6. AD5173 Pin Function Descriptions

Pin
No. Mnemonic Description

1 B1 B1 Terminal. GND ≤ VB1 ≤ VDD.
2 AD0

Programmable Address Bit 0 for Multiple

Package Decoding.
3 W2 W2 Terminal. GND ≤ VW2 ≤ VDD.
4 GND Digital Ground.
5 VDD

Positive Power Supply. Specified for

operation from 2.7 V to 5.5 V. For OTP

programming, V

needs to be a minimum

DD

of 5.6 V but no more than 5.8 V and to be

capable of driving 100 mA.
6 SCL

Serial Clock Input. Positive-edge triggered.

Requires a pull-up resistor. If this pin is driven

directly from a logic controller without a

pull-up resistor, ensure that the V

7 SDA

is 0.7 V × V

Serial Data Input/Output. Requires a pull-up

.

DD

resistor. If this pin is driven directly from a

logic controller without a pull-up resistor,

ensure that the VIH minimum is 0.7 V × VDD.
8 AD1

Programmable Address Bit 1 for Multiple

Package Decoding.
9 B2 B2 Terminal. GND ≤ VB2 ≤ VDD.
10 W1 W1 Terminal. GND ≤ VW1 ≤ VDD.

minimum

IH

Rev. H | Page 8 of 24