ANALOG DEVICES AD5172, AD5173 Service Manual

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256-Position, One-Time Programmable

Dual-Channel, I2C Digital Potentiometers

FEATURES

2-channel, 256-position potentiometers
One-time programmable (OTP) set-and-forget

resistance setting provides a low cost alternative to EEMEM
Unlimited adjustments prior to OTP activation
OTP overwrite allows dynamic adjustments with

user-defined preset
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Fast settling time: t
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins AD0 and AD1 (AD5173)
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: I
Wide operating temperature: −40°C to +125°C

Evaluation board and software are available
Software replaces μC in factory programming applications

APPLICATIONS

Systems calibration
Electronics level setting
Mechanical trimmers replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment

GENERAL OVERVIEW

The AD5172/AD5173 are dual-channel, 256-position, one-time
programmable (OTP) digital potentiometers
link technology to achieve memory retention of resistance
settings. OTP is a cost-effective alternative to EEMEM for users
who do not need to program the digital potentiometer setting in
memory more than once. This device performs the same
electronic adjustment function as mechanical potentiometers or
variable resistors with enhanced resolution, solid-state reliability,
and superior low temperature coefficient performance.

The AD5172/AD5173 are programmed using a 2-wire, I
compatible digital interface. Unlimited adjustments are allowed
before permanently setting the resistance value. During OTP
activation, a permanent blow fuse command freezes the wiper
position (analogous to placing epoxy on a mechanical trimmer).

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

= 5 μs typ in power-up

S

= 6 μA max

DD

1

that employ fuse

2

C-

AD5172/AD5173

FUNCTIONAL BLOCK DIAGRAMS

RDAC

RDAC

B2

B2

2

C controllers,

V

ND

SDA

SCL

A1

DD

12

REGISTER 1

W1

RDAC

SERIAL INPUT

B1 A2 W2

FUSE
LINKS

REGISTER 2

/

8

REGISTER

Figure 1. AD5172

B1 W2

W1

V

ND

AD0

AD1

SDA

SCL

DD

12

RDAC

REGISTER 1

ADDRESS

DECODE

FUSE

LINKS

/

8

SERIAL INPUT

REGISTER

REGISTER 2

Figure 2. AD5173

Unlike traditional OTP digital potentiometers, the AD5172/
AD5173 have a unique temporary OTP overwrite feature that
allows for new adjustments even after a fuse has been blown.
However, the OTP setting is restored during subsequent power­up conditions. This allows users to treat these digital potenti­ometers as volatile potentiometers with a programmable preset.

For applications that program the AD5172/AD5173 at the
factory, Analog Devices offers device programming software
running on Windows® 2000, NT, and XP operating systems.
This software effectively replaces any external I
thus enhancing the time-to-market of the user’s systems.

1

The terms digital potentiometer, VR, and RDAC are used interchangeably.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

04103-0-001

04103-0-002

AD5172/AD5173

TABLE OF CONTENTS

Electrical Characteristics—2.5 kΩ Version................................... 3

Terminal Voltage Operating Range ......................................... 17

Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions....... 5

Timing Characteristics—2.5 kΩ, 10 kΩ, 50 kΩ,

100 kΩ Versions ................................................................................ 7

Absolute Maximum Ratings............................................................ 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 10

Test Cir c ui t s .....................................................................................14

Theory of Operation ...................................................................... 15

One-Time Programming (OTP) .............................................. 15

Programming the Variable Resistor and Voltage ................... 15

Programming the Potentiometer Divider............................... 16

ESD Protection ........................................................................... 17

REVISION HISTORY

6/05—Rev. B to Rev. C

Added Footnote 8, Footnote 9, and Footnote 10 to Table 1 .......... 3

Added Footnote 8 to Table 2 .............................................................. 5

Changes to Table 5 and Table 6.......................................................... 9

Changes to Power Supply Considerations Section........................ 17

Changes to I
Added Level Shifting for Different Voltage Operation Section... 24

Updated Outline Dimensions.......................................................... 25

Changes to Ordering Guide............................................................. 25

2

C-Compatible 2-Wire Serial Bus Section................ 23

Power-Up Sequence ................................................................... 17

Power Supply Considerations................................................... 17

Layout Considerations............................................................... 18

Evaluation Software/Hardware..................................................... 19

Software Programming ............................................................. 19

Device Programming................................................................. 20

2

I

C Interface .................................................................................... 21

2

I

C-Compatible 2-Wire Serial Bus........................................... 23

Level Shifting for Different Voltage Operation ...................... 24

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 25

10/04—Rev. A to Rev. B

Updated Format ................................................................Universal

Changes to Specifications................................................................ 3

Changes to One-Time Programming (OTP) Section ............... 13

Changes to Power Supply Considerations Section.................... 15

Changes to Figure 44 and Figure 45 ............................................ 15

Changes to Figure 46 and Figure 47 ............................................ 16

11/03—Rev. 0 to Rev. A

Changes to Electrical Characteristics—2.5 kΩ............................. 3

Rev. C | Page 2 of 28

AD5172/AD5173

ELECTRICAL CHARACTERISTICS—2.5 kΩ VERSION

VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TB

Table 1.

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity

Resistor Integral Nonlinearity

Nominal Resistor Tolerance

2

2

3

R-DNL RWB, VA = No connect −2 ±0.1 +2 LSB
R-INL RWB, VA = No connect −6 ±0.75 +6 LSB
∆R

AB

Resistance Temperature Coefficient (∆RAB/RAB)/∆T 35 ppm/°C

RWB (Wiper Resistance) R

WB

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)

Differential Nonlinearity

Integral Nonlinearity

Voltage Divider Temperature

4

4

DNL −1.5 ±0.1 +1.5 LSB
INL −2 ±0.6 +2 LSB
(ΔV

)/ΔT Code = 0x80 15 ppm/°C

W/VW

Coefficient
Full-Scale Error V
Zero-Scale Error V

WFSE

WZSE

RESISTOR TERMINALS

Voltage Range
Capacitance6 A, B CA, C

Capacitance6 W C

Shutdown Supply Current
Common-Mode Leakage I

5

7

VA, VB, V

B

W

I

A_SD

CM

W

DIGITAL INPUTS AND OUTPUTS

Input Logic High (SDA and SCL)
Input Logic Low (SDA and SCL)
Input Logic High (AD0 and AD1) V
Input Logic Low (AD0 and AD1) V
Input Current I
Input Capacitance

6

8

8

V

IH

V

IL

IH

IL

IL

C

IL

POWER SUPPLIES

Power Supply Range V
OTP Supply Voltage

8, 9

Supply Current I
OTP Supply Current
Power Dissipation

8, 10

11

DD RANGE

V

DD_OTP

DD

I

DD_OTP

P

DISS

Power Supply Sensitivity PSS VDD = 5 V ± 10%, Code = Midscale ±0.02 ±0.08 %/%

< +125°C; unless otherwise noted.

A

TA = 25°C −20 +55 %

Code = 0x00, VDD = 5 V 160 200 Ω

Code = 0xFF −10 −2.5 0 LSB
Code = 0x00 0 2 10 LSB

GND V

f = 1 MHz, Measured to GND,

45 pF

DD

V

Code = 0x80

f = 1 MHz, Measured to GND,

60 pF

Code = 0x80
VDD = 5.5 V 0.01 1 μA
VA = VB = VDD/2 1 nA

VDD = 5 V 0.7 VDD

VDD + 0.5

V
VDD = 5 V −0.5 +0.3 VDDV
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
VIN = 0 V or 5 V ±1 μA
5 pF

2.7 5.5 V
TA = 25°C 5.25 5.5 V
VIH = 5 V or VIL = 0 V 3.5 6 μA
V

= 5.5 V, TA = 25°C 100 mA

DD_OTP

VIH = 5 V or VIL = 0 V, VDD = 5 V 30 μW

Rev. C | Page 3 of 28

AD5172/AD5173

Parameter Symbol Conditions Min Typ1Max Unit

DYNAMIC CHARACTERISTICS

Bandwidth −3 dB BW_2.5 K Code = 0x80 4.8 MHz
Total Harmonic Distortion THD
VW Settling Time t

Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, Wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification

limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the A terminal. The A terminal is open-circuited in shutdown mode.

8

The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH min = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to

V

. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-

DD

up resistors.

9

Different from operating power supply; power supply for OTP is used one time only.

10

Different from operating current; supply current for OTP lasts approximately 400 ms for one time only.

11

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

12

All dynamic characteristics use VDD = 5 V.

12

W

S

VA = 1 V rms, VB = 0 V, f = 1 kHz 0.1 %
VA = 5 V, VB = 0 V, ±1 LSB error

B

1 μs

band

N_WB

RWB = 1.25 kΩ, RS = 0 3.2 nV/√Hz

Rev. C | Page 4 of 28

AD5172/AD5173

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TB

Table 2.

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance

2

2

3

R-DNL RWB, VA = No connect –1 ±0.1 +1 LSB
R-INL RWB, VA = No connect –2.5 ±0.25 +2.5 LSB
ΔR

AB

Resistance Temperature Coefficient (ΔRAB/RAB)/ΔT 35 ppm/°C
RWB (Wiper Resistance) R

WB

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to all VRs)

Differential Nonlinearity
Integral Nonlinearity
Voltage Divider Temperature

4

4

DNL –1 ±0.1 +1 LSB
INL –1 ±0.3 +1 LSB
(ΔV

)/ΔT Code = 0x80 15 ppm/°C

W/VW

Coefficient
Full-Scale Error V
Zero-Scale Error V

WFSE

WZSE

RESISTOR TERMINALS

Voltage Range
Capacitance6 A, B CA, C

Capacitance W

Shutdown Supply Current
Common-Mode Leakage I

5

6

7

VA, VB, V

B

C

W

I

A_SD

CM

W

DIGITAL INPUTS AND OUTPUTS

Input Logic High (SDA and SCL)
Input Logic Low (SDA and SCL)

Input Logic High (AD0 and AD1) V
Input Logic Low (AD0 and AD1) V
Input Current I
Input Capacitance

6

8

8

V

IH

V

IL

IH

IL

IL

C

IL

POWER SUPPLIES

Power Supply Range V
OTP Supply Voltage

8, 9

Supply Current I
OTP Supply Current
Power Dissipation

8, 10

11

DD RANGE

V

DD_OTP

DD

I

DD_OTP

P

DISS

Power Supply Sensitivity PSS VDD = +5 V ± 10%, Code = Midscale ±0.02 ±0.08 %/%

< +125°C; unless otherwise noted.

A

TA = 25°C –20 +20 %

Code = 0x00, VDD = 5 V 160 200 Ω

Code = 0xFF –2.5 –1 0 LSB
Code = 0x00 0 1 2.5 LSB

GND V
f = 1 MHz, Measured to GND,

45 pF

DD

V

Code = 0x80

f = 1 MHz, Measured to GND,

60 pF

Code = 0x80
VDD = 5.5 V 0.01 1 μA
VA = VB = VDD/2 1 nA

VDD = 5 V 0.7 VDD V
VDD = 5 V –0.5

+ 0.5 V

DD

+0.3
V

DD

V

VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
VIN = 0 V or 5 V ±1 μA
5 pF

2.7 5.5 V

5.25 5.5 V
VIH = 5 V or VIL = 0 V 3.5 6 μA
V

= 5.5 V, TA = 25°C 100 mA

DD_OTP

VIH = 5 V or VIL = 0 V, VDD = 5 V 30 μW

Rev. C | Page 5 of 28

AD5172/AD5173

Parameter Symbol Conditions Min Typ1Max Unit

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW RAB = 10 kΩ, Code = 0x80 600 kHz
R
R
Total Harmonic Distortion THD

VW Settling Time (10 kΩ/50 kΩ/100 kΩ) t

Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, Wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification

limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the A terminal. The A terminal is open-circuited in shutdown mode.

8

The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH min = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA have resistors to be pulled
up to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without
pull-up resistors.

9

Different from operating power supply, power supply OTP is used one time only.

10

Different from operating current, supply current for OTP lasts approximately 400 ms for one time only.

11

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

12

All dynamic characteristics use VDD = 5 V.

12

= 50 kΩ, Code = 0x80 100 kHz

AB

= 100 kΩ, Code = 0x80 40 kHz

AB

W

S

VA = 1 V rms, VB = 0 V, f = 1 kHz,

= 10 kΩ

R

AB

VA = 5 V, VB = 0 V, ±1 LSB error

B

0.1 %

2 μs

band

N_WB

RWB = 5 kΩ, RS = 0 9 nV/√Hz

Rev. C | Page 6 of 28

AD5172/AD5173

TIMING CHARACTERISTICS—2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TB

Table 3.

Parameter Symbol Conditions Min Typ Max Unit

I2C INTERFACE TIMING CHARACTERISTICS

SCL Clock Frequency f
t

Bus Free Time Between Stop and Start t

BUF

t

Hold Time (Repeated Start) t

HD;STA

t

Low Period of SCL Clock t

LOW

t

High Period of SCL Clock t

HIGH

t

Setup Time for Repeated Start

SU;STA

1

SCL

1

2

3

4

t

5

Condition
t

Data Hold Time

HD;DAT

t

Data Setup Time t

SU;DAT

tF Fall Time of Both SDA and SCL Signals t
tR Rise Time of Both SDA and SCL Signals t
t

Setup Time for Stop Condition t

SU;STO

1

See the timing diagrams (Figure 51 to Figure 55) for locations of measured values.

2

The maximum t

HD;DAT

2

has only to be met if the device does not stretch the low period (t

t

6

7

8

9

10

< +125°C; unless otherwise noted.

A

400 kHz

1.3 μs
After this period, the first clock pulse

0.6 μs

is generated.

1.3 μs

0.6 μs

0.6 μs

0.9 μs
100 ns
300 ns
300 ns

0.6 μs

) of the SCL signal.

LOW

Rev. C | Page 7 of 28

AD5172/AD5173

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND –0.3 V to +7 V
VA, VB, VW to GND V
Terminal Current, Ax to Bx, Ax to Wx, Bx to

1

Wx

DD

Pulsed ±20 mA

Continuous ±5 mA
Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (T

) 150°C

JMAX

Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Thermal Resistance2 θJA: MSOP-10 230°C/W

1

Maximum terminal current is bound by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Package power dissipation = (TJ max – TA)/θJA.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 8 of 28

AD5172/AD5173

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

W2

1

B1

2

A1

3

AD5172

TOP VIEW

4

5

DD

10

W1

9

B2

8

A2

7

SDAGND

6

SCLV

04103-0-045

Figure 3. AD5172 Pin Configuration

Table 5. AD5172 Pin Function Descriptions

Pin Mnemonic Description

1 B1 B1 Terminal. GND ≤ VB1 ≤ VDD.
2 A1 A1 Terminal. GND ≤ VA1 ≤ VDD.
3 W2 W2 Terminal. GND ≤ VW2 ≤ VDD.
4 GND Digital Ground.
5 V

DD

Positive Power Supply. Specified for
operation from 2.7 V to 5.5 V. For OTP
programming, VDD needs to be a minimum
of 5.25 V but no more than 5.5 V and have a
100 mA driving capability.

6 SCL

Serial Clock Input. Positive-edge triggered.
Requires a pull-up resistor. If it is driven
direct from a logic controller without the
pull-up resistor, ensure that V

.

DD

7 SDA

0.7 V × V
Serial Data Input/Output. Requires a pull-

up resistor. If it is driven direct from a logic
controller without the pull-up resistor,
ensure that V

min is 0.7 V × VDD.

IH

8 A2 A2 Terminal. GND ≤ VA2 ≤ VDD.
9 B2 B2 Terminal. GND ≤ VB2 ≤ VDD.
10 W1 W1 Terminal. GND ≤ VW1 ≤ VDD.

min is

IH

AD0

W2

1

B1

2

3

AD5173

TOP VIEW

4

5

DD

10

W1

9

B2

8

AD1

7

SDAGND

6

SCLV

04103-0-046

Figure 4. AD5173 Pin Configuration

Table 6. AD5173 Pin Function Descriptions

Pin Mnemonic Description

1 B1 B1 Terminal. GND ≤ VB1 ≤ VDD.
2 AD0

Programmable Address Bit 0 for Multiple

Package Decoding.
3 W2 W2 Terminal. GND ≤ VW2 ≤ VDD.
4 GND Digital Ground.
5 V

DD

Positive Power Supply. Specified for

operation from 2.7 V to 5.5 V. For OTP

programming, VDD needs to be a minimum

of 5.25 V but no more than 5.5 V and have a

100 mA driving capability.
6 SCL

Serial Clock Input. Positive-edge triggered.

Requires a pull-up resistor. If it is driven

direct from a logic controller without the

pull-up resistor, ensure that V

7 SDA

0.7 V × V

Serial Data Input/Output. Requires a pull-

.

DD

up resistor. If it is driven direct from a logic

controller without the pull-up resistor,

8 AD1

ensure that V

Programmable Address Bit 1 for Multiple

min is 0.7 V × VDD.

IH

Package Decoding.
9 B2 B2 Terminal. GND ≤ VB2 ≤ VDD.
10 W1 W1 Terminal. GND ≤ VW1 ≤ VDD.

min is

IH

Rev. C | Page 9 of 28