ANALOG DEVICES AD5171 Service Manual

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64-

Position

OTP Digital Potentiometer

FEATURES

64 positions
OTP (one-time programmable)

setting—low cost alternative over EEMEM
Unlimited adjustments prior to OTP activation
5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ end-to-end resistance

o

Low tempco 5 ppm/

C in potentiometer mode
Low tempco 35 ppm/°C in rheostat mode
Compact standard SOT-23-8 package
Low power, I
Fast settling time, t

2

I

C compatible digital interface

= 8 µA max

DD

= 5 µs typ in power-up

s

Computer software replaces µc in factory programming
applications

Full read/write of wiper register

2

C device address pin

Extra I
Power-on preset to midscale
6 V one-time programming voltage
Low operating voltage, 2.7 V to 5.5 V
OTP validation check function
Automotive temperature range −40°C to +125°C

APPLICATIONS

Systems calibrations
Electronics level settings
Mechanical potentiometers and trimmers® replacements
Automotive electronics adjustments
Gain control and offset adjustments
Transducer circuits adjustments
Programmable filters up to 1.5 MHz BW

GENERAL DESCRIPTION

The AD5171 is a 64-position, one-time programmable (OTP)

2

digital potentiometer

, which employs fuse link technology to
achieve the memory retention of resistance setting function.
OTP is a cost-effective alternative over the EEMEM approach
for users who do not need to reprogram new memory setting in
the digital potentiometer. This device performs the same
electronic adjustment function like most mechanical trimmers
and variable resistors do. The AD5171 is programmed using a

2

2-wire I

C compatible digital control. It allows unlimited
adjustments before permanently setting the resistance value.
During the OTP activation, a permanent fuse blown command
is sent after the final value is determined; therefore freezing the
wiper position at a given setting (analogous to placing epoxy on

Rev. PrC

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

1

set-and-forget resistance

AD5171

a mechanical trimmer). When this permanent setting is
achieved, the value will not change regardless of supply
variations or environmental stresses under normal operating
conditions. To verify the success of permanent programming,
Analog Devices patterned the OTP validation such that the fuse
status can be discerned from two validation bits in read mode.

For applications that program AD5171 in the factories, Analog
Devices offers a device programming software, which operates
across Windows® 95 to XP® platforms including Windows NT®.
This software application effectively replaces the need for
external I
significantly reduces users’ development time.

An AD5171 evaluation kit is available, which includes the
software, connector, and cable that can be converted for the
factory programming applications.

The AD5171 is available in a compact SOT-23-8 package. All
parts are guaranteed to operate over the automotive
temperature range of −40°C to +125°C. Besides its unique OTP
feature, the AD5171 lends itself well to other general-purpose
digital potentiometer applications due to its temperature
performance, small form factor, and low cost.

1

One-time programmable (OTP) - Unlimited adjustments before permanent

setting.

2

The terms digital potentiometer and RDAC are used interchangeably.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

2

C controllers or host processors and therefore

SCL

SDA

AD0

V

GND

DD

I2C INTERFACE

AND

CONTROL LOGIC

FUSE

LINK

Functional Block Diagram

Figure 1.

1

W

2

AD5171

V

DD

TOP VIEW

3

GND

(Not to Scale)

4

SCL

Figure 2. Pin Configuration

WIPER

REGISTER

8

A

7

B

6

AD0

5

SDA

AD5171

03437-0-002

A

W

B

03437-0-001

AD5171

TABLE OF CONTENTS

AD5171—Electrical Characteristics .............................................. 3

I2C Controller Programming................................................ 15

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Functional Descriptions.......................... 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 11

One-Time Programming (OTP).............................................. 11

Determining the Variable Resistance and Voltage................. 11

Rheostat Mode Operation..................................................... 11

Potentiometer Mode Operation ........................................... 12

ESD Protection ........................................................................... 12

Terminal Voltage Operating Range.......................................... 13

Power-Up/Power-Down Sequences......................................... 13

Power Supply Considerations................................................... 13

Controlling the AD5171............................................................ 14

Software Programming ......................................................... 14

Controlling Two Devices on One Bus..................................... 16

Applications..................................................................................... 17

Programmable Voltage Reference (DAC) ............................... 17

Gain Control Compensation.................................................... 17

Programmable Voltage Source with Boosted Output............ 17

Level Shifting for Different Voltage Operation ...................... 17

Resistance Scaling ...................................................................... 17

Resolution Enhancement.......................................................... 18

RDAC Circuit Simulation Model............................................. 18

AD5171 Evaluation Board ........................................................ 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

Revision 0: Initial Version

Rev. PrC | Page 2 of 20

AD5171

ELECTRICAL CHARACTERISTICS

Table 1. 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ versions, VDD = 3 V to 5 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +125°C,
unless otherwise noted.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS RHEOSTAT MODE

Resistor Differential Nonlinearity2 R-DNL

, VA = No Connect,

R

WB

R

= 10 kΩ, 50 kΩ, and 100

AB

kΩ

, VA = No Connect, RAB = 5

R

WB

kΩ

Resistor Integral Nonlinearity2 R-INL

, VA = No Connect,

R

WB

= 10 kΩ, 50 kΩ, and 100 kΩ

R

AB

, VA = No Connect, RAB = 5

R

WB

kΩ
Nominal Resistor Tolerance3 ∆RAB/RAB –30 +30 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T 35 ppm/°C
Wiper Resistance RW V

DC CHARACTERISTICS POTENTIOMETER DIVIDER

= 5 V 60 115 Ω

DD

MODE (Specifications apply to all RDACs)

Resolution N 6 Bits
Differential Nonlinearity4 DNL –0.5 ±0.1 +0.5 LSB
Integral Nonlinearity4 INL –1 ±0.2 +1 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T Code = 0x20 5 ppm/°C
Full-Scale Error V
Zero-Scale Error V

Code = 0x3F –1.5 -0.5 +0 LSB

WFSE

WZSE

Code = 0x00, R

=10 kΩ,

AB

50 kΩ, and 100 kΩ

Code = 0x00, RAB = 5 kΩ 0 2 LSB
RESISTOR TERMINALS

Voltage Range5 V
Capacitance6 A, B C

With respect to GND VDD V

A, B, W

A, B

f = 1 MHz, measured to GND,

Code = 0x20
Capacitance6 W CW

f = 1 MHz, measured to GND,

Code = 0x20
Common-Mode Leakage ICM V

= VB = VDD/2 1 nA

A

DIGITAL INPUTS

Input Logic High (SDA and SCL) VIH 0.7 VDD VDD+0.5 V
Input Logic Low (SDA and SCL) VIL –0.5 0.3VDD V
Input Logic High (AD0) VIH V
Input Logic Low (AD0) VIL V
Input Current IIL V
Input Capacitance6 C

3 pF

IL

= 3 V 3.0 VDD V

DD

= 3 V 0 1.0 V

DD

= 0 V or 5 V ±1 µA

IN

DIGITAL OUTPUTS
Output Logic Low (SDA) VOL I
Three-State Leakage Current (SDA) IOZ V
Output Capacitance6 C

3 pF

OZ

= 6 mA 0.4 V

OL

= 0 V or 5 V ±1 µA

IN

POWER SUPPLIES

Power Supply Range VDD 2.7 5.5 V
OTP Power Supply7 V

DD_OTP

Supply Current IDD V
OTP Supply Current8 I
Power Dissipation9 P

V

DD_OTP

V

DISS

TA = 25°C 6 6.5 V

= 5 V or VIL = 0 V 4 8 µA

IH

= 6 V, TA = 25°C 100 mA

DD_OTP

= 5 V or VIL = 0 V, VDD = 5 V 0.02 0.04 mW

IH

Power Supply Sensitivity PSSR −0.025 +0.001 +0.025 %/%

–0.5 ±0.2 +0.5 LSB

–1 ±0.25 +1 LSB

–1 ±0.25 +1 LSB

–1.5 ±0.5 +1.5 LSB

0 0.5 1.5 LSB

25 pF

55 pF

Rev. PrC | Page 3 of 20

AD5171

S

Parameter Symbol Conditions Min Typ1 Max Unit

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_5k RAB = 5 kΩ, Code = 0x20 1500 kHz
BW_10k RAB = 10 kΩ, Code = 0x20 600 kHz
BW_50k RAB = 50 kΩ, Code = 0x20 110 kHz
BW_100k RAB = 100 kΩ, Code = 0x20 60 kHz

Total Harmonic Distortion THD

Adjustment Settling Time tS1

OTP Settling Time12 t

Power-up Settling Time—Post Fuses Blown tS2

Resistor Noise Voltage e

INTERFACE TIMING CHARACTERISTICS
(Applies to all parts

6,12

SCL Clock Frequency f

t

Bus Free Time between Start and Stop t1 1.3 µs

BUF

t

Hold Time (Repeated Start) t2

HD;STA

t

Low Period of SCL Clock t3 1.3 µs

LOW

t

High Period of SCL Clock t4 0.6 50 µs

HIGH

t

Setup Time for Start Condition t5 0.6 µs

SU;STA

t

Data Hold Time t6 0.9 µs

HD;DAT

t

Data Setup Time t7 0.1 µs

SU;DAT

tF Fall Time of Both SDA and SCL Signals t8 0.3 µs

tR Rise Time of Both SDA and SCL signals t9 0.3 µs

t

Setup Time for Stop Condition t10 0.6 µs

SU;STO

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, Wiper (VW) = No connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of

±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Different from operating power supply, power supply for OTP is used one-time only.

8

Different from operating current, supply current for OTP lasts approximately 400 ms for one-time needed only.

9

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

10

Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value result in the minimum overall power consumption.

11

All dynamic characteristics use VDD = 5 V.

12

Different from settling time after fuse is blown. The OTP settling time occurs once only.

6, 10, 11

0.05 %

5 µs

400 ms

5 µs

8 nV/√Hz

S_OTP

N_WB

=1 V rms, RAB = 10 kΩ,

V

A

= 0 V DC, f = 1 kHz

V

B

= 5 V ± 1 LSB error band,

V

A

V

= 0, measured at VW

B

= 5 V ± 1 LSB error band,

V

A

= 0, measured at VW

V

B

= 5 V ±1 LSB error band,

V

A

= 0, measured at VW

V

B

= 5 kΩ, f = 1 kHz,

R

AB

Code = 0x20

= 10 kΩ, f = 1 kHz,

R

AB

12 nV/√Hz

Code = 0x20

)

400 kHz

SCL

After this period, the first

0.6 µs

clock pulse is generated

t

8

t

9

t

6

SCL

t

2

t

3

t

8

DA

t

1

t

t

4

5

t

9

t

7

t

10

03437-0-024

PPS

Figure 3. Interface Timing Diagram

Rev. PrC | Page 4 of 20

AD5171

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VDD to GND –0.3, +7 V
VA, VB, VW to GND GND, VDD
Maximum Current

I

, IWA Pulsed

WB

I

Continuous (RWB ≤ 1 kΩ, A open)

WB

IWA Continuous (R

≤ 1 kΩ, B open)1

WA

±20 mA

1

±5 mA

±5 mA
Digital Inputs and Output Voltage to GND 0 V, VDD
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Thermal Resistance2 θJA 230°C/W

1

Maximum terminal current is bounded by the maximum applied voltage

across any two of the A, B, and W terminals at a given resistance, the
maximum current handling of the switches, and the maximum power
dissipation of the package. V

2

Package Power Dissipation = (TJ max – TA) / θ

DD

= 5 V.

300°C

215°C

220°C

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. PrC | Page 5 of 20

AD5171

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

8

A

7

B

6

AD0

5

SDA

03437-0-003

V

DD

GND

SCL

W

1

2

AD5171

TOP VIEW

3

(Not to Scale)

4

Figure 4. SOT-23-8

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 W Wiper Terminal W. GND ≤ VW ≤ VDD.
2 VDD

Positive Power Supply. Specified for operation from 2.7 V to 5.5 V. For OTP programming, V

minimum of 6 V and 100 mA driving capability.
3 GND Common Ground.
4 SCL Serial Clock Input. Requires pull-up resistor.
5 SDA Serial Data Input/Output. Requires pull-up resistor.
6 AD0 I2C Device Address Bit. Allows maximum of two AD5171s to be addressed.
7 B Resistor Terminal B. GND ≤ VB ≤ VDD.
8 A Resistor Terminal A. GND ≤ VA ≤ VDD.

needs to be a

DD

Rev. PrC | Page 6 of 20