ANALOG DEVICES AD5116 Service Manual

Single-Channel, 64-Position, Push Button,

V

±8% Resistor Tolerance, Nonvolatile Digital Potentiometer

Data Sheet

FEATURES

Nominal resistor tolerance error: ±8% maximum
Wiper current: ±6 mA
Rheostat mode temperature coefficient: 35 ppm/°C
Low power consumption: 2.5mA max @ 2.7 V and 125°C
Wide bandwidth: 4 MHz (5 kΩ option)
Power-on EEPROM refresh time < 50 μs
50-year typical data retention at 125°C
1 million write cycles

2.3 V to 5.5 V supply operation
Built-in adaptive debouncer
Wide operating temperature: −40°C to +125°C
Thin, 2 mm × 2 mm × 0.55 mm 8-lead LFCSP package

APPLICATIONS

Mechanical potentiometer replacement
Portable electronics level adjustment
Audio volume control
Low resolution DAC
LCD panel brightness and contrast control
Programmable voltage to current conversion
Programmable filters, delays, time constants
Feedback resistor programmable power supply
Sensor calibration

AD5116

FUNCTIONAL BLOCK DIAGRAM

DD

DATA

DATA

EEPROM

RDAC

REGISTER

AD5116

A
W
B

09657-001

CONTROL

LOGIC

V

DD

ASE

PU

PD

BLOCK

ADAPTIVE

DEBOUNCER

Figure 1.

GND

Table 1. NVM ±8% Resistance Tolerance Family

Model Resistance (kΩ) Position Interface

AD5110 10, 80 128 I2C
AD5111 10, 80 128 Up/down
AD5112 5, 10, 80 64 I2C
AD5113 5, 10, 80 64 Up/down
AD5116 5, 10, 80 64 Push button
AD5114 10, 80 32 I2C
AD5115 10, 80 32 Up/down

GENERAL DESCRIPTION

The AD5116 provides a nonvolatile digital potentiometer
solution for 64-position adjustment applications, offering
guaranteed low resistor tolerance errors of ±8% and up to
±6 mA current density in the A, B, and W pins. The low resistor
tolerance, low nominal temperature coefficient, and high
bandwidth simplify open-loop applications, as well as tolerance
matching applications.

The new low A-W and B-W resistance feature minimizes
the wiper resistance in the extremes of the resistor array to
typically 45 Ω.

A simple push button interface allows manual control with
just two external push button switches. The AD5116 is designed
with a built-in adaptive debouncer that ignores invalid bounces

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

due to contact bounce (commonly found in mechanical
switches). The debouncer is adaptive, accommodating a
variety of push buttons.

The AD5116 can automatically save the last wiper position into
EEPROM, making it suitable for applications that require a
power-up in the last wiper position, for example, audio
equipment.

The AD5116 is available in a 2 mm × 2 mm 8-lead LFCSP
package. The part is guaranteed to operate over the extended
industrial temperature range of −40°C to +125°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011–2012 Analog Devices, Inc. All rights reserved.

AD5116 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics ............................................................. 3

Interface Timing Specifications .................................................. 5

Timing Diagrams .......................................................................... 5

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Test Circuits ..................................................................................... 12

Theory of Operation ...................................................................... 13

RDAC Register ............................................................................ 13

EEPROM ..................................................................................... 13

Automatic Save Enable .............................................................. 13

End Scale Resistance Indicator ................................................. 14

RDAC Architecture .................................................................... 14

Programming the Variable Resistor ......................................... 14

Programming the Potentiometer Divider ............................... 15

Terminal Voltage Operating Range ......................................... 15

Power-Up Sequence ................................................................... 15

Layout and Power Supply Biasing ............................................ 15

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

REVISION HISTORY

4/12—Rev. 0 to Rev. A

Changes to Features Section............................................................ 1

Changes to Positive Supply Current, Table 2 ................................ 4

Changes to Ordering Guide .......................................................... 16

10/11—Revision 0: Initial Version

Rev. A | Page 2 of 16

Data Sheet AD5116

Wiper Resistance

RW

Code = zero scale

70

140

Ω

R

=10 kΩ

−1.5

LSB

RAB = 80 kΩ

−1.5 +1.5

mA

VOH

I

= 2 mA, VDD = 5 V

4.8

V

A

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

5 kΩ, 10 kΩ, and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.

Table 2.

Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution N 6 Bits
Resistor Integral Nonlinearity2 R-INL RAB = 5 kΩ, VDD = 2.3 V to 2.7 V −2.5 ±0.5 +2.5 LSB
RAB = 5 kΩ, VDD = 2.7 V to 5.5 V −1 ±0.25 +1 LSB
RAB = 10 kΩ −1 ±0.25 +1 LSB
RAB = 80 kΩ −0.25 ±0.1 +0.25 LSB
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance ΔRAB/RAB −8 +8 %
Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C

RBS Code = bottom scale 45 80 Ω
RTS Code = top scale 70 140 Ω

DC CHARACTERISTICS—POTENTIOMETER

DIVIDER MODE
Integral Nonlinearity

4

Differential Nonlinearity4
Full-Scale Error V

R
Zero-Scale Error V
R
R
Voltage Divider Temperature Coefficient

RESISTOR TERMINALS

Maximum Continuous IA, IB, and IW Current3

R-DNL −1 ±0.25 +1 LSB

INL −0.5 ±0.15 +0.5 LSB
DNL −0.5 ±0.15 +0.5 LSB

R

WFSE

R

WZSE

3

(ΔVW/VW)/ΔT × 106 Code = half scale ±10 ppm/°C

R

= 5 kΩ −2.5 LSB

AB

AB

= 80 kΩ −1 LSB

AB

= 5 kΩ +1.5 LSB

AB

=10 kΩ +1 LSB

AB

= 80 kΩ +0.25 LSB

AB

= 5 kΩ, 10 kΩ −6 +6 mA

AB

Terminal Voltage Range5 GND VDD V
Capacitance A, Capacitance B

Capacitance W

3, 6

3, 6

Common-Mode Leakage Current3

, CB f = 1 MHz, measured to GND,

C

A

code = half scale, V

= VB = 2.5 V

or V

W

f = 1 MHz, measured to GND,

C

W

code = half scale, V

V

= VW = VB 50 nA

A

= VA = 2.5 V

W

= VB = 2.5 V

A

20 pF

35 pF

DIGITAL INPUTS (PU AND PD)

Input Logic3

High V

Low V
Input Current3
Input Capacitance3

DIGITAL OUTPUT (ASE)

Output High Voltage3
Output Current3
Three-State Leakage Current3
Input Capacitance3

2 V

INH

0.8 V

INL

±1 µA

I

N

5 pF

C

IN

SINK

VDD = 5 V 16 mA

I

O

±1 µA

I

OZ

5 pF

C

IN

Rev. | Page 3 of 16

AD5116 Data Sheet

Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit

POWER SUPPLIES

Single-Supply Power Range 2.3 5.5 V
Positive Supply Current IDD V
V
V
EEMEM Store Current
EEMEM Read Current

3, 7

3, 8

Power Dissipation9 P
Power Supply Rejection3

I

DD_NVM_STORE

I

DD_NVM_READ

DISS

PSR ∆V

2 mA

320 μA

V

R
R
R

DYNAMIC CHARACTERISTICS

3, 10

Bandwidth BW Code = half scale − 3 dB
R
R
R
Total Harmonic Distortion THD VA = VDD/2 + 1 V rms, VB = VDD/2,

R
R
R
VW Settling Time ts V

R
R
R
Resistor Noise Density e

Code = half scale, TA = 25°C,

N_WB

R
R
R

FLASH/EE MEMORY RELIABILITY3

Endurance11 T
100 kCycles
Data Retention12 50 Years

1

Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and V

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.8 × VDD/RAB.

3

Guaranteed by design and characterization, not subject to production test.

4

INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.

6

CA is measured with VW = VA = 2.5 V, CB is measured with VW = VB = 2.5 V, and CW is measured with VA = VB = 2.5 V.

7

Different from operating current; supply current for NVM program lasts approximately 30 ms.

8

Different from operating current; supply current for NVM read lasts approximately 20 μs.

9

P

is calculated from (IDD × VDD).

DISS

10

All dynamic characteristics use VDD = 5.5 V, and V

11

Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.

12

Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV

LOGIC

= 5 V.

derates with junction temperature in the Flash/EE memory.

= 5 V 0.75 3.5 mA

DD

= 2.7 V 2.5 mA

DD

= 2.3 V 2.4 mA

DD

= V

IH

AB

AB

AB

AB

AB

AB

or VIL = GND 5 μW

LOGIC

/∆VSS = 5 V ± 10%

DD

= 5 kΩ −43 dB
=10 kΩ −50 dB
= 80 kΩ −64 dB

= 5 kΩ 4 MHz
= 10 kΩ 2 MHz
= 80 kΩ 200 kHz

f = 1 kHz, code = half scale

= 5 kΩ −75 dB

AB

= 10 kΩ −80 dB

AB

= 80 kΩ −85 dB

AB

= 5 V, VB = 0 V, ±0.5 LSB error

A

band

= 5 kΩ 2.5 μs

AB

= 10 kΩ 3 μs

AB

= 80 kΩ 10 μs

AB

f = 100 kHz

= 5 kΩ 7 nV/√Hz

AB

= 10 kΩ 9 nV/√Hz

AB

= 80 kΩ 20 nV/√Hz

AB

= 25°C 1 MCycles

A

= 5 V.

LOGIC

Rev. A | Page 4 of 16

Data Sheet AD5116

A

INTERFACE TIMING SPECIFICATIONS

VDD = 2.3 V to 5.5 V; all specifications T

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit Description

t1 8 ms Debounce time
t2 1 sec Manual to auto scan time
t3 140 ms Auto scan step
t4

t5
t

EEPROM_PROGRAM

t

POWER_UP

1

EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.

2

Maximum time after VDD is equal to 2.3 V.

1

15 50 ms Memory program time

2

50 μs Power-on EEPROM restore time

= 0 V, PD = GND, PU = GND

ASE

= VDD

ASE

TIMING DIAGRAMS

t

1

PU

PD (LOW)

R

W

Figure 2. Manual Increment Mode Timing

MIN

to T

, unless otherwise noted.

MAX

09657-002

1 sec Auto save execute time
8 ms Low pulse time to manual storage

PD/PU (LOW)

t

EEPROM

PROGRAM

DATA NEW DATA

ASE

EEPROM

t

5

Figure 5. Manual Save Mode Timing

09657-005

t

1

PU

PD (LOW)

R

W

t

2

Figure 3. Auto Increment Mode Timing

t

1

PD

R

W

ASE (LOW)

EEPROM DATA NEW DATA

t

EEPROM

t

4

PROGRAM

Figure 4. Auto Save Mode Timing

t

1

t

3

09657-003

PD

R

ASE

RW= 45Ω

W

09657-006

Figure 6. End Scale Indication Timing

9657-004

Rev. | Page 5 of 16

AD5116 Data Sheet

A

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND –0.3 V to +7.0 V
VA, VW , VB to GND GND − 0.3 V to VDD + 0.3 V
IA, IW , IB

Pulsed1

Frequency > 10 kHz

RAW = 5 kΩ and 10 kΩ ±6 mA/d2
RAW = 80 kΩ

±1.5 mA/d

2

Frequency ≤ 10 kHz

RAW = 5 kΩ and 10 kΩ
RAW = 80 kΩ

±6 mA/√d
±1.5 mA/√d

2

2

Continuous

RAW = 5 kΩ and 10 kΩ ±6mA
RAW = 80 kΩ ±1.5mA

Push Button Inputs −0.3 V to +7 V or VDD + 0.3 V

(whichever is less)
Operating Temperature Range3 −40°C to +125°C
Maximum Junction Temperature (TJ Max) 150°C
Storage Temperature Range −65°C to +150°C
Reflow Soldering

Peak Temperature 260°C
Time At Peak Temperature 20 sec to 40 sec

Package Power Dissipation (TJ max − TA)/θJA

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Pulse duty factor.

3

Includes programming of EEPROM memory.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is defined by JEDEC specification JESD-51, and the value is
dependent on the test board and test environment.

Table 5. Thermal Resistance

Package Type θJA θ

8-Lead LFCSP 901 25 °C/W

1

JEDEC 2S2P test board, still air (0 m/sec air flow).

Unit

JC

ESD CAUTION

Rev. | Page 6 of 16

Data Sheet AD5116

AD5116

TOP VIEW

(Not to S cale)

NOTES

1. THE EXPOSED PAD IS INTERNALLY
FLOATING.

09657-007

3 W
4 B

1V

DD

2 A

6 PD
5 GND

8
7 PU

ASE

6

PD

Push-Down Pin. Connect to the external push button. Active high. An internal 100 kΩ pull-down resistor is

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 7. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 VDD Positive Power Supply. This pin should be decoupled with 0.1µF ceramic capacitors and 10 µF capacitors.
2 A Terminal A of RDAC. GND ≤ VA ≤ VDD.
3 W Wiper terminal of RDAC. GND ≤ VW ≤ VDD.
4 B Terminal B of RDAC. GND ≤ VB ≤ VDD.
5 GND Ground Pin.

connected to GND.

7 PU

Push-Up Pin. Connect to the external push button. Active high. An internal 100 kΩ pull-down resistor is
connected to GND.

8

ASE Automatic Save Enable. Automatic save enable is configured at power-up. Active low. This pin requires a pull

resistor connected between V

or GND. If ASE is enabled, this pin also indicates when the end scale (maximum

DD

or minimum resistance) has been reached.

EPAD Exposed Pad. The exposed pad is internally floating.

Rev. | Page 7 of 16

AD5116 Data Sheet

–0.06

–0.04

–0.02

0

0.02

0.04

0.06

0.08

0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63

5kΩ, –40°C
5kΩ, +25°C
5kΩ, +125°C
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C

CODE (Decimal)

R-INL (LSB)

09657-008

5kΩ, –40°C
5kΩ, +25°C
5kΩ, +125°C
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C

–0.08

–0.06

–0.04

–0.02

0

0.02

0.04

0.06

0.08

0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63

CODE (Decimal)

INL (LSB)

09657-009

09657-010

–100

0

100

200

300

SUPPLY CURRENT (nA)

400

500

600

700

800

–40 –25 –10 5 20 35

TEMPERATURE (°C)

50 65 80 95 110 125

VDD= 2.3V
V

DD

= 3.3V

V

DD

= 5V

0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63

5kΩ, –40°C

5kΩ, +25°C 5kΩ, +125°C

10kΩ, –40°C

10kΩ, +25°C

10kΩ, +125°C

80kΩ, –40°C 80kΩ, + 25°C 80kΩ, +125°C

–0.07

–0.06

–0.05

–0.04

–0.03

–0.02

–0.01

0

0.01

0.02

CODE (Decimal )

R-DNL (LSB)

09657-011

–0.06

–0.05

–0.04

–0.03

–0.02

–0.01

0

0.01

0.02

0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63

5kΩ, –40°C

5kΩ, +25°C 5kΩ, +125°C

10kΩ, –40°C

10kΩ, +25°C

10kΩ, +125°C

80kΩ, –40°C

80kΩ, +25°C 80kΩ, +125° C

CODE (Decimal )

DNL (LSB)

09657-012

0

0.2

0.4

0.6

0.8

1.0

1.2

0.05 0.65 1.25 1.85 2.45 3.05

3.65

4.25

4.85

DIGITAL INPUT VOLTAGE (V)

SUPPLY CURRENT (mA)

VDD = 5V
VDD = 3.3V
V

DD

= 2.3V

TA = 25°C

09657-013

A

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 8. R-INL vs. Code

Figure 9. INL vs. Code

Figure 11. R-DNL vs. Code

Figure 12. DNL vs. Code

Figure 10. Supply Current vs. Temperature

Figure 13. Supply Current (IDD) vs. Digital Input Voltage

Rev. | Page 8 of 16

Data Sheet AD5116

0

–60

–50

–40

–30

–20

–10

100M10M1M100k10k

GAIN (dB)

FREQUENCY (Hz )

0x20
0x10
0x08
0x04

0x02
0x01

0x00

09657-014

–60

–50

–40

–30

–10

0

10k 1M100k

GAIN (dB)

FREQUENCY (Hz)

–20

–80

–70

0x20

0x08

0x02
0x01

0x04

0x00

0x10

09657-015

0

20

40

60

80

100

120

140

160

180

200

10kΩ
80kΩ
5kΩ

V

DD

= 5V

RHEOSTAT MODE TEMPCO (ppm/°C)

CODE (Decimal )

0 10 20 30 40 50 60

09657-016

–50

–40

–30

–10

0

1M 10M100k10k

GAIN (dB)

FREQUENCY ( Hz )

–20

–70

–60

0x20

0x08

0x02
0x01

0x04

0x00

0x10

09657-017

–80

–70

–60

–50

–40

–30

–20

–10

0

10k 100k 1M 10M

PHASE (Degrees)

FREQUENCY (Hz)

FULL SCALE
HALF SCALE
QUARTER SCAL E

RAB = 10kΩ

09657-018

0

20

40

60

80

100

120

140

160

180

200

POTENTIOMETER MODE TEMPCO (ppm/°C)

10kΩ
80kΩ
5kΩ

V

DD

= 5V

CODE (Decimal)

0 10 20 30 40 50 60

09657-019

A

Figure 14. 5 kΩ Gain vs. Frequency vs. Code

Figure 15. 80 kΩ Gain vs. Frequency vs. Code

Figure 17. 10 kΩ Gain vs. Frequency vs. Code

Figure 18. Normalized Phase Flatness vs. Frequency

Figure 16. Rheostat Mode Tempco ΔRWB/ΔT vs. Code

Figure 19. Potentiometer Mode Tempco ΔRWB/ΔT vs. Code

Rev. | Page 9 of 16

AD5116 Data Sheet

0

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

THD + N (dB)

FREQUENCY (Hz)

20 200 2k 20k 200k

10kΩ

5kΩ

80kΩ

09657-020

VDD = 5V
V

A

= 2.5V + 1V

RMS

V

B

= 2.5V

CODE = HALF S CALE
NOISE F ILTER = 22kHz

0

10

20

30

40

50

60

70

BANDWIDTH (MHz )

80

5k + 250pF
10k + 75pF
10k + 150pF
10k + 250pF
80k + 0pF
80k + 75pF

80k + 150pF
80k + 250pF
5k + 0pF
5k + 75pF
5k + 150pF
10k + 0pF

CODE (Decimal)

0 10 20 30 40 50 60

09657-021

0

30

60

90

INCREMENTAL WIPER O N RE S ISTANCE (Ω)

120

150

0 1 2 3

V

DD

(V)

4 5 6

5.5V

5V

3.3V

2.7V

2.3V

T

A

= 25°C

09657-022

THD + N (dB)

AMPLITUDE ( V rms)

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

0.001 0.01 0.1 1

10kΩ

5kΩ

80kΩ

09657-023

V

DD

= 5V

V

A

= 2.5V + V

IN

VB = 2.5V

f

IN

= 1kHz
CODE = HALF S CALE
NOISE FILTER = 22kHz

–0.10

–0.05

0

0.05

0.10

0.15

RELATIVE VOLTAGE (V)

0.20

0.25

0.30

0.35

–1 1 3

5

TIME (µs)

7 9

5kΩ
10kΩ
80kΩ

V

DD

= 5V

V

A

= V

DD

V

B

= GND

09657-024

0

0.2

0.4

0.6

0.8

1.0

1.2

0

0.0005

0.0010

0.0015

0.0020

0.0025

–400–500–600 –300 –200 –100 0 100 200 300 400 500 600

CUMULATIVE PROBABILITY

PROBABILITY DENSITY

RESISTOR DRIFT (ppm)

09657-047

A

Figure 20. Total Harmonic Distortion + Noise (THD + N) vs. Frequency

Figure 23. Total Harmonic Distortion + Noise (THD + N) vs. Amplitude

Figure 21. Maximum Bandwidth vs. Code vs. Net Capacitance

Figure 22. Incremental Wiper on Resistance vs. V

Figure 24. Maximum Transition Glitch

DD

Rev. | Page 10 of 16

Figure 25. Resistor Lifetime Drift

Data Sheet AD5116

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (Hz)

PSRR (dB)

10 100 1k 10k 100k 1M

5kΩ
10kΩ
80kΩ

09657-026

V

DD

= 5V ± 10% AC

V

A

= 4V

V

B

= GND
HALF SCALE
T

A

= 25°C

–0.5

–0.4

–0.3

–0.2

–0.1

0

0.1

0.2

0.3

0.4

10kΩ
80kΩ
5kΩ

2.50.6 1.2 1.80

VOLTAGE (mV)

TIME (µs)

V

DD

= 5V

V

A

= V

DD

V

B

= GND

09657-027

–70

–60

–50

–40

–30

–20

–10

0

1k 10k 1M 10M

GAIN (dB)

FREQUENCY (Hz)

5kΩ
10kΩ
80kΩ

09657-028

0

1

2

3

4

5

6

7

THEORETICAL I

MAX

(mA)

10kΩ
80kΩ
5kΩ

CODE (Decimal )

0 10 20 30 40 50 60

09657-029

0

2

4

6

8

10

12

14

16

18

20

0 1 2 3 4 5

CURRENT (mA)

V

DD

(V)

T

A

= 25°C

09657-044

0

1

2

3

4

5

6

7

8

–40 –20 0 20 40 60 80 100 120

CURRENT (mA)

TEMPERATURE (°C)

VDD = 3V

09657-045

A

Figure 26. Power Supply Rejection Ratio (PSRR) vs. Frequency

Figure 27. Digital Feedthrough

Figure 29. Theoretical Maximum Current vs. Code

Figure 30. Maximum

ASE

Output Current vs. Voltage

Figure 28. Shutdown Isolation vs. Frequency

Figure 31. Maximum

ASE

Output Current vs. Temperature

Rev. | Page 11 of 16

AD5116 Data Sheet

V+=V

V

O

V

V

A

TEST CIRCUITS

Figure 32 to Figure 37 define the test conditions used in the Specifications section.

NC

DUT
A

W

B

NC = NO CONNECT

Figure 32. Resistor Position Nonlinearity Error

(Rheostat Operation: R-INL, R-DNL)

I

W

V+

V

MS

09657-030

~

A

V

A

DD

W

B

V

MS

V+=V

± 10%

DD

PSRR (dB) = 20 log

∆V

PSS (%/%) =

∆V

MS

DD

∆V

MS

∆V

DD

%

%

09657-033

Figure 35. Power Supply Sensitivity (PSS, PSRR)

DUT

A

V+

W

B

DD

1LSB = V+/2

V

MS

Figure 33. Potentiometer Divider Nonlinearity Error (INL, DNL)

NC

DUT

A

W

B

NC = NO CO NNECT

I

WB

GND TO V

=

R

W

+

–

DD

Figure 34. Wiper Resistance

0.1V

0.1V

A

N

09657-031

FFSET

GND

V

IN

DUT

W

B

2.5V

+15

OP42

–15V

V

OUT

09657-034

Figure 36. Gain and Phase vs. Frequency

DD

I

WB

09657-032

V

DD

GND

DUT

V

DD

GND

A

B

I

CM

W

GND

GND

V

DD

09657-035

Figure 37. Common-Mode Leakage Current

Rev. | Page 12 of 16

09657-036

AD5116

100kΩ

ASE

GND

09657-037

AD5116

100kΩ

ASE

V

DD

V

DD

A

Data Sheet AD5116

THEORY OF OPERATION

The AD5116 digital programmable resistor is designed to
operate as a true variable resistor for analog signals within
the terminal voltage range of GND < V

< VDD. The resistor

TERM

wiper position is determined by the RDAC register contents.
The RDAC register is a standard logic register; there is no
restriction on the number of changes allowed.

The RDAC register can be programmed with any position
setting using the push button interface. Once a desirable wiper
position is found, this value can be stored in the EEPROM
memory. Thereafter, the wiper position is always restored to
that position for subsequent power-up. The storing of EEPROM
data takes approximately 20 ms; during this time, the device
is locked and does not accept any new operation, thus
preventing any changes from taking place.

The AD5116 is designed to support external push buttons
(tactile switches) directly, as shown in Figure 1.

RDAC REGISTER

The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register
is 0x20, the wiper is connected to midscale of the variable
resistor. The RDAC register is controlled using the PD and PU
push buttons. The step-up and step-down operations require
the activation of the PU (push-up) and PD (push-down) pins.
These pins have 100 kΩ internal pull-up resistors that PU and
PD activate at logic high. The following paragraphs explain how
to increment the RDAC register, but all the descriptions are
valid to decrement the RDAC register, swapping PU by PD.

Manual Increment

The AD5116 features an adaptive debouncer that monitors the
duration of the logic high level of PU signal between bounces. If
the PU logic high level signal duration is shorter than 8 ms, the
debouncer ignores it as an invalid incrementing command.
Whenever the logic high level of PU signal lasts longer than
8 ms, the debouncer assumes that the last bounce is met and,
therefore, increments the RDAC register by one step. The wiper
is incremented by one tap position, as shown in Figure 2.

Auto Scan Increment

If the PU button is held for longer than 1 second, continuously
holding it activates auto scan mode, and the AD5116 increments
the RDAC register by one step every 140 ms until PU is
released. Typical timing is shown in Figure 3.

Low Wiper Resistance Feature

The AD5116 includes extra steps to achieve a minimum wiper
resistance. Between Terminal W and Terminal B, this extra step
is called bottom scale and the wiper resistance decreases from
70 Ω to 45 Ω. Between Terminal A and Terminal W, this extra
step is called top scale and connects the A and W terminals,
reducing the 1 LSB resistor typical at full-scale code. These new
extra steps are loaded automatically in the RDAC register after
zero-scale or full-scale position has been reached. The extra

Rev. | Page 13 of 16

steps are not equal to 1 LSB, and are not included in the INL,
DNL, R-INL, and R-DNL specifications.

Whenever the minimum R

(= RBS) is reached, the resistance

WB

stops decrementing. Any continuous holding of the PD to logic
high simply elevates the supply current. When R
minimum resistance (= R

), continuous holding of PU only

TS

elevates the supply current.

EEPROM

The AD5116 contains an EEPROM memory that allows
wiper position storage. Once a desirable wiper position is
found, this value can be saved into the EEPROM. Thereafter,
the wiper position will always be set at that position for any
future on-off-on power supply sequence.

AUTOMATIC SAVE ENABLE

At power-up, the AD5116 checks the level in the
pin is pulled low, as shown in Figure 38, the automatic store is
enabled. If the pin is pulled high, as shown in Figure 39,
automatic store is disabled and the RDAC register should be
stored manually. During the storage cycle, the device is locked
and does not accept any new operation preventing any changes
from taking place.

Figure 38. Automatic Store Enables

Auto Save

If there is no activity on inputs during 1 second, the AD5116
stores the RDAC register data into EEPROM, as shown in
Figure 4.

Manual Store

The storage is controlled by the
an adaptive debouncer. If the
8 ms, the

AD5116 saves the RDAC register data into EEPROM,

ASE

pin, which is connected to

ASE

pin is pulled low longer than

as shown in Figure 5.

Figure 39. Automatic Store Disables with Manual Storage

Push Button

reaches the

AW

ASE

pin. If the

AD5116 Data Sheet











A

END SCALE RESISTANCE INDICATOR

When the auto save mode is enabled, the

when the RDAC register reaches the maximum or minimum

scale. The AD5116 pulls the

ASE

pin high and holds it as long
as PD or PU is active, and the part is placed in the end scale
resistance (R

or RBS), as shown in Figure 6. The typical pin

TS

configuration is shown in Figure 40.

When the part is placed at the end of the resistance scale (R

), the

BS

ASE

pin is pulled high during the debounce time, until

R
the RDAC register is incremented (R
activating PU or PD.

ASE

100kΩ

Figure 40. Typical End Scale Indicator Circuit

ASE

pin also indicates

) or decremented (RTS) by

BS

AD5116

GND

9657-038

or

TS

RDAC ARCHITECTURE

To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5116 employs a two-stage
segmentation approach as shown in Figure 41. The AD5116
wiper switch is designed with the transmission gate CMOS
topology and with the gate voltage derived from V

6-BIT

ADDRESS

DECODER

A

B

Figure 41. Simplified RDAC Circuit

TS

R

L

R

L

R

W

R

W

R

L

R

L

BS

Top Scale/Bottom Scale Architecture

In addition, the AD5116 includes a new feature to reduce the
resistance between terminals. These extra steps are called
bottom scale and top scale. At bottom scale, the typical wiper
resistance decreases from 70 Ω to 45 Ω. At top scale, the
resistance between Terminal A and Terminal W is decreased
by 1 LSB and the total resistance is reduced to 70 Ω. The extra
steps are not equal to 1 LSB and are not included in the INL,
DNL, R-INL, and R-DNL specifications.

.

DD

S

W

W

09657-039

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation—±8% Resistor Tolerance

The AD5116 operates in rheostat mode when only two terminals
are used as a variable resistor. The unused terminal can be
floating or tied to the W terminal as shown in Figure 42.

A

W

B

Figure 42. Rheostat Mode Configuration

Th e nom i na l re s is t an c e b et w ee n Ter m in a l A a nd Te rm i na l B,
R

, is available in 5 k, 10 k, and 80 k and has 64 tap points

AB

accessed by the wiper terminal. The 6-bit data in the RDAC
latch is decoded to select one of the 64 possible wiper settings.
The general equation for determining the digitally programmed
output resistance between the W terminal and B terminal is:

RR

WB

WB

Bottom scale (1)

BS

D

DR 64)(

where:
D is the decimal equivalent of the binary code in the 6-bit
RDAC register.

R

is the end-to-end resistance.

AB

R

is the wiper resistance at bottom scale.

BS

Similar to the mechanical potentiometer, the resistance of
the RDAC between the W terminal and the A terminal also
produces a digitally controlled complementary resistance, R

starts at the maximum resistance value and decreases as the

R

WA

data loaded into the latch increases. The general equation for
this operation is:

RRR

W

ABAW

64

DR 



)(

64

RR

AW

Top scale (5)

TS

where:
D is the decimal equivalent of the binary code in the 6-bit
RDAC register.

R

is the end-to-end resistance.

AB

is the wiper resistance.

R

W

R

is the wiper resistance at top scale.

TS

Regardless of which setting the part is operating in, take care
to limit the current between the A terminal to B terminal, W
terminal to A terminal, and W terminal to B terminal, to the
maximum continuous current or pulsed current specified in
Table 4. Otherwise, degradation or possible destruction of
the internal switch contact can occur.

A

W

B

From 0 to 64 (2)

RR

W

AB

A

W

B

09657-040

WA

Bottom scale (3)

D

ABAW

From 0 to 63 (4)

RR

W

.

Rev. | Page 14 of 16

Data Sheet AD5116

V

A

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A that is proportional to the input
voltage at A to B, as shown in Figure 43. Unlike the polarity of
V

to GND, which must be positive, voltage across A-to-B, W-

DD

to-A, and W-to-B can be at either polarity.

V

IN

A

W

V

OUT

B

09657-041

Figure 43. Potentiometer Mode Configuration

If ignoring the effect of the wiper resistance for simplicity,
connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 5 V. The general equation defining the
output voltage at V

, with respect to ground for any valid

W

input voltage applied to Terminal A and Terminal B, is:

DR

DR

)(

W

R

WB

DV 

)( (6)

V

AB

A

AW

)(

V

R

AB

B

where:

RWB(D) can be obtained from Equation 1 or Equation 2.
RAW(D) can be obtained from Equation 3 to Equation 5 .

Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly
on the ratio of the internal resistors, R

and RWB, and not the

WA

absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.

TERMINAL VOLTAGE OPERATING RANGE

The AD5116 is designed with internal ESD diodes for
protection. These diodes also set the voltage boundary of
the terminal operating voltages. Positive signals present on
Ter min al A , Te rm i na l B, or Te rm i na l W t ha t ex c ee d V

DD

are
clamped by the forward-biased diode. There is no polarity
constraint between V
than V

or lower than GND.

DD

, VW, and VB, but they cannot be higher

A

POWER-UP SEQUENCE

Because of the ESD protection diodes that limit the voltage
compliance at Terminal A, Terminal B, and Terminal W (see
Figure 44), it is important to power on V

before applying

DD

any voltage to Terminal A, Terminal B, and Terminal W.
Otherwise, the diodes are forward-biased such that V

DD

is
powered on unintentionally and can affect other parts of the
circuit. Similarly, V
power-on sequence is in the following order: GND, V
V

A/VB/VW

. The order of powering VA, VB, and VW is not

important as long as they are powered on after V

should be powered down last. The ideal

DD

, and

DD

. The

DD

states of the PU and PD pins can be logic low or floating,
but they should not be logic high during power-on.

DD

A

W

B

GND

09657-042

Figure 44. Maximum Terminal Voltages Set by V

and VSS

DD

LAYOUT AND POWER SUPPLY BIASING

It is always a good practice to use compact, minimum lead
length layout design. The leads to the input should be as direct
as possible with a minimum conductor length. Ground paths
should have low resistance and low inductance. It is also good
practice to bypass the power supplies with quality capacitors.
Low equivalent series resistance (ESR) 1 μF to 10 μF tantalum
or electrolytic capacitors should be applied at the supplies to
minimize any transient disturbance and to filter low frequency
ripple. Figure 45 illustrates the basic supply bypassing config­uration for the AD5116.

AD5116

V

DD

+

C2

10µF

Figure 45. Power Supply Bypassing

C1

0.1µF

V

DD

GND

AGND

09657-043

Rev. | Page 15 of 16

AD5116 Data Sheet

OUTLINE DIMENSIONS

1.70

1.60

2.00

BSC SQ

1.50

5

0.50 BSC

8

0.175 REF

PIN 1 INDEX

AREA

0.60

0.55

0.50

SEATING

PLANE

TOP VIEW

0.30

0.25

0.20

0.425

0.350

0.275

0.05 MAX

0.02 NOM

0.20 REF

EXPOSED

PAD

4

BOTTOM VIEW

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NF IGURATI O N AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

1

1.10

1.00

0.90

1

P

N

I

A

R

O

T

N

I

D

C

I

)

5

1

.

0

R

(

07-11-2011-B

Figure 46. 8-Lead Lead Frame Chip Scale Package [LFCSP_UD]

2.00 mm × 2.00 mm Body, Ultra Thin, Dual Lead
(CP-8-10)

Dimensions shown in millimeters

ORDERING GUIDE

1, 2

Model

AD5116BCPZ5-RL7 5 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7G
AD5116BCPZ5-500R7 5 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7G
AD5116BCPZ10-RL7 10 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7F
AD5116BCPZ10-500R7 10 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7F
AD5116BCPZ80-RL7 80 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7H
AD5116BCPZ80-500R7 80 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7H
EVAL-AD5116EBZ Evaluation Board

1

Z = RoHS Compliant Part.

2

The EVAL-AD5116EBZ has an RAB of 10 kΩ.

RAB (kΩ) Resolution Temperature Range Package Description Package Option Branding Code

©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09657-0-4/12(A)

Rev. A | Page 16 of 16