Datasheet AD5066 Datasheet (ANALOG DEVICES)

Fully Accurate, 16-Bit, Unbuffered V

V

A

V

, Quad SPI

OUT

FEATURES

Low power quad 16-bit nanoDAC, ±1 LSB INL
Low total unadjusted error of ±0.1 mV typically
Low zero code error of 0.05 mV typically
Individually buffered reference pins

2.7 V to 5.5 V power supply
Specified over full code range of 0 to 65535
Power-on reset to zero scale or midscale
Per channel power-down with 3 power-down functions
Hardware

function to programmable code

CLR
Small 16-lead TSSOP

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources

GENERAL DESCRIPTION

The AD5066 is a low power, 16-bit quad-channel, unbuffered
voltage output nanoDAC offering relative accuracy specifica­tions of ±1 LSB INL with individual reference pins and can
operate from a single 2.7 V to 5.5 V supply. The AD5066 also
offers a differential accuracy specification of ±1 LSB DNL.
Reference buffers are also provided on-chip. The part uses a
versatile 3-wire, low power Schmitt trigger serial interface that
operates at clock rates up to 50 MHz and is compatible with
standard SPI®, QSPI™, MICROWIRE™, and most DSP interface
standards. The AD5066 incorporates a power-on reset circuit
that ensures the DAC output powers up to zero scale or
midscale and remains there until a valid write to the device
takes place.

with software

LDAC

override function

LDAC

Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP

AD5066

Total unadjusted error for the part is <0.8 mV. Zero code error
for the part is 0.05 mV typically.

The AD5066 contains a power-down feature that reduces the
current consumption of the device to typically 400 nA at 5 V
and provides software selectable output loads while in power­down mode.

The outputs of all DACs can be updated simultaneously using
the hardware
user software selectable DAC channels to update simultaneously.
There is also an asynchronous
software-selectable code—0 V, midscale, or full scale.

PRODUCT HIGHLIGHTS

1. Quad channel available in 16-lead TSSOP, ±1 LSB INL.

2. Individually buffered voltage reference pins.

3. TUE = ±0.8 mV max and zero code error = 0.1 mV max.

4. High speed serial interface with clock speeds up to 50 MHz.

5. Three power-down modes available to the user.

6. Reset to known output voltage (zero scale or midscale).

Table 1. Related Devices

Part No. Description

AD5666 Quad,16-bit buffered DAC,16 LSB INL, TSSOP
AD5025/AD5045/AD5065

AD5024/AD5044/AD5064
AD50621 Single, 16-bit nanoDAC, SOT-23
AD5063
AD5061 Single,16-bit nanoDAC, ±4 LSB INL, SOT-23
AD5040/AD5060

1

±1 LSB INL

LDAC

function, with the added functionality of

CLR

that clears all DACs to a

1

Dual,12-/14-/16-bit buffered nanoDAC,
TSSOP

1

Quad 16-bit nanoDAC, TSSOP

1

1

Single, 16-bit nanoDAC, MSOP

14-/16-bit nanoDAC, SOT-23

FUNCTIONAL BLOCK DIAGRAM

V

DD

AD5066

SCLK

SYNC

DIN

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

LDAC

INTERFACE

LOGIC

LDAC

CLR

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

POWER-ON RESET

POR

DAC

REGIS TER

DAC

REGIS TER

DAC

REGIS TER

DAC

REGIS TER

Figure 1.

REF

V

REF

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

B

REF

DAC A

DAC B

DAC C

DAC D

POWER-DOW N LOGI C

C V

D

REF

GND

V

A

OUT

B

V

OUT

V

C

OUT

V

D

OUT

06845-001

AD5066

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Characteristics ........................................................................ 4

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Terminolog y .................................................................................... 14

Theory of Operation ...................................................................... 15

Digital-to-Analog Converter .................................................... 15

DAC Architecture ....................................................................... 15

Reference Buffer ......................................................................... 15

Serial Interface ............................................................................ 15

Input Shift Register .................................................................... 15

Power-On Reset .......................................................................... 17

Clear Code Register ................................................................... 18

LDAC

Function ........................................................................... 18

Power Supply Bypassing and Grounding ................................ 19

Microprocessor Interfacing ....................................................... 19

Applications Information .............................................................. 21

Using a Reference as a Power Supply ....................................... 21

Bipolar Operation....................................................................... 21

Using the AD5066 with a Galvanically Isolated Interface .... 21

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 22

REVISION HISTORY

7/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD5066

SPECIFICATIONS

VDD = 2.7 V to 5.5 V, 2.0 V ≤ V

REF

A, V

REF

B, V

REF

C, V

D ≤ VDD − 0.4 V, all specifications T

REF

MIN

to T

, unless otherwise noted.

MAX

Table 2.

1

Parameter

STATIC PERFORMANCE

A Grade

Min Typ Max Min Typ Max

2

Resolution 16 16 Bits
Relative Accuracy (INL) ±0.5 ±4 ±0.5 ±1 LSB TA = −40°C to +105°C
±0.5 ±4 ±0.5 ±2 TA = −40°C to +125°C
Differential Nonlinearity (DNL) ±0.2 ±1 ±0.2 ±1 LSB
Total Unadjusted Error (TUE) ±0.1 ±0.8 ±0.1 ±0.8 mV VDD = 2.7 V, V
Zero-Code Error 0.05 0.1 0.05 0.1 mV All 0s loaded to the DAC register
Zero-Code Error Drift

3

±0.5 ±0.5 µV/°C
Full-Scale Error ±0.01 ±0.05 ±0.01 ±0.05 % FSR All 1s loaded to the DAC register
Gain Error ±0.005 ±0.05 ±0.005 ±0.05 % FSR
Gain Error Drift3
DC Crosstalk3

±0.5 ±0.5 ppm ppm of FSR/°C

1 5 1 5 V Due to single-channel full-scale

5 25 5 25 V Due to powering down (per channel)

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 V
DC Output Impedance (Normal

0 V

REF

8 8 kΩ Output impedance tolerance ± 10%

Mode)

DC Output Impedance DAC in power-down mode

Output Connected to 100 kΩ

100 100 kΩ Output impedance tolerance ± 20 kΩ

Network

Output Connected to 1 kΩ

1 1 kΩ Output impedance tolerance ± 400 Ω

Network
Power-Up Time4 2.9 2.9 µs
DC PSRR −120 −120 dB VDD ± 10%, DAC = full scale

REFERENCE INPUTS

Reference Input Range 2 V

− 0.4 2 VDD − 0.4 V

DD

Reference Current 0.002 ±1 0.002 ±1 µA Per DAC channel
Reference Input Impedance 40 40 MΩ Per DAC channel

LOGIC INPUTS3

Input Current5 ±1 ±1 µA
Input Low Voltage, V
Input High Voltage, V

0.8 0.8 V

INL

2.2 2.2 V

INH

Pin Capacitance 4 4 pF

POWER REQUIREMENTS

VDD 2.7 5.5 2.7 5.5 V All digital inputs at 0 V or VDD
DAC active, excludes load current
IDD V
Normal Mode6 2.5 3 2.5 3 mA
All Power-Down Modes7 0.4 0.4 µA

1

Temperature range is −40°C to +125°C, typical at 25°C.

2

Linearity calculated using a code range of 0 to 65,535; output unloaded.

3

Guaranteed by design and characterization; not production tested.

4

Time taken to exit power-down mode and enter normal mode, 32nd clock edge to 90% of DAC midscale value, output unloaded.

5

Current flowing into individual digital pins. VDD = 5.5 V; VREF = 4.096 V; Code = midscale.

6

Interface inactive. All DACs active. DAC outputs unloaded.

7

All four DACs powered down.

B Grade

1

Unit Conditions/Comments

V

REF

= 2 V

REF

output change

= VDD and VIL = GND

IH

Rev. 0 | Page 3 of 24

AD5066

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V, 2.0 V ≤ V

REF

A, V

REF

B, V

REF

C, V

D ≤ VDD − 0.4 V all specifications T

REF

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Parameter

1, 2

Min Ty p Max Unit Conditions/Comments3

DYNAMIC PERFORMACE

Output Voltage Settling Time 7.5 10 µs

¼ to ¾ scale settling to ±2 LSB, single channel update, output
unloaded

Output Voltage Settling Time 12 15 µs

¼ to ¾ scale settling to ±2 LSB, all channel update, output

unloaded
Slew Rate 1.7 V/µs
Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry
Reference Feedthrough −70 dB V

= 3 V ± 0.5 V p-p, frequency = 60 Hz to 20 MHz

REF

Digital Feedthrough 0.02 nV-sec
Digital Crosstalk 1.7 nV-sec
Analog Crosstalk 3.7 nV-sec
DAC-to-DAC Crosstalk 5.4 nV-sec
Total Harmonic Distortion −83 dB V

= 3 V ± 0.2 V p-p, frequency = 10 kHz

REF

Output Noise Spectral Density 30 nV/√Hz DAC code = 0x8000, 1 kHz
25 nV/√Hz DAC code = 0x8000, 10 kHz
Output Noise 4.7 V p-p 0.1 Hz to 10 Hz

1

Temperature range is −40°C to +125°C, typical at +25°C.

2

See the Terminology section.

3

Guaranteed by design and characterization; not production tested.

Rev. 0 | Page 4 of 24

AD5066

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2, VDD = 2.7 V to

5.5 V, all specifications T

Table 4.

Parameter1 Symbol Min Typ M ax Uni t
SCLK Cycle Time t1 20 ns
SCLK High Time t2 10 ns
SCLK Low Time t3 10 ns
SYNC to SCLK Falling Edge Set-Up Time
Data Set-Up Time t5 5 ns
Data Hold Time t6 5 ns
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC high time

Single Channel Update 2 µs

All Channel Update 8 µs
SYNC Rising Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SCLK Falling Edge to LDAC Rising Edge
CLR Pulse Width Low
SCLK Falling Edge to LDAC Falling Edge
CLR Pulse Activation Time

1

Maximum SCLK frequency is 50 MHz. Guaranteed by design and characterization; not production tested.

SCLK

SYNC

DIN

LDAC

to T

MIN

1

, unless otherwise noted. See Figure 2.

MAX

t

1

t

t

8

DB31

t

4

t

t

3

t

6

5

2

DB0

t

17 ns

4

t

5 30 ns

7

t

8

t

17 ns

9

t

20 ns

10

t

20 ns

11

t

10 ns

12

t

10 ns

13

t

10.6 µs

14

t

9

t

7

t

10

t

13

t

11

2

LDAC

t

CLR

V

OUT

1

ASYNCHRONOUS LDAC UPDATE MODE.

2

SYNCHRONOUS LDAC UPDATE MODE.

12

t

14

06845-003

Figure 2. Serial Write Operation

Rev. 0 | Page 5 of 24

AD5066

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
V

x to GND −0.3 V to VDD + 0.3 V

OUT

V

x to GND −0.3 V to VDD + 0.3 V

REF

Operating Temperature Range

Industrial −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ
TSSOP Package

Power Dissipation (TJ

θJA Thermal Impedance 150.4°C/W
Reflow Soldering Peak Temperature

SnPb 240°C

Pb-Free 260°C

) +150°C

MAX

− TA)/θJA

MAX

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 6 of 24

AD5066

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

LDAC

SYNC

V

REF

V

REF

V

OUT

OUT

POR

V

DD

B

A

A

C

1

2

3

AD5066

4

TOP VIEW

5

(Not to Scal e)

6

7

8

16

SCLK

15

DIN

14

GND

13

B

V

OUT

12

V

D

OUT

11

V

D

REF

10

CLR

9

C

V

REF

06845-004

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1

LDAC

Load DAC. Logic input. This is used to update the DAC register and, consequently, the analog outputs.
When tied permanently low, the addressed DAC register is updated on the falling edge of the 32
clock. If LDAC

is held high during the write cycle, the addressed DAC input shift register is updated but
the output is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated
simultaneously on the falling edge of LDAC.

2

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

SYNC

low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the
falling edges of the next 32 clocks. If SYNC

is taken high before the 32nd falling edge, the rising edge of

SYNC acts as an interrupt, and the write sequence is ignored by the device.

3 VDD

Power Supply Input. The AD5066 can be operated from 2.7 V to 5.5 V. Decouple the supply with a 10 µF
capacitor in parallel with a 0.1 µF capacitor to GND.

4 V
5 V
6 V
7 V
8 POR

B External Reference Voltage Input for DAC B.

REF

A External Reference Voltage Input for DAC A.

REF

A Unbuffered Analog Output Voltage from DAC A.

OUT

C Unbuffered Analog Output Voltage from DAC C.

OUT

Power-On Reset Pin. Tying this pin to GND powers the DAC outputs to zero scale on power-up. Tying
this pin to VDD powers the DAC outputs to midscale.

9 V
10

11 V
12 V
13 V

C External Reference Voltage Input for DAC C.

REF

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are

CLR

ignored. When CLR
contained in the CLR

D External Reference Voltage Input for DAC D.

REF

D Unbuffered Analog Output Voltage from DAC D.

OUT

B Unbuffered Analog Output Voltage from DAC B.

OUT

is activated, the input register and the DAC register are updated with the data

code register—zero, midscale, or full scale. Default setting clears the output to 0 V.

14 GND Ground Reference Point for All Circuitry on the Part.
15 DIN

Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.

16 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.

nd

Rev. 0 | Page 7 of 24

AD5066

TYPICAL PERFORMANCE CHARACTERISTICS

0.3

0.2

0.1

0

–0.1

–0.2

INL ERROR (LSB)

–0.3

VDD = 5V
V

= 4.096V

–0.4

–0.5

REF

T

= 25°C

A

0 10,000 20,000 30, 000 40,000 50,000 60,000

CODE

Figure 4. INL Error vs. Code

0.3
VDD = 5V

= 4.096V

V

REF

0.2

= 25°C

T

A

0.1

0

–0.1

DNL ERROR (LSB)

–0.2

–0.3

–0.4

0 10,000 20,000 30,000 40, 000 50, 000 60,000

CODE

Figure 5. DNL Error vs. Code

0.5

0.4

0.3

0.2

0.1

0

INL (LSB)

–0.1

–0.2

–0.3

VDD = 5V
T

–0.4

–0.5

6845-105

= 25°C

A

2345

MAX INL

MIN INL

REFERENCE VOLTAGE (V)

06845-108

Figure 7. INL vs. Reference Input Voltage

0.5

0.4

0.3

0.2

0.1

0

DNL (LSB)

–0.1

–0.2

–0.3

VDD = 5.5V

–0.4

T

= 25°C

A

–0.5

2345

06845-106

MAX DNL

MIN DNL

REFERENCE VOLTAGE (V)

06845-109

Figure 8. DNL vs. Reference Input Voltage

0.03

0.02

0.01

0

–0.01

–0.02

–0.03

TOTAL UNADJUSTED ERROR (mV)

–0.04

–0.05

–0.06

–0.07

VDD = 5V
V

= 4.096V

REF

T

= 25°C

A

0 10,000 20,000 30,000 40,000 50, 000 60,000

CODE

Figure 6. Total Unadjusted Error vs. Code

06845-107

Rev. 0 | Page 8 of 24

100

80

60

40

20

0

–20

–40

–60

TOTAL UNADJUST ED ERROR (µV)

VDD = 5.5V

–80

T

= 25°C

A

–100

234

MAX TUE

MIN TUE

REFERENCE VOL TAGE (V)

Figure 9. Total Unadjusted Error vs. Reference Input Voltage

5

6845-110

AD5066

0.010

0.005

0

GAIN ERROR (%FSR)

–0.005

V

= 5.5V

DD

T

= 25°C

A

–0.010

2345

REFERENCE VOLTAGE (V)

Figure 10. Gain Error Vs. Reference Input Voltage

06845-111

1.2

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL (LSB)

–0.4

–0.6

–0.8

–1.0

–1.2

VDD = 5V
V

= 4.096V

REF

–40 –20 0 20 40 60 80 100 120

MAX DNL

MIN DNL

TEMPERATURE (° C)

Figure 13. DNL vs. Temperature

06845-114

0.10

0.09

0.08

0.07

0.06

0.05

0.04

0.03

ZERO-SCALE ERROR (mV)

VDD = 5.5V

0.02

T

= 25°C

A

0.01

0

2345

REFERENCE VOL TAGE (V)

6845-112

Figure 11. Zero-Code Error Vs. Reference Input Voltage

1.2

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

= 5V

V

DD

V

= 4.096V

REF

–40 –20 0 20 40 60 80 100 120

MAX INL

MIN INL

TEMPERATURE (° C)

06845-113

Figure 12. INL vs. Temperature

100

80

60

40

20

0

–20

–40

–60

TOTAL UNADJUSTED ERROR (µV )

–80

–100

VDD = 5V
V

= 4.096V

REF

–40 –20 0 20 40 60 80 100 120

MAX TUE

MIN TUE

TEMPERATURE (° C)

Figure 14. Total Unadjusted Error vs. Temperature

50

40

30

20

10

0

–10

–20

–30

ZERO-SCALE ERROR (µV)

–40

–50

VDD = 5V

= 4.096V

V

REF

–40 –20 0 20 40 60 80 100 120

TEMPERATURE (° C)

Figure 15. Zero-Code Error vs. Temperature

06845-115

6845-116

Rev. 0 | Page 9 of 24

AD5066

R
%

0.0020

0.0015

0.0010

0.0005

0

–0.0005

GAIN ERROR (%F SR)

–0.0010

–0.0015

–0.0020

VDD = 5V
V

= 4.096V

REF

–40 –20 0 20 40 60 80 100 120

TEMPERATURE (° C)

Figure 16. Gain Error vs. Temperature

06845-117

7

VDD = 5V
DAC OUTPUT UNLOADED

6

T

= 25°C

A

5

4

HITS

3

2

1

0

2.45

2.50 2.55 2.60 2. 65 2.70

Figure 19. IDD Histogram VDD = 5.5 V

IDD POWER-UP (mA)

06845-120

0.010

0.005

FSR)

0

OR (

ER

–0.005

–0.010

VDD = 5V
V

= 4.096V

REF

T

= 25°C

A

2.7 3.2 3.7 4.2 4. 7 5.2
VDD (V)

FULL-SCALE ERROR

GAIN ERROR

Figure 17. Gain Error and Full-Scale Error vs. Supply Voltage

20

15

10

VDD = 5V

ZERO-SCALE Error (µV)

5

V

= 4.096V

REF

T

= 25°C

A

60

50

40

30

HITS

20

10

0

0.2 0.4 0.6

06845-118

I

POWERDOWN (µA)

DD

= 5V

V

DD

T

= 25°C

A

DAC OUTPUT UNLO ADED

+125°C IDD POWERDOW N
+25°C I

POWERDOWN

DD

–40°C I

POWERDOWN

DD

0.8 1.0

06845-139

Figure 20. IDD Power-Down Histogram

5

VDD = 5.5V
V

= 4.096V

REF

T

= 25°C

A

4

3

(mA)

DD

I

2

1

0

2.7 3.7 4.7
VDD (V)

Figure 18. Zero-Code Error vs. Supply Voltage

06845-119

0

0 10,000 20, 000 30,000 40,00 0

DAC CODE

Figure 21. IDD vs. Code

50,000 60,000

06845-121

Rev. 0 | Page 10 of 24

AD5066

5

VDD = 5.5V
V

= 4.096V

REF

T

= 25°C

A

CODE = MIDSCALE

4

3

(mA)

DD

I

2

1

0

–40 –20 0 20 40

TEMPERATURE (° C)

Figure 22. IDD vs. Temperature

5

V

= 4.096V

REF

= 25°C

T

A

CODE = MIDSCALE

4

3

(mA)

DD

I

2

1

0

2.7 3.0 3.5 4. 0 4.5
SUPPLY VOLTAGE (V)

Figure 23. IDD vs. Supply Voltage

60 80 100 120

06845-122

5.0 5.5

06845-123

3.5

1/4 TO 3/ 4

3.0

2.5

2.0

1.5

OUTPUT VOLTAGE (V)

1.0
VDD = 4.5V

= 4.096V

V

REF

0.5

OUTPUT AMPLIFIER = AD797

= 25°C

T

A

DAC LOAD = 9pF

0

012345678910

3/4 TO 1/ 4

TIME (µs)

Figure 25. Settling Time

V

DD

V

REF

V

OUT

V

= 4.096V

REF

T

= 25°C

A

CH1 2.00V

CH3 2.00V

CH2 2.00V M10.00ms A CH1 640mV

T 30.20%

Figure 26. POR to 0 V

6845-125

06845-126

10

VDD = 5.5V

= 4.096V

V

REF

= 25°C

T

A

8

6

(mA)

DD

I

4

2

0

0123456

DIGITAL INPUT VOLTAGE (V)

Figure 24. IDD vs. Digital Input Voltage

06845-124

Rev. 0 | Page 11 of 24

VDD = 5.5V
V

= 4.096V

REF

CH1 2.00V

CH3 2.00V

V

DD

V

REF

V

OUT

CH2 2.00V M10.00ms A CH1 640mV

T 30.20%

Figure 27. POR to MS

06845-127

AD5066

15

CH1 = SCLK

1

CH2 = V

OUT

2

CH1 5V CH2 500mV M2µs A CH2 1.2V

VDD = 5V
POWER-UP T O MIDSCALE
OUTPUT UNLOADED

T 55%

Figure 28. Exiting PD to MS

15

10

5

10

5

0

–5

GLITCH AM PLITUDE (mV)

–10

–15

–20246810

06845-128

TIME (µs)

Figure 31. Digital Crosstalk

20

15

10

5

VDD = 5V
V

= 4.096V

REF

T

= 25°C

A

VDD = 5V
V

= 4.096V

REF

T

= 25°C

A

06845-131

0

–5

VDD = 5V

GLITCH AM PLITUDE (mV)

V

= 4.096V

REF

T

= 25°C

–10

A

CODE = 0x8000 TO 0x7FFF
OUTPUT UNLO ADED WITH 5kΩ AND 200pF

–15

–20246810

TIME (µs)

Figure 29. Glitch

15

VDD = 5V
V

10

5

0

–5

GLITCH AM PLITUDE (mV)

–10

–15

–20246810

TIME (µs)

REF

T

A

= 4.096V

= 25°C

Figure 30. Analog Crosstalk

0

–5

GLITCH AM PLITUDE (mV)

–10

–15

–20

–20246810

06845-129

TIME (µs)

06845-132

Figure 32. DAC-to-DAC Crosstalk

4

3

2

1

0

–1

OUTPUT VOLTAGE (µV)

–2

VDD = 5V

–3

V

= 4.096V

REF

T

= 25°C

A

–4

0147

6845-130

25836910

Time (Seco nds)

06845-133

Figure 33. 1/f Noise

Rev. 0 | Page 12 of 24

AD5066

0

–10

–20

–30

–40

–50

LEVEL (dB)

–60

OUT

V

–70

–80

–90

–100

5 10 30 40 55

20 50

Figure 34. Total Harmonic Distortion

VDD= 5V,
T

= 25ºC

A

DAC LOADED WITH MIDSCALE
V

= 3.0V ± 200mV p -p

REF

FREQUENCY (kHz)

CLR

V

OUT

CH1 PEAK TO PEAK
155mV

V

OUT

LAST SCLK

VDD = 5V
V

= 4.096V

REF

T

= 25°C

06845-016

CH1 50.0mV CH2 5.00V M4.00µs A CH2 1.80V

T 9.800%

A

06845-137

Figure 37. Glitch Upon Entering Power Down

CH1 PEAK TO PEAK
159mV

V

OUT

CH1 5.00V CH2 2. 00V M2.00ms A CH1 1.80V

T 10.20%

Figure 35. Hardware

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

OUTPUT VOLTAGE (V)

1.4

VDD = 4.5V
V

= 4.096V

REF

1.2

T

= 25°C

A

1.0

1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4

1/4 TO 3/4

3/4 TO 1/4

TIME (µs)

Figure 36. Slew Rate

CLR

LAST SCLK

VDD = 5V
V

= 4.096V

REF

T

= 25°C

A

CH1 50.0mV CH2 5.00V M4.00µs A CH2 1.80V

06845-135

Figure 38. Glitch Upon Exiting Power Down

T 9.800%

06845-138

06845-136

Rev. 0 | Page 13 of 24

AD5066

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

Relative accuracy or INL is a measure of the maximum
deviation in LSBs from a straight line passing through the
endpoints of the DAC transfer function. Figure 4, Figure 5,
and Figure 6 show typical INL vs. code plots.

Differential Nonlinearity (DNL)

DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures mono­tonicity. Figure 7, Figure 8, and Figure 9 show typical DNL vs.
code plots.

Zero-Code Error

Zero-code error is a measure of the output error when zero
code (0x0000) is loaded into the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5066, because the output of the DAC cannot go below
0 V. Zero-code error is expressed in millivolts. Figure 17 shows
a typical zero-code error vs. supply voltage plot.

Gain Error

Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.

Gain Error Drift

Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.

Zero-Code Error Drift

Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in microvolts
per degrees Celsius.

Full-Scale Error

Full-scale error is a measure of the output error when a full­scale code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be V
percentage of the full-scale range.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nanovolts
per second and is measured when the digital input code is
changed by 1 LSB at the major carry transition (0x7FFF to
0x8000). See Figure 28.

DC Power Supply Rejection Ratio (PSRR)

DC PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. DC PSRR is the ratio of the
change in V
DAC. It is measured in decibels.

OUT

− 1 LSB. Full-scale error is expressed as a

REF

to a change in VDD for full-scale output of the

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.

Reference Feedthrough

Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is,
decibels.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device but is measured when the DAC is not being written to

SYNC

(

held high). It is specified in nanovolts per second and
measured with one simultaneous DIN and SCLK pulse loaded
to the DAC.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nanovolts per second.

Analog Crosstalk

Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s or vice versa) while keeping

high and then pulsing
the DAC whose digital code has not changed. The area of the
glitch is expressed in nanovolts per second.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
LDAC

low and monitoring the output of another DAC. The

energy of the glitch is expressed in nanovolts per second.

Total Harmonic Distortion (THD)

THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as
the reference for the DAC, and the THD is a measure of the
harmonics present on the DAC output. It is measured in
decibels.

LDAC

is high). It is expressed in

LDAC

low and monitoring the output of

LDAC

Rev. 0 | Page 14 of 24

AD5066

V

V

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

The AD5066 is a quad 16-bit, serial input, voltage output
nanoDAC. The part operates from supply voltages of 2.7 V to

5.5 V. Data is written to the AD5066 in a 32-bit word format via
a 3-wire serial interface. The AD5066 incorporates a power-on
reset circuit to ensure the DAC output powers up to a known
output state. The devices also have a software power-down mode
that reduces the typical current consumption to typically 400 nA.

Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by

D

⎞

⎛

OUT

VV

REFIN

×=

⎟

⎜

N

2

⎠

⎝

where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register (0 to 65,535).
N is the DAC resolution.

DAC ARCHITECTURE

The DAC architecture of the AD5066 consists of two matched
DAC sections. A simplified circuit diagram is shown in
Figure 39. The four MSBs of the 16-bit data word are decoded
to drive 15 switches, E1 to E15. Each of these switches connects
one of 15 matched resistors to either GND or the V

output.

The remaining 12 bits of the data word drive the S0 to

buffer

REF

S11 switches of a 12-bit voltage mode R-2R ladder network.

OUT

2R

E15

06845-005

REF

2R

2R

2R

S1

S0

12-BIT R-2R LADDER FOUR MSBs DECODED

Figure 39. DAC Ladder Structure

2R

S11

2R

E12RE2

INTO 15 EQUAL

SEGMENTS

REFERENCE BUFFER

The AD5066 operates with an external reference. Each of the
four on-board DACs has a dedicated voltage reference pin that
is buffered. The reference input pin has an input range of 2 V
to V

− 0.4 V. This input voltage is then used to provide a

DD

buffered reference for the DAC core.

DB31 (MSB) DB0 (LSB)

SERIAL INTERFACE

Figure 2

SYNC

, SCLK, and

The AD5066 has a 3-wire serial interface (
DIN) that is compatible with SPI, QSPI, MICROWIRE, and
most DSP interface standards. See for a timing diagram
of a typical write sequence.

INPUT SHIFT REGISTER

The input shift register is 32 bits wide (see Figure 40). The first
four bits are don’t cares. The next four bits are the command
bits, C3 to C0 (see Tab le 7), followed by the 4-bit DAC address
bits, A3 to A0 (see Tab le 8), and finally the bit data-word. The
data-word comprises of a 16-bit input code followed by four
don’t care bits (see Figure 40). These data bits are transferred to
the Input register on the 32
can be executed on individually selected DAC channels or on all
DACs.

Table 7. Command Definitions

Command Description

C3 C2 C1 C0

0 0 0 0 Write to Input Register n
0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0
0 1 0 1
0 1 1 0

0 1 1 1 Reset (power-on reset)
1 0 0 0
1 0 0 1
1 1 1 1 Reserved

Table 8. DAC Input Register Address Bits

Address (n)

0 0 0 0 DAC A
0 0 0 1 DAC B
0 0 1 0
0 0 1 1
1 1 1 1 All DACs

nd

falling edge of SCLK. Commands

Transfer contents of Input Register n to
DAC Register n

Write to Input Register n and update all
DAC Registers

Write to Input Register n and update
DAC Register n

Power down/power up DAC
Load clear code register
Load LDAC register

Reserved
Reserved

Selected DAC Channel A3 A2 A1 A0

DAC C
DAC D

X

XXX

C3 C2 C1 C0 A3 A2 A1 A0 DB1 5 DB14 DB13 DB 12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X X

DATA BITS

ADDRESS BITSCOMMAND BITS

Figure 40. Input Shift Register Content

Rev. 0 | Page 15 of 24

06845-007

AD5066

The write sequence begins by bringing the

SYNC

Bringing the

line low enables the DIN and SCLK input

SYNC

line low.

buffers. Data from the DIN line is clocked into the 32-bit shift
register on the falling edge of SCLK. The serial clock frequency
can be as high as 50 MHz, making the AD5066 compatible with
high speed DSPs. On the 32

nd

falling clock edge, the last data bit
is clocked in, and the programmed function is executed, that is,
a change in the input register contents (see ) and/or a
change in the mode of operation. At this stage, the

Table 8

SYNC

line
can be kept low or be brought high. In either case, it must be
brought high for a minimum of 2 s (single-channel update, see
the t

parameter in ) before the next write sequence so

8

that a falling edge of

SYNC

Idle

high between write sequences for even lower power

Tabl e 4

SYNC

can initiate the next write sequence.

operation of the part.

SYNC

Interrupt

In a normal write sequence, the

SYNC

line is kept low for at

least 32 falling edges of SCLK, and the DAC is updated on the

nd

falling edge. However, if

32

nd

falling edge, this acts as an interrupt to the write sequence.

32

SYNC

is brought high before the

The input shift register is reset, and the write sequence is seen
as invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see ). Figure 42

Power-Down Modes

The AD5066 can be configured through software, in one of
four different modes: normal mode (default) and three separate
power-down modes (see Table 9). Any or all DACs can be
powered down. Command 0100 is reserved for the power­down function (see Ta b le 7 ). These power-down modes are
software-programmable by setting two bits, Bit DB9 and
Bit DB8, in the input shift register. Table 9 shows how the state
of the bits corresponds to the mode of operation of the device.
Any or all DACs (DAC A to DAC D) can be powered down to
the selected mode by setting the corresponding four bits (DB3,
DB2, DB1, DB0) to 1. See Table 1 0 for the contents of the input
shift register during power-down/power-up operation.

When Bit DB9 and Bit DB8 in the control register are set to 0,
the part is configured in normal mode with its normal power
consumption of 2.5 mA at 5 V. However, for the three power­down modes, the supply current falls to 0.4 µA if all the channels
are powered down. Not only does the supply current fall, but
the output pin is also internally switched from the output of the
DAC to a resistor network of known values. This has the advantage
that the output impedance of the part is known while the part
is in power-down mode. There are three different options: the
output is connected internally to GND through either a 1 kΩ or
a 100 kΩ resistor, or it is left open-circuited (three-state). The
output stage is illustrated in Figure 41.

DAC

POWER-DOWN

CIRCUITRY

Figure 41. Output Stage During Power-Down Mode

RESISTOR
NETWORK

V

OUT

06845-008

The bias generator, DAC core, and other associated linear
circuitry are shut down when all channels are powered down.
However, the contents of the DAC register are unaffected when
in power-down mode. The time to exit power-down mode is
typically 2.9 µs (see Figure 27).

Table 9. Modes of Operation

DB9 DB8 Operating Mode

0 0 Normal operation
Power-down modes
0 1
1 0

1 kΩ to GND
100 kΩ to GND

1 1 Three-state

SCLK

SYNC

DIN

SYNC HIGH BEFO RE 32

DB31 DB0

INVALID WRITE SEQUENCE:

ND

FALLING EDGE

Figure 42.

SYNC

Interrupt Facility

DB31 DB0

OUTPUT UPDATES ON THE 32

VALID WRITE SE QUENCE:

ND

FALLING EDGE

06845-017

Rev. 0 | Page 16 of 24

AD5066

POWER-ON RESET

The AD5066 contains a power-on reset circuit that controls
the output voltage during power-up. By connecting the POR
pin low, the AD5066 output powers up to 0 V; by connecting
the POR pin high, the AD5066 output powers up to midscale.
The output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications

Table 10. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function

MSB LSB
DB31 to

DB28 DB27 DB26 DB25 DB24

X 0 1 0 0 X X PD1 PD0 X DAC D DAC C DAC B DAC A
Don’t

cares

Command bits (C2 to C0)

DB23 to
DB20

Address bits
(A3 to A0)—
don’t cares

DB10 to
DB19 DB9 DB8

Don’t
cares

where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code. Command 0111 is reserved for this reset function
(see Tabl e 7). Any events on

LDAC

CLR

or

during power-on

reset are ignored.

DB4 to
DB7 DB3 DB2 DB1 DB0

Power- down
mode

Don’t
cares

Power-down/power-up channel
selection—set bit to 1 to select

Rev. 0 | Page 17 of 24

AD5066

LDAC

CLEAR CODE REGISTER

The AD5066 has a hardware
clear input. The
CLR

line low clears the contents of the input register and the

CLR

DAC registers to the data contained in the user-configurable
CLR

register and sets the analog outputs accordingly (see

Tabl e 11

). This function can be used in system calibration to
load zero scale, midscale, or full scale to all channels together.
These clear code values are user-programmable by setting two
bits, Bit DB1 and Bit DB0, in the control register (see ).
The default setting clears the outputs to 0 V. Command 0101 is
reserved for loading the clear code register (see ).

Table 11. Clear Code Register

DB1 (CR1) DB0 (CR0) Clears to Code

0 0 0x0000
0 1 0x8000
1 0 0xFFFF
1 1 No operation

The part exits clear code mode on the 32nd falling edge of the
next write to the part. If
sequence, the write is aborted.

CLR

The

pulse activation time (the falling edge of
the output starts to change) is typically 10.6 µs. See for
contents of the input shift register during the loading clear code
register operation.

CLR

pin that is an asynchronous

input is falling edge sensitive. Bringing the

Tabl e 11

Table 7

CLR

is activated during a write

CLR

to when

Tabl e 13

LDAC FUNCTION

Hardware

The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin, as shown in Figure 2. There are two
methods of using the hardware LDAC pin: synchronously

LDAC

(

LDAC

Pin

permanently low) and asynchronously (

LDAC

pulsed).

Synchronous
data is read, the DAC registers are updated on the falling edge
of the 32

nd

SCLK pulse, provided

Asynchronous
update. The outputs are not updated at the same time that the
input registers are written to. When
DAC registers are updated with the contents of the input
registers.

Command 0001, 0010 and 0011 (see Tab l e 7) update the DAC
Register/Registers, regardless of the level of the

Software

LDAC

Writing to the DAC using Command 0110 loads the 4-bit
LDAC

register (DB3 to DB0). The default for each channel is

0; that is, the

LDAC

updates the DAC channel regardless of the state of the hardware
LDAC

pin, so that it effectively sees the hardware
as being tied low (see for the LDAC register mode of
operation.) This flexibility is useful in applications where the
user wants to simultaneously update select channels while the
remainder of the channels are synchronously updating.

Table 12. Load

Bits

LDAC
(DB3 to

DB0)

0 1/0
1 X1

1

X = don’t care.

LDAC

The

register gives the user extra flexibility and control
over the hardware
bits (DB0 to DB3) to 0 for a DAC channel means that this
channel’s update is controlled by the hardware

LDAC

:

is held permanently low. After new

LDAC

is held low.

LDAC

LDAC

:

is held high then pulsed low to

LDAC

is pulsed low, the

LDAC

Function

pin works normally. Setting the bits to 1

Tabl e 12

LDAC

Register

LDAC

Operation

Pin

LDAC

Determined by LDAC
DAC channels update, overrides the LDAC

pin; DAC channels see LDAC as 0

LDAC

pin (see Table 14). Setting the

pin

LDAC

LDAC

pin.

pin

pin

LDAC

Table 13. 32-Bit Input Shift Register Contents for Clear Code Function

MSB
DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB2 to DB19 DB1 DB0

X 0 1 0 1 X X X X X 1/0 1/0
Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares

Clear code register

(CR1 to CR0)

LSB

LDAC

Table 14. 32-Bit Input Shift Register Contents for

MSB
DB31

to DB28

X 0 1 1 0 X X DAC D DAC C DAC B DAC A
Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares

DB27 DB26 DB25 DB24 DB23 to DB20

Overwrite Function

Rev. 0 | Page 18 of 24

DB4
to DB19

LSB

DB3 DB2 DB1 DB0

Setting LDAC

bit to 1 override LDAC pin

AD5066

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5066 should
have separate analog and digital sections. If the AD5066 is in a
system where other devices require an AGND-to-DGND con­nection, make the connection at one point only and as close as
possible to the AD5066.

Bypass the power supply to the AD5066 with 10 µF and 0.1 µF
capacitors. The capacitors should be physically as close as
possible to the device, with the 0.1 µF capacitor, ideally, right up
against the device. The 10 µF capacitors are the tantalum bead
type. It is important that the 0.1 µF capacitor has low effective
series resistance and low effective series inductance, typical of
common ceramic types of capacitors. This 0.1 µF capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.

The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Shield the clocks and other fast switching digital
signals from other parts of the board by digital ground. Avoid
crossover of digital and analog signals if possible. When traces
cross on opposite sides of the board, ensure that they run at
right angles to each other to reduce feedthrough effects through
the board. The best board layout technique is the microstrip
technique, where the component side of the board is dedicated
to the ground plane only, and the signal traces are placed on
the solder side. However, this is not always possible with a
2-layer board.

AD5066 to 68HC11/68L11 Interface

Figure 44 shows a serial interface between the AD5066 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5066, and the MOSI output drives
DIN of the DAC. A port line (PC7) drives the

68HC11/68L11*

*ADDITIONAL PINS OMI TTED FO R CLARITY.

Figure 44. AD5066 to 68HC11/68L11 Interface

AD5066*

SYNCPC7

SCLKSCK

DINMOSI

SYNC

signal.

06845-010

The setup conditions for correct operation of this interface are
as follows: The 68HC11/68L11 is configured with its CPOL bit
as 0, and the CPHA bit as 1. When data is being transmitted to
the DAC, the

SYNC

line is taken low (PC7). When the 68HC11/
68L11 is configured as described previously, data appearing on
the MOSI output is valid on the falling edge of SCK. Serial data
from the 68HC11/68L11 is transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5066, PC7 is left
low after the first eight bits are transferred, and a second serial
write operation is performed to the DAC. PC7 is taken high at
the end of this procedure.

MICROPROCESSOR INTERFACING

AD5066 to Blackfin® ADSP-BF53X Interface

Figure 43 shows a serial interface between the AD5066 and
the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multipro­cessor communications. Using SPORT0 to connect to the
AD5066, the setup for the interface is as follows: DT0PRI
drives the DIN pin of the AD5066, TSCLK0 drives the SCLK
of the parts, and TFS0 drives

ADSP-BF53x*

*ADDITIONAL PINS OMI TTED FO R CLARITY.

Figure 43. AD5066 to Blackfin ADSP-BF53X Interface

SYNC

.

AD5066*

SYNCTFS0

DINDT 0PRI

SCLKTSCLK0

06845-009

Rev. 0 | Page 19 of 24

AD5066

AD5066 to 80C51/80L51 Interface

Figure 45 shows a serial interface between the AD5066 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/80L51 drives SCLK of the AD5066,
RxD drives DIN on the AD5066, and a bit-programmable pin on
the port (P3.3) drives the

SYNC

signal. When data is to be
transmitted to the AD5066, P3.3 is taken low. The 80C51/80L51
transmit data in 8-bit bytes only; thus, only eight falling clock
edges occur in the transmit cycle. To load data to the DAC, P3.3
is left low after the first eight bits are transmitted, and a second,
third, and fourth write cycle is initiated to transmit the second,
third, and fourth byte of data. P3.3 is taken high following the
completion of this cycle. The 80C51/80L51 output the serial
data in a format that has the LSB first. The AD5066 must
receive data with the MSB first. The 80C51/80L51 transmit
routine should take this into account.

AD5066 to MICROWIRE Interface

Figure 46 shows an interface between the AD5066 and any
MICROWIRE-compatible device. Serial data is clocked into
the AD5066 on the falling edge of the SCLK.

80C51/80L51*

*ADDITIONAL PINS OMI TTED FO R CLARITY.

Figure 45. AD5066 to 80C512/80L51 Interface

MICROWIRE *

*ADDITIONAL PINS OMI TTED FO R CLARITY.

Figure 46. AD5066 to MICROWIRE Interface

AD5066*

SYNCP3.3

SCLKTxD

DINRxD

AD5066*

SYNCCS

DINSK

SCLKSO

06845-011

06845-012

Rev. 0 | Page 20 of 24

AD5066

V

APPLICATIONS INFORMATION

USING A REFERENCE AS A POWER SUPPLY

Because the supply current required by the AD5066 is extremely
low, an alternative option is to use a voltage reference to supply
the required voltage to the parts (see Figure 47). This is espe­cially useful if the power supply is quite noisy or if the system
supply voltages are at some value other than 5 V or 3 V, for
example, 15 V. The voltage reference outputs a steady supply
voltage for the AD5066. If the low dropout REF195 is used, it
must supply 2.5 mA of current to the AD5066 with no load on
the output of the DAC.

15

5V 4.5V

V

DDVREF

AD5066

REF194

x = 0V TO 4. 5V

V

OUT

3-WIRE

SERIAL

INTERFACE

REF195

SYNC

SCLK

DIN

Figure 47. REF195 as a Power Supply to the AD5066

BIPOLAR OPERATION

The AD5066 has been designed for single-supply operation,
but a bipolar output range is also possible using the circuit in
Figure 48. The circuit gives an output voltage range of ±5 V.
Rail-to-rail operation at the amplifier output is achieved
using an AD8638 or AD8639 the output amplifier.

The output voltage for any input code can be calculated as
follows:

+5.5V

10µF

+5V

V

REF

0.1µF

R1 = 10kΩ

V

REF

V

V

OUT

DD

AD5066

3-WIRE

SERIAL INTE RFACE

Figure 48. Bipolar Operation with the AD5066

USING THE AD5066 WITH A GALVANICALLY ISOLATED INTERFACE

In process control applications in industrial environments,
it is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous

06845-013

common-mode voltages that can occur in the area where
the DAC is functioning. iCoupler® provides isolation in excess
of 2.5 kV. The AD5066 uses a 3-wire serial logic interface, so
the ADuM1300 three-channel digital isolator provides the
required isolation (see Figure 49). The power supply to the
part also needs to be isolated, which is done by using a
transformer. On the DAC side of the transformer, a 5 V
regulator provides the 5 V supply required for the AD5066.

5V

POWER

REGULATOR

R2 = 10kΩ

+5V

AD820/

OP295

–5V

10µF

±5V

0.1µF

6845-014

⎡

O

⎝

⎣

⎛

×=

VV

⎜

⎢

⎞

×

⎟

536,65

⎠

R2R1D

+

R1

⎞

V

⎟

DDDD

⎠

⎛
⎜
⎝

⎤

R2

⎞

⎛

×−

⎟

⎜

⎥

R1

⎠

⎝

⎦

where:

D = the input code in decimal (0 to 65,535).
V

= 5 V.

DD

R1 = R2 = 10 kΩ.

10

×=D

⎛

V

⎜

O

⎝

⎞

V5

−

⎟

536,65

⎠

This is an output voltage range of ±5 V, with 0x0000 corre­sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.

SCLK

DATA

Rev. 0 | Page 21 of 24

V

SCLK

AD5066

SYNC

DIN

GND

SDI

V

IA

ADuM1300

V

IB

V

IC

V

OA

V

OB

V

OC

Figure 49. AD5066 with a Galvanically Isolated Interface

DD

V

x

OUT

06845-015

AD5066

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 50. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeter

ORDERING GUIDE

Package

Model Temperature Range Package Description

Option

AD5066BRUZ1 −40°C to +125°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 16 bits
AD5066BRUZ-REEL71 −40°C to +125°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 16 bits
AD5066ARUZ
AD5066ARUZ-REEL7

1

Z = RoHS Compliant Part.

1

−40°C to +125°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 16 bits

1

−40°C to +125°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 16 bits

Power-On
Reset to Code Accuracy Resolution

Rev. 0 | Page 22 of 24

AD5066

NOTES

Rev. 0 | Page 23 of 24

AD5066

NOTES

©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06845-0-7/09(0)

Rev. 0 | Page 24 of 24