ANALOG DEVICES AD5066 Service Manual

Fully Accurate, 16-Bit, Unbuffered V

V

A

V

, Quad SPI

OUT

FEATURES

Low power quad 16-bit nanoDAC, ±1 LSB INL Low total unadjusted error of ±0.1 mV typically Low zero code error of 0.05 mV typically Individually buffered reference pins

2.7 V to 5.5 V power supply Specified over full code range of 0 to 65535 Power-on reset to zero scale or midscale Per channel power-down with 3 power-down functions Hardware

function to programmable code

CLR Small 16-lead TSSOP

APPLICATIONS

Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources

GENERAL DESCRIPTION

The AD5066 is a low power, 16-bit quad-channel, unbuffered voltage output nanoDAC offering relative accuracy specifications of ±1 LSB INL with individual reference pins and can operate from a single 2.7 V to 5.5 V supply. The AD5066 also offers a differential accuracy specification of ±1 LSB DNL. Reference buffers are also provided on-chip. The part uses a versatile 3-wire, low power Schmitt trigger serial interface that operates at clock rates up to 50 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and most DSP interface standards. The AD5066 incorporates a power-on reset circuit that ensures the DAC output powers up to zero scale or midscale and remains there until a valid write to the device takes place.

with software

LDAC

override function

LDAC

Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP

AD5066

Total unadjusted error for the part is <0.8 mV. Zero code error for the part is 0.05 mV typically.

The AD5066 contains a power-down feature that reduces the current consumption of the device to typically 400 nA at 5 V and provides software selectable output loads while in powerdown mode.

The outputs of all DACs can be updated simultaneously using the hardware user software selectable DAC channels to update simultaneously. There is also an asynchronous software-selectable code—0 V, midscale, or full scale.

PRODUCT HIGHLIGHTS

1. Quad channel available in 16-lead TSSOP, ±1 LSB INL.

2. Individually buffered voltage reference pins.

3. TUE = ±0.8 mV max and zero code error = 0.1 mV max.

4. High speed serial interface with clock speeds up to 50 MHz.

5. Three power-down modes available to the user.

6. Reset to known output voltage (zero scale or midscale).

Table 1. Related Devices

Part No. Description

AD5666 Quad,16-bit buffered DAC,16 LSB INL, TSSOP AD5025/AD5045/AD5065

AD5024/AD5044/AD5064 AD50621 Single, 16-bit nanoDAC, SOT-23 AD5063 AD5061 Single,16-bit nanoDAC, ±4 LSB INL, SOT-23 AD5040/AD5060

1

±1 LSB INL

LDAC

function, with the added functionality of

CLR

that clears all DACs to a

1

Dual,12-/14-/16-bit buffered nanoDAC, TSSOP

1

Quad 16-bit nanoDAC, TSSOP

1

Single, 16-bit nanoDAC, MSOP

14-/16-bit nanoDAC, SOT-23

FUNCTIONAL BLOCK DIAGRAM

V

DD

AD5066

SCLK

SYNC

DIN

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

LDAC

INTERFACE

LOGIC

LDAC

CLR

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

POWER-ON RESET

POR

DAC

REGIS TER

DAC

REGIS TER

DAC

REGIS TER

DAC

REGIS TER

Figure 1.

REF

V

REF

B

REF

DAC A

DAC B

DAC C

DAC D

POWER-DOW N LOGI C

C V

D

REF

GND

V

A

OUT

B

V

OUT

V

C

OUT

V

D

OUT

06845-001

AD5066

REVISION HISTORY

7/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD5066

SPECIFICATIONS

VDD = 2.7 V to 5.5 V, 2.0 V ≤ V

REF

A, V

REF

B, V

REF

C, V

D ≤ VDD − 0.4 V, all specifications T

REF

MIN

to T

, unless otherwise noted.

MAX

Table 2.

1

Parameter

STATIC PERFORMANCE

A Grade

Min Typ Max Min Typ Max

2

Resolution 16 16 Bits Relative Accuracy (INL) ±0.5 ±4 ±0.5 ±1 LSB TA = −40°C to +105°C ±0.5 ±4 ±0.5 ±2 TA = −40°C to +125°C Differential Nonlinearity (DNL) ±0.2 ±1 ±0.2 ±1 LSB Total Unadjusted Error (TUE) ±0.1 ±0.8 ±0.1 ±0.8 mV VDD = 2.7 V, V Zero-Code Error 0.05 0.1 0.05 0.1 mV All 0s loaded to the DAC register Zero-Code Error Drift

3

±0.5 ±0.5 µV/°C Full-Scale Error ±0.01 ±0.05 ±0.01 ±0.05 % FSR All 1s loaded to the DAC register Gain Error ±0.005 ±0.05 ±0.005 ±0.05 % FSR Gain Error Drift3 DC Crosstalk3

±0.5 ±0.5 ppm ppm of FSR/°C

1 5 1 5 V Due to single-channel full-scale

5 25 5 25 V Due to powering down (per channel)

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 V DC Output Impedance (Normal

0 V

REF

8 8 kΩ Output impedance tolerance ± 10%

Mode)

DC Output Impedance DAC in power-down mode

Output Connected to 100 kΩ

100 100 kΩ Output impedance tolerance ± 20 kΩ

Network

Output Connected to 1 kΩ

1 1 kΩ Output impedance tolerance ± 400 Ω

Network Power-Up Time4 2.9 2.9 µs DC PSRR −120 −120 dB VDD ± 10%, DAC = full scale

REFERENCE INPUTS

Reference Input Range 2 V

− 0.4 2 VDD − 0.4 V

DD

Reference Current 0.002 ±1 0.002 ±1 µA Per DAC channel Reference Input Impedance 40 40 MΩ Per DAC channel

LOGIC INPUTS3

Input Current5 ±1 ±1 µA Input Low Voltage, V Input High Voltage, V

0.8 0.8 V

INL

2.2 2.2 V

INH

Pin Capacitance 4 4 pF

POWER REQUIREMENTS

VDD 2.7 5.5 2.7 5.5 V All digital inputs at 0 V or VDD DAC active, excludes load current IDD V Normal Mode6 2.5 3 2.5 3 mA All Power-Down Modes7 0.4 0.4 µA

1

Temperature range is −40°C to +125°C, typical at 25°C.

2

Linearity calculated using a code range of 0 to 65,535; output unloaded.

3

Guaranteed by design and characterization; not production tested.

4

Time taken to exit power-down mode and enter normal mode, 32nd clock edge to 90% of DAC midscale value, output unloaded.

5

Current flowing into individual digital pins. VDD = 5.5 V; VREF = 4.096 V; Code = midscale.

6

Interface inactive. All DACs active. DAC outputs unloaded.

7

All four DACs powered down.

B Grade

1

Unit Conditions/Comments

V

REF

= 2 V

REF

output change

= VDD and VIL = GND

IH

Rev. 0 | Page 3 of 24

AD5066

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V, 2.0 V ≤ V

REF

A, V

REF

B, V

REF

C, V

D ≤ VDD − 0.4 V all specifications T

REF

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Parameter

1, 2

Min Ty p Max Unit Conditions/Comments3

DYNAMIC PERFORMACE

Output Voltage Settling Time 7.5 10 µs

¼ to ¾ scale settling to ±2 LSB, single channel update, output unloaded

Output Voltage Settling Time 12 15 µs

¼ to ¾ scale settling to ±2 LSB, all channel update, output

unloaded Slew Rate 1.7 V/µs Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry Reference Feedthrough −70 dB V

= 3 V ± 0.5 V p-p, frequency = 60 Hz to 20 MHz

REF

Digital Feedthrough 0.02 nV-sec Digital Crosstalk 1.7 nV-sec Analog Crosstalk 3.7 nV-sec DAC-to-DAC Crosstalk 5.4 nV-sec Total Harmonic Distortion −83 dB V

= 3 V ± 0.2 V p-p, frequency = 10 kHz

REF

Output Noise Spectral Density 30 nV/√Hz DAC code = 0x8000, 1 kHz 25 nV/√Hz DAC code = 0x8000, 10 kHz Output Noise 4.7 V p-p 0.1 Hz to 10 Hz

1

Temperature range is −40°C to +125°C, typical at +25°C.

2

See the Terminology section.

3

Guaranteed by design and characterization; not production tested.

Rev. 0 | Page 4 of 24

AD5066

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2, VDD = 2.7 V to

5.5 V, all specifications T

Table 4.

Parameter1 Symbol Min Typ M ax Uni t SCLK Cycle Time t1 20 ns SCLK High Time t2 10 ns SCLK Low Time t3 10 ns SYNC to SCLK Falling Edge Set-Up Time Data Set-Up Time t5 5 ns Data Hold Time t6 5 ns SCLK Falling Edge to SYNC Rising Edge Minimum SYNC high time

Single Channel Update 2 µs

All Channel Update 8 µs SYNC Rising Edge to SCLK Fall Ignore LDAC Pulse Width Low SCLK Falling Edge to LDAC Rising Edge CLR Pulse Width Low SCLK Falling Edge to LDAC Falling Edge CLR Pulse Activation Time

1

Maximum SCLK frequency is 50 MHz. Guaranteed by design and characterization; not production tested.

SCLK

SYNC

DIN

LDAC

to T

MIN

1

, unless otherwise noted. See Figure 2.

MAX

t

1

t

8

DB31

t

4

t

3

t

6

5

2

DB0

t

17 ns

4

t

5 30 ns

7

t

8

t

17 ns

9

t

20 ns

10

t

20 ns

11

t

10 ns

12

t

10 ns

13

t

10.6 µs

14

t

9

t

7

t

10

t

13

t

11

2

LDAC

t

CLR

V

OUT

1

ASYNCHRONOUS LDAC UPDATE MODE.

2

SYNCHRONOUS LDAC UPDATE MODE.

12

t

14

06845-003

Figure 2. Serial Write Operation

Rev. 0 | Page 5 of 24

AD5066

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V V

x to GND −0.3 V to VDD + 0.3 V

OUT

V

x to GND −0.3 V to VDD + 0.3 V

REF

Operating Temperature Range

Industrial −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ TSSOP Package

Power Dissipation (TJ

θJA Thermal Impedance 150.4°C/W Reflow Soldering Peak Temperature

SnPb 240°C

Pb-Free 260°C

) +150°C

MAX

− TA)/θJA

MAX

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 6 of 24

AD5066

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

LDAC

SYNC

V

REF

V

REF

V

OUT

POR

V

DD

B

A

C

1

2

3

AD5066

4

TOP VIEW

5

(Not to Scal e)

6

7

8

16

SCLK

15

DIN

14

GND

13

B

V

OUT

12

V

D

OUT

11

V

D

REF

10

CLR

9

C

V

REF

06845-004

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1

LDAC

Load DAC. Logic input. This is used to update the DAC register and, consequently, the analog outputs. When tied permanently low, the addressed DAC register is updated on the falling edge of the 32 clock. If LDAC

is held high during the write cycle, the addressed DAC input shift register is updated but the output is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC.

2

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

SYNC

low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC

is taken high before the 32nd falling edge, the rising edge of

SYNC acts as an interrupt, and the write sequence is ignored by the device.

3 VDD

Power Supply Input. The AD5066 can be operated from 2.7 V to 5.5 V. Decouple the supply with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

4 V 5 V 6 V 7 V 8 POR

B External Reference Voltage Input for DAC B.

REF

A External Reference Voltage Input for DAC A.

REF

A Unbuffered Analog Output Voltage from DAC A.

OUT

C Unbuffered Analog Output Voltage from DAC C.

OUT

Power-On Reset Pin. Tying this pin to GND powers the DAC outputs to zero scale on power-up. Tying this pin to VDD powers the DAC outputs to midscale.

9 V 10

11 V 12 V 13 V

C External Reference Voltage Input for DAC C.

REF

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are

CLR

ignored. When CLR contained in the CLR

D External Reference Voltage Input for DAC D.

REF

D Unbuffered Analog Output Voltage from DAC D.

OUT

B Unbuffered Analog Output Voltage from DAC B.

OUT

is activated, the input register and the DAC register are updated with the data

code register—zero, midscale, or full scale. Default setting clears the output to 0 V.

14 GND Ground Reference Point for All Circuitry on the Part. 15 DIN

Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input.

16 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz.

nd

Rev. 0 | Page 7 of 24

AD5066

TYPICAL PERFORMANCE CHARACTERISTICS

0.3

0.2

0.1

0

–0.1

–0.2

INL ERROR (LSB)

–0.3

VDD = 5V V

= 4.096V

–0.4

–0.5

REF

T

= 25°C

A

0 10,000 20,000 30, 000 40,000 50,000 60,000

CODE

Figure 4. INL Error vs. Code

0.3 VDD = 5V

= 4.096V

V

REF

0.2

= 25°C

T

A

0.1

0

–0.1

DNL ERROR (LSB)

–0.2

–0.3

–0.4

0 10,000 20,000 30,000 40, 000 50, 000 60,000

CODE

Figure 5. DNL Error vs. Code

0.5

0.4

0.3

0.2

0.1

0

INL (LSB)

–0.1

–0.2

–0.3

VDD = 5V T

–0.4

–0.5

6845-105

= 25°C

A

2345

MAX INL

MIN INL

REFERENCE VOLTAGE (V)

06845-108

Figure 7. INL vs. Reference Input Voltage

0.5

0.4

0.3

0.2

0.1

0

DNL (LSB)

–0.1

–0.2

–0.3

VDD = 5.5V

–0.4

T

= 25°C

A

–0.5

2345

06845-106

MAX DNL

MIN DNL

REFERENCE VOLTAGE (V)

06845-109

Figure 8. DNL vs. Reference Input Voltage

0.03

0.02

0.01

0

–0.01

–0.02

–0.03

TOTAL UNADJUSTED ERROR (mV)

–0.04

–0.05

–0.06

–0.07

VDD = 5V V

= 4.096V

REF

T

= 25°C

A

0 10,000 20,000 30,000 40,000 50, 000 60,000

CODE

Figure 6. Total Unadjusted Error vs. Code

06845-107

Rev. 0 | Page 8 of 24

100

80

60

40

20

0

–20

–40

–60

TOTAL UNADJUST ED ERROR (µV)

VDD = 5.5V

–80

T

= 25°C

A

–100

234

MAX TUE

MIN TUE

REFERENCE VOL TAGE (V)

Figure 9. Total Unadjusted Error vs. Reference Input Voltage

5

6845-110

ANALOG DEVICES AD5066 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AC CHARACTERISTICS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS