ANALOG DEVICES AD5025, AD5045 Service Manual
Fully Accurate, 12-/14-/16-Bit, Dual, V
V
V
V
A
nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP
OUT
FEATURES
Low power dual 12-/14-/16-bit DAC, ±1 LSB INL
Individual voltage reference pins
Rail-to-rail operation
4.5 V to 5.5 V power supply
Power-on reset to zero scale or midscale
Power down to 400 nA @ 5 V
3 power-down functions
Per channel power-down
Low glitch upon power-up
Hardware power-down lockout capability
Hardware
function to programmable code
CLR
SDO daisy-chaining option
14-lead TSSOP
APPLICATIONS
Process controls
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5025/AD5045/AD5065 are low power, dual 12-/14-/16-bit
buffered voltage output nanoDAC® DACs offering relative accuracy
specifications of ±1 LSB INL with individual reference pins, and
can operate from a single 4.5 V to 5.5 V supply. The AD5025/
AD5045/AD5065 also offer a differential accuracy specification of
±1 LSB. The parts use a versatile 3-wire, low power Schmitt
trigger serial interface that operates at clock rates up to 50 MHz
and is compatible with standard SPI®, QSPI™, MICROWIRE™,
and DSP interface standards. The reference for the AD5025/
AD5045/AD5065 are supplied from an external pin and a refer-
with software
LDAC
override function
LDAC
POR
FUNCTIONAL BLOCK DIAGRAM
AD5025/AD5045/AD5065
ence buffer is provided on chip. The AD5025/AD5045/AD5065
incorporate a power-on reset circuit that ensures the DAC output
powers up zero scale or midscale and remains there until a valid
write takes place to the device. The AD5025/AD5045/AD5065
contain a power-down feature that reduces the current consumption of the device to typically 400 nA at 5 V and provides software
selectable output loads while in power-down mode. The parts are
put into power-down mode over the serial interface. Total unadjusted error for the parts is <2.5 mV. The parts exhibit very low
glitch on power-up. The outputs of all DACs can be updated
simultaneously using the
functionality of user-selectable DAC channels to simultaneously
update. There is also an asynchronous
to a software-selectable code—0 V, midscale, or full scale. The
parts also feature a power-down lockout pin,
used to prevent the DAC from entering power-down under any
circumstances over the serial interface.
PRODUCT HIGHLIGHTS
1. Dual channel available in a 14-lead TSSOP package with
individual voltage reference pins.
2. 12-/14-/16-bit accurate, ±1 LSB INL.
3. Low glitch on power-up.
4. High speed serial interface with clock speeds up to 50 MHz.
5. Three power-down modes available to the user.
6. Reset to known output voltage (zero scale or midscale).
7. Power-down lockout capability.
Table 1. Related Devices
Part No. Description
AD5666 Quad,16-bit buffered DAC, 16 LSB INL, TSSOP
AD5024/AD5044/AD5064 Quad 16-bit nanoDAC, 1 LSB INL, TSSOP
AD5062/AD5063 16-bit nanoDAC, 1 LSB INL, MSOP
AD5061 16-bit nanoDAC, 4 LSB INL, SOT-23
AD5040/AD5060 14-/16-bit nanoDAC, 1 LSB INL, SOT-23
DD
REF
REF
B
LDAC
function, with the added
CLR
that clears all DACs
PDL
, which can be
LDAC
SCLK
SYNC
DIN
LDAC
SDO
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
INTERFACE
LOGIC
CLR
PDL
INPUT
REGISTER
INPUT
REGISTER
AD5025/AD5045/AD5065
DAC
REGISTER
DAC
REGISTER
Figure 1.
DAC A
DAC B
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
BUFFER
BUFFER
POWER-DOW N
LOGIC
GND
A
V
OUT
V
B
OUT
06844-001
AD5025/AD5045/AD5065
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 17
Digital-to-Analog Converter .................................................... 17
DAC Architecture ....................................................................... 17
Reference Buffer ......................................................................... 17
Output Amplifier ........................................................................ 17
Serial Interface ............................................................................ 17
Input Register .............................................................................. 17
Standalone Mode ........................................................................ 19
Interrupt .......................................................................... 19
SYNC
Daisy-Chaining ........................................................................... 19
Power-On Reset and Software Reset ....................................... 20
Power-Down Modes .................................................................. 20
Clear Code Register ................................................................... 21
Function ........................................................................... 21
LDAC
Power-Down Lockout ................................................................ 22
Power Supply Bypassing and Grounding ................................ 22
Microprocessor Interfacing ....................................................... 23
Applications Information .............................................................. 24
Using a Reference as a Power Supply for the
AD5025/AD5045/AD5065 ....................................................... 24
Bipolar Operation Using the AD5025/AD5045/AD5065 ..... 24
Using the AD5025/AD5045/AD5065 with a
Galvanically Isolated Interface ................................................. 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD5025/AD5045/AD5065
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ V
T
, unless otherwise noted.
MAX
≤ VDD, unless otherwise specified. All specifications T
REFIN
MIN
to
Table 2.
1
A Grade
Parameter
STATIC PERFORMANCE
B Grade
Min Typ Max Min Typ Max
3
Resolution
AD5065 16 16 Bits
AD5045 14
AD5025 12
Relative Accuracy
AD5065 ±0.4 ±1 ±0.5 ±4 LSB TA = −40°C to +105°C
AD5065 +0.4 ±2 ±0.5 ±4 TA = −40°C to +125°C
AD5045 ±0.1 ±0.5 LSB TA = −40°C to +105°C
AD5045 ±0.1 ±1 TA = −40°C to +125°C
AD5025 ±0.05 ±0.25 LSB TA = −40°C to +105°C
AD5025 ±0.05 ±0.5 TA = −40°C to +125°C
Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB
Total Unadjusted Error ±0.2 ±2.5 ±0.2 ±2.5 mV V
Offset Error ±0.2 ±1.8 ±0.2 ±1.8 mV Code 512 (AD5065), Code 128 (AD5045),
Offset Error Drift4 ±2 ±2 µV/°C
Full-Scale Error ±0.01 ±0.07 ±0.01 ±0.07 % FSR
Gain Error ±0.005 ±0.05 ±0.005 ±0.05 % FSR
Gain Temperature Coefficient4 ±1 ±1 ppm Of FSR/°C
DC Crosstalk4 40 40 µV Due to single channel full-scale output
40 40 µV/mA Due to load current change
40 40 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS4
Output Voltage Range 0 VDD 0 VDD V
Capacitive Load Stability 1 1 nF RL = 5 kΩ, RL = 100 kΩ, and RL = ∞
DC Output Impedance
Normal Mode 0.5 0.5 Ω
Power-Down Mode
Output Connected to
100 100 kΩ Output impedance tolerance ± 400 Ω
100 kΩ Network
Output Connected to
1 1 kΩ Output impedance tolerance ± 20 Ω
1 kΩ Network
Short-Circuit Current 60 60 mA DAC = full scale, output shorted to GND
45 45 mA DAC = zero-scale, output shorted to VDD
Power-Up Time 4.5 4.5 µs Time to exit power-down mode to
DC PSRR −92 −92 dB VDD ± 10%, DAC = full scale, V
REFERENCE INPUTS
Reference Input Range 2.2 VDD 2.2 VDD V
Reference Current 35 50 35 50 µA Per DAC channel
Reference Input Impedance 120 120 kΩ
1, 2
Unit Conditions/Comments
= 2.5 V; VDD = 5.5 V
REF
Code 32 (AD5025) loaded to DAC register
All 1s loaded to DAC register, V
change, R
normal mode of AD5024/AD5044/
AD5064, 32
= 5 kΩ to GND or VDD
L
nd
clock edge to 90% of DAC
REF
< VDD
midscale value, output unloaded
<VDD
REF
Rev. 0 | Page 3 of 28
AD5025/AD5045/AD5065
Parameter
1
B Grade
A Grade
Min Typ Max Min Typ Max
1, 2
Unit Conditions/Comments
LOGIC INPUTS
Input Current5 ±1 ±1 µA
Input Low Voltage, V
Input High Voltage, V
0.8 0.8 V
INL
2.2 2.2 V
INH
Pin Capacitance4 4 4 pF
LOGIC OUTPUTS (SDO)
Output Low Voltage, VOL 0.4 0.4 V I
Output High Voltage, VOH V
High Impedance Leakage
Current
4
High Impedance Output
3, 4
= 2 mA
SINK
− 1 VDD − 1 I
DD
SOURCE
±0.002 ±1 ±0.002 ±1 A
7 7 pF
= 2 mA
Capacitance
POWER REQUIREMENTS
VDD 4.5 5.5 4.5 5.5 V
6
I
DAC active, excludes load current
DD
Normal Mode 2.2 2.7 2.2 2.7 mA VIH = VDD and VIL = GND
All Power-Down Modes7 0.4 2 0.4 2 µA TA = −40°C to +105°C
30 30 µA TA = −40°C to +125°C
1
Temperature range is −40°C to +125°C, typical at 25°C.
2
A grade offered in AD5065 only.
3
Linearity calculated using a reduced code range—AD5065: Code 512 to Code 65,024; AD5045: Code 128 to Code 16,256; AD5025: Code 32 to Code 4064. Output
unloaded.
4
Guaranteed by design and characterization; not production tested.
5
Current flowing into or out of individual digital pins.
6
Interface inactive. All DACs active. DAC outputs unloaded.
7
Both DACs powered down.
AC CHARACTERISTICS
VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ V
Table 3.
Parameter
1
Min Typ Max Unit Conditions/Comments2
Output Voltage Settling Time 5.8 8 µs
Output Voltage Settling Time 10.7 13 µs
Slew Rate 1.5 V/µs
Digital-to-Analog Glitch Impulse3 4 nV-sec 1 LSB change around major carry
Reference Feedthrough3 −90 dB V
SDO Feedthrough 0.07 nV-sec Daisy-chain mode; SDO load is 10 pF
Digital Feedthrough3 0.1 nV-sec
Digital Crosstalk3 1.9 nV-sec
Analog Crosstalk3 1.2 nV-sec
DAC-to-DAC Crosstalk3 2.1 nV-sec
Multiplying Bandwidth3 340 kHz V
Total Harmonic Distortion3 −80 dB V
Output Noise Spectral Density 64 nV/√Hz DAC code = 0x8400, 1 kHz
60 nV/√Hz DAC code = 0x8400, 10 kHz
Output Noise 6 V p-p 0.1 Hz to 10 Hz
1
Guaranteed by design and characterization; not production tested.
2
Temperature range is −40°C to + 125°C, typical at 25°C.
3
See the Terminology section.
≤ VDD. All specifications T
REFIN
¼ to ¾ scale settling to ±1 LSB, R
to T
MIN
= 5 kΩ single-channel update
L
including DAC calibration sequence
¼ to ¾ scale settling to ±1 LSB, R
= 5 kΩ all channel update including
L
DAC calibration sequence
= 3 V ± 0.86 V p-p, frequency = 100 Hz to 100 kHz
REF
= 3 V ± 0.86 V p-p
REF
= 3 V ± 0.86 V p-p, frequency = 10 kHz
REF
, unless otherwise noted.
MAX
Rev. 0 | Page 4 of 28
AD5025/AD5045/AD5065
T
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and
Figure 4. V
Table 4.
Parameter Symbol Min Typ Max Un it
SCLK Cycle Time t
SCLK High Time t2 10 ns
SCLK Low Time t3 10 ns
SYNC to SCLK Falling Edge Setup Time
Data Setup Time t5 5 ns
Data Hold Time t6 5 ns
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time (Single Channel Update)
Minimum SYNC High Time (All Channel Update)
SYNC Rising Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SCLK Falling Edge to LDAC Rising Edge
CLR Pulse Width Low
SCLK Falling Edge to LDAC Falling Edge
CLR Pulse Activation Time
SCLK Rising Edge to SDO Valid t
SCLK Falling Edge to SYNC Rising Edge
SYNC Rising Edge to SCLK Rising Edge
SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (Single Channel Update)
SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (All Channel Update)
PDL Minimum Pulse Width
1
Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2
Daisy-chain mode only.
3
Measured with the load circuit of Figure 2. t15 determines the maximum SCLK frequency in daisy-chain mode.
Circuit and Timing Diagrams
= 4.5 V to 5.5 V. All specifications T
DD
MIN
to T
, unless otherwise noted.
MAX
1
20 ns
1
t
16.5 ns
4
t
0 30 ns
7
t
2 µs
8
t
4 µs
8
t
17 ns
9
t
20 ns
10
t
20 ns
11
t
10 ns
12
t
10 ns
13
t
10.6 µs
14
2, 3
15
2
t
5 30 ns
16
2
t
8 ns
17
2
t
2 µs
18
2
t
4 µs
18
t
19
22 ns
20 ns
2mA I
OL
O OUTPUT
PIN
50pF
C
L
2mA I
OH
VOH (MIN) + VOL (MAX)
2
06844-002
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. 0 | Page 5 of 28
AD5025/AD5045/AD5065
SCLK
t
8
SYNC
DIN
1
LDAC
2
LDAC
CLR
V
OUT
PDL
1
ASYNCHRONOUS LDAC UPDAT E MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
DB31
t
4
t
6
t
5
t
12
t
14
t
1
t
t
3
2
DB0
t
9
t
7
t
10
t
13
t
11
t
19
06844-003
Figure 3. Serial Write Operation
SCLK
t8t
4
SYNC
t
5
t
6
DIN
INPUT WORD FOR DAC N
SDO
UNDEFINED
1
LDAC
CLR
PDL
1
IF IN DAIS Y-CHAIN MODE, LDAC MUST BE USED ASYNCHRONOUSLY.
32 64
t
16
DB0DB31
DB31
INPUT WORD FOR DAC N + 1
t
15
DB31
INPUT WORD FOR DAC N
t
t
t
DB0
18
18
18
DB0
t
17
t
10
t
12
t
19
06844-004
Figure 4. Daisy-Chain Timing Diagram
Rev. 0 | Page 6 of 28
AD5025/AD5045/AD5065
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to GND −0.3 V to +7 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
V
A or V
OUT
V
A or V
REF
Operating Temperature Range, Industrial −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ
Power Dissipation (TJ
θJA Thermal Impedance 150.4°C/W
Reflow Soldering Peak Temperature
SnPb 240°C
Pb-Free 260°C
B to GND −0.3 V to VDD + 0.3 V
OUT
B to GND −0.3 V to VDD + 0.3 V
REF
) 150°C
MAX
− TA)/θJA
MAX
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 7 of 28
AD5025/AD5045/AD5065
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LDAC
SYNC
V
REF
V
OUT
POR
SDO
V
DD
A
A
1
2
AD5025/
3
AD5045/
4
AD5065
TOP VIEW
5
(Not to Scale)
6
7
14
SCLK
13
DIN
12
PDL
11
GND
V
B
10
OUT
9
V
B
REF
8
CLR
06844-005
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This
LDAC
allows all DAC outputs to simultaneously update. This pin can be tied permanently low in standalone
mode. When daisy-chain mode is enabled, this pin cannot be tied permanently low. The LDAC
be used in asynchronous LDAC update mode, as shown in Figure 3, and the LDAC pin must be brought
high after pulsing. This allows all DAC outputs to simultaneously update.
2
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
SYNC
low, it powers on the SCLK and DIN buffers and enables the input register. Data is transferred in on the
3 VDD
falling edges of the next 32 clocks. If SYNC
SYNC
acts as an interrupt and the write sequence is ignored by the device.
Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled
is taken high before the 32nd falling edge, the rising edge of
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4 V
5 V
6 POR
A DAC A Reference Input. This is the reference voltage input pin for DAC A.
REF
A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
OUT
Power-On Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to V
the part to midscale.
7 SDO
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading
back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising
edge of SCLK and is valid on the falling edge of the clock.
8
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
CLR
ignored. When CLR
is activated, the input register and the DAC register are updated with the data
contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
9 V
10 V
B DAC B Reference Input. This is the reference voltage input pin for DAC B.
REF
B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
OUT
11 GND Ground Reference Point for All Circuitry on the Part.
12
The PDL pin is used to ensure hardware shutdown lockout of the device under any circumstance. A
PDL
Logic 1 at the PLO
pin causes the device to behave as normal. The user may successfully enter
software power-down over the serial interface while Logic 1 is applied to the PDL
If a Logic 0 is applied to this pin, it ensures that the device cannot enter software power-down under
any circumstances. If the device had previously been placed in software power-down mode, a high-to-
low transition at the PDL pin causes the DAC(s) to exit power-down and output a voltage corresponding to
the previous code in the DAC register before the device entered software power-down.
13 DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
14 SCLK
Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 50 MHz.
pin.
pin should
powers up
DD
Rev. 0 | Page 8 of 28
AD5025/AD5045/AD5065
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
0.6
0.4
0.2
0
INL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
512 16,640 32,768 48,896 65,024
DAC CODE
Figure 6. AD5065 INL
06844-019
1.0
0.8
0.6
0.4
0.2
0
DNL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
512 16,640 32,768 48,896 65,024
DAC CODE
Figure 9. AD5065 DNL
06844-022
1.0
0.8
0.6
0.4
0.2
0
INL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
0 512 1024 153 6 2048 2560 3072 35 84 4096
DAC CODE
Figure 7. AD5045 INL
1.0
0.8
0.6
0.4
0.2
0
INL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
0 512 1024 153 6 2048 2560 3072 35 84 4096
DAC CODE
Figure 8. AD5025 INL
1.0
0.8
0.6
0.4
0.2
0
DNL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
0 4096 8192 12,288 16,384
06844-020
DAC CODE
06844-023
Figure 10. AD5045 DNL
1.00
0.75
0.50
0.25
0
DNL (LSB)
–0.25
–0.50
–0.75
–1.00
0 4096 8192 12,288 16,384
06844-021
DAC CODE
06844-024
Figure 11. AD5025 DNL
Rev. 0 | Page 9 of 28
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