Analog Devices AD2S93BP, AD2S93AP Datasheet

Low Cost

DEMODIN

CLKOUT

DEMOD OUT

ERROR

AMP

LOS

LATCHES

FREQUENCY

SHAPING

VCO

PHASE

SENSITIVE

DEMODULATOR

C1

C2

R2

VEL

UP-DOWN
COUNTER

REFERENCE

(PRIMARY

EXCITATION)

DIFFERENTIAL

(SECONDARY

VOLTAGE)

REF

A
B

LOS

GAIN

V

DD

OVR

UNR

NULL

CS

DATA
SCLK

ACERROR

AC RATIO

BRIDGE

DIFF

DECODE

LOGIC

C3

AD2S93

INTIN

R4

R3

SERIAL

INTERFACE

DIR

R5

R1

C4

R6

R7

VCO GAIN

a

FEATURES
Full Function Monolithic LVDT-to-Digital Converter
Absolute Serial Data Output
Uncommitted Differential Input
Repeatability
Remote Diagnostics
14-Bit Resolution
Industrial Temperature Range
28-Pin PLCC
Low Power

APPLICATIONS
Industrial Gauging
Industrial Process Control
Linear Positioning Systems
Linear Actuator Control
Automotive Motion Sensing and Control
Torque Sensing Conditioner
AC Strain Gages Conditioning
Avionics

LVDT-to-Digital Converter

AD2S93

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The AD2S93 is a complete 14-bit resolution tracking LVDT-to­digital converter. A Type II tracking loop is employed to track
the A–B input and produce a digital output equal to (A–B)/
(REF/2), where REF is a fixed amplitude ac reference phase co­herent with the A–B input. This allows the measurement of any
2-, 3-, 4- and 5-wire LVDT or linear amplitude modulated in­put. The operating frequency range is from 360 Hz to 10 kHz
with user definable bandwidth set externally within a range of
45 Hz to 1250 Hz.

The AD2S93 has a 16-bit serial output. The MSB (LOS), read
first, indicates a loss of the signal A, B, or reference inputs to the
converter or transducer. The second and third MSBs are flags
indicating whether [–REF/2 (UNR) ≤ A–B ≤ +REF/2 (OVR]) is
outside the linear operating range of the converter. The dis­placement data is presented as 13-bit offset binary giving a ±12­bit operating range. LOS, OVR and UNR are pinned out on
the device, in addition a NULL flag is available which is set
when (A–B) = 0.

Absolute displacement information is accessed when

CS is taken
LO followed by the application of an external clock (SCLK)
with a maximum rate of 2 MHz. Data is read MSB first. When
CS is high the DATA output is high impedance; this allows
daisy chaining of more than one converter onto a common bus.

The A, B differential input allows the user to scale the A, B in­puts between 1 and 10. This enables the user to accurately set
up the inputs matching the REF input to the DIFF output. The

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

DIFF output is the resultant A–B. The AD2S93 operates using
±5 V ± 5% power supplies and is fabricated on Analog Devices’
linear compatible CMOS process (LC

2

MOS). The (LC2MOS)
is a mixed technology process that combines precision bipolar
circuits with low power logic.

PRODUCT HIGHLIGHTS

Complete LVDT-to-Digital Interface. The AD2S93 pro-

vides the complete solution for digitizing LVDT signals to 14­bit resolution.

Serial 16-Bit Output Data. One 16-bit read from the
AD2S93 determines input signal continuity (LOS), over and
underrange detection and 13 bits of offset binary displacement
information.

High Accuracy Grade in Low Cost Package. 0.05% and

0.1% integral linearity over the full –40°C to +85°C operating
temperature range.

Uncommitted Differential Input. Allows configuration of 2-,
3-, 4- and 5-wire LVDTs.

Multiple Converter Interfacing. High impedance data out­put and a simple three-wire interface reduces cabling and elimi­nates bus contention.

Low Power. 70 mW power consumption (typ).

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

(VDD = +5 V ± 5%; VSS = –5 V ± 5%, AGND = DGND = 0 V, TA = –40°C to +85°C

AD2S93–SPECIFICATIONS

Parameter Test Conditions Min Typ Max Units

unless otherwise noted)

SIGNAL INPUTS

Frequency 0.36 1.0 10 kHz
Max Voltage Level
Nominal Full Scale

1

2

0.8 1.0 1.2 V rms

1.0 V rms

Input Bias Current @ +25°C 1.1 µA
Input Impedance 1.0 MΩ
CMRR 57 dB
Maximum Sensitivity

3

V

= 1 V rms, G = 1 342 µV pk/LSB

A–B

REFERENCE INPUT

Frequency 0.36 10 kHz
Voltage Level 1.8 2.0 2.2 V rms
Input Bias Current @ 0 V +25°C1µA
Input Impedance 1.0 MΩ
Permissible Phase Shift

4

Signal to Reference –10 +10 Degrees

CONVERTER DYNAMICS

Bandwidth Set by User

VCO Mode = 1 VCO Gain Connected to

VCO I/P 500 1250 Hz

VCO Mode = 2 VCO Gain No Connect 45 500 Hz

Maximum Slew Rate

Mode = 1 2400 3000 LSB/ms
Mode = 2 800 1000 LSB/ms

ACCURACY

Integral Linearity AP 0.1 % FSD

BP 0.05 % FSD

Differential Linearity AP <2 LSB

BP <1 LSB

Repeatability ±1 LSB
Zero Position Offset AP @ +25°C –3 3 LSB

BP @ +25°C –1 1 LSB
AP @ –40°C to +85°C –4 4 LSB
BP @ –40°C to +85°C –2 2 LSB

Gain Error ±0.7 % FS

VELOCITY OUTPUT

Max Output Voltage Denotes Max Input Speed ±4.0 V dc
Load Drive Capability ±250 µA

INL

INH

CS

3.5 V dc

1.5 V dc
500 nA

LOGIC INPUTS SCLK,

Input High Voltage V
Input Low Voltage V
Input Current I

IN

Input Capacitance 10 pF

LOGIC OUTPUTS

OVR, UNR, NULL, DATA, A, B CLKOUT DIR
Output High Voltage @ 1 mA 4.0 V dc
Output Low Voltage @ 1 mA 1.0 V dc

LOS OUTPUT Open Drain Output

Pull-Up to +V

via 12 kΩ 400 µA

DD

Drive Capability

Signal Threshold (A-B) 0.1 0.2 V rms
REF Threshold 0.22 V rms
Timeout Threshold 50 ms

–2–

REV. A

AD2S93

Parameter Test Conditions Min Typ Max Units

SERIAL CLOCK (SCLK)

SCK Input Rate 2 MHz
Maximum Read Rate (16 Bits) Continuous 9.2 µs

POWER SUPPLY

I

DD

I

SS

NOTES

1

The signal input voltage maximum should always be set at 10% less than the reference input.

2

Nominal + FS = V

3

With G = 10; Sensitivity 34.2 µV pk/LSB

4

Phase shift cause gain errors. “See Phase Shift and Quadrative Effects.”

A–B

= V

/2, FS = –V

REF

A–B

= V

REF

/2

Specifications subject to change without notice.

5710 mA
5710 mA

TIMING CHARACTERISTICS

(VDD = +5 V ± 5%, AGND = DGND = 0 V, TA = –40°C to +85°C unless otherwise noted)

Parameter AD2S93 Units Test Conditions

1

t

1

t

2

t

3

t

4

t

5

t

6

t

7

NOTE

1

SCLK can only be applied after t2 has elapsed.

150 ns max CS to DATA Enable
600 ns min CS to 1st SCLK Positive Edge
250 ns min SCLK High Pulse
250 ns min SCLK Low Pulse
100 ns max SCLK Positive Edge to DATA Valid
600 ns min CS High Pulse Width
150 ns max CS High to DATA High Z (Bus Relinquish)

t

6

*

t

LSBMSB

CS

SCLK

DATA

t

2

t

3

t

4

t

1

t

5

t

7

REV. A

t * = THE MINIMUM ACCESS TIME: USER DEPENDENT
TOTAL MAX READ TIME =

TOTAL MAX READ TIME = 600 +16 (250 + 250) + 150 ns
TOTAL MAX READ TIME = 600 + 8000 + 150 ns
TOTAL MAX READ TIME = 8.750 µs (SINGLE READ ONLY)

t

+ 16. (

2

t

+

t

) +

t

3

4

7

Timing Diagram

–3–

AD2S93

WARNING!

ESD SENSITIVE DEVICE

RECOMMENDED OPERATING CONDITIONS

Power Supply Voltage (VDD–V

) . . . . . . . . . . . ±5 V dc ± 5%

SS

Analog Input Voltage (A, B) . . . . . . . . . . . . . . 1 V rms ± 10%

Analog Reference Input (REF) . . . . . . . . . . . . 2 V rms ± 10%

Signal and Reference Harmonic Distortion . . . . . . . . . . . <10%

Operating Temperature Range

Industrial (AP, BP) . . . . . . . . . . . . . . . . . . .–40°C to +85°C

ABSOLUTE MAXIMUM RATINGS*

VDD to AGND . . . . . . . . . . . . . . . . . . .–0.3 V dc to + 7.0 V dc

to AGND . . . . . . . . . . . . . . . . . . . +0.3 V dc to – 7.0 V dc

V

SS

AGND to DGND . . . . . . . . . . . . –0.3 V dc to V

Analog Inputs to AGND REF . . . . V

A, B . . . . . . . . . . . . . . . . . . . . . . . . . V

– 0.3 V to VDD + 0.3 V

SS

– 0.3 V to VDD + 0.3 V

SS

Analog Output to AGND VEL . . . . . . . . . . . . . . . . V

+ 0.3 V dc

DD

to V

SS

DD

Digital Inputs to DGND

CS, SCLK . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

+ 0.3 V

DD

Digital Outputs to DGND

NULL, DIR, CLKOUT, DATA . . . . –0.3 V to V

+ 0.3 V

DD

Operating Temperature Range

Industrial (A, B) . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . +300°C

Power Dissipation to +75°C . . . . . . . . . . . . . . . . . . +100 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C

*

Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

DIFF

AGND

DATA
SCLK

CS

NC

UNR

CLKOUT

NC

GAIN

LOS

423

5
6
7
8

9
10
11

OVR

NULL

NC = NO CONNECT

AD2S93

TOP VIEW

(Not to Scale)

DIR

B

A

28

27

1

15 18

16121413

17

SS

DD

V

V

DGND

NC

26

25
24
23
22

21
20
19

DEMODOUT

NC
REF
VEL
INTIN
VCOGAIN
ACERROR
DEMODIN

ORDERING GUIDE

Temperature Package

Model Range Linearity Option

AD2S93AP –40°C to +85°C 0.1% P-28A
AD2S93BP –40°C to +85°C 0.05% P-28A

PIN DESIGNATIONS

Pin
No. Mnemonic Description

1 AGND Analog Ground.
2 DIFF Output of Signal Input Preamplifier.
3 GAIN Connect GAIN Pin to DIFF for

nominal × 1. Gains greater than
1 can be resistively scaled.
Do not leave unconnected.

4 LOS Denotes A or B lines loss of

connection and/or loss of reference
to transducer or converter.

5 DATA 16-bit serial data output 13 bits of

absolute position information plus
overrange and underrange plus LOS.

6 SCLK Serial Clock. Maximum rate = 2 MHz.

CS Chip Select. Loads serial interface

7

with current positional information
and enable output.

9, 12 UNR, OVR Two pins that denote whether the

input signals are underrange or

overrange.
10 CLKOUT Updates every LSB.
13 NULL Denotes Null Position.
14 DIR Indicates direction. DIR is HI for

positive displacement and LO for

negative displacement.
15 DGND Digital Ground.
16 V

SS

Negative Power Supply –5.0 V dc

± 5%.
17 V

DD

Positive Power Supply +5.0 V dc

± 5%.
18 DEMODOUT Output of the Phase Sensitive

Demodulator.
19 DEMODIN Input to Phase Sensitive

Demodulator.
20 ACERROR AC Error Output.

21 VCO GAIN Sets the VCO gain internally.

Connect to VEL for 2400 LSB/s.

Disconnect for 800 LSB/s.
22 INTIN Determines system dynamics connect

C and RC (serial) parallel

combination across INTIN and

VEL to determine loop dynamics.
23 VEL Analog Velocity Output.
24 REF Single ended input for fixed

amplitude reference.
27, 28 B, A Uncommitted differential inputs

for the A, B signal inputs.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD2S93 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. A