Analog Devices AD2S90 Datasheet

Low Cost, Complete 12-Bit

a

FEATURES
Complete Monolithic Resolver-to-Digital Converter
Incremental Encoder Emulation (1024-Line)
Absolute Serial Data (12-Bit)
Differential Inputs
12-Bit Resolution
Industrial Temperature Range
20-Lead PLCC
Low Power (50 mW)

APPLICATIONS
Industrial Motor Control
Servo Motor Control
Industrial Gauging
Encoder Emulation
Automotive Motion Sensing and Control
Factory Automation
Limit Switching

GENERAL DESCRIPTION

The AD2S90 is a complete 12-bit resolution tracking resolver­to-digital converter. No external components are required to
operate the device.

The converter accepts 2 V rms ± 10% input signals in the range

3 kHz–20 kHz on the SIN, COS and REF inputs. A Type II
servo loop is employed to track the inputs and convert the input
SIN and COS information into a digital representation of the
input angle. The bandwidth of the converter is set internally at
1 kHz within the tolerances of the device. The guaranteed maxi­mum tracking rate is 500 rps.

Angular position output information is available in two forms,
absolute serial binary and incremental A quad B.

The absolute serial binary output is 12-bit (1 in 4096). The data
output pin is high impedance when Chip Select CS is logic HI.
This allows the connection of multiple converters onto a com­mon bus. Absolute angular information in serial pure binary
form is accessed by CS followed by the application of an exter­nal clock (SCLK) with a maximum rate of 2 MHz.

The encoder emulation outputs A, B and NM continuously
produce signals equivalent to a 1024 line encoder. When de­coded this corresponds to 12 bits of resolution. Three common
north marker pulsewidths are selected via a single pin (NMC).

An analog velocity output signal provides a representation of
velocity from a rotating resolver shaft traveling in either a clock­wise or counterclockwise direction.

Resolver-to-Digital Converter

AD2S90

FUNCTIONAL BLOCK DIAGRAM

REF

SIN

SIN LO

COS

COS LO

NMC

NM

CS

SCLK
DATA

A
B

ANGLE

u

DECODE

LOGIC

HIGH ACCURACY

SIN COS

MULTIPLIER

DIGITAL

ANGLE f

UP-DOWN
COUNTER

LATCH

SERIAL INTERFACE

The AD2S90 operates on ±5 V dc ± 5% power supplies and is

fabricated on Analog Devices’ Linear Compatible CMOS pro­cess (LC

2

MOS). LC2MOS is a mixed technology process that
combines precision bipolar circuits with low power CMOS logic
circuits.

PRODUCT HIGHLIGHTS

Complete Resolver-Digital Interface. The AD2S90 provides

the complete solution for digitizing resolver signals (12-bit reso­lution) without the need for external components.

Dual Format Position Data. Incremental encoder emulation
in standard A QUAD B format with selectable North Marker
width. Absolute serial 12-bit angular binary position data
accessed via simple 3-wire interface.

Single High Accuracy Grade in Low Cost Package. ±10.6 arc

minutes of angular accuracy available in a 20-lead PLCC.

Low Power. Typically 50 mW power consumption.

SIN (u – f

ERROR

AMPLIFIER

U/D
CLK

)

P.S.D. AND

FREQUENCY

SHAPING

HIGH

DYNAMIC

RANGE V.C.O.

VEL

CLKOUT

DIR

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

(VDD = +5 V ⴞ 5%, VSS = –5 V ⴞ 5%, AGND = DGND = 0 V, TA = –40ⴗC to +85ⴗC unless

AD2S90–SPECIFICATIONS

otherwise noted)

Parameter Min Typ Max Units Test Condition

SIGNAL INPUTS

Voltage Amplitude 1.8 2.0 2.2 V rms Sinusoidal Waveforms, Differential

SIN to SINLO, COS to COSLO
Frequency 3 20 kHz
Input Bias Current 100 nA V

Input Impedance 1.0 MΩ V

Common-Mode Volts

1

100 mV peak CMV @ SINLO, COSLO w.r.t.

= 2 ± 10% V rms

IN

= 2 ± 10% V rms

IN

CMRR 60 dB AGND @ 10 kHz

REFERENCE INPUT

Voltage Amplitude 1.8 2.0 3.35 V rms Sinusoidal Waveform
Frequency 3 20 kHz
Input Bias Current 100 nA

Input Impedance 100 kΩ

Permissible Phase Shift –10 +10 Degrees Relative to SIN, COS Inputs

CONVERTER DYNAMICS

Bandwidth 700 840 1000 Hz
Maximum Tracking Rate 500 rps
Maximum VCO Rate (CLKOUT) 2.048 MHz
Settling Time

1° Step 2 7 ms
179° Step 20 ms

ACCURACY

Angular Accuracy
Repeatability

2

3

±10.6 + 1 LSB arc min

1 LSB

VELOCITY OUTPUT

Scaling 120 150 180 rps/V dc

Output Voltage at 500 rps ±2.78 ±3.33 ±4.17 V dc
Load Drive Capability ±250 µAV

= ±2.5 V dc (typ), RL ≥ 10 kΩ

OUT

LOGIC INPUTS SCLK, CS

Input High Voltage (V
Input Low Voltage (V
Input Current (I

IN

) 3.5 V dc VDD = +5 V dc, VSS = –5 V dc

INH

) 1.5 V dc VDD = +5 V dc, VSS = –5 V dc

INL

) 10µA

Input Capacitance 10 pF

LOGIC OUTPUTS DATA, A, B,

4

NM, CLKOUT, DIR VDD = +5 V dc, VSS = –5 V dc

Output High Voltage 4.0 V dc I
Output Low Voltage 1.0 V dc I

0.4 V dc I

= 1 mA

OH

= 1 mA

OL

= 400 µA

OL

SERIAL CLOCK (SCLK)

SCLK Input Rate 2 MHz

NORTH MARKER CONTROL (NMC)

90° +4.75 +5.0 +5.25 V dc North Marker Width Relative to
180° –0.75 DGND +0.75 V dc “A” Cycle
360° –4.75 –5.0 –5.25 V dc

POWER SUPPLIES

V

DD

V

SS

I

DD

I

SS

NOTES

1

If the tolerance on signal inputs = ±5%, then CMV = 200 mV.

2

1 LSB = 5.3 arc minute.

3

Specified at constant temperature.

4

Output load drive capability.

Specifications subject to change without notice.

+4.75 +5.00 +5.25 V dc
–4.75 –5.00 –5.25 V dc

10 mA
10 mA

–2–

REV. D

TIMING CHARACTERISTICS

(VDD = +5 V ⴞ 5%, VSS = –5 V ⴞ 5%, AGND = DGND = 0 V, TA = –40ⴗC to +85ⴗC unless

1, 2

otherwise noted)

AD2S90

CSB

SCLK

DATA

t

2

t

3

t

4

t

1

*THE MINIMUM ACCESS TIME: USER DEPENDENT

t

5

t

6

t*

LSBMSB

t

7

Figure 1. Serial Interface

NOTES

1

Timing data are not 100% production tested. Sample tested at +25°C only to ensure conformance to data sheet limits. Logic output timing tests carried out using
10 pF, 100 kΩ load.

2

Capacitance of data pin in high impedance state = 15 pF.

Parameter AD2S90 Units Test Conditions/Notes

t

1

1

t

2

t

3

t

4

t

5

t

6

t

7

NOTE

1

SCLK can only be applied after t2 has elapsed.

150 ns max CS to DATA Enable
600 ns min CS to 1st SCLK Negative Edge
250 ns min SCLK Low Pulse
250 ns min SCLK High Pulse
100 ns max SCLK Negative Edge to DATA Valid
600 ns min CS High Pulsewidth
150 ns max CS High to DATA High Z (Bus Relinquish)

A

B

908

1808

NM

3608

NUMBER OF DEGREES REFERS TO WIDTH RELATIVE TO "A" CYCLE

Figure 2. Incremental Encoder

CLKOUT

A, B, NM

t

DIR

DIR

Figure 3. DIR/CLKOUT/A, B and NM Timing

AD2S90

Parameter Min Max Units Test Conditions/Notes

t

DIR

t

CLK

t

ABN

250 400 ns CLKOUT Pulsewidth

200 ns DIR to CLKOUT Positive Edge

250 ns CLKOUT Negative Edge to A, B and NM Transition

COUNTER IS CLOCKED

ON THIS EDGE

t

CLK

t

ABN

REV. D

–3–

AD2S90

RECOMMENDED OPERATING CONDITIONS

Power Supply Voltage (VDD – V

) . . . . . . . . . . ±5 V dc ± 5%

SS

Analog Input Voltage (SIN, COS & REF) . . . . .2 V rms ± 10%

Signal and Reference Harmonic Distortion . . . . . . . . . . . . 10%

Phase Shift between Signal and Reference . . . . . . . . . . . . . ±10°

Ambient Operating Temperature Range

Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

ABSOLUTE MAXIMUM RATINGS*

VDD to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V dc to +7.0 V dc

to AGND . . . . . . . . . . . . . . . . . . . . +0.3 V dc to –7.0 V dc

V

SS

AGND to DGND . . . . . . . . . . . . –0.3 V dc to V

+ 0.3 V dc

DD

Analog Inputs to AGND

REF . . . . . . . . . . . . . . . . . . V

SIN, SIN LO . . . . . . . . . . . V

COS, COS LO . . . . . . . . . . V

– 0.3 V dc to VDD + 0.3 V dc

SS

– 0.3 V dc to VDD + 0.3 V dc

SS

– 0.3 V dc to VDD + 0.3 V dc

SS

Analog Output to AGND

VEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

SS

to V

DD

Digital Inputs to DGND, CSB,

SCLK, RES . . . . . . . . . . . . . . . –0.3 V dc to V

+ 0.3 V dc

DD

Digital Outputs to DGND, NM, A, B,

DIR, CLKOUT DATA . . . . . . –0.3 V dc to V

+ 0.3 V dc

DD

Operating Temperature Range

Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C

Power Dissipation to +75°C . . . . . . . . . . . . . . . . . . . . 300 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model Temperature Range Accuracy Package Option

AD2S90AP –40°C to +85°C 10.6 arc min P-20A

PIN CONFIGURATION

SIN LO

SIN

AGND

COS

DATA
SCLK

CS

4
5
6
7

A

8

B

3 2 1 20 19

AD2S90

TOP VIEW

(Not to Scale)

9 10 11 12 13

NM

DIR

PIN 1
IDENTIFIER

SS

V

DGND

COS LO

18
17
16
15
14

DD

V

REF
VEL
CLKOUT
NMC
V

DD

PIN DESCRIPTIONS

Pin
No. Mnemonic Function

1 AGND Analog ground, reference ground.

2 SIN SIN channel noninverting input connect to

resolver SIN HI output. SIN to SIN LO =

2 V rms ± 10%.

3 SIN LO SIN channel inverting input connect to

resolver SIN LO.

4 DATA Serial interface data output. High impedance

with CS = HI. Enabled by CS = 0.

5 SCLK Serial interface clock. Data is clocked out on

“first” negative edge of SCLK after a LO transi­tion on CS. 12 SCLK pulses to clock data out.

6 CS Chip select. Active LO. Logic LO transition

enables DATA output.

7 A Encoder A output.

8 B Encoder B output.

9 NM Encoder North Marker emulation output.

Pulse triggered as code passes through zero.
Three common pulsewidths available.

10 DIR Indicates direction of rotation of input.

Logic HI = increasing angular rotation.
Logic LO = decreasing angular rotation.

11 DGND Digital power ground return.

12 V

13 V

14 V

SS

DD

DD

Negative power supply, –5 V dc ± 5%.
Positive power supply, +5 V dc ± 5%.
Positive power supply, +5 V dc ± 5%. Must

be connected to Pin 13.

15 NMC North marker width control. Internally pulled

HI via 50 kΩ nominal.

16 CLKOUT Internal VCO clock output. Indicates angular

velocity of input signals. Max nominal rate =

1.536 MHz. CLKOUT is a 300 ns positive pulse.

17 VEL Indicates angular velocity of input signals.

Positive voltage w.r.t. AGND indicates in­creasing angle. FSD = 375 rps.

18 REF Converter reference input. Normally derived

from resolver primary excitation. REF = 2 V
rms nominal. Phase shift w.r.t. COS and SIN

= ±10° max

19 COS LO COS channel inverting input. Connect to

resolver COS LO.

20 COS COS channel noninverting input. Connect to

resolver COS HI output. COS = 2 V rms ± 10%.

CAUTION

The AD2S90 features an input protection circuit consisting of large “distributed” diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and
fast, low energy pulses (Charges Device Model).

Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. For further information on ESD precautions, refer to Analog Devices ESD
Prevention Manual.

–4–

WARNING!

ESD SENSITIVE DEVICE

REV. D