Analog Devices AD2S80A Datasheet

Variable Resolution, Monolithic

a

FEATURES
Monolithic (BiMOS ll) Tracking R/D Converter
40-Pin DIP Package
44-Pin LCC Package
10-,12-,14- and 16-Bit Resolution Set by User
Ratiometric Conversion
Low Power Consumption: 300 mW typ
Dynamic Performance Set by User
High Max Tracking Rate 1040 RPS (10 Bits)
Velocity Output
Industrial Temperature Range Versions
Military Temperature Range Versions
ESD Class 2 Protection (2,000 V min)
/883 B Parts Available

APPLICATIONS
DC Brushless and AC Motor Control
Process Control
Numerical Control of Machine Tools
Robotics
Axis Control
Military Servo Control

GENERAL DESCRIPTION

The AD2S80A is a monolithic 10-, 12-, 14- or 16-bit tracking
resolver-to-digital converter contained in a 40-pin DIP or 44­pin LCC ceramic package. It is manufactured on a BiMOS II
process that combines the advantages of CMOS logic and bipo­lar high accuracy linear circuits on the same chip.

The converter allows users to select their own resolution and dy-
namic performance with external components. This allows the users
great flexibility in defining the converter that best suits their sys­tem requirements. The converter allows users to select the reso­lution to he 10, 12, 14 or 16 bits and to track resolver signals
rotating at up to 1040 revs per second (62,400 rpm) when set to
10-bit resolution.

The AD2S80A converts resolver format input signals into a par­allel natural binary digital word using a ratiometric tracking con­version method. This ensures high-noise immunity and tolerance
of lead length when the converter is remote from the resolver.

The 10-, 12-, 14- or 16-bit output word is in a three-state digi­tal logic available in 2 bytes on the 16 output data lines. BYTE
SELECT,

ENABLE and INHIBIT pins ensure easy data trans-
fer to 8- and 16-bit data buses, and outputs are provided to al­low for cycle or pitch counting in external counters.

An analog signal proportional to velocity is also available and
can be used to replace a tachogenerator.

The AD2S80A operates over 50 Hz to 20,000 Hz reference
frequency.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

SIG GND

ANALOG

Resolver-to-Digital Converter

AD2S80A

FUNCTIONAL BLOCK DIAGRAM

DEMOD

O/P

DEMOD

I/P

AC ERROR

O/P

SIN I/P

COS I/P

GND

RIPPLE

CLK

+12V
–12V

DATA
LOAD

A1

SEGMENT

SWITCHING

A2

16-BIT UP/DOWN COUNTER

SC1

SC2

ENABLE

AD2S80A

R-2R
DAC

OUTPUT DATA LATCH

16 DATA BITS

A3

BYTE

PHASE

SENSITIVE

DETECTOR

VCO DATA
TRANSFER

+5V

SELECT

PRODUCT HIGHLIGHTS

Monolithic. A one chip solution reduces the package size re-

quired and increases the reliability.
Resolution Set by User. Two control pins are used to select

the resolution of the AD2S80A to be 10, 12, 14 or 16 bits al­lowing the user to use the AD2S80A with the optimum resolu­tion for each application.

Ratiometric Tracking Conversion. Conversion technique
provides continuous output position data without conversion
delay and is insensitive to absolute signal levels. It also provides
good noise immunity and tolerance to harmonic distortion on
the reference and input signals.

Dynamic Performance Set by the User. By selecting exter­nal resistor and capacitor values the user can determine band­width, maximum tracking rate and velocity scaling of the
converter to match the system requirements. The external com­ponents required are all low cost preferred value resistors and
capacitors, and the component values are easy to select using
the simple instructions given.

Velocity Output. An analog signal proportional to velocity is
available and is linear to typically one percent. This can be used
in place of a velocity transducer in many applications to provide
loop stabilization in servo controls and velocity feedback data.

Low Power Consumption. Typically only 300 mW.
Military Product. The AD2S80A is available processed in ac-

cordance with MIL-STD-883B, Class B.

MODELS AVAILABLE

Information on the models available is given in the section
“Ordering Information.”

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

LOGIC

BUSY

DIG GND

INTEGRATOR

I/P

INTEGRATOR
O/P

VCO I/P

DIR

INHIBIT

AD2S80A–SPECIFICA TIONS

(typical at +258C unless otherwise noted)

Parameter Conditions Min Typ Max Units

SIGNAL INPUTS

Frequency 50 20,000 Hz
Voltage Level 1.8 2.0 2.2 V rms
Input Bias Current 60 150 nA
Input Impedance 1.0 MΩ
Maximum Voltage 8V pk

REFERENCE INPUT

Frequency 50 20,000 Hz
Voltage Level 1.0 8.0 V pk
Input Bias Current 60 150 nA
Input Impedance 1.0 MΩ

CONTROL DYNAMICS

Repeatability 1 LSB
Allowable Phase Shift (Signals to Reference) –10 +10 Degrees
Tracking Rate 10 Bits 1040 rps

Bandwidth

ACCURACY

Angular Accuracy A, J, S 68 +1 LSB arc min

Monotonicity Guaranteed Monotonic
Missing Codes (16-Bit Resolution) A, B, J, K, S, T 4 Codes

VELOCITY SIGNAL

Linearity Over Full Range ±1 63 % FSD
Reversion Error ±1 ±2 % FSD
DC Zero Offset
DC Zero Offset Tempco –22 µV/°C
Gain Scaling Accuracy ±10 % FSD
Output Voltage 1 mA Load ±8 ±9 ±10.5 V
Dynamic Ripple Mean Value 1.5 % rms O/P
Output Load 1.0 kΩ

INPUT/OUTPUT PROTECTION

Analog Inputs Overvoltage Protection ±8V
Analog Outputs Short Circuit O/P Protection ±5.6 ±8 ±10.4 mA

DIGITAL POSITION

Resolution 10, 12, 14, and 16
Output Format Bidirectional Natural Binary
Load 3 LSTTL

INHIBIT

Sense Logic LO to Inhibit
Time to Stable Data 600 ns

ENABLE

ENABLE Time High Impedance State 35 110 ns

BYTE SELECT

Sense MS Byte DB1–DB8,
LOGIC LO LS Byte DB1–DB8,
Time to Data Available 60 140 ns

SHORT CYCLE INPUTS Internally Pulled High

SC1 SC2

0 0 10 Bit
0 1 12 Bit
1 0 14 Bit
1 1 16 Bit

1

2

3

3

3

12 Bits 260 rps
14 Bits 65 rps
16 Bits 16.25 rps
User Selectable

B, K, T 64 +1 LSB arc min
L, U 62 +1 LSB arc min

L, U 1 Code

Logic LO Enables Position
Output. Logic HI Outputs in

LS Byte DB9–DB16
LS Byte DB9–DB16

(100 kΩ) to +V

S

AD2S80A

6 mV

–2–

REV. A

AD2S80A

Parameter Conditions Min Typ Max Units

AD2S80A

DATA LOAD

Sense Internally Pulled High (100 kΩ) 150 300 ns

to +V

. Logic LO Allows

S

Data to be Loaded into the
Counters from the Data Lines

3

BUSY

Sense Logic HI When Position O/P

Changing
Width 200 600 ns
Load Use Additional Pull-Up 1 LSTTL

DIRECTION

3

Sense Logic HI Counting Up

Logic LO Counting Down
Max Load 3 LSTTL

RIPPLE CLOCK

3

Sense Logic HI

All 1s to All 0s

All 0s to All 1s
Width Dependent on Input Velocity 300
Reset Before Next Busy
Load 3 LSTTL

DIGITAL INPUTS

High Voltage, V

IH

INHIBIT, ENABLE 2.0 V

DB1–DB16, Byte Select

±V

= ±10.8 V, VL = 5.0 V

Low Voltage, V

IL

S

INHIBIT, ENABLE 0.8 V

DB1–DB16, Byte Select

±VS = ±13.2 V, VL = 5.0 V

DIGITAL INPUTS

High Current, I

IH

INHIBIT, ENABLE ±100 µA

DB1–DB16

±V

= ±13.2 V , VL = 5.5 V

Low Current, I

IL

S

INHIBIT, ENABLE ±100 µA

DB1–DB16, Byte Select

±VS = ±13.2 V, VL = 5.5 V

DIGITAL INPUTS

Low Voltage, V

IL

ENABLE = HI 1.0 V

SC1, SC2, Data Load

±V

= ±12.0 V, VL = 5.0 V

Low Current, I

IL

S

ENABLE = HI –400 µA

SC1, SC2, Data Load

±VS = ±12.0 V, VL = 5.0 V

DIGITAL OUTPUTS

High Voltage, V

OH

DB1–DB16 2.4 V

RIPPLE CLK, DIR

±V

= ±12.0 V, VL = 4.5 V

S

I

= 100 µA

Low Voltage, V

OL

OH

DB1–DB16 0.4 V

RIPPLE CLK, DIR

±V

= ±12.0 V, VL = 5.5 V

S

IOL = 1.2 mA

THREE-STATE LEAKAGE DB1–DB16 Only

Current I

L

±VS = ±12.0 V, VL = 5.5 V ±100 µA

V

= 0 V

OL

±V

= ±12.0 V, VL = 5.5 V ±100 µA

S

VOH = 5.0 V

NOTES

1

Refer to small signal bandwidth.

2

Output offset dependent on value for R6.

3

Refer to timing diagram.
Specifications subject to change without notice.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.

REV. A

–3–

AD2S80A–SPECIFICA TIONS

WARNING!

ESD SENSITIVE DEVICE

(typical at +258C unless otherwise noted)

Parameter Conditions Min Typ Max Units

AD2S80A

RATIO MULTIPLIER

AC Error Output Scaling 10 Bit 177.6 mV/Bit

12 Bit 44.4 mV/Bit
14 Bit 11.1 mV/Bit
16 Bit 2.775 mV/Bit

PHASE SENSITIVE DETECTOR

Output Offset Voltage 12 mV
Gain

In Phase w.r.t. REF –0.882 –0.9 –0.918 V rms/V dc
In Quadrature w.r.t. REF ±0.02 V rms/V dc

Input Bias Current 60 150 nA
Input Impedance 1 MΩ
Input Voltage ±8V

INTEGRATOR

Open-Loop Gain At 10 kHz 57 63 dB
Dead Zone Current (Hysteresis) 100 nA/LSB
Input Offset Voltage 15 mV
Input Bias Current 60 150 nA
Output Voltage Range ±VS = ±10.8 V dc ±7V

VCO

Maximum Rate ±V

= ±12 V dc 1.1 MHz

S

VCO Rate Positive Direction 7.1 7.9 8.7 kHz/µA

Negative Direction 7.1 7.9 8.7 kHz/µA

VCO Power Supply Sensitivity

Increase +V

–V

Decrease +V

–V

S

S

S

S

+0.5 %/V
–8.0 %/V
–8.0 %/V

+2.0 %/V
Input Offset Voltage 15 mV
Input Bias Current 70 380 nA
Input Bias Current Tempco –1.22 nA/°C
Input Voltage Range ±8V
Linearity of Absolute Rate

Full Range <2 % FSD

Over 0% to 50% of Full Range <1 % FSD
Reversion Error 1.5 % FSD
Sensitivity of Reversion Error ±8 %/V of

to Symmetry of Power Supplies Asymmetry

POWER SUPPLIES

Voltage Levels

+V

–V

+V

S

S

L

+10.8 +13.2 V
–10.8 –13.2 V
+5 +13.2 V

Current

±I

S

±I

S

±I

L

Specification subject to change without notice.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.

±VS @ ±12 V 612 623 mA
±VS @ 13.2 V 619 630 mA

+VL @ ±5.0 V 60.5 61.5 mA

ESD SENSITIVITY

The AD2S80A features an input protection circuit consisting of large “distributed” diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and
fast, low energy pulses (Charges Device Model).

The AD2S80A is ESD protection Class II (2000 V min). Proper ESD precautions are strongly
recommended to avoid functional damage or performance degradation. For further information
on ESD precautions, refer to Analog Devices ESD Prevention Manual.

–4–

REV. A

AD2S80A

DB3

RIPPLE CLK

INHIBIT

ENABLE

DEMOD O/P
INTEGRATOR O/P

–V

S

SC1

DIRECTION

INTEGRATOR I/P
VCO I/P

BUSY
DATA LOAD
SC2

DIGITAL GND

BYTE SELECT

V

L

DB16 LSB

DB14

DB15

DB13

DB5

DB7

REFERENCE I/P

DEMOD I/P

ANALOG GND

SIGNAL GND

SIN

AC ERROR O/P

COS

+V

S

MSB DB1

DB2

DB4

DB6

DB8
DB9

DB11

DB10

DB12

13

30

1
2

40
39

5
6
7

36
35

34

3
4

38
37

833
932

10 31
11

12 29

28

14

27

15

26

16

25

17

24
18 23
19

22
20

21

TOP VIEW

(Not to Scale)

AD2S80A

RECOMMENDED OPERATING CONDITIONS

Power Supply Voltage (+VS, –VS) . . . . . . . . . ±12 V dc ± 10%

Power Supply Voltage V

. . . . . . . . . . . . . . . . . +5 V dc ± 10%

L

Analog Input Voltage (SIN and COS) . . . . . . . 2 V rms ± 10%

Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak

Signal and Reference Harmonic Distortion . . . . . . .10% (max)

Phase Shift Between Signal and Reference . . . ±10 Degrees (max)
Ambient Operating Temperature Range

Commercial (JD, KD, LD) . . . . . . . . . . . . . . 0°C to +70°C

Industrial (AD, BD) . . . . . . . . . . . . . . . . . . .–40°C to +85°C

Extended (SD, SE, TD, TE, UD, UE) . . . –55°C to +125°C

ABSOLUTE MAXIMUM RATINGSl

2

+V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V dc

S

–V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –14 V dc

S

+V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +V

L

Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V

SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V

COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V

(

with respect to GND

)

S
S
S
S

Any Logical Input .. . . . . . . . . . . . . . . . . . . –0.4 V dc to +VL dc

Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V

Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V

VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V

S
S
S

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 mW

Operating Temperature

Commercial (JD, KD, LD) . . . . . . . . . . . . . . 0°C to +70°C

Industrial (AD, BD) . . . . . . . . . . . . . . . . . . .–40°C to +85°C

Extended (SD, SE, TD, TE, UD, UE) . . . –55°C to +125°C

3

θ

(40-Pin DIP 883 Parts Only) . . . . . . . . . . . . . . . . 11°C/W

JC

3

θ

(44-Pin LCC 883 Parts Only) . . . . . . . . . . . . . . . . 10°C/W

JC

Storage Temperature (All Grades) . . . . . . . . .–65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C

CAUTION:

1. Absolute Maximum Ratings are those values beyond which damage to the device
may occur.

2. Correct polarity voltages must be maintained on the +VS and –VS pins.

3. With reference to Appendix C of MIL-M-38510.

Bit Weight Table

DIP (D) Package

COS

SIGNAL GND

ANALOG GND

AC ERROR O/P

3124444342414056

SIN

7

+V

8

S

NC

9

MSB DB1

10

DB2

11

DB3

12

DB4

13

DB5

14

DB6

15

DB7

16

DB8

17

NC = NO CONNECT

AD2S80A

(Not to Scale)

18 19 242320 2221 28272625

DB9

DB11

DB10

DB12

PIN CONFIGURATIONS

DEMOD I/P

REFERENCE I/P

TOP VIEW

DB13

DB14

DEMOD O/P

INTEGRATOR I/P

INTEGRATOR O/P

L

+V

DB15

LSB DB16

NC

ENABLE

LCC (E) Package

VCO I/P

–V

39

S

RIPPLE CLOCK

38

DIRECTION

37

BUSY

36

DATA LOAD

35

NC

34
33

SC2
SC1

32

DIGITAL GND

31
30

INHIBIT

NC

29

BYTE SELECT

Binary Resolution Degrees Minutes Seconds
Bits (N) (2N) /Bit /Bit /Bit

0 1 360.0 21600.0 1296000.0
1 2 180.0 10800.0 648000.0
2 4 90.0 5400.0 324000.0
3 8 45.0 2700.0 162000.0
4 16 22.5 1350.0 81000.0

REV. A

5 32 11.25 675.0 40500.0
6 64 5.625 337.5 20250.0
7 128 2.8125 168.75 10125.0
8 256 1.40625 84.375 5062.5
9 512 0.703125 42.1875 2531.25

10 1024 0.3515625 21.09375 1265.625
11 2048 0.1757813 10.546875 632.8125
12 4096 0.0878906 5.273438 316.40625
13 8192 0.0439453 2.636719 158.20313
14 116384 0.0219727 1.318359 79.10156

15 32768 0.0109836 0.659180 39.55078
16 65536 0.0054932 0.329590 19.77539
17 131072 0.0027466 0.164795 9.88770
18 262144 0.0013733 0.082397 4.94385

–5–

PIN DESIGNATIONS

MNEMONIC DESCRIPTION
REFERENCE I/P REFERENCE SIGNAL INPUT

DEMOD I/P DEMODULATOR INPUT
AC ERROR O/P RATIO MULTIPLIER OUTPUT
COS COSINE INPUT
ANALOG GROUND POWER GROUND
SIGNAL GROUND RESOLVER SIGNAL GROUND
SIN SINE INPUT
+V

S

DB1–DB16 PARALLEL OUTPUT DATA
V

L

ENABLE LOGIC Hl-OUTPUT DATA IN HIGH IMPEDANCE

BYTE SELECT LOGIC Hl-MOST SIGNIFICANT BYTE TO DB1–DB8

INHIBIT LOGIC LO INHIBITS DATA TRANSFER TO

DIGITAL GROUND DlGITAL GROUND
SC1–SC2 SELECT CONVERTER RESOLUTION
DATA LOAD LOGIC LO DB1–DB16 INPUTS LOGIC Hl DB1–D16

BUSY CONVERTER BUSY, DATA NOT VALID WHILE

DIRECTION LOGIC STATE DEFINES DIRECTION

RIPPLE CLOCK POSITIVE PULSE WHEN CONVERTER OUTPUT

–V

S

VCO I/P VCO INPUT
INTEGRATOR I/P INTEGRATOR INPUT
INTEGRATOR O/P INTEGRATOR OUTPUT
DEMOD O/P DEMODULATOR OUTPUT

POSITIVE POWER SUPPLY

LOGIC POWER SUPPLY

STATE, LOGIC LO PRESENTS DATA TO THE
OUTPUT LATCHES

LOGIC LO-LEAST SlGNlFlCANT BYTE TO DB1–DB8

OUTPUT LATCHES

OUTPUTS

BUSY Hl

OF INPUT SIGNAL ROTATION

CHANGES FROM 1S TO ALL 0S OR VICE VERSA
NEGATIVE POWER SUPPLY