Analog Devices AD28MSP02KR, AD28MSP02KN, AD28MSP02BR, AD28MSP02BN Datasheet
VOICEBAND
ANALOG
INPUT A
VOICEBAND
ANALOG
INPUT B
DIFFERENTIAL
ANALOG
OUTPUT
DIGITAL
DATA AND
CONTROL
SERIAL
PORT
16-BIT
SIGMA-
DELTA DAC
16-BIT
SIGMA-
DELTA ADC
MUX
+20dB
AMP
VOLTAGE
REFERENCE
PGA
a
Voiceband Signal Port
AD28msp02
FEATURES
Complete Analog I/O Port for Voiceband DSP
Applications
Linear-Coded 16-Bit Sigma-Delta ADC
Linear-Coded 16-Bit Sigma-Delta DAC
On-Chip Anti-Aliasing and Anti-lmaging Filters
On-Chip Voltage Reference
8 kHz Sampling Frequency
Twos Complement Coding
65 dB SNR + THD
Programmable Gain on DAC and ADC
Serial Interface To DSP Processors
24-Pin DlP/28-Lead SOIC
Single 5 V Power Supply
GENERAL DESCRIPTION
The AD28msp02 Voiceband Signal Port is a complete analog
front end for high performance voiceband DSP applications.
Compared to traditional µ-law and A-law codecs, the
AD28msp02’s linear-coded ADC and DAC maintain wide
dynamic range while maintaining superior SNR and THD. A
sampling rate of 8.0 kHz coupled with 65 dB SNR + THD performance make the AD28msp02 attractive in many telecom and
speech processing applications, for example digital cellular radio
and high quality telephones. The AD28msp02 simplifies overall
system design by requiring only a single +5 V power supply.
The inclusion of on-chip anti-aliasing and anti-imaging filters,
16-bit sigma-delta ADC and DAC, and programmable gain
amplifiers ensures a highly integrated and compact solution to
voiceband analog processing requirements. Sigma-delta conversion technology eliminates the need for complex off-chip antialiasing filters and sample-and-hold circuitry.
The AD28msp02’s serial I/O port provides an easy interface to
host DSP microprocessors such as the ADSP-2101, ADSP-2105
and ADSP-2111. The AD28msp02 is available in a 24-pin, 0.3"
plastic DIP and a 28-lead SOIC package.
FUNCTIONAL DESCRIPTION
Figure 1 shows a block diagram of the AD28msp02.
A/D CONVERSION
The A/D conversion circuitry of the AD28msp02 consists of two
analog input amplifiers, an optional 20 dB preamplifier, and
a sigma-delta analog-to-digital converter (ADC). The analog
input signal to the AD28msp02 must be ac-coupled.
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reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
Analog Input Amplifiers
The two analog input amplifiers (NORM, AUX) are internally
biased by an on-chip voltage reference in order to allow operation of the AD28msp02 with a single +5 V power supply.
An analog multiplexer selects either the NORM or AUX amplifier as the input to the ADC’s sigma-delta modulator. The
optional 20 dB preamplifier may be used to increase the signal
level; the preamplifier can be inserted before the modulator or
can be bypassed. Input signal level to the sigma-delta modulator
should not exceed V
, which is specified under “Analog
INMAX
Interface Electrical Characteristics.” Refer to “Analog Input” in
the “Design Considerations” section of this data sheet for more
information.
The input multiplexer and 20 dB preamplifier are configured by
Bits 0 and 1 (IPS, IMS) of the AD28msp02’s control register. If
the multiplexer setting is changed while an input signal is being
processed, the ADC’s output must be allowed time to settle to
ensure that the output data is valid.
ADC
The ADC consists of a 2nd-order analog sigma-delta modulator,
an anti-aliasing decimation filter, and a digital high-pass filter.
The sigma-delta modulator noise-shapes the signal and produces 1-bit samples at a 1.0 MHz rate. This bit stream, which
represents the analog input signal, is fed to the anti-aliasing
decimation filter.
Decimation Filter
The anti-aliasing decimation filter contains two stages. The first
stage is a sinc
4
digital filter that increases resolution to 16 bits
and reduces the sample rate to 40 kHz. The second stage is an
IIR low-pass filter.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
AD28msp02
VFB
NORM
VIN
NORM
VFB
AUX
VIN
AUX
V
REF
VOUT
P
VOUT
N
VOLTAGE
REFERENCE
OUTPUT
DIFFERENTIAL
AMP
NORM
AUX
INPUT
AMP
INPUT
AMP
PGA
MUX
16-BIT SIGMA-DELTA ADC
+20dB
AMP
ANALOG
SMOOTHING
FILTER
1.0
MHz
1
SIGMA-DELTA
MODULATOR
SIGMA-DELTA
MODULATOR
ANALOG
16-BIT SIGMA-DELTA DAC
DIGITAL
1.0
MHz
1.0
MHz
1
16
ANTI-ALIASING
DECIMATION
FILTER
ANTI-IMAGING
INTERPOLATION
FILTER
Figure 1. AD28msp02 Block Diagram
8.0
kHz
16
DIGITAL
HIGH-PASS
FILTER
CONTROL
REGISTER
DIGITAL
HIGH-PASS
FILTER
16 16
8.0
kHz
kHz
8.0
kHz
SDOFS
SDO
8.0
DATA/
SERIAL
PORT
16
CNTRL
SCLK
SDI
SDIFS
CS
The IIR low-pass filter is a 10th-order elliptic filter with a passband edge at 3.7 kHz and a stopband attenuation of 65 dB at
4 kHz. This filter has the following specifications:
Filter type: 10th-order low-pass elliptic IIR
Sample frequency: 40.0 kHz
Passband cutoff:* 3.70 kHz
Passband ripple: ±0.2 dB
Stopband cutoff: 4.0 kHz
Stopband ripple: –65.00 dB
*The passband cutoff frequency is defined to be the last point in the passband
that meets the passband ripple specification.
(Note that these specifications apply only to this filter, and not to the entire
ADC. The specifications can be used to perform further analysis of the exact
characteristics of the filter, for example using a digital filter design software
package.)
Figure 2 shows the frequency response of the IIR low-pass filter.
0
–20
–40
–60
LOG MAGNITUDE – dB
–80
–100
2000
FREQUENCY – Hz
4400380032002600
5000
Figure 2. IIR Low-Pass Filter Frequency Response
High-Pass Filter
The digital high-pass filter removes frequency components at
the low end of the spectrum; it attenuates signal energy below
the passband of the converter. The high-pass filter can be
bypassed by setting the ADBY bit (Bit 3) of the AD28msp02’s
control register.
The high-pass filter is a 4th-order elliptic filter with a passband
cutoff at 150 Hz. Stopband attenuation is 25 dB. This filter has
the following specifications:
Filter type: 4th-order high-pass elliptic IIR
Sample frequency: 8.0 kHz
Passband cutoff: 150.0 Hz
Passband ripple: ±0.2 dB
Stopband cutoff: 100.0 Hz
Stopband ripple: –25.00 dB
(Note that these specifications apply only to this filter, and not to the entire
ADC. The specifications can be used to perform further analysis of the exact
characteristics of the filter, for example using a digital filter design software
package.)
Figure 3 shows the frequency response of the high-pass filter.
0
–20
–40
–60
LOG MAGNITUDE – dB
–80
–100
0
FREQUENCY – Hz
24018012060
300
Figure 3. High-Pass Filter Frequency Response
Passband ripple is ±0.2 dB for the combined effects of the
ADC’s digital filters (i.e., high-pass filter and IIR low-pass of
the decimation filter) in the 300 Hz–3400 Hz passband.
The output of the ADC is transferred to the AD28msp02’s
serial port (SPORT) at an 8 kHz rate, for transmission to the
host DSP processor. Maximum group delay in the ADC will not
exceed 1 ms in the region from 300 Hz to 3 kHz.
–2–
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AD28msp02
PIN DESCRIPTIONS
Pin Name I/O/Z Function
VIN
NORM
I Analog input to inverting terminal of
NORM input amplifier.
VFB
VIN
NORM
AUX
O Output terminal of NORM amplifier.
I Analog input to inverting terminal of
AUX input amplifier.
VFB
AUX
VOUT
P
O Output terminal of AUX amplifier.
O Analog output from noninverting
terminal of differential output amplifier.
VOUT
N
O Analog output from inverting terminal of
differential output amplifier.
V
REF
O On-chip bandgap voltage reference
(2.5 V ± 10%).
MCLK I Master clock input; frequency must
equal 13.0 MHz to guarantee listed
specifications.
SCLK O/Z Serial clock used to clock data or control
bits to and from the serial port
(SPORT). The frequency of SCLK is
equal to the frequency of the master
clock (MCLK) divided by 5. SCLK is
3-stated when CS is low.
SDI I Serial data input of SPORT. Both data
and control information are input on
this pin. Input at SDI is ignored when
CS is low.
SDO O/Z Serial data output of SPORT. Both data
and control information are output on
this pin. SDO is 3-stated when CS is
low.
SDIFS I Framing signal for SDI serial transfers.
Input at SDIFS is ignored when CS is
low.
SDOFS O/Z Framing signal for SDO serial transfers.
SDOFS is 3-stated when CS is low.
DATA/
CNTRL I Configures AD28msp02 for either data
or control information transfers (via
SPORT).
CS I Active-high chip select. Can be used to
3-state the SPORT interface; when CS
is low, the SCLK, SDO, and SDOFS
outputs are 3-stated and the SDI and
SDIFS inputs are ignored. If CS is de-
asserted during a serial data transfer, the
16-bit word being transmitted is lost.
RESET I Active low reset signal; resets Control
Register and clears digital filters.
RESET
does not 3-state the SPORT outputs
(SCLK, SDO, SDOFS).
V
CC
GND
V
DD
GND
A
D
Analog supply voltage; nominal +5 V.
Analog ground.
Digital supply voltage; nominal +5 V.
Digital ground.
D/A CONVERSION
The D/A conversion circuitry of the AD28msp02 consists of a
sigma-delta digital-to-analog converter (DAC), an analog
smoothing filter, a programmable gain amplifier, and a differential output amplifier.
DAC
The AD28msp02’s sigma-delta DAC implements digital filters
and a sigma-delta modulator with the same characteristics as the
filters and modulator of the ADC. The DAC consists of a digital
high-pass filter, an anti-imaging interpolation filter, and a digital
sigma-delta modulator.
The DAC receives 16-bit samples from the host DSP processor
via AD28msp02’s serial port at an 8 kHz rate. If the host processor fails to write a new value to the serial port, the existing
(previous) data is read again. The data stream is filtered first by
the DAC’s high-pass filter and then by the anti-imaging interpolation filter. These filters have the same characteristics as the
ADC’s anti-aliasing decimation filter and digital high-pass filter.
The output of the interpolation filter is fed to the DAC’s digital
sigma-delta modulator, which converts the 16-bit data to 1-bit
samples at a 1.0 MHz rate. The modulator noise-shapes the signal such that errors inherent to the process are minimized in the
passband of the converter. The bit stream output of the sigmadelta modulator is fed to the AD28msp02’s analog smoothing
filter where it is converted to an analog voltage.
High-Pass Filter
The digital high-pass filter of the AD28msp02’s DAC has the
same characteristics as the high-pass filter of the ADC. The
high-pass filter removes frequency components at the low end of
the spectrum; it attenuates signal energy below the passband of
the converter. The DAC’s high-pass filter can be bypassed by
setting the DABY bit (Bit 2) of the AD28msp02’s control
register.
The high-pass filter is a 4th-order elliptic filter with a passband
cutoff at 150 Hz. Stopband attenuation is 25 dB. This filter has
the following specifications:
Filter type: 4th-order high-pass elliptic IIR
Sample frequency: 8.0 kHz
Passband cutoff: 150.0 Hz
Passband ripple: ±0.2 dB
Stopband cutoff: 100.0 Hz
Stopband ripple: –25.00 dB
(Note that these specifications apply only to this filter, and not to the entire DAC.
The specifications can be used to perform further analysis of the exact characteristics of the filter, for example using a digital filter design software package.)
Figure 3 shows the frequency response of the high-pass filter.
Interpolation Filter
The anti-imaging interpolation filter contains two stages. The
first stage is an IIR low-pass filter that interpolates the data rate
from 8 kHz to 40 kHz and removes images produced by the interpolation process. The output of this stage is then interpolated
to 1.0 MHz and fed to the second stage, a sinc
4
digital filter that
attenuates images produced by the 40 kHz to 1.0 MHz interpolation process.
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–3–
AD28msp02
AD28msp02
SDO SERIAL DATA RECEIVE
SDOFS RECEIVE FRAME SYNC
SCLK SERIAL CLOCK
SDI SERIAL DATA TRANSMIT
SDIFS TRANSMIT FRAME SYNC
Host Processor
DATA/CNTRL FLAG
The IIR low-pass filter is a 10th-order elliptic filter with a passband edge at 3.70 kHz and a stopband attenuation of 65 dB at
4 kHz. This filter has the following specifications:
Filter type: l0th-order low-pass elliptic IIR
Sample frequency: 40.0 kHz
Passband cutoff:* 3.70 kHz
Passband ripple: ±0.2 dB
Stopband cutoff: 4.0 kHz
Stopband ripple: –65.00 dB
*The passband cutoff frequency is defined to be the last point in the passband
that meets the passband ripple specification.
(Note that these specifications apply only to this filter, and not to the entire
DAC. The specifications can be used to perform further analysis of the exact
characteristics of the filter, for example using a digital filter design software
package.)
Figure 2 shows the frequency response of the IIR low-pass filter.
Passband ripple is ±0.2 dB for the combined effects of the
DAC’s digital filters (i.e., high-pass filter and IIR low pass of the
interpolation filter) in the 300 Hz–3400 Hz passband.
Analog Smoothing Filter and Programmable Gain Amplifier
The programmable gain amplifier (PGA) can be used to adjust
the output signal level by –15 dB to +6 dB. This gain is selected
by bits 7–9 (OG0, OG1, OG2) of the AD28msp02’s control
register.
The AD28msp02’s analog smoothing filter consists of a 2ndorder Sallen-Key continuous-time filter and a 3rd-order
switched capacitor filter. The Sallen-Key filter has a 3 dB point
at approximately 80 kHz.
Differential Output Amplifier
The AD28msp02’s analog output (VOUTP, VOUTN) is produced by a differential output amplifier. The differential amplifier can drive loads of 2 kΩ or greater and has a maximum
differential output voltage swing of ± 3.156 V peak-to-peak
(3.17 dBm0). The output signal is dc-biased to the
AD28msp02’s on-chip voltage reference (V
) and can be
REF
ac-coupled directly to a load or dc-coupled to an external amplifier. Refer to “Analog Output” in the “Design Considerations”
section of this data sheet for more information.
The VOUT
–VOUTN outputs must be used as differential out-
P
puts; do not use either as a single-ended output.
SERIAL PORT
The AD28msp02 communicates with a host processor via the
bidirectional synchronous serial port (SPORT). The SPORT is
used to transmit and receive digital data and control information.
All serial transfers are 16 bits long, MSB first. Data bits are
transferred at the serial clock rate (SCLK). SCLK equals the
master clock frequency divided by 5. SCLK = 2.6 MHz for the
master clock frequency MCLK = 13.0 MHz.
Host Processor Interface
The AD28msp02-to-host processor interface is shown in Figure 4.
Figure 4. AD28msp02-to-Host Processor Interface
Table I describes the SPORT signals and how they are used to
communicate with the host processor. The AD28msp02’s chip
select (CS) must be held high to enable SPORT operation. CS
can be used to 3-state the SPORT pins and disable communication with the host processor.
To use the ADSP-2101 or ADSP-2111 as host DSP processor
for the AD28msp02, the following connections can be used (as
shown in Figure 5):
AD28msp02 Pin ADSP-2101/2111 Pin
SCLK – SCLK0
SDO – DR0
SDOFS – RFS0
SDI – DT0
SDIFS – TFS0
DATA/CNTRL – FO (Flag Output)
Signal Signal State When Signal State During
Name Description Generated By RESET Low (CS High) Powerdown (CS High)
SCLK Serial clock AD28msp02 Low Active
SDO Serial data output AD28msp02 Low Active*
SDOFS Serial data output frame sync AD28msp02 Low Low
SDI Serial data input Host Processor — —
SDIFS Serial data input frame sync Host Processor — —
(CS must be held high to enable SPORT operation.)
*Outputs last data value that was valid prior to entering powerdown.
Table I. SPORT Signals
–4–
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Note that the ADSP-2101’s SPORT0 communicates with the
SDO
SDOFS
SCLK
DATA/CNTRL
SDI
SDIFS
AD28msp02
DR0
RFS0
SCLK0
FO
DT0
TFS0
ADSP-2101
AD28msp02’s SPORT while the ADSP-2101’s Flag Output
(FO) is used to signal the AD28msp02’s DATA/
CNTRL input.
SPORT1 on the ADSP-2101 must be configured for flags and
interrupts in this system.
Figure 6 shows an ADSP-2101 assembly language program that
initializes the AD28msp02 and implements digital loopback
through the DSP processor.
{ This ADSP-2101 program initializes the AD28msp02 }
{ and executes a loopback, or talk-through, routine. }
.MODULE/ABS = 0/BOOT = 0 test1;
resetv: JUMP begin; {restart}
RTI; RTI; RTI;
irq2v: RTI; RTI; RTI; RTI; {IRQ2}
st0x: RTI; RTI; RTI; RTI; {SPORT0 Tx}
sr0x: ax0 = rx0; {SPORT0 Rx}
tx0 = ax0;
RTI; RTI;
irq1v: RTI; RTI; RTI; RTI; {irq1}
irq0v: RTI; RTI; RTI; RTI; {irq0}
timerv: RTI; RTI; RTI; RTI;
begin: RESET FLAG
OUT;
AX0 = 0x2A0F; {Configure ADSP-2101 SPORT0 for }
DM (0x3FF6) = AX0; { ext. SCLK, ext. RFS, int. TFS }
AX0 = 0x101F; { Enable ADSP-2101 SPORT0, }
DM (0x3FFF) = AX0; { configure SPORT1 for Flag Out }
IMASK= 0x10;
AX0 = 0x30; { Write control word to take}
TX0 = AX0; { AD28msp02 out of powerdown }
IDLE;
NOP;
IMASK= 0x08;
SET FLAG
OUT;
wait: JUMP wait; { Wait for receive interrupt }
NOP;
.ENDMOD;
AD28msp02
Figure 5. AD28msp02-to-ADSP-2101 Interface
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Figure 6. ADSP-2101 Digital Loopback Routine
–5–
AD28msp02
Serial Data Output
The AD28msp02’s SPORT will begin transmitting data to the
host processor at an 8 kHz rate when the PWDD and PWDA
bits (Bits 4, 5) of the control register are set to 1. In the program shown in Figure 6, the instructions
AX0 = 0x30; { Write control word to take }
TX0 = AX0; { AD28msp02 out of powerdown }
accomplish this by writing 0x30 to the AD28msp02’s control
register. There is a short start-up time (after the end of this control register write) before the AD28msp02 raises SDOFS and
begins transmitting data; see Figure 11.
At the 13 MHz MCLK frequency, data is transmitted at an
8 kHz rate with a single 16-bit word transmitted every 125 µs.
While data is being output, the AD28msp02 asserts SDOFS at
an 8 kHz rate. Each 16-bit word transfer begins one serial clock
cycle after SDOFS is asserted.
Serial Data Input
The host processor must initiate data transfers to the
AD28msp02 by asserting the serial data input frame sync
(SDIFS) high. The 16-bit word transfer begins one serial clock
cycle after SDIFS is asserted. The DATA/CNTRL line must be
driven high when SDIFS is driven high.
The host processor must assert SDIFS shortly after the rising
edge of SCLK and must maintain SDIFS high for one cycle.
Data is then driven from the host processor (to the SDI input)
shortly after the rising edge of the next SCLK and is clocked
into the AD28msp02 on the falling edge of SCLK in that cycle.
Each bit of a 16-bit data word is thus clocked into the
AD28msp02 on the falling edge of SCLK (MSB first).
If SDIFS is asserted high again before the end of the present
data word transfer, it is not recognized until the falling edge of
SCLK in the last (LSB) cycle.
(Note: Exact SPORT timing requirements are defined in the
“Specifications” section of this data sheet.)
CONTROL REGISTER
The AD28msp02’s control register configures the device for
various modes of operation including ADC and DAC gain settings, ADC input mux selection, filter bypass, and powerdown.
The AD28msp02’s host processor can read and write to the
control register through the AD28msp02’s serial port (SPORT)
by driving the DATA/
The control register is cleared (set to 0x0000) when the
AD28msp02 is reset.
Control Register Writes
To write the control register, the host processor must assert
DATA/
CNTRL low when it asserts SDIFS. If the MSB of
the bit stream is also low, the SPORT recognizes the incoming
serial data as a new control word and copies it to the
AD28msp02’s control register. The format for the control word
write is shown in Table II; reserved Bits 10-15 must be set to
zero.
CNTRL pin low.
Table II. Control Word Write Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 OG2 OG1 OG0 0 PWDD PWDA ADBY DABY IMS IPS
0 IPS Analog input preamplifier select: 1 = insert (+20 dB), 0 = bypass (0 dB)
1 IMS Analog input multiplexer select: 1 = AUX input, 0 = NORM input
2 DABY DAC high-pass filter bypass select: 0 = insert, 1 = bypass
3 ADBY ADC high-pass filter bypass select: 0 = insert, 1 = bypass
4 PWDA Powerdown analog: 0 = powerdown, 1 = operating
5 PWDD Powerdown digital: 0 = powerdown, 1 = operating
7–9 OG2-OG0 Analog output gain setting (for D/A output PGA)
10–15 Reserved
Gain OG2 OG1 OG0
+6 dB 0 0 0
+3 dB 0 0 1
0 dB 0 1 0
–3 dB 0 1 1
–6 dB 1 0 0
–9 dB 1 0 1
–12 dB 1 1 0
–15 dB 1 1 1
Gain settings are accurate within ±0.6 dB.
(Control Register is set to 0x0000 at RESET. Reserved Bits
10–15 must be set to 0 for all Control Register writes.)
–6–
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