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AD1981B c
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Analog Devices AD1981B c Datasheet

R
AC ’97 SoundMAX® Codec
AC ’97 2.3 COMPATIBLE FEATURES
S/PDIF output, 20-bit data format, supporting
48 kHz and 44.1 kHz sample rates Integrated stereo headphone amplifier Variable sample rate audio External audio power-down control >90 dB dynamic range Stereo full-duplex codec 20-bit PCM DAC 3 analog line-level stereo inputs for line-in, AUX, and CD Mono line-level phone input Dual MIC input with built-in programmable preamplifier High quality CD input with ground sense Mono output for speakerphone or internal speaker
power management support 48-lead LQFP package, Pb-free available

FUNCTIONAL BLOCK DIAGRAM

V
REFOUT
AD1981B
MIC1
MIC2
PHONE_IN
CD_L
CD_GND
CD_R AUX_L AUX_R
LINE_IN_L LINE_IN_R
MONO_OUT
HP_OUT_L
LINE_OUT_L
LINE_OUT_
HP_OUT_R
MS
CD
DIFF AMP
M
HP
MZ
MZ
HP
M
M
MIC PREAMP
G
G
2CMIC
A
MIX
A
GA
MGAM
GA
MGAM
M
A
A
A
MGAM
OUTPUT SELECTOR
G
GA
MGAM
V
REF
GA
M

ENHANCED FEATURES

Stereo MIC preamplifier support Built-in digital equalizer function for optimized
speaker sound
Full-duplex variable sample rates from 7040 Hz to
48 kHz with 1 Hz resolution Jack sense pins for automatic output switching Software-programmed V
microphone and external power amplifier Split power supplies: 3.3 V digital and 5 V analog Multiple codec configuration options
VOLTAGE
REFERENCE
CODEC CORE
PCM L/R
ADC RATE
M
M
M
M
16-BIT
Σ-∆ ADC
16-BIT
Σ-∆ ADC
16-BIT

Σ-∆ ADC
16-BIT
Σ-∆ ADC
20-BIT
Σ-∆ DAC
20-BIT
Σ-∆ DAC
PCM FRONT
DAC RATE
BYPASS
BYPASS
EQ
G
G
RECORD
SELECTOR
G
G
GA
M
GA
M
G = GAIN A = ATTENUATION M = MUTE Z = HIGH Z
output for biasing
REFOUT
XTL_OUT XTL_IN SPDIF
PLL
ADC AND DAC
SLOT
LOGIC
EQ
EQ CORE STORAGE
AC '97
CONTROL
REGISTERS
ANALOG MIXING CONTROL LOGIC
SPDIF
TX
AC '97 INTERFACE
AD1981B
ID0
ID1
RESET
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
EAPD
Rev. C
JS0 JS1 EAPD
03091-001
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
www.analog.com
AD1981B
TABLE OF CONTENTS
Specifications..................................................................................... 3
PCM-Out Volume Register ....................................................... 18
Test Conditions............................................................................. 3
General Specifications ................................................................. 3
Power-Down States ...................................................................... 5
Timing Parameters....................................................................... 5
Absolute Maximum Ratings............................................................ 9
Environmental Conditions.......................................................... 9
Pin Configuration and Function Descriptions........................... 10
Indexed Control Registers............................................................. 12
Control Register Details ................................................................ 13
Reset Register.............................................................................. 13
Master Volume Register............................................................. 13
Headphone Volume Register .................................................... 14
Mono Volume Register .............................................................. 15
Phone Volume Register.............................................................. 15
MIC Volume Register................................................................. 16
Record Select Control Register................................................. 19
Record Gain Register................................................................. 19
General-Purpose Register ......................................................... 20
Power-Down Control/Status Register ..................................... 21
Extended Audio ID Register ..................................................... 22
Extended Audio Status and Control Register ......................... 22
PCM Front DAC Rate Register................................................. 23
PCM ADC Rate Register ........................................................... 23
SPDIF Control Register ............................................................. 24
EQ Control Register................................................................... 24
EQ Data Register........................................................................ 26
Mixer ADC, Input Gain Register ............................................. 26
Jack Sense/Audio Interrupt/Status Register............................ 27
Serial Configuration Register ................................................... 29
Miscellaneous Control Bit Register ......................................... 29
Line-In Volume Register............................................................ 16
CD Volume Register................................................................... 17
AUX Volume Register ................................................................ 17
REVISION HISTORY
1/05—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Ordering Guide.......................................................... 32
6/03—Rev. A to Rev. B
Changes to TIMING PARAMETERS............................................ 4
Changes to ENVIRONMENTAL CONDITIONS ....................... 7
Changes to ORDERING GUIDE ................................................... 7
Updated OUTLINE DIMENSIONS ............................................ 27
Vendor ID Registers................................................................... 31
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
2/03—Rev. 0 to Rev. A
Changes to FUNCTIONAL BLOCK DIAGRAM.........................1
Changes to SPECIFICATIONS .......................................................2
Changes to TIMING PARAMETERS.............................................4
Change to Figure 6 Caption.............................................................6
................................................................................................................
10/02—Revision 0: Initial Version
Rev. C | Page 2 of 32
AD1981B

SPECIFICATIONS

TEST CONDITIONS

Standard test conditions, unless otherwise noted.
Table 1.
Parameter Test Condition
Temperature 25°C Digital Supply (DVDD) 3.3 V Analog Supply (AVDD) 5.0 V Sample Rate (fS) 48 kHz Input Signal 1008 Hz Analog Output Pass Band 20 Hz to 20 kHz DAC Calibrated
−3 dB Attenuation Relative to Full Scale 0 dB Input 10 kΩ Output Load (LINE_OUT) 32 Ω Output Load (HP_OUT) ADC Calibrated 0 dB Gain Input −3.0 dB Relative to Full Scale

GENERAL SPECIFICATIONS

Table 2.
Parameter Min Typ Max Unit
ANALOG INPUT
Input Voltage (RMS Values Assume Sine Wave Input)
LINE_IN, AUX, CD, PHONE_IN 1 V rms
2.83 V p-p MIC_IN with 20 dB Gain 0.1 V rms
0.283 V p-p MIC_IN with 0 dB Gain 1 V rms
2.83 V p-p Input Impedance Input Capacitance1 5 7.5 pF
MASTER VOLUME
Step Size (0 dB to −46.5 dB): LINE_OUT_L, LINE_OUT_R 1.5 dB Output Attenuation Range1 46.5 dB Step Size (0 dB to −46.5 dB): MONO_OUT 1.5 dB Output Attenuation Range1 46.5 dB Step Size (0 dB to −46.5 dB): HP_OUT_R, HP_OUT_L 1.5 dB Output Attenuation Range Span1 46.5 dB Mute Attenuation of 0 dB Fundamental1 80 dB
PROGRAMMABLE GAIN AMPLIFIER—ADC
Step Size (0 dB to 22.5 dB) 1.5 dB PGA Gain Range 22.5 dB
ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS
Signal-to-Noise Ratio (SNR)
CD to LINE_OUT 90 dB Other to LINE_OUT1 90 dB
1
20 kΩ
Rev. C | Page 3 of 32
AD1981B
Parameter Min Typ Max Unit
Step Size (+12 dB to −34.5 dB) (All Steps Tested):
MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC 1.5 dB
Input Gain/Attenuation Range:
MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC 46.5 dB
DIGITAL DECIMATION AND INTERPOLATION FILTERS1
Pass Band 0 0.4 × f
S
Pass-Band Ripple ±0.09 dB Transition Band 0.4 × f Stop Band 0.6 × f
S
S
0.6 × f ∞
S
Stop-Band Rejection −74 dB Group Delay 16/fS s Group Delay Variation over Pass Band 0 µs
ANALOG-TO-DIGITAL CONVERTERS
Resolution 16 Bits Total Harmonic Distortion (THD) −84 dB Dynamic Range (−60 dB Input THD + N Referenced to Full Scale, A-Weighted) 80 85 dB Signal-to-Intermodulation Distortion1 (CCIF Method) 85 dB ADC Crosstalk1
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) −80 dB
Line_In to Other −100 −80 dB Gain Error2 (Full-Scale Span Relative to Nominal Input Voltage) ±10 % Interchannel Gain Mismatch (Difference of Gain Errors) ± 0.5 dB ADC Offset Error1 ±5 mV
DIGITAL-TO-ANALOG CONVERTERS
Resolution 20 Bits Total Harmonic Distortion (THD) LINE_OUT −85 dB Total Harmonic Distortion (THD) HP_OUT −75 dB Dynamic Range (−60 dB Input THD + N Referenced to Full Scale, A-Weighted) 85 90 dB Signal-to-Intermodulation Distortion1 (CCIF Method) −100 dB Gain Error2 (Output FS Voltage Relative to Nominal Output FS Voltage) ±10 % Interchannel Gain Mismatch (Difference of Gain Errors) ±0.7 dB DAC Crosstalk1 (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure
−80 dB
L_OUT) Total Audible Out-of-Band Energy1 (Measured from 0.6 × fS to 20 kHz) −40 dB
ANALOG OUTPUT
Full-Scale Output Voltage; LINE_OUT and MONO_OUT 1 V rms
2.83 V p-p Output Impedance1 800 Ω External Load Impedance1 10 kΩ Output Capacitance1 15 pF External Load Capacitance1 100 pF Full-Scale Output Voltage; HP_OUT (0 dB Gain) 1 V rms External Load Impedance1 32 Ω V
2.05 2.25 2.45 V
REF
V
(Programmable to 3.70 V Nominal) 2.25 V
REFOUT
V
Current Drive 5 mA
REFOUT
Mute Click (Muted Output Minus Unmuted Midscale DAC Output) ±5 mV
STATIC DIGITAL SPECIFICATIONS
High Level Input Voltage (VIH): Digital Inputs 0.65 × DVDD V Low Level Input Voltage (VIL) 0.35 × DV
Hz
Hz Hz
V
DD
Rev. C | Page 4 of 32
AD1981B
Parameter Min Typ Max Unit
High Level Output Voltage (VOH), IOH = 2 mA 0.9 × DVDD V Low Level Output Voltage (VOL), IOL = 2 mA 0.1 × DV Input Leakage Current −10 +10 µA Output Leakage Current −10 +10 µA
POWER SUPPLY
Power Supply Range—Analog (AVDD) 4.5 5.5 V Power Supply Range—Digital (DVDD) 3.0 3.47 V Power Dissipation—5 V/3.3 V 400 mW Analog Supply Current—5 V (AVDD) 50 mA Digital Supply Current—3.3 V (DVDD) 46 mA Power Supply Rejection (100 mV p-p Signal @ 1 kHz)1
40 dB
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)
CLOCK SPECIFICATIONS1
Input Clock Frequency 24.576 MHz Recommended Clock Duty Cycle 40 50 60 %
1
Guaranteed but not tested.
2
Measurements reflect main ADC.
V
DD

POWER-DOWN STATES

Values presented with V
Table 3.
Parameter Set Bits DVDD Typ AVDD Typ Unit
Fully Active No Bits Value 42 51 mA
ADC PR0 36 45 mA
DAC PR1 29 35 mA
ADC + DAC PR1, PR0 12 28 mA
Mixer PR2 42 24 mA
ADC + Mixer PR2, PR0 36 18 mA
DAC + Mixer PR2, PR1 29 9 mA
ADC + DAC + Mixer PR2, PR1, PR0 12 1.5 mA
Standby PR5, PR4, PR3, PR2, PR1, PR0 0 0 mA
Headphone Standby PR6 42 44 mA
REFOUT
not loaded.

TIMING PARAMETERS

Guaranteed over operating temperature range.
Table 4.
Parameter Symbol Min Typ Max Unit
t
RESET Active Low Pulse Width
RESET Inactive to BIT_CLK Start-Up Delay
SYNC Active High Pulse Width t
SYNC Low Pulse Width t
SYNC Inactive to BIT_CLK Start-Up Delay t
BIT_CLK Frequency 12.288 MHz
BIT_CLK Frequency Accuracy ±1 ppm
BIT_CLK Period t
BIT_CLK Output Jitter
1, , 2 3
BIT_CLK High Pulse Width t
1.0 ms
RST_LOW
t
162.8 ns
RST2CLK
1.3 ms
SYNC_HIGH
19.5 µs
SYNC_LOW
162.8 ns
SYNC2CLK
CLK_PERIOD
81.4 ns
750 2000 ps
32.56 42 48.84 ns
CLK_HIGH
Rev. C | Page 5 of 32
AD1981B
Parameter Symbol Min Typ Max Unit
BIT_CLK Low Pulse Width t SYNC Frequency 48.0 kHz SYNC Period t Setup to Falling Edge of BIT_CLK t Hold from Falling Edge of BIT_CLK t BIT_CLK Rise Time t BIT_CLK Fall Time t SYNC Rise Time t SYNC Fall Time t SDATA_IN Rise Time t SDATA_IN Fall Time t SDATA_OUT Rise Time t SDATA_OUT Fall Time t End of Slot 2 to BIT_CLK, SDATA_IN Low t Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) Rising Edge of RESET to High Z Delay Propagation Delay 15 ns RESET Rise Time Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid 15 ns
1
Guaranteed but not tested.
2
Output jitter is directly dependent on crystal input jitter.
3
Maximum jitter specification for noncrystal operation only. Crystal operation maximum is much lower.
32.56 38 ns
CLK_LOW
SYNC_PERIOD
SETUP
HOLD
RISECLK
FALLCLK
RISESYNC
FALLSYNC
RISEDIN
FALLDIN
RISEDOUT
FALLDOUT
S2_PDOWN
t
SETUP2RST
t
OFF
20.8 ms
5 2.5 ns
5 ns
2 4 6 ns
2 4 6 ns
2 4 6 ns
2 4 6 ns
2 4 6 ns
2 4 6 ns
2 4 6 ns
2 4 6 ns
0 1.0 ms
15 ns
25 ns
50 ns
t
t
TRI2ACTV
t
TRI2ACTV
RST2CLK
03091-002
RESET
BIT_CLK
SDATA_IN
t
RST_LOW
Figure 2. Cold Reset Timing (Codec is Supplying the BIT_CLK Signal)
SYNC
BIT_CLK
t
SYNC_HIGH
Figure 3. Warm Reset Timing
t
SYNC2CLK
03091-003
Rev. C | Page 6 of 32
AD1981B
t
CLK_LOW
BIT_CLK
t
CLK_HIGH
t
CLK_PERIOD
t
SYNC_LOW
SYNC
t
SYNC_HIGH
t
SYNC_PERIOD
03091-004
Figure 4. Clock Timing
BIT_CLK
t
FALLCLK
t
FALLSYNC
t
FALLDIN
SYNC
SDATA_IN
t
RISECLK
t
RISESYNC
t
RISEDIN
SDATA_OUT
t
RISEDOUT
t
FALLDOUT
03091-005
Figure 5. Signal Rise and Fall Times
SLOT 1 SLOT 2
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
WRITE TO
BIT_CLK NOT TO SCALE
0x20
DATA
PR4
t
S2_PDOWN
03091-006
Figure 6. AC-Link Low Power Mode Timing
Rev. C | Page 7 of 32
AD1981B
S
T
t
CO
t
SETUP
BIT_CLK
DATA_OU
SDATA_IN
SYNC
V
IH
V
OH
V
OL
t
HOLD
V
IL
03091-007
Figure 7. AC-Link Low Power Mode Timing, SYNC and BIT_CLK Chopped
RESET
SDATA_OUT
SDATA_IN, BIT_CLK,
EAPD, SPDIF_OUT
AND DIGITAL I/O
t
OFF
t
SETUP2RST
HIGH Z
03091-008
Figure 8. ATE Test Mode
Rev. C | Page 8 of 32
AD1981B

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
Power Supplies
Digital (DVDD) Analog (AVDD)
Input Current (Except Supply Pins) ±10 mA
Signals Pins
Digital Input Voltage
Analog Input Voltage
Ambient Temperature Range
(Operating)
−0.3 V to +3.6 V
−0.3 V to +6.0 V
−0.3 V to DV
−0.3 V to AV
0°C to 70°C
−40°C to 85°C, DV
DD
DD
DD
, 3.3 V ± 5%
+ 0.3 V
+ 0.3 V
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ENVIRONMENTAL CONDITIONS
All measurements per EIA-JESD51 with 2S2P test board per EIA-JESD51-7.
Ambient Temperature Rating (LQFP Package)
= Case Temperature in °C
T
CASE
PD = Power Dissipation in W
Thermal Resistance (Junction to Ambient)
θ
JA
Thermal Resistance (Junction to Case)
θ
JC
Table 6. Thermal Resistance
Package θJA θJC
LQFP 50.1°C/W 17.8°C/W
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada-
tion or loss of functionality.
Rev. C | Page 9 of 32
AD1981B

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DVDD1
XTL_IN
XTL_OUT
DV
SS
SDATA_OUT
BIT_CLK
DV
SS
SDATA_IN
DV
DD
SYNC
RESET
NC
NC = NO CONNECT
3
3
SS
DD
NC
SPDIF
EAPD
ID1
48 47 46 45 44 43 42 41 40 39 38 37
1 2 3 4
1
5 6 7
2
8 9
2
10 11 12
13 14 15 16 17 18 19 20 21 22 23 24
AUX_L
AUX_R
PHONE_IN
ID0
AV
AD1981B
TOP VIEW
(Not to Scale)
JS1
JS0
AV
CD_L
CD_GND_REF
HP_OUT_R
CD_R
2
AV
MIC1
2
SS
DD
MONO_OUT
HP_OUT_L
AV
36
LINE_OUT_R
35
LINE_OUT_L
34
4
AV
DD
33
4
AV
SS
32
AFILT4
31
AFILT3
30
AFILT2
29
AFILT1
28
V
REFOUT
27
V
REF
26
AVSS1
25
1
AV
DD
MIC2
LINE_IN_L
LINE_IN_R
03091-009
Figure 9. 48-Lead LQFP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic I/O Description
DIGITAL I/O 2 XTL_IN I Crystal Input (24.576 MHz) or External Clock Input. 3 XTL_OUT O Crystal Output. 5 SDATA_OUT I AC-Link Serial Data Output, AD1981B Data Input Stream. 6 BIT_CLK O/I
AC-Link Bit Clock Output (12.288 MHz) or Bit Clock Input, if Secondary Mode
Selected. 8 SDATA_IN O AC-Link Serial Data Input, AD1981B Data Output Stream. 10 SYNC I AC-Link Frame Sync. 11
RESET
I AC-Link Reset, AD1981B Master Hardware Reset. 48 SPDIF O S/PDIF Output. CHIP SELECTS1 45
ID0
I
Chip Select Input 0 (Active Low). This pin can also be used as the chain input from a secondary codec.
46
ID1
I Chip Select Input 1 (Active Low).
JACK SENSE AND EAPD 17 JS0 I Jack Sense 0 Input. 16 JS1 I Jack Sense 1 Input. 47 EAPD O External Amp Power-Down Control. ANALOG I/O 13 PHONE_IN I Phone Input. Mono input from telephony subsystem speaker phone or handset. 14 AUX_L I Auxiliary Input Left Channel. 15 AUX_R I Auxiliary Input Right Channel. 18 CD_L I CD Audio Left Channel. 19 CD_GND_REF I CD Audio Analog Ground Reference for Differential CD Input. 20 CD_ R I CD Audio Right Channel. 21 MIC1 I
Microphone 1 Input (Mono) or Left Channel when 2-Channel Mode Selected (Stereo MIC).
Rev. C | Page 10 of 32
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