ANALOG DEVICES AD1936 Service Manual

4 ADC/8 DAC with PLL,

www.BDTIC.com/ADI

Preliminary Technical Data

Features

PLL generated (32-192kHz) or direct master clock
Low EMI design
109 dB DAC/ 107dB ADC Dynamic Range and SNR

-94dB THD+N
Single 3.3V Supply
Tolerance for 5V logic inputs
Supports 24-bits and 8 kHz - 192 kHz sample rates
Differential ADC input
Single-ended or Differential DAC output versions
Log volume control with "auto-ramp" function
Hardware and software controllable clickless mute
Software and hardware power-down
Right justified, left justified, I
Master and slave modes up to 16 channel in/out
48-lead LQFP or 64-lead LQFP plastic package

2

S and TDM Modes

192 kHz, 24 Bit CODEC

AD1935/AD1936/AD1937/AD1938/AD1939

Applications

Automotive audio systems
Home theater systems
Set-top boxes
Digital audio effects processors

GENERAL DESCRIPTION

The

AD193X family are
provide 4 ADCs with differential input and 8 DACs with either
single-ended or differential output using ADI’s patented multibit
sigma-delta architecture. An SPI® or I2C® port is included, allowing
a microcontroller to adjust volume and many other parameters.
The

AD193X family
The

AD193X

is available in a 48-lead (SE output) or 64-lead

(differential output) LQFP package.

The AD193X is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures. By
using the on-board PLL to derive master clock from L-R clock, the
AD193X eliminates the need for a separate high frequency master
clock. It can also be used with a suppressed bit clock. The D-A and
A-D converters are designed using the latest ADI continuous time
architectures to further minimize EMI. By using 3.3V supplies,
power consumption is minimized, further reducing emissions.

high performance, single-chip codecs that

operates from 3.3V digital and analog supplies.

Functional Block Diagram

AD193X

AD193X

ADC

ADC

ADC

Analog

Analog

Audio

Audio
Inputs

Inputs

Rev. PrI

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

ADC

ADC

ADC

ADC

ADC

Precision

Precision

Voltage

Voltage

Reference

Reference

Digital

Digital

Filter

Filter

Timing Management

Timing Management

Digital Audio

Digital Audio
Input/Output

Input/Output

Serial Data Port

Serial Data Port

CLOCKS

CLOCKS

&

&

Control

Control

(Clock & PLL)

(Clock & PLL)

Control Port

Control Port

Control Port

2

2

2

SPI / I

SPI / I

SPI / I

C

C

C

Control Data

Control Data
Input/Output

Input/Output

Figure 1

DAC

DAC

DAC

DAC

DAC

SDATAI NSDATAOUT

SDATAI NSDATAOUT

Digital

Digital

Filter

Filter

&

&

Volume

Volume
Control

Control

DAC

DAC

DAC

DAC

DAC

DAC

DAC

DAC

DAC

DAC

DAC

Analog

Analog

Audio

Audio

Outputs

Outputs

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD1935/AD1936/AD1937/AD1938/AD1939

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Preliminary Technical Data

AD193X—SPECIFICATIONS

Test Conditions, Unless Otherwise Noted.

Performance of all channels is identical (exclusive of the Inter-channel Gain Mismatch and Inter-channel Phase Deviation specifications).

Parameter Rating

Supply Voltages (AVDD, DVDD) 3.3 V
Case Temperature 25°C
Master Clock 12.288 MHz (48 kHz fS, 256 × fS Mode)
Input Signal 1.000 kHz, 0 dBFS (Full Scale), -1 dBVrms (0.9Vrms)
Input Sample Rate 48 kHz
Measurement Bandwidth 20 Hz to 20 kHz
Word Width 24 Bits
Load Capacitance (Digital Output) 50 pF
Load Current (Digital Output)

Input Voltage HI 2.0 V
Input Voltage LO 0.8 V

Analog Performance

Parameter Min Typ Max Unit

ADC Resolution (all ADCs) 24 Bits
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)1

No Filter (RMS) 102 dB
With A-Weighted Filter (RMS) 105 dB

With A-Weighted Filter (Avg) 107 dB
Total Harmonic Distortion + Noise (–1 dBFS)1 –92 dB
Full-Scale Input Voltage (Differential) 1.9 V rms
Gain Error –5.0 +5.0 %

ANALOG-TO-DIGITAL CONVERTERS

DIGITAL-TO-ANALOG CONVERTERS

1

Total harmonic distortion + noise and dynamic range typical specifications are for two channels active, max/min are all channels active.

Interchannel Gain Mismatch –0.1 +0.1 dB
Offset Error –10 0 +10 mV
Gain Drift 100 ppm/°C
Interchannel Isolation –110 dB
CMRR, 100 mV RMS, 1 kHz 70 dB
CMRR, 100 mV RMS, 20 kHz 70 dB
Input Resistance 14
Input Capacitance 10 pF
Input Common-Mode Bias Voltage 1.5 V
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)1

No Filter (RMS), Single-ended version 101 dB

With A-Weighted Filter (RMS), Single-ended version 104 dB

With A-Weighted Filter (Avg), Single-ended version 106 dB

No Filter (RMS), Differential version 104 dB

With A-Weighted Filter (RMS), Differential version 107 dB

With A-Weighted Filter (Avg), Differential version 109 dB
Total Harmonic Distortion + Noise (0 dBFS)1

Single-ended version –92 dB

Differential version –94 dB
Full-Scale Output Voltage (Single-ended version) 0.9 (2.5) V rms (V pp)
Full-Scale Output Voltage (Differential version) 1.8 (5.0) V rms (V pp)
Gain Error -6% TBD +6% %

±1 mA or 1.5kΩ to ½ DVDD supply

Tab le 1

kΩ

Rev. PrI | Page 2 of 30

Preliminary Technical Data

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Parameter Min Typ Max Unit

Interchannel Gain Mismatch -0.5 +0.5 dB
Offset Error, Single-ended version -15 mV
Offset Error, Differential version -10 mV
Gain Drift -30 30 ppm/°C
Interchannel Isolation 100 dB
Interchannel Phase Deviation 0 Degrees
Volume Control Step 0.375 dB
Volume Control Range 95 dB
De-emphasis Gain Error ±0.6 dB
Output Resistance at Each Pin 100
Internal Reference Voltage, FILTR 1.50 V

REFERENCE

External Reference Voltage, FILTR 0.90 1.50 1.80 V
Common-Mode Reference Output, CM 1.50 V

AD1935/AD1936/AD1937/AD1938/AD1939

Ω

Tab le 2

Crystal Oscillator

Parameter Min Typ Max Unit

Transconductance 10 mmhos

Tab le 3

Digital I/O

Parameter Min Typ Max Unit

Input Voltage HI (VIH) 2.0 V
Input Voltage LO (VIL) 0.8 V
Input Leakage (IIH @ VIH = 2.4 V) 10 µA
Input Leakage (IIL @ VIL = 0.8 V) 10 µA
High Level Output Voltage (VOH) IOH = 4 mA DVDD – 0.5 V
Low Level Output Voltage (VOL) IOL = 4 mA 0.5 V
Input Capacitance 5 pF

Tab le 4

Power Supplies

Parameter Min Typ Max Unit

Voltage, DVDD 3.0 3.3 3.6 V
Voltage, AVDD 3.0 3.3 3.6 V
Digital Current 56 mA

Supplies

Dissipation

Power Supply Rejection Ratio

Digital Current—Power-Down TBD mA
Digital Current—Reset TBD mA
Analog Current 74 mA
Analog Current—Power-Down TBD mA
Analog Current—Reset TBD mA
Operation—All Supplies 429 mW
Operation—Digital Supply 185 mW
Operation—Analog Supply 244 mW
Power-Down—All Supplies TBD mW
1 kHz 200 mV p-p Signal at Analog Supply Pins TBD dB
20 kHz 200 mV p-p Signal at Analog Supply Pins TBD dB

Tab le 5

Rev. PrI | Page 3 of 30

AD1935/AD1936/AD1937/AD1938/AD1939

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Preliminary Technical Data

Temperature Range

Parameter Min Typ Max Unit

Specifications Guaranteed 25 °C Case

Functionality Guaranteed

Storage –65 +150 °C

–40 +105 °C Ambient
–40 +125 °C Case

Tab le 6

Digital Filters

Mode Parameter Factor Min Typ Max Unit

Pass Band 0.4375 fS 21 kHz

ADC
DECIMATION
FILTER

DAC
INTERPOLATION
FILTER

All Modes,
Typ @ 48 kHz

48 kHz Mode,
Typ @ 48 kHz

96 kHz Mode,
Typ @ 96 kHz

192 kHz Mode,
Typ @ 192 kHz

Pass-Band Ripple ±0.015 dB
Transition Band 0.5 fS 24 kHz
Stop Band 0.5625 fS 27 kHz
Stop-Band Attenuation 79 dB
Group Delay 22.9844/ f
Pass Band 0.4535 fS 22 kHz
Pass-Band Ripple ±0.01 dB
Transition Band 0.5 fS 24 kHz
Stop Band 0.5465 fS 26 kHz
Stop-Band Attenuation 70 dB
Group Delay 25/ f
Pass Band 0.3646 fS 35 kHz
Pass-Band Ripple ±0.05 dB
Transition Band 0.5 fS 48 kHz
Stop Band 0.6354 fS 61 kHz
Stop-Band Attenuation 70 dB
Group Delay 11/ f
Pass Band 0.3646 fS 70 kHz
Pass-Band Ripple ±0.1 dB
Transition Band 0.5 fS 96 kHz
Stop Band 0.6354 fS 122 kHz
Stop-Band Attenuation 70 dB
Group Delay 8/ f

Tab le 7

479 µs

S

521 µs

S

115 µs

S

42 µs

S

Timing Specifications

Parameter Comments Min Max Unit

tMH MCLK High PLL Mode 15 ns
tML MCLK Low PLL Mode 15 ns
t

MCLK Period PLL Mode, 256 fS reference 73 146 ns

MCLK

f

MCLK Frequency PLL Mode, 256 fS reference 6.9 13.8 MHz

MCLK

MASTER CLOCK AND RESET

SPI PORT

tMH MCLK High Direct 512 fS Mode 15 ns
tML MCLK Low Direct 512 fS Mode 15 ns
t

MCLK Period Direct 512 fS Mode 36 ns

MCLK

f

MCLK Frequency Direct 512 fS Mode 27.6 MHz

MCLK

t

PDR

t

PDRR

t

CCLK High TBD ns

CCH

t

CCLK Low TBD ns

CCL

t

CCLK Period 50 ns

CCP

PD/RST

PD/RST

Low

Recovery

Rev. PrI | Page 4 of 30

TBD ns

Reset to Active Output TBD t

MCLK

Preliminary Technical Data

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AD1935/AD1936/AD1937/AD1938/AD1939

Parameter Comments Min Max Unit

f

CCLK Frequency 20 MHz

CCLK

t

CDATA Setup To CCLK Rising TBD ns

CDS

t

CDATA Hold From CCLK Rising TBD ns

CDH

t

CLS

t

CLH

t

CLH

t

COUT Enable From CCLK Falling TBD ns

COE

t

COUT Delay From CCLK Falling TBD ns

COD

t

COUT Hold From CCLK Falling TBD ns

COH

t

COUT Three-State From CCLK Falling TBD ns

COTS

f

SCL Clock

SCL

t

SCL High 0.6 µS

SCLH

t

SCL Low 1.3 µS

SCLL

t

Setup Time Relevant for Repeated Start

SCS

CLATCH

Setup

CLATCH

Hold

CLATCH

High

Frequency

To CCLK Rising TBD ns

From CCLK Falling TBD ns

TBD ns

400 kHz

0.6 µS

Condition

I2C PORT

DAC SERIAL PORT

ADC SERIAL PORT

AUXILIARY INTERFACE

Hold Time After this period the 1st clock is

SCH

Start Condition

Stop Condition t

Slave Mode

Master Mode t

Slave Mode

Master Mode t
t

tDS Data Setup Time 100 ns
t

SCL Rise Time 300 ns

SCR

t

SCL Fall Time 300 ns

SCF

t

SDA Rise Time 300 ns

SDR

SDA Fall Time 300 ns

t

SDF

Setup Time 0.6 µS

SCS

t

DBCLK High TBD ns

DBH

t

DBCLK Low TBD ns

DBL

fDB DBCLK Frequency TBD ns
t

DLRCLK Setup To DBCLK Rising TBD ns

DLS

t

DLRCLK Hold From DBCLK Rising TBD ns

DLH

DLRCLK Skew From DBCLK Falling TBD TBD ns

DLS

t

DSDATA Setup To DBCLK Rising TBD ns

DDS

DSDATA Hold From DBCLK Rising TBD ns

t

DDH

t

ABCLK High TBD ns

ABH

t

ABCLK Low TBD ns

ABL

fDB ABCLK Frequency TBD ns
t

ALRCLK Setup To ABCLK Rising TBD ns

ALS

t

ALRCLK Hold From ABCLK Rising TBD ns

ALH

ALRCLK Skew From ABCLK Falling TBD TBD ns

ALS

ASDATA Delay From ABCLK Falling TBD ns

ABDD

t

AAUXDATA Setup To AUXBCLK Rising TBD ns

AXDS

t

AAUXDATA Hold From AUXBCLK Rising TBD ns

AXDH

t

DAUXDATA Delay From AUXBCLK Falling TBD ns

DXDD

t

AUXBCLK High TBD ns

XBH

t

AUXBCLK Low TBD ns

XBL

fXB AUXBCLK

generated

TBD ns

0.6 µS

t

Frequency

t

AUXLRCLK Setup To AUXBCLK Rising TBD ns

DLS

AUXLRCLK Hold From AUXBCLK Rising TBD ns

t

DLH

Tab le 8

Rev. PrI | Page 5 of 30

AD1935/AD1936/AD1937/AD1938/AD1939

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ABSOLUTE MAXIMUM RATINGS

Preliminary Technical Data

Parameter Min Max Unit

Analog (AVDD) –0.3 +3.6 V
Digital (DVDD) –0.3 +3.6 V
Input Current (Except Supply Pins) ±20 mA
Analog Input Voltage (Signal Pins) –0.3 AVDD + 0.3 V
Digital Input Voltage (Signal Pins) –0.3 DVDD + 0.3 V
Case Temperature (Operating) –40 +125 °C

Tab le 9

Stresses above those listed under the Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Package Characteristics

Parameter Min Typ Max Unit

θJA (Thermal Resistance

[Junction to Ambient]), 48-lead LQFP

θJC (Thermal Resistance

[Junction to Case]), 48-lead LQFP

θJA (Thermal Resistance

[Junction to Ambient]), 64-lead LQFP

θJC (Thermal Resistance

[Junction to Case]), 64-lead LQFP

Note: Characteristics are for a 4-layer board

50.1 °C/W

17 °C/W

47 °C/W

11.1 °C/W

Table 10

Rev. PrI | Page 6 of 30

Preliminary Technical Data

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AD1935/AD1936/AD1937/AD1938/AD1939

Figure 2. ADC Passband Filter Response, 48 kHz Figure 3. ADC Stopband Filter Response, 48 kHz

Figure 4. DAC Passband Filter Response, 48 kHz Figure 5. DAC Stopband Filter Response, 48 kHz

Figure 6. DAC Passband Filter Response, 96 kHz Figure 7. DAC Stopband Filter Response, 96 kHz

Rev. PrI | Page 7 of 30

AD1935/AD1936/AD1937/AD1938/AD1939

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Preliminary Technical Data

Figure 8. DAC Passband Filter Response, 192 kHz Figure 9. DAC Stopband Filter Response, 192 kHz

Rev. PrI | Page 8 of 30

Preliminary Technical Data

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FUNCTIONAL OVERVIEW

ADCs

There are four ADC channels in the AD193X configured as two
stereo pairs with differential inputs. The ADCs can operate at a
nominal sample rate of 48, 96 , or 192 kHz. The ADCs include on­board digital anti-aliasing filters with 79 dB stop-band attenuation
and linear phase response, operating at an oversampling ratio of
128 (48 kHz, 96 kHz, and 192 kHz modes). Digital outputs are
supplied through two serial data output pins (one for each stereo
pair) and a common frame (ALRCLK) and bit (ABCLK) clock.
Alternatively, one of the TDM modes may be used to access up to
16 channels on a single TDM data line.

The ADCs must be driven from a differential signal source for best
performance. The input pins of the ADCs connect to internal
switched capacitors. To isolate the external driving op amp from the
“glitches” caused by the internal switched capacitors, each input pin
should be isolated by using a series-connected external 100
Ω resistor together with a 1 nF capacitor connected from each
input to ground. This capacitor must be of high quality; for
example, ceramic NPO or polypropylene film.

The differential inputs have a nominal common-mode voltage of

1.5V. The voltage at the common-mode reference pin, CM can be
used to bias external op amps to buffer the input signals (see the
Power Supply and Voltage Reference section). The inputs can also
be AC coupled and do not need an external DC bias to CM.

A digital high-pass filter can be switched in line with the ADCs
under serial control to remove residual dc offsets. It has a 1.4 Hz,
6 dB per octave cutoff at a 48 kHz sample rate. The cutoff
frequency will scale directly with sample frequency.

DACs

AD1935/AD1936/AD1937/AD1938/AD1939

rate or low bandwidth may cause high frequency noise and tones to
fold down into the audio band; care should be exercised in selecting
these components.

The voltage at the common-mode reference pin, CM can be used to
bias the external op amps that buffer the output signals (see the
Power Supply and Voltage Reference section).

Clock Signals

The on-chip Phase Locked Loop (PLL) can be selected to use as its
reference the input sample rate from either of the LRCLK pins or
256, 384, 512, or 768 times the sample rate, referenced to 48kHz
mode, from the MCLKI pin. The default at power-up is 256 × fS
from MCLKI. In 96 kHz mode, the master clock frequency will stay
at the same absolute frequency so the actual multiplication rate will
be divided by 2. In 192 kHz mode, the actual multiplication rate will
be divided by 4. For example, if the AD193X is programmed in 256
× fS mode, the frequency of the master clock input would be 256 ×
48 kHz = 12.288 MHz. If the AD193X is then switched to 96 kHz
operation (by writing to the SPI or I2C port), the frequency of the
master clock should remain at 12.288 MHz, which is now 128 × fS.
In 192kHz mode, this would be 64 × fS.

The internal clock for the ADCs is 256 × f
internal clock for the DACs is 512 × fS (48 kHz mode), 256 × fS (96
kHz mode), or 128 × fS (192 kHz mode). By default, the on-board
PLL is used to generate this internal master clock from an external
clock. A direct 512 × f
can be used for either the ADCs or DACs if selected in PLL and
Clock Control Register 1.

Note that it is not possible to use a direct clock for the ADCs set to
192kHz mode. It is required that the on-chip PLL be used in this
mode.

( referenced to 48 kHz mode) master clock

S

for all clock modes. The

S

The AD193X DAC channels are arranged as four stereo pairs
giving eight analog outputs, either single-ended for minimum
external components or differential for improved noise and
distortion performance. The DACs include on-board digital
reconstruction filters with 70 dB stop-band attenuation and linear
phase response, operating at an oversampling ratio of 4 (48 kHz or
96 kHz modes) or 2 (192 kHz mode). Each channel has its own
independently programmable attenuator, adjustable in 255 0.375 dB
steps. Digital inputs are supplied through four serial data input pins
(one for each stereo pair) and a common frame (DLRCLK) and bit
(DBCLK) clock. Alternatively, one of the TDM modes may be used
to access up to 16 channels on a single TDM data line.

Each output pin has a nominal common-mode dc level of 1.5V and
swings ±1.27 V for a 0 dBFS digital input signal. A single op amp
third order external low-pass filter is recommended to remove high
frequency noise present on the output pins, as well as to provide
differential-to-single-ended conversion in the case of the
differential output part. Note that the use of op amps with low slew

Rev. PrI | Page 9 of 30

The PLL can be powered down in PLL and Clock Control Register

0. To ensure reliable locking when changing PLL modes or if the
reference clock may be unstable at power-on, the PLL should be
powered down and then powered back up when the reference clock
is stable.

The internal MCLK can be disabled in PLL and Clock Control
Register 0 to reduce power dissipation when the AD193X is idle.
The clock should be stable before it is enabled. Unless a stand­alone mode is selected (see Serial Control Port), the clock is
disabled by reset and must be enabled by writing to the SPI or I
port for normal operation.

To maintain the highest performance possible, it is recommended
that the clock jitter of the internal master clock signal be limited to
less than 300 ps rms TIE (time interval error). Even at these levels,
extra noise or tones may appear in the DAC outputs if the jitter
spectrum contains large spectral peaks. If the internal PLL is not
being used, it is highly recommended that an independent crystal

2

C