Datasheet AD1896 Datasheet (Analog Devices)

192 kHz Stereo Asynchronous

FEATURES Automatically Senses Sample Frequencies No Programming Required Attenuates Sample Clock Jitter

3.3 V–5 V Input and 3.3 V Core Supply Voltages Accepts 16-/18-/20-/24-Bit Data Up to 192 kHz Sample Rate Input/Output Sample Ratios from 7.75:1 to 1:8 Bypass Mode Multiple AD1896 TDM Daisy-Chain Mode Multiple AD1896 Matched-Phase Mode 142 dB Signal-to-Noise and Dynamic Range

(A-Weighted, 20 Hz–20 kHz BW) Up to –133 dB THD + N Linear Phase FIR Filter Hardware Controllable Soft Mute Supports 256  f

Mode Clock Flexible 3-Wire Serial Data Port with Left-Justified,

S, Right-Justified (16-,18-, 20-, 24-Bits), and

TDM Serial Port Modes Master/Slave Input and Output Modes 28-Lead SSOP Plastic Package

APPLICATIONS Home Theater Systems, Studio Digital Mixers,

Automotive Audio Systems, DVD, Set-Top Boxes,

Digital Audio Effects Processors, Studio-to-Transmitter

Links, Digital Audio Broadcast Equipment,

DigitalTape Varispeed Applications

PRODUCT OVERVIEW

The AD1896 is a 24-bit, high performance, single-chip, secondgeneration asynchronous sample rate converter. Based on Analog Devices experience with its first asynchronous sample rate converter, the AD1890, the AD1896 offers improved performance and additional features. This improved performance includes a THD + N range of –117 dB to –133 dB depending on the sample rate and input frequency, 142 dB (A-Weighted) dynamic range, 192 kHz sampling frequencies for both input and output sample rates, improved jitter rejection, and 1:8 upsampling and 7.75:1 downsampling ratios. Additional features include more serial formats, a bypass mode, better interfacing to digital signal processors, and a matched-phase mode.

The AD1896 has a 3-wire interface for the serial input and output ports that supports left-justified, I (16-, 18-, 20-, 24-bit) modes. Additionally, the serial output

*Patents pending.

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

, 512  fS, or 768  fS Master

S, and right-justified

Sample Rate Converter

AD1896

FUNCTIONAL BLOCK DIAGRAM

VDD_CORE

AD1896

SERIAL

OUTPUT

(Continued on Page 17)

MUTE_I

SDATA_I

SCLK_I

LRCLK_I

SMODE_IN_0 SMODE_IN_1 SMODE_IN_2

BYPASS

MUTE_O

MCLK_I

MCLK_O

GRPDLYS VDD_IO

SERIAL

INPUT

CLOCK DIVIDER

MSMODE_0

RESET

FIFO

DIGITAL

PLL

MSMODE_2

MSMODE_1

OUT

FIR

FILTER

ROM

port supports TDM mode for daisy-chaining multiple AD1896s to a digital signal processor. The serial output data is dithered down to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data is selected. The AD1896 sample rate converts the data from the serial input port to the sample rate of the serial output port. The sample rate at the serial input port can be asynchronous with respect to the output sample rate of the output serial port. The master clock to the AD1896, MCLK, can be asynchronous to both the serial input and output ports.

MCLK can be generated either off-chip or on-chip by the AD1896 master clock oscillator. Since MCLK can be asynchronous to the input or output serial ports, a crystal can be used to generate MCLK internally to reduce noise and EMI emissions on the board. When MCLK is synchronous to either the output or input serial port, the AD1896 can be configured in a master mode where MCLK is divided down and used to generate the left/right and bit clocks for the serial port that is synchronous to MCLK. The AD1896 supports master modes of 256 ¥ f and 768 ¥ f

Conceptually, the AD1896 interpolates the serial input data by a rate of 2

for both input and output serial ports.

and samples the interpolated data stream by the output sample rate. In practice, a 64-tap FIR filter with 2 polyphases, a FIFO, a digital servo loop that measures the time difference between the input and output samples within 5 ps, and a digital circuit to track the sample rate ratio are used to perform the interpolation and output sampling. Refer to the Theory of Operation section. The digital servo loop and sample rate ratio circuit automatically track the input and output sample rates.

SDATA_O SCLK_O LRCLK_O

TDM_IN

SMODE_O_0 SMODE_O_1

WLNGTH_O_0 WLNGTH_O_1

, 512 ¥ fS,

AD1896–SPECIFICA TIONS

TEST CONDITIONS, UNLESS OTHERWISE NOTED.

Supply Voltages

VDD_CORE 3.3 V

VDD_IO 5.0 V or 3.3 V Ambient Temperature 25°C Input Clock 30.0 MHz Input Signal 1.000 kHz, 0 dBFS Measurement Bandwidth 20 to f Word Width 24 Bits Load Capacitance 50 pF Input Voltage High 2.4 V Input Voltage Low 0.8 V

Specifications subject to change without notice.

DIGITAL PERFORMANCE (VDD_CORE = 3.3 V  5%, VDD_IO = 5.0 V  10%)

Parameter Min Typ Max Unit

Resolution 24 Bits Sample Rate @ MCLK_I = 30 MHz 6 215 kHz Sample Rate (@ Other Master Clocks)

Sample Rate Ratios

Upsampling 1:8 Downsampling (Short GRPDLYS) 7.75:1

Downsampling (Long GRPDLYS) 7.0:1 Dynamic Range (20 Hz to f

/2, 1 kHz, –60 dBFS Input) A-Weighted

S_OUT

Worst-Case (192 kHz:48 kHz) 132 dB

44.1 kHz:48 kHz 142 dB

48 kHz:44.1 kHz 141 dB

48 kHz:96 kHz 142 dB

44.1 kHz:192 kHz 141.5 dB

96 kHz:48 kHz 140 dB

192 kHz:32 kHz 140 dB (20 Hz to f

/2, 1 kHz, –60 dBFS Input) No Filter

S_OUT

Worst-Case (192 kHz:48 kHz) 132 dB

44.1 kHz:48 kHz 139 dB

48 kHz:44.1 kHz 139 dB

48 kHz:96 kHz 139 dB

44.1 kHz:192 kHz 137 dB

96 kHz:48 kHz 137 dB

192 kHz:32 kHz 138 dB Total Harmonic Distortion + Noise (20 Hz to f

/2, 1 kHz, 0 dBFS Input) No Filter

S_OUT

Worst-Case (32 kHz:48 kHz)

44.1 kHz:48 kHz –123 dB

48 kHz:44.1 kHz –124 dB

48 kHz:96 kHz –120 dB

44.1 kHz:192 kHz –123 dB

96 kHz:48 kHz –132 dB

192 kHz:32 kHz –133 dB Interchannel Gain Mismatch 0.0 dB Interchannel Phase Deviation 0.0 Degrees Mute Attenuation (24 Bits Word Width) (A-Weighted) –144 dB

NOTES

Lower sampling rates than given by this formula are possible, but the jitter rejection will decrease.

Refer to the Typical Performance Characteristics section for DNR and THD + N numbers over wide range of input and output sample rates.

For any other sample rate ratio, the minimum THD + N will be better than –117 dB. Please refer to detailed performance plots.

Specifications subject to change without notice.

S_OUT

/2 Hz

MCLK_I/5000 ≤ fS < MCLK_I/138 kHz

–117 dB

–2–

REV. A

AD1896

DIGITAL TIMING (–40C < TA < +105C, VDD_CORE = 3.3 V  5%, VDD_IO = 5.0 V  10%)

Parameter

MCLKI

MCLK

MPWH

MPWL

Input Serial Port Timing

LRIS

SIH

SIL

DIS

DIH

Propagation Delay from MCLK_I Rising Edge to SCLK_I Rising Edge (Serial Input Port MASTER) 12 ns Propagation Delay from MCLK_I Rising Edge to LRCLK_I Rising Edge (Serial Input Port MASTER) 12 ns

Output Serial Port Timing

TDMS

TDMH

DOPD

DOH

LROS

LROH

SOH

SOL

RSTL

Propagation Delay from MCLK_I Rising Edge to SCLK_O Rising Edge (Serial Output Port MASTER) 12 ns Propagation Delay from MCLK_I Rising Edge to LRCLK_O Rising Edge

(Serial Output Port MASTER) 12 ns

NOTES

Refer to Timing Diagrams section.

The maximum possible sample rate is: FS

MCLK

Specifications subject to change without notice.

Min Typ Max Unit

MCLK_I Period 33.3 ns MCLK_I Frequency 30.0 MCLK_I Pulsewidth High 9 ns MCLK_I Pulsewidth Low 12 ns

LRCLK_I Setup to SCLK_I 8 ns SCLK_I Pulsewidth High 8 ns SCLK_I Pulsewidth Low 8 ns SDATA_I Setup to SCLK_I Rising Edge 8 ns SDATA_I Hold from SCLK_I Rising Edge 3 ns

TDM_IN Setup to SCLK_O Falling Edge 3 ns TDM_IN Hold from SCLK_O Falling Edge 3 ns SDATA_O Propagation Delay from SCLK_O, LRCLK_O 20 ns SDATA_O Hold from SCLK_O 3 ns LRCLK_O Setup to SCLK_O (TDM Mode Only) 5 ns LRCLK_O Hold from SCLK_O (TDM Mode Only) 3 ns SCLK_O Pulsewidth High 10 ns SCLK_O Pulsewidth Low 5 ns RESET Pulsewidth Low 200 ns

= f

MCLK

/138.

of up to 34 MHz is possible under the following conditions: 0∞C < TA < 70∞C, 45/55 or better MCLK_I duty cycle.

MAX

2, 3

MHz

REV. A

–3–

AD1896

TIMING DIAGRAMS

LRCLK_I

DOH

SIH

SOH

SIL

SOL

SCLK

SDATA I

LRCLK

SCLK

SDATA

LRCLK

SCLK

TDM

LRIS

DIS

DIH

DOPD

LROS

TDMS

LROH

TDMH

Figure 1. Input and Output Serial Port Timing (SCLK I/O, LRCLK I/O, SDATA I/O, TDM_IN)

MCLK I

RESET

RSTL

Figure 2.

MPWH

RESET

MPWL

Timing

Figure 3. MCLK_I Timing

–4–

REV. A

AD1896

DIGITAL FILTERS (VDD_CORE = 3.3 V  5%, VDD_IO = 5.0 V  10%)

Parameter Min Typ Max Unit

Pass-Band 0.4535 f

S_OUT

Pass-Band Ripple ± 0.016 dB Transition Band 0.4535 f Stop-Band 0.5465 f

S_OUT

0.5465 f

S_OUT

Stop-Band Attenuation –125 dB Group Delay Refer to the Group Delay Equations section.

Specifications subject to change without notice.

DIGITAL I/O CHARACTERISTICS (VDD_CORE = 3.3 V  5%, VDD_IO = 5.0 V  10%)

Parameter Min Typ Max Unit

Input Voltage High (V Input Voltage Low (V Input Leakage (I Input Leakage (I Input Leakage (I Input Leakage (I

) 2.4

) 0.8 V

@ VIH = 5 V)

@ VIL = 0 V)

@ VIH = 5 V)

@ VIL = 0 V)

+2 mA –2 mA +150 mA –150 mA

Input Capacitance 5 10 pF Output Voltage High (V Output Voltage Low (V Output Source Current High (I

@ IOH = –4 mA) VDD_CORE – 0.5 VDD_CORE – 0.4 V

@ IOL = +4 mA) 0.2 0.5 V

)–4mA

Output Sink Current Low (IOL)+4mA

NOTES

All input pins except GRPDLYS.

GRPDLYS pin only.

Specifications subject to change without notice.

Hz Hz

POWER SUPPLIES

Parameter Min Typ Max Unit

Supply Voltage

VDD_CORE 3.135 3.3 3.465 V VDD_IO* VDD_CORE 3.3/5.0 5.5 V

Active Supply Current

I_CORE_ACTIVE

48 kHz:48 kHz 20 mA 96 kHz:96 kHz 26 mA 192 kHz:192 kHz 43 mA

I_IO_ACTIVE 2 mA

Power-Down Supply Current: (All Clocks Stopped)

I_CORE_PWRDN 0.5 mA I_IO_PWRDN 10 mA

*For 3.3 V tolerant inputs, VDD_IO supply should be set to 3.3 V; however, VDD_CORE supply voltage should not exceed VDD_IO.

Specifications subject to change without notice.

REV. A

–5–

AD1896

POWER SUPPLIES (VDD_CORE = 3.3 V  5%, VDD_IO = 5.0 V  10%)

Parameter Min Typ Max Unit

Total Active Power Dissipation

48 kHz:48 kHz 65 mW 96 kHz:96 kHz 85 mW 192 kHz:192 kHz 132 mW

Total Power-Down Dissipation: (RESET LO) 2 mW

Specifications subject to change without notice.

TEMPERATURE RANGE

Parameter Min Typ Max Unit

Specifications Guaranteed 25 ∞C Functionality Guaranteed –40 +105 ∞C Storage –55 +150 ∞C Thermal Resistance, qJA (Junction to Ambient) 109 ∞C/W

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

Parameter Min Max Unit

Power Supplies

VDD_CORE –0.3 +3.6 V VDD_IO –0.3 +6.0 V

Digital Inputs

Input Current ± 10 mA Input Voltage DGND – 0.3 VDD_IO + 0.3 V

Ambient Temperature (Operating) –40 +105 ∞C

*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD1896AYRS –40∞C to +105∞C 28-Lead SSOP RS-28 AD1896AYRSRL –40∞C to +105∞C 28-Lead SSOP RS-28 on 13" Reel

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1896 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–6–

REV. A

PIN CONFIGURATION

AD1896

SCLK_I

VDD_IO

DGND

RESET

AD1896

TOP VIEW

(NOT TO SCALE

MMODE_2

MMODE_1

MMODE_0

SCLK_O

LRCLK_O

)

SDATA_O

VDD_CORE

DGND

TDM_IN

SMODE_OUT_0

SMODE_OUT_1

WLNGTH_OUT_0

WLNGTH_OUT_1

MUTE_OUT

GRPDLYS

MCLK_IN

MCLK_OUT

SDATA_I

LRCLK_I

BYPASS

SMODE_IN_0

SMODE_IN_1

SMODE_IN_2

MUTE_IN

PIN FUNCTION DESCRIPTIONS

Pin No. IN/OUT Mnemonic Description

1IN GRPDLYS Group Delay High = Short, Low = Long 2IN MCLK_IN Master Clock or Crystal Input 3 OUT MCLK_OUT Master Clock Output or Crystal Output 4IN SDATA_I Input Serial Data (at Input Sample Rate) 5 IN/OUT SCLK_I Master/Slave Input Serial Bit Clock 6 IN/OUT LRCLK_I Master/Slave Input Left/Right Clock 7IN VDD_IO 3.3 V/5 V Input/Output Digital Supply Pin 8IN DGND Digital Ground Pin 9IN BYPASS ASRC Bypass Mode, Active High 10 IN SMODE_IN_0 Input Port Serial Interface Mode Select Pin 0 11 IN SMODE_IN_1 Input Port Serial Interface Mode Select Pin 1 12 IN SMODE_IN_2 Input Port Serial Interface Mode Select Pin 2 13 IN RESET Reset Pin, Active Low 14 IN MUTE_IN Mute Input Pin—Active High Normally Connected to MUTE_OUT 15 OUT MUTE_OUT Output Mute Control, Active High 16 IN WLNGTH_OUT_1 Hardware Selectable Output Wordlength—Select Pin 1 17 IN WLNGTH_OUT_0 Hardware Selectable Output Wordlength—Select Pin 0 18 IN SMODE_OUT_1 Output Port Serial Interface Mode Select Pin 1 19 IN SMODE_OUT_0 Output Port Serial Interface Mode Select Pin 0 20 IN TDM_IN Serial Data Input* (Only for Daisy-Chain Mode). Ground when not used. 21 IN DGND Digital Ground Pin 22 IN VDD_CORE 3.3 V Digital Supply Pin 23 OUT SDATA_O Output Serial Data (at Output Sample Rate) 24 IN/OUT LRCLK_O Master/Slave Output Left/Right Clock 25 IN/OUT SCLK_O Master/Slave Output Serial Bit Clock 26 IN MMODE_0 Master/Slave Clock Ratio Mode Select Pin 0 27 IN MMODE_1 Master/Slave Clock Ratio Mode Select Pin 1 28 IN MMODE_2 Master/Slave Clock Ratio Mode Select Pin 2

*Also used to input matched-phase mode data.

REV. A

–7–

AD1896

–Typical Performance Characteristics

–20

–40

–60

–80

–100

dBFS

–120

–140

–160

–180

–200

2.5 22.55.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY – kHz

TPC 1. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:48 kHz (Asynchronous)

–20

–40

–60

–80

–100

dBFS

–120

–140

–160

–180

–200

5.0

2.5 22.5

7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY – kHz

TPC 2. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone,

44.1 kHz:48 kHz (Asynchronous)

–20

–40

–60

–80

–100

dBFS

–120

–140

–160

–180

–200

10 9020 30 40 50 60 70 80

FREQUENCY – kHz

TPC 4. Wideband FFT Plot (16k Points) 44.1 kHz:192 kHz, 0 dBFS 1 kHz Tone

–20

–40

–60

–80

–100

dBFS

–120

–140

–160

–180

–200

2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY – kHz

TPC 5. Wideband FFT Plot (16k Points) 48 kHz:44.1 kHz, 0 dBFS 1 kHz Tone

–20

–40

–60

–80

–100

dBFS

–120

–140

–160

–180

–200

54510 15 20 25 30 35 40

FREQUENCY – kHz

TPC 3. Wideband FFT Plot (16k Points) 48 kHz:96 kHz, 0 dBFS 1 kHz Tone

–20

–40

–60

–80

–100

dBFS

–120

–140

–160

–180

–200

2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0

FREQUENCY – kHz

TPC 6. Wideband FFT Plot (16k Points) 96 kHz:48 kHz, 0 dBFS 1 kHz Tone

–8–

22.5

REV. A

AD1896

–200

–50

–190

–180

–170

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

10 9020 30 40 50 60 70 80

FREQUENCY – kHz

dBFS

–200

–50

–190

–180

–170

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

2.5 7.5 12.5 17.5

FREQUENCY – kHz

dBFS

5.0 10.0 15.0 20.0

–20

–40

–60

–80

–100

dBFS

–120

–140

–160

–180

–200

2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY – kHz

22.5

TPC 7. Wideband FFT Plot (16k Points) 192 kHz:48 kHz, 0 dBFS 1 kHz Tone

–50

–60

–70 –80

–90

–100

–110

–120

–130

dBFS

–140

–150

–160

–170

–180

–190

–200

2.5 22.55.0 7.5 10.0 12.5 15.0 17.5 20.0

FREQUENCY – kHz

–50

–60

–70

–80

–90

–100

–110

–120

–130

dBFS

–140

–150

–160

–170

–180

–190

–200

54510 15 20 25 30 35 40

FREQUENCY – kHz

TPC 10. Wideband FFT Plot (16k Points) 48 kHz:96 kHz, –60 dBFS 1 kHz Tone

TPC 8. Wideband FFT Plot (16k Points) –60 dBFS 1 kHz Tone, 48 kHz:48 kHz (Asynchronous)

–50 –60

–70

–80 –90

–100

–110

–120

–130

dBFS

–140

–150

–160

–170

–180

–190

–200

2.5 22.55.0 7.5 10.0 12.5 15.0 17.5 20.0

FREQUENCY – kHz

TPC 9. Wideband FFT Plot (16k Points) 44.1 kHz:48 kHz, –60 dBFS 1 kHz Tone

REV. A

TPC 11. Wideband FFT Plot (16k Points) 44.1 kHz:192 kHz, –60 dBFS 1 kHz Tone

TPC 12. Wideband FFT Plot (16k Points) 48 kHz:44.1 kHz, –60 dBFS 1 kHz Tone

–9–

AD1896

–50

–60

–70

–80

–90

–100

–110 –120

–130

dBFS

–140

–150 –160

–170

–180 –190

–200

2.5 22.57.5 12.5 17.5

5.0 10.0 15.0 20.0 FREQUENCY – kHz

TPC 13. Wideband FFT Plot (16k Points) 96 kHz:48 kHz, –60 dBFS 1 kHz Tone

–50

–60

–70

–80

–90

–100 –110

–120

–130

dBFS

–140

–150

–160

–170

–180 –190

–200

2.5 22.57.5 12.5 17.5

5.0 10.0 15.0 20.0 FREQUENCY – kHz

TPC 14. Wideband FFT Plot (16k Points) 192 kHz:48 kHz, –60 dBFS 1 kHz Tone

–20

–40

–60

–80

–100

dBFS

–120

–140

–160

–180

2.5 20.05.0 7.5 10.0 12.5 15.0 17.5 22.5 FREQUENCY – kHz

TPC 16. IMD, 10 kHz and 11 kHz 0 dBFS Tone 96 kHz:48 kHz

–20

–40

–60

–80

dBFS

–100

–120

–140

–160

–180

2.5 20.05.0 7.5 10.0 12.5 15.0 17.5 FREQUENCY – kHz

TPC 17. IMD, 10 kHz and 11 kHz 0 dBFS Tone 48 kHz:44.1 kHz

–20

–40

–60

–80

dBFS

–100

–120

–140

–160

–180

2.5 20.05.0 7.5 10.0 12.5 15.0 17.5 22.5 FREQUENCY – kHz

TPC 15. IMD, 10 kHz and 11 kHz 0 dBFS Tone 44:1 kHz:48 kHz

–20

–40

–60

–80

–100

dBFS

–120

–140

–160

–180

–200

2.5 20.05.0 7.5 10.0 12.5 15.0 17.5 22.5 FREQUENCY – kHz

TPC 18. Wideband FFT Plot (16k Points) 44.1 kHz:48 kHz, 0 dBFS 20 kHz Tone

–10–

REV. A

AD1896

–119

–121

–123

–125

–127

–129

–131

–133

–135

30 55 80 105 130 155 180

THD+N – dBFS

OUTPUT SAMPLE RATE – kHz

–20

–40

–60

–80

–100

dBFS

–120

–140

–160

–180

–200

10 9020 30 40 50 60 70 80

FREQUENCY – kHz

TPC 19. Wideband FFT Plot (16k Points) 192 kHz:192 kHz, 0 dBFS 80 kHz Tone

–20

–40

–60

–80

–100

dBFS

–120

–140

–160

–180

–200

2.5 22.55.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY – kHz

TPC 20. Wideband FFT Plot (16k Points) 48 kHz:48 kHz, 0 dBFS 20 kHz Tone

–20

–40

–60

–80

–100

dBFS

–120

–140

–160

–180

–200

54510 15 20 25 30 35 40

FREQUENCY – kHz

TPC 22. Wideband FFT Plot (16k Points) 48 kHz:96 kHz, 0 dBFS 20 kHz Tone

–20

–40

–60

–80

–100

dBFS

–120

–140

–160

–180

–200

2.5 20.05.0 7.5 10.0 12.5 15.0 17.5 22.5 FREQUENCY – kHz

TPC 23. Wideband FFT Plot (16k Points) 96 kHz:48 kHz, 0 dBFS 20 kHz Tone

–20

–40

–60

–80

–100

dBFS

–120

–140

–160

–180

–200

2.5 20.05.0 7.5 10.0 12.5 15.0 17.5

TPC 21. Wideband FFT Plot (16k Points) 48 kHz:44:1 kHz, 0 dBFS 20 kHz Tone

REV. A

FREQUENCY – kHz

TPC 24. THD + N vs. Output Sample Rate, f 0 dBFS 1 kHz Tone

–11–

= 192 kHz,

S_IN

AD1896

–119

–121

–123

–125

–127

–129

THD+N – dBFS

–131

–133

–135

30 55 80 105 130 155 180

OUTPUT SAMPLE RATE – kHz

TPC 25. THD + N vs. Output Sample Rate, f 0 dBFS 1 kHz Tone

–119

–121

–123

–125

–127

THD+N – dBFS

–129

–131

–133

–135

30 55 80 105 130 155 180

OUTPUT SAMPLE RATE – kHz

TPC 26. THD + N vs. Output Sample Rate, f 0 dBFS 1 kHz Tone

= 48 kHz,

S_IN

= 44.1 kHz,

S_IN

–119

–121

–123

–125

–127

–129

THD+N – dBFS

–131

–133

–135

30 55 80 105 130 155 180

OUTPUT SAMPLE RATE – kHz

TPC 28. THD + N vs. Output Sample Rate, f 0 dBFS 1 kHz Tone

–130

–131

–132

–133

–134

–135

–136

DNR – dBFS

–137

–138

–139

–140

30 55 80 105 130 155 180

TPC 29. DNR vs. Output Sample Rate, f

OUTPUT SAMPLE RATE – kHz

S_IN

–60 dBFS 1 kHz Tone

= 96 kHz,

S_IN

= 192 kHz,

–119

–121

–123

–125

–127

THD+N – dBFS

–129

–131

–133

–135

30 55 80 105 130 155 180

OUTPUT SAMPLE RATE – kHz

TPC 27. THD + N vs. Output Sample Rate, f 0 dBFS 1 kHz Tone

= 32 kHz,

S_IN

–135

–136

–137

–138

–139

–140

–141

DNR – dBFS

–142

–143

–144

–145

30 55 80 105 130 155 180

OUTPUT SAMPLE RATE – kHz

TPC 30. DNR vs. Output Sample Rate, f –60 dBFS 1 kHz Tone

–12–

= 32 kHz,

S_IN

REV. A

–130

–135

–136

–137

–138

–139

–140

30 55 80 105 130 155 180

OUTPUT SAMPLE RATE – kHz

DNR – dBFS

–131

–132

–133

–134

–135

–136

DNR – dBFS

–137

–138

–139

–140

30 55 80 105 130 155 180

OUTPUT SAMPLE RATE – kHz

TPC 31. DNR vs. Output Sample Rate, f –60 dBFS 1 kHz Tone

= 96 kHz,

S_IN

TPC 34. DNR vs. Output Sample Rate, f –60 dBFS 1 kHz Tone

AD1896

= 44.1 kHz,

S_IN

–20

–40

–60

dBFS

–80

–100

192kHz:32kHz

–120

–140

0 10 20 30 40 50 60

FREQUENCY – kHz

192kHz:96kHz

192kHz:48kHz

TPC 32. Digital Filter Frequency Response

–135

–136

–137

–138

–139

–140

–141

DNR – dBFS

–142

–143

–144

–145

30 55 80 105 130 155 180

OUTPUT SAMPLE RATE – kHz

TPC 33. DNR vs. Output Sample Rate, f –60 dBFS 1 kHz Tone

= 48 kHz,

S_IN

0.00

–0.01

–0.02

–0.03

–0.04

–0.05

dBFS

–0.06

–0.07

–0.08

–0.09

–0.10

0 2 4 6 8 10 12 14 16 18 20 22 24

FREQUENCY – kHz

192kHz:48kHz

TPC 35. Pass-Band Ripple, 192 kHz:48 kHz

–1

–2

LINEARITY ERROR – dBr

–3

–4

–5

–140 0–120 –100 –80 –60 –40 –20

INPUT LEVEL – dBFS

TPC 36. Linearity Error, 48 kHz:48 kHz, 0 dBFS to –140 dBFS Input, 200 Hz Tone

REV. A

–13–

AD1896

–1

–2

LINEARITY ERROR – dBr

–3

–4

–5

–

140

–

120–100–80–60

INPUT LEVEL – dBFS

–

40–20

TPC 37. Linearity Error, 48 kHz:44.1 kHz, 0 dBFS to –140 dBFS Input, 200 Hz Tone

–1

–2

LINEARITY ERROR – dBr

–3

–4

–5

–

140

–

120–100–80–60

INPUT LEVEL – dBFS

–

40–20

–1

–2

LINEARITY ERROR – dBr

–3

–4

–5

–

140

–

120–100–80–60–40–20

INPUT LEVEL – dBFS

TPC 40. Linearity Error, 48 kHz:96 kHz, 0 dBFS to –140 dBFS Input, 200 Hz Tone

–1

–2

LINEARITY ERROR – dBr

–3

–4

–5

–

140

–

120–100–80–60–40–20

INPUT LEVEL – dBFS

TPC 38. Linearity Error, 96 kHz:48 kHz, 0 dBFS to –140 dBFS Input, 200 Hz Tone

–1

–2

LINEARITY ERROR – dBr

–3

–4

–5

–

140

–

120–100–80–60–40

INPUT LEVEL – dBFS

–

TPC 39. Linearity Error, 44.1 kHz:48 kHz, 0 dBFS to –140 dBFS Input, 200 Hz Tone

TPC 41. Linearity Error, 44.1 kHz:192 kHz, 0 dBFS to –140 dBFS Input, 200 Hz Tone

–1

–2

LINEARITY ERROR – dBr

–3

–4

–5

–

140

–

120–100–80–60–40–20

INPUT LEVEL – dBFS

TPC 42. Linearity Error, 192 kHz:44:1 kHz, 0 dBFS to –140 dBFS Input, 200 Hz Tone

–14–

REV. A

AD1896

–180

–110

–175

–170

–165

–160

–155

–150

–145

–140

–135

–130

–125

–120

–115

–140 0–120 –100 –80 –60 –40 –20

INPUT LEVEL – dBFS

dBr

–110

–115

–120

–125

–130

–135

–140

–145

dBr

–150

–155

–160

–165

–170

–175

–180

–140 0–120 –100 –80 –60 –40 –20

INPUT LEVEL – dBFS

TPC 43. THD + N vs. Input Amplitude, 48 kHz:44.1 kHz, 1 kHz Tone

–110

–115

–120

–125

–130

–135

–140

–145

dBr

–150

–155

–160

–165

–170

–175

–180

–140 0–120 –100 –80 –60 –40 –20

INPUT LEVEL – dBFS

TPC 44. THD + N vs. Input Amplitude, 96 kHz:48 kHz, 1 kHz Tone

–110

–115

–120

–125

–130

–135

–140

–145

dBr

–150

–155

–160

–165

–170

–175

–180

–140 0–120 –100 –80 –60 –40 –20

INPUT LEVEL – dBFS

TPC 46. THD + N vs. Input Amplitude, 48 kHz:96 kHz, 1 kHz Tone

–110

–115

–120

–125

–130

–135

–140

–145

dBr

–150

–155

–160

–165

–170

–175

–180

–140 0–120 –100 –80 –60 –40 –20

INPUT LEVEL – dBFS

TPC 47. THD + N vs. Input Amplitude, 44.1 kHz:192 kHz, 1 kHz Tone

–110

–115

–120

–125

–130

–135

–140

–145

dBr

–150

–155

–160

–165

REV. A

–170

–175

–180

–140 0–120 –100 –80 –60 –40 –20

TPC 45. THD + N vs. Input Amplitude, 44.1 kHz:48 kHz, 1 kHz Tone

INPUT LEVEL – dBFS

TPC 48. THD + N vs. Input Amplitude, 192 kHz:48 kHz, 1 kHz Tone

–15–

AD1896

–110

–115

–120

–125

–130

–135

–140

–145

dBr

–150

–155

–160

–165

–170

–175

–180

2.5 20.05.0 7.5 10.0 12.5 15.0 17.5 FREQUENCY – kHz

TPC 49. THD + N vs. Frequency Input, 48 kHz:44.1 kHz, 0 dBFS

–110

–115

–120

–125

–130

–135

–140

–145

dBr

–150

–155

–160

–165

–170

–175

–180

2.5 20.05.0 7.5 10.0 12.5 15.0 17.5 FREQUENCY – kHz

–110

–115

–120

–125

–130

–135

–140

–145

dBr

–150

–155

–160

–165

–170

–175

–180

2.5 20.05.0 7.5 10.0 12.5 15.0 17.5 FREQUENCY – kHz

TPC 51. THD + N vs. Frequency Input, 48 kHz:96 kHz, 0 dBFS

–110

–115

–120

–125

–130

–135

–140

–145

dBr

–150

–155

–160

–165

–170

–175

–180

2.5 20.05.0 7.5 10.0 12.5 15.0 17.5 FREQUENCY – kHz

TPC 50. THD + N vs. Frequency Input, 44.1 kHz:48 kHz, 0 dBFS

TPC 52. THD + N vs. Frequency Input, 96 kHz:48 kHz, 0 dBFS

–16–

REV. A

AD1896

(Continued from Page 1)

The digital servo loop measures the time difference between the input and output sample rates within 5 ps. This is necessary in order to select the correct polyphase filter coefficient. The digital servo loop has excellent jitter rejection for both input and output sample rates as well as the master clock. The jitter rejection begins at less than 1 Hz. This requires a long settling time whenever RESET is deasserted or when the input or output sample rate changes. To reduce the settling time, upon deassertion of RESET or a change in a sample rate, the digital servo loop enters the fast settling mode. When the digital servo loop has adequately settled in the fast mode, it switches into the normal or slow settling mode and continues to settle until the time difference measurement between input and output sample rates is within 5 ps. During fast mode, the MUTE_OUT signal is asserted high. Normally, the MUTE_OUT is connected to the MUTE_IN pin. The MUTE_IN signal is used to softly mute the AD1896 upon assertion and softly unmute the AD1896 when it is deasserted.

The sample rate ratio circuit is used to scale the filter length of the FIR filter for decimation. Hysteresis in measuring the sample rate ratio is used to avoid oscillations in the scaling of the filter length, which would cause distortion on the output.

However, when multiple AD1896s are used with the same serial input port clock and the same serial output port clock, the hysteresis causes different group delays between multiple AD1896s. A phase-matching mode feature was added to the AD1896 to address this problem. In phase-matching mode, one AD1896, the master, transmits its sample rate ratio to the other AD1896s, the slaves, so that the group delay between the multiple AD1896s remains the same.

The group delay of the AD1896 can be adjusted for short or long delay. An address offset is added to the write pointer of the FIFO in the sample rate converter. This offset is set to 16 for short delay and 64 for long delay. In long delay, the group delay is effectively increased by 48 input sample clocks.

The sample rate converter of the AD1896 can be bypassed altogether using the bypass mode. In bypass mode, the AD1896’s serial input data is directly passed to the serial output port without any dithering. This is useful for passing through nonaudio data or when the input and output sample rates are synchronous to one another and the sample rate ratio is exactly 1 to 1.

The AD1896 is a 3.3 V, 5 V input tolerant part and is available in a 28-lead SSOP package. The AD1896 is 5 V input-tolerant only when the VDD_IO supply pin is supplied with 5 V.

REV. A

–17–

AD1896

ASRC FUNCTIONAL OVERVIEW THEORY OF OPERATION

Asynchronous sample rate conversion is converting data from one clock source at some sample rate to another clock source at the same or a different sample rate. The simplest approach to an asynchronous sample rate conversion is the use of a zero-order hold between the two samplers shown in Figure 4. In an asynchronous system, T2 is never equal to T1 nor is the ratio between T2 and T1 rational. As a result, samples at f

will be repeated

S_OUT

or dropped producing an error in the resampling process. The frequency domain shows the wide side lobes that result from this error when the sampling of f

is convolved with the

S_OUT

attenuated images from the sin(x)/x nature of the zero-order hold. The images at f

, dc signal images, of the zero-order

S_IN

hold are infinitely attenuated. Since the ratio of T2 to T1 is an irrational number, the error resulting from the resampling at

can never be eliminated. However, the error can be sig-

S_OUT

nificantly reduced through interpolation of the input data at

. The AD1896 is conceptually interpolated by a factor of 220.

S_IN

= 1/T1

S_IN

ZERO-ORDER

HOLD

ORIGINAL SIGNAL

SAMPLED AT f

S_IN

S_OUT

OUT

= 1/T2

between each f signal with a digital low-pass filter to suppress the images. In the time domain, it can be seen that f sample from the zero-order hold as opposed to the nearest f

sample and convolving this interpolated

S_IN

selects the closest f

S_OUT

S_IN

¥ 2

S_IN

sample in the case of no interpolation. This significantly reduces the resampling error.

IN OUT

S_IN

INTERPOLATE

BY N

TIME DOMAIN OF f

TIME DOMAIN OUTPUT OF THE LOW-PASS FILTER

TIME DOMAIN OF f

TIME DOMAIN OF THE ZERO-ORDER HOLD OUTPUT

LOW-PASS

FILTER

SAMPLES

S_IN

RESAMPLING

S_OUT

ZERO-ORDER

HOLD

S_OUT

SIN(X)/X OF ZERO-ORDER HOLD

SPECTRUM OF ZERO-ORDER HOLD OUTPUT

SPECTRUM OF f

f FREQUENCY RESPONSE OF f HOLD SPECTRUM

S_OUT

Figure 4. Zero-Order Hold Being Used by f Resample Data from f

S_IN

SAMPLING

S_OUT

CONVOLVED WITH ZERO-ORDER

2  f

S_OUT

THE CONCEPTUAL HIGH INTERPOLATION MODEL

Interpolation of the input data by a factor of 220 involves placing

– 1) samples between each f both the time domain and the frequency domain of interpolation by a factor of 2

. Conceptually, interpolation by 220 would

involve the steps of zero-stuffing (2

sample. Figure 5 shows

S_IN

– 1) number of samples

Figure 5. Time Domain of the Interpolation and Resampling

In the frequency domain shown in Figure 6, the interpolation expands the frequency axis of the zero-order hold. The images from the interpolation can be sufficiently attenuated by a good low-pass filter. The images from the zero-order hold are now pushed by a factor of 2 of the zero-order hold, which is f

closer to the infinite attenuation point

¥ 220. The images at the

S_IN

zero-order hold are the determining factor for the fidelity of the output at f

. The worst-case images can be computed from

S_OUT

the zero-order hold frequency response, maximum image =

sin (p ¥ F/f

S_INTERP

)/(p ¥ F/f

worst-case image that would be 2

is f

S_INTERP

S_IN

¥ 220.

The following worst-case images would appear for f

). F is the frequency of the

S_INTERP

¥ f

± f

S_IN

/2 , and

S_IN

192 kHz:

Image at f Image at f

S_INTERP

– 96 kHz = –125.1 dB + 96 kHz = –125.1 dB

–18–

REV. A

AD1896

RIGHT DATA IN

LEFT DATA IN

FIFO

ROM A

ROM B

ROM C

ROM D

HIGH

ORDER

INTERP

DIGITAL

SERVO LOOP

FIR FILTER

SAMPLE RATE

RATIO

S_IN

COUNTER

SAMPLE RATE RATIO

EXTERNAL

RATI O

S_IN

S_OUT

L/R DATA OUT

IN OUT

S_IN

INTERPOLATE

BY N

FREQUENCY DOMAIN OF SAMPLES AT f

FREQUENCY DOMAIN OF THE INTERPOLATION

SIN(X)/X OF ZERO-ORDER HOLD

FREQUENCY DOMAIN OF f

FREQUENCY DOMAIN AFTER RESAMPLING

LOW-PASS

FILTER

RESAMPLING

S_OUT

S_IN

ZERO-ORDER

HOLD

S_IN

 f

S_IN

S_OUT

Figure 6. Frequency Domain of the Interpolation and Resampling

the output samples is less than the Nyquist frequency of the input samples. To move the cutoff frequency of the antialiasing filter, the coefficients are dynamically altered and the length of the convolution is increased by a factor of (f

S_IN/fS_OUT

This technique is supported by the Fourier transform property that if f(t) is F(w), then f(k ¥ t) is F(w/k). Thus, the range of decimation is simply limited by the size of the RAM.

THE SAMPLE RATE CONVERTER ARCHITECTURE

The architecture of the sample rate converter is shown in Figure 7. The sample rate converter’s FIFO block adjusts the left and right input samples and stores them for the FIR filter’s convolution cycle. The f

counter provides the write address

S_IN

to the FIFO block and the ramp input to the digital servo loop. The ROM stores the coefficients for the FIR filter convolution and performs a high order interpolation between the stored coefficients. The sample rate ratio block measures the sample rate for dynamically altering the ROM coefficients and scaling of the FIR filter length as well as the input data. The digital servo loop automatically tracks the f

S_IN

and f

S_OUT

sample rates and provides the RAM and ROM start addresses for the start of the FIR filter convolution.

HARDWARE MODEL

The output rate of the low-pass filter of Figure 5 would be the interpolation

rate, 220 ¥ 192000 kHz = 201.3 GHz. Sampling at a rate of 201.3 GHz is clearly impractical, not to mention the number of taps required to calculate each interpolated sample. However, since interpolation by 2 samples between each f

S_IN

involves zero-stuffing 220– 1

sample, most of the multiplies in the low-pass FIR filter are by zero. A further reduction can be realized by the fact that since only one interpolated sample is taken at the output at the f needs to be performed per f lutions. A 64-tap FIR filter for each f

rate, only one convolution

S_OUT

period instead of 220 convo-

S_OUT

sample is sufficient

S_OUT

to suppress the images caused by the interpolation.

The difficulty with the above approach is that the correct interpolated sample needs to be selected upon the arrival of f Since there are 2 arrival of the f of 1/201.3 GHz = 4.96 ps. Measuring the f

possible convolutions per f

clock must be measured with an accuracy

S_OUT

period, the

S_OUT

period with a

S_OUT

clock of 201.3 GHz frequency is clearly impossible; instead, several coarse measurements of the f

clock period are made

S_OUT

and averaged over time.

Another difficulty with the above approach is the number of coefficients required. Since there are 2 with a 64-tap FIR filter, there needs to be 2 cients for each tap, which requires a total of 2 reduce the amount of coefficients in ROM, the AD1896 stores a small subset of coefficients and performs a high order interpolation between the stored coefficients. So far the above approach works for the case of f the output sample rate, f rate, f of the convolution must be scaled. As the input sample rate rises over the output sample rate, the antialiasing filter’s cutoff frequency has to be lowered because the Nyquist frequency of

REV. A

, the ROM starting address, input data, and the length

S_IN

S_OUT

> f

, is less than the input sample

S_OUT

possible convolutions

polyphase coeffi-

coefficients. To

. However, in the case when

S_IN

–19–

Figure 7. Architecture of the Sample Rate Converter

The FIFO receives the left and right input data and adjusts the amplitude of the data for both the soft muting of the sample rate converter and the scaling of the input data by the sample rate ratio before storing the samples in the RAM. The input data is scaled by the sample rate ratio because as the FIR filter length of the convolution increases, so does the amplitude of the convolution output. To keep the output of the FIR filter from saturating, the input data is scaled down by multiplying it by (f

S_OUT/fS_IN

) when f

S_OUT

< f

. The FIFO also scales the input

S_IN

data for muting and unmuting of the AD1896.

The RAM in the FIFO is 512 words deep for both left and right channels. An offset to the write address provided by the f

S_IN

counter is added to prevent the RAM read pointer from ever overlapping the write address. The offset is selectable by the GRPDLYS, group delay select, signal. A small offset, 16, is added to the write address pointer when GRPDLYS is high, and a large offset, 64, is added to the write address pointer when GRPDLYS is low. Increasing the offset of the write address pointer is useful for applications when small changes in the sample rate ratio between f

S_IN

and f

are expected. The maximum deci-

S_OUT

mation rate can be calculated from the RAM word depth and GRPDLYS as (512 – 16)/64 taps = 7.75 for short group delay and (512 – 64)/64 taps = 7 for long group delay.

AD1896

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

–180

–190

–200

–210

–220

0.01 0.1 1 10 100 1e3 1e4 1e5

SLOW MODE

FA ST MODE

FREQUENCY – Hz

Figure 8. Frequency Response of the Digital Servo Loop. f Frequency Is 30 MHz.

The digital servo loop is essentially a ramp filter that provides the initial pointer to the address in RAM and ROM for the start of the FIR convolution. The RAM pointer is the integer output of the ramp filter while the ROM is the fractional part. The digital servo loop must be able to provide excellent rejection of jitter on the f of the f

S_OUT

and f

S_IN

clock within 4.97 ps. The digital servo loop will

clocks as well as measure the arrival

S_OUT

also divide the fractional part of the ramp output by the ratio of f

S_IN/fS_OUT

for the case when f

S_IN

> f

, to dynamically alter

S_OUT

the ROM coefficients.

The digital servo loop is implemented with a multirate filter. To settle the digital servo loop filter quicker upon start-up or a change in the sample rate, a “fast mode” was added to the filter. When the digital servo loop starts up or the sample rate is changed, the digital servo loop kicks into “fast mode” to adjust and settle on the new sample rate. Upon sensing the digital servo loop settling down to some reasonable value, the digital servo loop will kick into “normal” or “slow mode.” During “fast mode” the MUTE_OUT signal of the sample rate converter is asserted to let the user know that they should mute the sample rate converter to avoid any clicks or pops. The frequency response of the digital servo loop for “fast mode” and “slow mode” are shown in Figure 8.

Is the X-Axis, f

S_IN

The FIR filter is a 64-tap filter in the case of f (f

S_IN/fS_OUT

) ¥ 64 taps for the case when f

= 192 kHz, Master Clock

S_OUT

S_IN

S_OUT

> f

≥ f

S_IN

S_OUT

and is

. The FIR filter performs its convolution by loading in the starting address of the RAM address pointer and the ROM address pointer from the digital servo loop at the start of the f

S_OUT

period. The FIR filter then steps through the RAM by decrementing its address by 1 for each tap, and the ROM pointer increments its address by the (f for f

S_OUT

≥ f

S_IN

S_OUT/fS_IN

) ¥ 220 ratio for f

. Once the ROM address rolls over, the con-

S_IN

> f

S_OUT

or 2

volution is completed. The convolution is performed for both the left and right channels, and the multiply accumulate circuit used for the convolution is shared between the channels.

The f

S_IN/fS_OUT

alter the coefficients in the ROM for the case when f

. The ratio is calculated by comparing the output of an

S_OUT

counter to the output of an f

S_OUT

, the ratio is held at one. If f

S_IN

ratio is updated if it is different by more than two f from the previous f

sample rate ratio circuit is used to dynamically

S_IN

counter. If f

S_OUT

to f

S_IN

> f

S_IN

comparison. This is done to

S_IN

, the sample rate

S_OUT

periods

provide some hysteresis to prevent the filter length from oscillating and causing distortion.

–20–

REV. A

AD1896

However, the hysteresis of the f

S_OUT/fS_IN

ratio circuit can cause phase mismatching between two AD1896s operating with the same input clock and the same output clock. Since the hysteresis requires a difference of more than two f f

S_OUT/fS_IN

ferences in their ratios from 0 to 4 f f

S_OUT/fS_IN

ratio to be updated, two AD1896s may have dif-

S_OUT

ratio adjusts the filter length of the AD1896, which

periods for the

S_OUT

period counts. The

corresponds directly with the group delay. Thus, the magnitude in the phase difference will depend upon the resolution of the f

S_OUT

and f

counters. The greater the resolution of the

S_IN

counters, the smaller the phase difference error will be.

The f

S_IN

and f

counters of the AD1896 have three bits of

S_OUT

extra resolution over the AD1890, which reduces the phase mismatch error by a factor of 8. However, an additional feature was added to the AD1896 to eliminate the phase mismatching completely. One AD1896 can set the f AD1896s by transmitting its f

S_OUT/fS_IN

ratio of other

ratio through the

serial output port.

OPERATING FEATURES RESET and Power-Down

When RESET is asserted low, the AD1896 will turn off the master clock input to the AD1896, MCLK_I, initialize all of its internal registers to their default values, and three-state all of the I/O pins. While RESET is active low, the AD1896 is consuming minimum power. For the lowest possible power consumption while RESET is active low, all of the input pins to the AD1896 should be static.

When RESET is deasserted, the AD1896 begins its initialization routine where all locations in the FIFO are initialized to zero, MUTE_OUT is asserted high, and any I/O pins configured as outputs are enabled. When RESET is deasserted, the master serial port clock pins SCLK_I/O and LRCLK_I/O become active after 1024 MCLK-I cycles. The mute control counter, which controls the soft mute attenuation of the input samples, is initialized to maximum attenuation, –144 dB (see the Mute Control section).

When asserting RESET and deasserting RESET, the RESET should be held low for a minimum of five MCLK_I cycles. During power-up, the RESET should be held low until the power supplies have stabilized. It is recommended that the AD1896 be reset when changing modes.

Power Supply and Voltage Reference

The AD1896 is designed for 3 V operation with 5 V input tolerance on the input pins. VDD_CORE is the 3 V supply that is used to power the core logic of the AD1896 and to drive the output pins. VDD_IO is used to set the input voltage tolerance of the input pins. In order for the input pins to be 5 V input tolerant, VDD_IO must be connected to a 5 V supply. If the input pins do not have to be 5 V input tolerant, then VDD_IO can be connected to VDD_CORE. VDD_IO should never be less than VDD_CORE. VDD_CORE and VDD_IO should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize power supply and ground bounce caused by inductance in the traces. A bulk aluminium electrolytic capacitor of 47 mF should also be provided on the same PC board as the AD1896.

Digital Filter Group Delay

The group delay of the digital filter may be selected by the logic pin GRPDLYS. As mentioned in the Theory of Operation section, this pin is particularly useful in varispeed applications. The GRPDLYS pin has an internal pull-up resistor of approximately 33 kW to VDD_CORE. When GRPDLYS is high, the filter group delay will be short and is given by the equation:

GDS

16 32

=+ >

S_IN S_IN

16 32

ffff

S_IN S_IN

seconds

Ê Á

for f f

S_OUT S_IN

S_IN

seconds

˜ ¯

S_OUT

for f f

S_OUT S_IN

For short filter group delay, the GRPDLYS pin can be left open. When GRPDLYS is low, the group delay of the filter will be long and is given by the equation:

GDL

64 32

=+ >

S_IN S_IN

64 32

ffff

S_IN S_IN

seconds

Ê Á

for f f

S_OUT S_IN

S_IN

seconds

˜ ¯

S_OUT

for f f

S_OUT S_IN

NOTE: For the long group delay mode, the decimation ratio is limited to less than 7:1.

Mute Control

When the MUTE_IN pin is asserted high, the MUTE_IN control will perform a soft mute by linearly decreasing the input data to the AD1896 FIFO to zero, –144 dB attenuation. When MUTE_IN is deasserted low, the MUTE_IN control will linearly decrease the attenuation of the input data to 0 dB. A 12-bit counter, clocked by LRCLK_I, is used to control the mute attenuation. Therefore, the time it will take from the assertion of MUTE_IN to –144 dB full mute attenuation is 4096/LRCLK_I seconds. Likewise, the time it will take to reach 0 dB mute attenuation from the deassertion of MUTE_IN is 4096/LRCLK_I seconds.

Upon RESET, or a change in the sample rate between LRCLK_I and LRCLK_O, the MUTE_OUT pin will be asserted high. The MUTE_OUT pin will remain asserted high until the digital servo loop’s internal fast settling mode has completed. When the digital servo loop has switched to slow settling mode, the MUTE_OUT pin will deassert. While MUTE_OUT is asserted, the MUTE_IN pin should be asserted as well to prevent any major distortion in the audio output samples.

Master Clock

A digital clock connected to the MCLK_I pin or a fundamental or third overtone crystal connected between MCLK_I and MCLK_O can be used to generate the master clock, MCLK_I. The MCLK_I pin can be 5 V input tolerant just like any of the other AD1896 input pins. A fundamental mode crystal can be inserted between MCLK_I and MCLK_O for master clock frequency generation up to 27 MHz. For master clock frequency generation with a crystal beyond 27 MHz, it is recommended that the user use a third overtone crystal and to add an LC filter at the output of MCLK_O to filter out the fundamental, do not notch filter the fundamental. Please refer to your quartz crystal supplier for values for external capacitors and inductor components.

REV. A

–21–

AD1896

Table I. Serial Data Input Port Mode

AD1896

MCLK_I MCLK_O

C1 C2

Figure 9a. Fundamental-Mode Circuit Configuration

AD1896

MCLK_I MCLK_O

C1 C2

1nF

Figure 9b. Third-Overtone Circuit Configuration

There are, of course, maximum and minimum operating frequencies for the AD1896 master clock. The maximum master clock frequency at which the AD1896 is guaranteed to operate is 30 MHz. A frequency of 30 MHz is more than sufficient to sample rate convert sampling frequencies of 192 kHz + 12%. The minimum required frequency for the master clock generation for the AD1896 depends upon the input and output sample rates. The master clock has to be at least 138 times greater than the maximum input or output sample rate.

Serial Data Ports—Data Format

The serial data input port mode is set by the logic levels on the SMODE_IN_0/SMODE_IN_1/SMODE_IN_2 pins. The serial data input port modes available are left justified, I

S, and right

justified (RJ), 16, 18, 20, or 24 bits as defined in Table I.

SMODE_IN_[0:2]

Interface Format

21 0

00 0Left Justified 00 1I

S 01 0Undefined 01 1Undefined 10 0Right Justified, 16 Bits 10 1Right Justified, 18 Bits 11 0Right Justified, 20 Bits 11 1Right Justified, 24 Bits

The serial data output port mode is set by the logic levels on the SMODE_OUT_0/SMODE_OUT_1 and WLNGTH_OUT_0/ WLNGTH_OUT_1 pins. The serial mode can be changed to left justified, I

S, right justified, or TDM as defined in the following table. The output word width can be set by using the WLNGTH_OUT_0/WLNGTH_OUT_1 pins as shown in Table III. When the output word width is less than 24 bits, dither is added to the truncated bits. The right justified serial data out mode assumes 64 SCLK_O cycles per frame, divided evenly for left and right. Please note that 8 bits of each 32-bit subframe are used for transmitting matched-phase mode data. Please refer to Figure 14. The AD1896 also supports 16-bit, 32-clock packed input and output serial data in LJ and I

S format.

Table II. Serial Data Output Port Mode

SMODE_OUT_[0:1]

Interface Format

00Left Justified (LJ) 01I

S 10TDM Mode 11Right Justified (RJ)

Table III. Word Width

WLNGTH_OUT_[0:1]

Word Width

0024 Bits 0120 Bits 1018 Bits 1116 Bits

The following timing diagrams show the serial mode formats.

–22–

REV. A

AD1896

LRCLK

SCLK

MSB

SDATA

LRCLK

SCLK

SDATA

LRCLK

SCLK

SDATA

LRCLK

SCLK

SDATA

MSB

NOTES

LRCLK NORMALLY OPERATES AT ASSOCIATIVE INPUT OR OUTPUT SAMPLE FREQUENCY (fs).

SCLK FREQUENCY IS NORMALLY 64  LRCLK EXCEPT FOR TDM MODE WHICH IS N  64  fs,

WHERE N = NUMBER OF STEREO CHANNELS IN THE TDM CHAIN, IN MASTER MODE N = 4.

PLEASE NOTE THAT 8 BITS OF EACH 32-BIT SUBFRAME ARE USED FOR TRANSMITTING

MATCHED-PHASE MODE DATA. PLEASE REFER TO FIGURE 14.

LEFT CHANNEL

MSB LSB

LSB

MSB

1/f

LSB

LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL

LEFT CHANNEL

LSB

I2S MODE – 16 BITS TO 24 BITS PER CHANNEL

LEFT CHANNEL

MSB

RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL

LSB

TDM MODE – 16 BITS TO 24 BITS PER CHANNEL

MSB

MSBMSB

RIGHT CHANNEL

MSB

LSB

Figure 10. Input/Output Serial Data Formats

TDM MODE APPLICATION

In TDM mode, several AD1896s can be daisy-chained together and connected to the serial input port of a SHARC DSP. The AD1896 contains a 64-bit parallel load shift register. When the LRCLK_O pulse arrives, each AD1896 parallel loads its left and right data into the 64-bit shift register. The input to the shift register is connected to TDM_IN, while the output is connected to SDATA_O. By connecting the SDATA_O to the TDM_IN

LRCLK

SCLK

AD1896

TDM_IN

PHASE-MASTER

M1 M2 M0

0 0 0

SDATA_O

LRCLK_O

SCLK_O

AD1896

TDM_IN

SDATA_O

LRCLK_O

SCLK_O

SLAV E-1 SLAVE-n

M1 M2 M0

0 0 0

0 1 0

of the next AD1896, a large shift register is created, which is clocked by SCLK_O.

The number of AD1896s that can be daisy-chained together is limited by the maximum frequency of SCLK_O, which is about 25 MHz. For example, if the output sample rate, f up to eight AD1896s could be connected since 512 ¥ f

, is 48 kHz,

is less

than 25 MHz. In master/TDM mode, the number of AD1896s that can be daisy-chained is fixed to four.

TDM_IN

AD1896

SDATA_O

LRCLK_O

SCLK_O

M1 M2 M0

0 0 0

0 1 0

STANDARD MODE

MATCHED-PHASE MODE

DR0

RFS0

RCLK0

SHARC

DSP

REV. A

Figure 11. Daisy-Chain Configuration for TDM Mode (All AD1896s Being Clock-Slaves)

–23–

AD1896

TDM_IN

CLOCK-MASTER

AND

PHASE-MASTER

M1 M2 M0

1 0 1

SDATA_O

LRCLK_O

SCLK_O

TDM_IN

AD1896

SDATA_O

LRCLK_O

SCLK_O

SLAV E-1

M1 M2 M0

0 0 0

0 1 0

Figure 12. Daisy-Chain Configuration for TDM Mode (First AD1896 Being Clock-Master)

MATCHED-PHASE MODE (NON-TDM MODE) APPLICATION

LRCLKI (f

SCLK

)

S_IN

AD1896

PHASE-MASTER

TDM_IN

SDATA_I

SDATA_O

LRCLK_I

LRCLK_O

SCLK_I

MCLK

RESET

SCLK_O

M2 M1 M0

AD1896

SLAVE1

TDM_IN

SDATA_I

LRCLK_I

SCLK_I

MCLK

RESET

M2 M1 M0

SDATA_O

LRCLK_O

SCLK_O

TDM_IN

AD1896

SLAVE2

TDM_IN

SDATA_I

LRCLK_I

SCLK_I

MCLK

RESET

M2 M1 M0

AD1896

SDATA_O

LRCLK_O

SCLK_O

SLAV E-n

M1 M2 M0

0 0 0

0 1 0

SDATA_O

LRCLK_O

SCLK_O

SHARC

DSP

DR0

RFS0

RCLK0

STANDARD MODE

MATCHED-PHASE MODE

AD1896

SLAVEn

TDM_IN

SDATA_I

SDATA_O

LRCLK_I

LRCLK_O

SCLK_I

MCLK

RESET

SCLK_O

M2 M1 M0

SDOm SDO1 SDO2

SDOn

0 0 0

1 0 0

Figure 13. Typical Configuration for Matched-Phase Mode Operation

Serial Data Port Master Clock Modes

Either of the AD1896 serial ports can be configured as a master serial data port. However, only one serial port can be a master while the other has to be a slave. In master mode, the AD1896 requires a 256 ¥ f

, 512 ¥ fS, or 768 ¥ fS master clock (MCLK_I).

For a maximum master clock frequency of 30 MHz, the maximum sample rate is limited to 96 kHz. In slave mode, sample rates up to 192 kHz can be handled.

When either of the serial ports is operated in master mode, the master clock is divided down to derive the associated left/ right subframe clock (LRCLK) and serial bit clock (SCLK). The master clock frequency can be selected for 256, 512, or 768 times the input or output sample rate. Both the input and output serial ports will support master mode LRCLK and SCLK generation for all serial modes, left justified, I2S, right justified, and TDM for the output serial port.

1 0 0

LRCLKO (f SCLK

MCLK

RESET

Table IV. Serial Data Port Clock Modes

MMODE_0/ MMODE_1/ MMODE_2

Interface Format

210

000Both serial ports are in slave mode. 001Output serial port is master with 768 ¥ f 010Output serial port is master with 512 ¥ f 011Output serial port is master with 256 ¥ f 100Matched-phase Mode 101Input serial port is master with 768 ¥ f 110Input serial port is master with 512 ¥ f 111Input serial port is master with 256 ¥ f

(64f

S_OUT

S_IN

S_OUT

)

. . .

–24–

REV. A

AD1896

Matched-Phase Mode

The matched-phase mode is the mode discussed in the Theory of Operation section that eliminates the phase mismatch between multiple AD1896s. The master AD1896 device transmits its f

S_OUT/fS_IN

ratio through the SDATA_O pin to the slave AD1896’s TDM_IN pins. The slave AD1896s receive the transmitted f f

ratio instead of their own internally derived f

S_IN

S_OUT/fS_IN

ratio and use the transmitted f

S_OUT/fS_IN

S_OUT

ratio. The master device can have both its serial ports in slave mode as depicted or either one in master mode. The slave AD1896s must have their MMODE_2, MMODE_1, and MMODE_0 pins set to 100, respectively. LRCLK_I and LRCLK_O may be asynchronous with respect to each other in this mode. Another requirement of the matched-phase mode is that there must be 32 SCLK_O cycles per subframe. The AD1896 will support the matched-phase mode for all serial output data formats, left justified, I

S, right justified, and TDM. In the case of TDM, the AD1896 shown in the TDM mode operation figure with its TDM_IN tied to ground would be

AUDIO DATA LEFT CHANNEL, 24 BITS

MATCHED-PHASE

DATA , 8 BITS

configured as the master, while the rest of the AD1896s in the chain would be configured as slaves with their MMODE_2, MMODE_1, and MMODE_0 pins set to 100, respectively.

Please note that in the left-justified, I

S, and TDM modes, the lower eight bits of each channel subframe are used to transmit the matched-phase data. In right-justified mode, the upper eight bits are used to transmit the matched-phase data. This is shown in Figures 14a and 14b.

Bypass Mode

When the BYPASS pin is asserted high, the input data bypasses the sample rate converter and is sent directly to the serial output port. Dithering of the output data when the word length is set to less than 24 bits is disabled. This mode is ideal when the input and output sample rates are the same and LRCLK_I and LRCLK_O are synchronous with respect to each other. This mode can also be used for passing through non-AUDIO data since no processing is performed on the input data in this mode.

AUDIO DATA RIGHT CHANNEL, 24 BITS

MATCHED-PHASE

DATA , 8 BITS

Figure 14a. Matched-Phase Data Transmission (Left-Justified, I2S, and TDM Mode)

MATCHED-PHASE

DATA , 8 BITS

AUDIO DATA LEFT CHANNEL,

16 BITS – 24 BITS

MATCHED-PHASE

DATA , 8 BITS

AUDIO DATA RIGHT CHANNEL,

16 BITS – 24 BITS

Figure 14b. Matched-Phase Data Transmission (Right-Justified Mode)

REV. A

–25–

AD1896

OUTLINE DIMENSIONS

28-Lead Shrink Small Outline Package [SSOP]

(RS-28)

Dimensions shown in millimeters

10.50

10.20

9.90

28 15

8.20

5.60

7.80

5.30

7.40

5.00

1.85

1.75

1.65

SEATING

PLANE

0.10 COPLANARITY

0.25

0.09

0.05 MIN

2.00 MAX

0.65

BSC

0.38

0.22

COMPLIANT TO JEDEC STANDARDS MO-150AH

8ⴗ 4ⴗ 0ⴗ

0.95

0.75

0.55

–26–

REV. A

AD1896

Revision History

Location Page

3/03—Data Sheet changed from REV. 0 to REV. A.

Edits to DIGITAL PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to DIGITAL TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Edits to RESETand Power-Down section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Edits to Figures 9a and 9b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Edits to Serial Data Ports—Data Format section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Edits to Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Update to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

REV. A

–27–

C02403–0–3/03(A)

–28–

PRINTED IN U.S.A.

Datasheet AD1896 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

PRODUCT OVERVIEW

FUNCTIONAL BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS*

ORDERING GUIDE

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

ASRC FUNCTIONAL OVERVIEW THEORY OF OPERATION

THE CONCEPTUAL HIGH INTERPOLATION MODEL

THE SAMPLE RATE CONVERTER ARCHITECTURE

HARDWARE MODEL

OPERATING FEATURES RESET and Power-Down

Power Supply and Voltage Reference

Digital Filter Group Delay

Mute Control

Master Clock

Serial Data Ports—Data Format

TDM MODE APPLICATION

MATCHED-PHASE MODE (NON-TDM MODE) APPLICATION

Serial Data Port Master Clock Modes

Matched-Phase Mode

Bypass Mode

OUTLINE DIMENSIONS

Revision History