Analog Devices AD1855 b Datasheet

a

Stereo, 96 kHz, Multibit ⌺⌬ DAC

AD1855*

FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 96 kHz Sample Rate
Multibit Sigma-Delta Modulator with “Perfect Differen-

tial Linearity Restoration” for Reduced Idle Tones
and Noise Floor

Data Directed Scrambling DAC—Least Sensitive to

Jitter
Differential Output for Optimum Performance
113 dB Signal-to-Noise and Dynamic

Range at 48 kHz

Sample Rate
110 dB Signal-to-Noise and Dynamic Range at 96 kHz

Sample Rate
–97 dB THD+N
On-Chip Volume Control with 1024 Steps
Hardware and Software Controllable Clickless Mute
Zero Input Flag Outputs for Left and Right Channels
Digital De-Emphasis Processing
Supports 128, 256, 384, and 512 ⴛ F

Master Mode

S

Clock
Switchable Clock Doubler
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-

Justified, I

2

S-Compatible and DSP Serial Port Modes

28-Lead SSOP Plastic Package

APPLICATIONS
DVD, CD, Set-Top Boxes, Home Theater Systems, Auto-

motive Audio Systems, Computer Multimedia Prod-

ucts, Sampling Musical Keyboards, Digital Mixing

Consoles, Digital Audio Effects Processors

PRODUCT OVERVIEW

The AD1855 is a high performance, single-chip stereo, audio
DAC delivering 113 dB Dynamic Range and SNR (A-weighted—
not muted) at 48 kHz sample rate. It is comprised of a multibit
sigma-delta modulator with dither, continuous time analog
filters and analog output drive circuitry. Other features include
an on-chip stereo attenuator and mute, programmed through an
SPI-compatible serial control port. The AD1855 is fully com­patible with current DVD formats, including 96 kHz sample
frequency and 24 bits. It is also backwards compatible by sup­porting 50 µs/15 µs digital de-emphasis intended for “redbook”

44.1 kHz sample frequency playback from compact discs.

The AD1855 has a very simple but very flexible serial data input
port that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers and sample rate converters.
The AD1855 can be configured in left-justified, I

2

S, right­justified, or DSP serial port compatible modes. The AD1855
accepts 16-/18-/20-/24-bit serial audio data in MSB first, twos­complement format. A power-down mode is offered to mini­mize power consumption when the device is inactive. The
AD1855 operates from a single +5 V power supply. It is fabri­cated on a single monolithic integrated circuit and housed in a
28-lead SSOP package for operation over the temperature range
0°C to +70°C.

FUNCTIONAL BLOCK DIAGRAM

VOLUME

MUTE

AD1855

16-/18-/20-/24-BIT

DATA INPUT

*Patents Pending.

DIGITAL

SERIAL

MODE

3

2

SERIAL

DATA

INTERFACE

ATTEN/

MUTE

ATTEN/

MUTE

PD/RST

8ⴛ

INTERPOLATOR

8ⴛ

INTERPOLATOR

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

96/48F

CONTROL DATA

INPUT

3

SERIAL CONTROL

INTERFACE

MULTIBIT SIGMA-

DELTA MODULATOR

MULTIBIT SIGMA-

DELTA MODULATOR

DE-EMPHASISMUTE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

VOLTAGE

REFERENCE

DAC

DAC

ANALOG

SUPPLY

DIGITAL
SUPPLY

2

CLOCK

ZERO
FLAG

IN

CLOCK

CIRCUIT

22

CLOCK

OUTPUT
BUFFER

OUTPUT
BUFFER

S

384/256

X2MCLK

ANALOG
OUTPUTS

AD1855–SPECIFICATIONS

TEST CONDITIONS UNLESS OTHERWISE NOTED

Supply Voltages (AVDD, DVDD) +5.0 V
Ambient Temperature +25°C
Input Clock 24.576 MHz (512 × F
Input Signal 1.0013 kHz

–0.5 dB Full Scale
Input Sample Rate 48 kHz
Measurement Bandwidth 20 Hz to 20 kHz
Word Width 20 Bits
Load Impedance 6 kΩ
Input Voltage HI 4.0 V
Input Voltage LO 0.8 V

Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).

ANALOG PERFORMANCE

Resolution 20 Bits
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)

No Filter 110 dB
With A-Weighted Filter 108 113 dB

Total Harmonic Distortion + Noise –97 –91 dB

Analog Outputs

Differential Output Range (±Full Scale) 5.6 V p-p
Output Impedance at Each Output Pin 200 Ω
Output Capacitance at Each Output Pin 20 pF

CMOUT 2.5 V
Gain Error –5.0 ± 3.0 +5.0 %
Interchannel Gain Mismatch –0.15 +0.15 dB
Gain Drift 150 300 ppm/°C
Interchannel Crosstalk (EIAJ Method) –120 dB
Interchannel Phase Deviation ± 0.1 Degrees
Mute Attenuation –120 dB
De-Emphasis Gain Error ± 0.1 dB

Mode)

S

Min Typ Max Units

0.0014 %

DIGITAL TIMING (Guaranteed over 0ⴗC to +70ⴗC, AV

t

DMP

t

DMP

t

DMP

t

DML

t

DMH

t

DBH

t

DBL

t

DBP

t

DLS

t

DLH

t

DDS

t

DDH

t

PDRP

MCLK Period (512 FS Mode) 35 ns
MCLK Period (384 FS Mode) 48 ns
MCLK Period (256 FS Mode) 70 ns
MCLK LO Pulsewidth (All Mode) 0.4 × t
MCLK HI Pulsewidth (All Mode) 0.4 × t
BCLK HI Pulsewidth 20 ns
BCLK LO Pulsewidth 20 ns
BCLK Period 140 ns
LRCLK Setup 20 ns
LRCLK Hold (DSP Serial Port Mode Only) 5 ns
SDATA Setup 5 ns
SDATA Hold 10 ns
PD/RST LO Pulsewidth 4 MCLK Periods ns

= DVDD = +5.0 V ⴞ 10%)

DD

Min Max Units

DMP

DMP

ns
ns

–2–

REV. B

AD1855

DIGITAL I/O (0ⴗC to +70ⴗC)

Min Typ Max Units

Input Voltage HI (V
Input Voltage LO (V
High Level Output Voltage (V
Low Level Output Voltage (V
Input Leakage (I
Input Leakage (I
Input Capacitance 10 pF

POWER

Supplies

Voltage, Analog and Digital 4.5 5 5.50 V
Analog Current 24 30 35 mA
Analog Current—Power-Down 23 29 33 mA
Digital Current 17 20 24 mA
Digital Current—Power-Down 1 2.5 5 mA

Dissipation

Operation—Both Supplies 250 mW
Operation—Analog Supply 150 mW
Operation—Digital Supply 100 mW
Power-Down—Both Supplies 190 mW

Power Supply Rejection Ratio

1 kHz 300 mV p-p Signal at Analog Supply Pins –60 dB
20 kHz 300 mV p-p Signal at Analog Supply Pins –50 dB

) 2.4 V

IH

) 1.0 V

IL

@ VIH = 5 V) 10 µA

IH

@ V

IL

IL

) IOH = 1 mA 2.0 V

OH

) IOL = 1 mA 0.4 V

OL

= 0 V) 10 µA

Min Typ Max Units

TEMPERATURE RANGE

Min Typ Max Units

Specifications Guaranteed 25 °C
Functionality Guaranteed 0 70 °C
Storage –55 +125 °C

DIGITAL FILTER CHARACTERISTICS

Min Typ Max Units

Passband Ripple ± 0.04 dB
Stopband Attenuation 47 dB
Passband 0.448 F
Stopband 0.552 F
Group Delay

32, 44.1, 48 kHz (8× Interpolation Mode) 106/F
96 kHz (4× Interpolation Mode) 53/F

S

S

sec
sec

Group Delay Variation 0 µs

Specifications subject to change without notice.

S

S

–3–REV. B

AD1855

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Min Max Units

DV

to DGND –0.3 6 V

DD

AV

to AGND –0.3 6 V

DD

Digital Inputs DGND – 0.3 DV
Analog Outputs AGND – 0.3 AV

+ 0.3 V

DD

+ 0.3 V

DD

AGND to DGND –0.3 0.3 V
Reference Voltage (AV

+ 0.3)/2

DD

Soldering +300 °C

10 sec

*Stresses greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

PACKAGE CHARACTERISTICS

Min Typ Max Units

(Thermal Resistance

θ

JA

[Junction-to-Ambient]) 109 °C/W

(Thermal Resistance

θ

JC

[Junction-to-Case]) 39 °C/W

ORDERING GUIDE

PIN CONFIGURATION

DGND

MCLK

CLATCH

CCLK

CDATA

384/256

X2MCLK

ZEROR

DEEMP

96/48

AGND

OUTR+

OUTR–

FILTR

1

2

3

4

5

6

AD1855

7

TOP VIEW

(Not to Scale)

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

DVDD

SDATA

BCLK

L/RCLK

PD/RST

MUTE

ZEROL

IDPM0

IDPM1

FILTB

AVDD

OUTL+

OUTL–

AGND

Model Temperature Package Description Package Options

AD1855JRS 0°C to +70°C 28-Lead Shrink Small Outline RS-28
AD1855JRSRL 0°C to +70°C 28-Lead Shrink Small Outline RS-28 on 13″ Reels

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1855 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

AD1855

PIN FUNCTION DESCRIPTIONS

Pin Input/Output Pin Name Description

1 I DGND Digital Ground.
2 I MCLK Master Clock Input. Connect to an external clock source at either 128, 256,

384 or 512 F
3 I CLATCH Latch input for control data. This input is rising-edge sensitive.
4 I CCLK Control clock input for control data. Control input data must be valid on the

rising edge of CCLK. CCLK may be continuous or gated.
5 I CDATA Serial control input, MSB first, containing 16 bits of unsigned data per

channel. Used for specifying channel specific attenuation and mute.
6 I 384/256 Selects the master clock mode as either 384 times the intended sample fre-

quency (HI) or 256 times the intended sample frequency (LO). The state of

this input should be hardwired to logic HI or logic LO, or may be changed

while the AD1855 is in power-down/reset. It must not be changed while the

AD1855 is operational.
7 I X2MCLK Selects internal clock doubler (LO) or internal clock = MCLK (HI).
8 O ZEROR Right Channel Zero Flag Output. This pin goes HI when Right Channel has

no signal input for more than 1024 LR Clock Cycles.
9 I DEEMP De-Emphasis. Digital de-emphasis is enabled when this input signal is HI.

This is used to impose a 50 µs/15 µs response characteristic on the output

audio spectrum at an assumed 44.1 kHz sample rate.
10 I 96/48 Selects 48 kHz (LO) or 96 kHz Sample Frequency Control.
11, 15 I AGND Analog Ground.
12 O OUTR+ Right Channel Positive line level analog output.
13 O OUTR– Right Channel Negative line level analog output.
14 O FILTR Voltage Reference Filter Capacitor Connection. Bypass and decouple the

voltage reference with parallel 10 µF and 0.1 µF capacitors to the AGND.
16 O OUTL– Left Channel Negative line level analog output.
17 O OUTL+ Left Channel Positive line level analog output.
18 I AVDD Analog Power Supply. Connect to analog +5 V supply.
19 O FILTB Filter Capacitor connection, connect 10 µF capacitor to AGND.
20 I IDPM1 Input serial data port mode control one. With IDPM0, defines one of four

serial modes.
21 I IDPM0 Input serial data port mode control zero. With IDPM1, defines one of four

serial modes.
22 O ZEROL Left Channel Zero Flag output. This pin goes HI when Left Channel has no

signal input for more than 1024 LR Clock Cycles.
23 I MUTE Mute. Assert HI to mute both stereo analog outputs. Deassert LO for nor-

mal operation.
24 I PD/RST Power-Down/Reset. The AD1855 is placed in a low power consumption

mode when this pin is held LO. The AD1855 is reset on the rising edge of

this signal. The serial control port registers are reset to the default values.

Connect HI for normal operation. A reset should always be performed at

power-on.
25 I L/RCLK Left/Right clock input for input data. Must run continuously.
26 I BCLK Bit clock input for input data. Need not run continuously; may be gated or

used in a burst fashion.
27 I SDATA Serial input, MSB first, containing two channels of 16, 18, 20, and 24 bits of

twos complement data per channel.
28 I DVDD Digital Power Supply Connect to digital +5 V supply.

, based on sample rate and clock doubler mode.

S

–5–REV. B