Analog Devices AD1853 Specification

a

Stereo, 24-Bit, 192 kHz, Multibit  DAC

AD1853*

FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:

32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz and 192 kHz

Multibit Sigma-Delta Modulator with “Perfect Differential

Linearity Restoration” for Reduced Idle Tones and

Noise Floor
Data Directed Scrambling DAC—Least Sensitive to Jitter
Differential Output for Optimum Performance
120 dB Signal to Noise (Not Muted) at 48 kHz

(A-Weighted Mono)

117 dB Signal to Noise (Not Muted) at 48 kHz

(A-Weighted Stereo)

119 dB Dynamic Range (Not Muted) at 48 kHz Sample

Rate (A-Weighted Mono)

116 dB Dynamic Range (Not Muted) at 48 kHz Sample

Rate (A-Weighted Stereo)
–107 dB THD+N (Mono Application Circuit, See Figure 30)
–104 dB THD+N (Stereo)
115 dB Stopband Attenuation (96 kHz)
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,

Interpolation Factor, Volume, Mute, De-Emphasis, Reset
Digital De-Emphasis Processing for 32, 44.1 and 48 kHz

Sample Rates
Clock Auto-Divide Circuit Supports Five Master-Clock

Frequencies
Flexible Serial Data Port with Right-Justified, Left-

Justified, I

2

S-Compatible and DSP Serial Port Modes

28-Lead SSOP Plastic Package

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS
Hi End: DVD, CD, Home Theater Systems, Automotive

Audio Systems, Sampling Musical Keyboards, Digital
Mixing Consoles, Digital Audio Effects Processors

PRODUCT OVERVIEW

The AD1853 is a complete high performance single-chip stereo
digital audio playback system. It is comprised of a high per­formance digital interpolation filter, a multibit sigma-delta
modulator, and a continuous-time current-out analog DAC
section. Other features include an on-chip clickless stereo at­tenuator and mute capability, programmed through an SPI­compatible serial control port. The AD1853 is fully compatible
with all known DVD formats and supports 48 kHz, 96 kHz and
192 kHz sample rates with up to 24 bits word lengths. It also
provides the “Redbook” standard 50 µs/15 µs digital de-emphasis
filters at sample rates of 32 kHz, 44.1 kHz and 48 kHz.

The AD1853 has a very flexible serial data input port that
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers and sample rate converters. The
AD1853 can be configured in left-justified, I

2

S, right-justified,
or DSP serial port compatible modes. The AD1853 accepts
serial audio data in MSB first, twos complement format.

The AD1853 operates from a single +5 V power supply. It is
fabricated on a single monolithic integrated circuit and is housed in
a 28-lead SSOP package for operation over the temperature
range 0°C to +70°C.

DATA INPUT

*Patents Pending.

DIGITAL

SERIAL

MODE

2

INT2 INT4

SERIAL

DATA

INTERFACE

AD1853

ATTEN/

MUTE

ATTEN/

MUTE

RESET

INTERPOLATOR

INTERPOLATOR

8  F

8  F

VOLUME

MUTE

S

S

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

2

AUTO-CLOCK

DIVIDE CIRCUIT

22

ZERO
FLAG

CLOCK

IN

ANALOG
OUTPUTS

CONTROL DATA

INPUT

3

SERIAL CONTROL

INTERFACE

MULTIBIT SIGMA-

DELTA MODULATOR

MULTIBIT SIGMA-

DELTA MODULATOR

DE-EMPHASISMUTE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

ANALOG

SUPPLY

DIGITAL
SUPPLY

VOLTAGE

REFERENCE

IDAC

IDAC

AD1853–SPECIFICATIONS

TEST CONDITIONS UNLESS OTHERWISE NOTED

Supply Voltages (AVDD, DVDD) +5.0 V
Ambient Temperature +25°C
Input Clock 24.576 MHz (512 × FS Mode)
Input Signal 996.094 kHz

–0.5 dB Full Scale
Input Sample Rate 48 kHz
Measurement Bandwidth 20 Hz to 20 kHz
Word Width 20 Bits
Input Voltage HI 3.5 V
Input Voltage LO 0.8 V

ANALOG PERFORMANCE (See Figures)

Min Typ Max Units

Resolution 24 Bits
Signal-to-Noise Ratio (20 Hz to 20 kHz)

No Filter (Stereo) 114 dB
No Filter (Mono—See Figure 30) 117 dB
With A-Weighted Filter (Stereo) 117 dB
With A-Weighted Filter (Mono—See Figure 30) 120 dB

Dynamic Range (20 Hz to 20 kHz, –60 dB Input)

No Filter (Stereo) 107.5 113 dB
No Filter (Mono—See Figure 30) 116 dB
With A-Weighted Filter (Stereo) 110 116 dB
With A-Weighted Filter (Mono—See Figure 30) 119 dB

Total Harmonic Distortion + Noise (Stereo) –94 –104 dB

0.00063 %

Total Harmonic Distortion + Noise (Mono—See Figure 30) –107 dB

0.00045 %

Analog Outputs

Differential Output Range (±Full Scale w/1 mA into I
Output Capacitance at Each Output Pin 30 pF
Out-of-Band Energy (0.5 × F

to 75 kHz) –90 dB

S

CMOUT 2.75 V
DC Accuracy

Gain Error ± 3.0 %
Interchannel Gain Mismatch –0.15 0.01 +0.15 dB

Gain Drift 25 ppm/°C
Interchannel Crosstalk (EIAJ Method) –125 dB
Interchannel Phase Deviation ± 0.1 Degrees
Mute Attenuation –100 dB
De-Emphasis Gain Error ± 0.1 dB

NOTES
Single-ended current output range: 1 mA ± 0.75 mA.

Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.

) 3.0 mA p-p

REF

DIGITAL I/O (+25C–AVDD, DVDD = +5.0 V  10%)

Min Typ Max Units

Input Voltage HI (V
Input Voltage LO (V
Input Leakage (I
Input Leakage (I

) 2.4 V

IH

) 0.8 V

IL

@ VIH = 3.5 V) 10 µA

IH

@ V

IL

= 0.8 V) 10 µA

IL

Input Capacitance 20 pF
Output Voltage HI (V

)DV

OH

–0.5 DVDD–0.4 V

DD

Output Voltage LO (VOL) 0.2 0.5 V

Specifications subject to change without notice.

–2–

REV. A

AD1853

POWER

Min Typ Max Units

Supplies

Voltage, Analog and Digital 4.5 5 5.5 V
Analog Current 12 15 mA
Digital Current 28 33 mA

Dissipation

Operation—Both Supplies 200 mW
Operation—Analog Supply 60 mW
Operation—Digital Supply 140 mW

Power Supply Rejection Ratio

1 kHz 300 mV p-p Signal at Analog Supply Pins –77 dB
20 kHz 300 mV p-p Signal at Analog Supply Pins –72 dB

Specifications subject to change without notice.

TEMPERATURE RANGE

Min Typ Max Units

Specifications Guaranteed 25 °C
Functionality Guaranteed 0 70 °C
Storage –55 125 °C

Specifications subject to change without notice.

DIGITAL FILTER CHARACTERISTICS

Sample Rate (kHz) Passband (kHz) Stopband (kHz) Stopband Attenuation (dB) Passband Ripple (dB)

44.1 DC–20 24.1–328.7 110 ± 0.0002
48 DC–21.8 26.23–358.28 110 ± 0.0002
96 DC–39.95 56.9–327.65 115 ± 0.0005
192 DC–87.2 117–327.65 95 +0/–0.04 (DC–21.8 kHz)

+0/–0.5 (DC–65.4 kHz)
+0/–1.5 (DC–87.2 kHz)

Specifications subject to change without notice.

GROUP DELAY

Chip Mode Group Delay Calculation F

INT8x Mode 5553/(128 × F
INT4x Mode 5601/(64 × F

) 48 kHz 903.8 µs

S

) 96 kHz 911.6 µs

S

S

Group Delay Units

INT2x Mode 5659/(32 × FS) 192 kHz 921 µs

Specifications subject to change without notice.

DIGITAL TIMING (Guaranteed Over 0C to +70C, AVDD = DVDD = +5.0 V  10%)

Min Units

t

DMP

t

DML

t

DMH

t

DBH

t

DBL

t

DBP

t

DLS

t

DLH

t

DDS

t

DDH

t

PDRP

*Higher MCLK frequencies are allowable when using the on-chip Master Clock Auto-Divide feature.

Specifications subject to change without notice.

MCLK Period (With F
MCLK LO Pulsewidth (All Modes) 0.4 × t
MCLK HI Pulsewidth (All Modes) 0.4 × t
BCLK HI Pulsewidth 20 ns
BCLK LO Pulsewidth 20 ns
BCLK Period 140 ns
LRCLK Setup 20 ns
LRCLK Hold (DSP Serial Port Mode Only) 5 ns
SDATA Setup 5 ns
SDATA Hold 10 ns
PD/RST LO Pulsewidth 5 ns

MCLK

= 256 × F

)* 54 ns

LRCLK

DMP

DMP

ns
ns

REV. A –3–

AD1853

WARNING!

ESD SENSITIVE DEVICE

TOP VIEW

(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AD1853

FILTR

OUTL–

OUTL+

AGND

IREF

DEEMP

ZEROR

DGND

MCLK

CLATCH

CCLK

INT2

INT4

CDATA

FCR

OUTR–

OUTR+

AVDD

FILTB

IDPM1

IDPM0

DVDD

SDATA

BCLK

L/RCLK

ZEROL

MUTE

RST

ABSOLUTE MAXIMUM RATINGS*

Min Max Units

to DGND –0.3 6 V

DV

DD

AV

to AGND –0.3 6 V

DD

Digital Inputs DGND – 0.3 DV
Analog Outputs AGND – 0.3 AV

+ 0.3 V

DD

+ 0.3 V

DD

AGND to DGND –0.3 0.3 V
Reference Voltage (AV

+ 0.3)/2

DD

Soldering +300 °C

10 sec

*Stresses greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

PACKAGE CHARACTERISTICS

Min Typ Max Units

(Thermal Resistance

θ

JA

[Junction-to-Ambient]) 109 °C/W

(Thermal Resistance

θ

JC

[Junction-to-Case]) 39 °C/W

ORDERING GUIDE

PIN CONFIGURATION

Model Temperature Package Description Package Options

AD1853JRS 0°C to +70°C 28-Lead Shrink Small Outline RS-28
AD1853JRSRL 0°C to +70°C 28-Lead Shrink Small Outline RS-28 on 13" Reels

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1853 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. A

AD1853

PIN FUNCTION DESCRIPTIONS

Pin Input/Output Pin Name Description

1 I DGND Digital Ground.
2 I MCLK Master Clock Input. Connect to an external clock source. See Table II for allowable

frequencies.
3 I CLATCH Latch input for control data. This input is rising-edge sensitive.
4 I CCLK Control clock input for control data. Control input data must be valid on the rising edge

of CCLK. CCLK may be continuous or gated.
5 I CDATA Serial control input, MSB first, containing 16 bits of unsigned data. Used for specifying

control information and channel-specific attenuation.
6 I INT4× Assert HI to select interpolation ratio of 4×, for use with double-speed inputs (88 kHz or

96 kHz). Assert LO to select 8× interpolation ratio.
7 I INT2× Assert HI to select interpolation ratio of 2×, for quad-speed inputs (176 kHz or 192 kHz).

Assert LO to select 8× interpolation ratio.
8 O ZEROR Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal

input for more than 1024 LR Clock Cycles.
9 I DEEMP De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used to

impose a 50 µs/15 µs response characteristic on the output audio spectrum at an assumed

44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected via

SPI control register.
10 I IREF Connection point for external bias resistor. Voltage held at V
11 I AGND Analog Ground.
12 O OUTL+ Left Channel Positive line level analog output.
13 O OUTL– Left Channel Negative line level analog output.
14 O FILTR Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage refer-

ence with parallel 10 µF and 0.1 µF capacitors to the AGND (Pin 11).
15 I FCR Filter cap return pin for cap connected to FILTB (Pin 19).
16 O OUTR– Right Channel Negative line level analog output.
17 O OUTR+ Right Channel Positive line level analog output.
18 I AVDD Analog Power Supply. Connect to analog +5 V supply.
19 O FILTB Filter Capacitor connection, connect 10 µF capacitor to FCR (Pin 15).
20 I IDPM1 Input serial data port mode control one. With IDPM0, defines one of four serial modes.
21 I IDPM0 Input serial data port mode control zero. With IDPM1, defines one of four serial modes.
22 O ZEROL Left Channel Zero Flag output. This pin goes HI when Left Channel has no signal input

for more than 1024 LR Clock Cycles.
23 I MUTE Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation.
24 I RST Reset. The AD1853 is placed in a reset state when this pin is held LO. The AD1853 is

reset on the rising edge of this signal. The serial control port registers are reset to the

default values. Connect HI for normal operation.
25 I L/RCLK Left/Right clock input for input data. Must run continuously.
26 I BCLK Bit clock input for input data.
27 I SDATA Serial input, MSB first, containing two channels of 16/18/20/24 bit twos-complement

data.
28 I DVDD Digital Power Supply Connect to digital +5 V supply.

REF

.

REV. A

–5–

AD1853

L/RCLK

INPUT

BCLK

INPUT

SDATA

INPUT

L/RCLK

INPUT

BCLK

INPUT

SDATA

INPUT

L/RCLK

INPUT

BCLK

INPUT

LEFT CHANNEL

LSB

MSB

LSBMSB–2MSB–1 LSB+2 LSB+1

RIGHT CHANNEL

MSB–1

MSB

MSB–2

LSB+2

LSB+1

LSB

Figure 1. Right-Justified Mode

MSB

LEFT CHANNEL

MSB–2MSB–1 LSB+2 LSB+1 LSB MSB–2MSB–1MSB LSB+2 LSB+1 LSB MSB

RIGHT CHANNEL

Figure 2. I2S-Justified Mode

LEFT CHANNEL

RIGHT CHANNEL

SDATA

INPUT

L/RCLK

INPUT

BCLK

INPUT

SDATA

INPUT

L/RCLK

INPUT

BCLK

INPUT

SDATA

INPUT

MSB

LSB MSB–1MSB–2 LSB+2 LSB+1 LSB MSB MSB–1MSB–2 LSB+2 LSB+1 LSB MSB MSB–1MSB

MSB–2MSB–1 LSB+2 LSB+1 LSB MSB–2MSB–1MSB LSB+2 LSB+1 LSB MSB–1MSB

Figure 3. Left-Justified Mode

LEFT CHANNEL

MSB–1 LSB+2 LSB+1 LSB MSB–1 LSB+2 LSB+1 LSBMSB MSB–1MSB

MSB

RIGHT CHANNEL

Figure 4. Left-Justified DSP Mode

LEFT CHANNEL

RIGHT CHANNEL

Figure 5. 32 × FS Packed Mode

–6–

REV. A

AD1853

OPERATING FEATURES
Serial Data Input Port

The AD1853’s flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The serial mode is
set by using either the external mode pins (IDPM0 Pin 21 and
IDPM1 Pin 20) or the mode select bits (Bits 4 and 5) in the SPI
control register. To control the serial mode using the external
mode pins, the SPI mode select bits should be set to zero
(default at power-up). To control the serial mode using the SPI
mode select bits, the external mode control pins should be
grounded.

In all modes except for the right-justified mode, the serial port
will accept an arbitrary number of bits up to a limit of 24 (extra
bits will not cause an error, but they will be truncated inter­nally). In the right-justified mode, control register Bits 8 and 9
are used to set the word length to 16, 20, or 24 bits. The default
on power-up is 24-bit mode. When the SPI Control Port is not
being used, the SPI pins (3, 4 and 5) should be tied LO.

Serial Data Input Mode

The AD1853 uses two multiplexed input pins to control the
mode configuration of the input data port mode.

Table I. Serial Data Input Modes

IDPM1 IDPM0
(Pin 20) (Pin 21) Serial Data Input Format

0 0 Right Justified (24 Bits) Default
01I

2

S-Compatible
1 0 Left Justified
1 1 DSP

Figure 1 shows the right-justified mode. LRCLK is HI for the
left channel, LO for the right channel. Data is valid on the rising
edge of BCLK.

In normal operation, there are 64-bit clocks per frame (or 32
per half-frame). When the SPI word length control bits (Bits 8
and 9 in the control register) are set to 24 bits (0:0), the serial
port will begin to accept data starting at the 8th bit clock pulse
after the L/RCLK transition. When the word length control bits
are set to 20-bit mode, data is accepted starting at the 12th bit
clock position. In 16-bit mode, data is accepted starting at the
16th-bit clock position. These delays are independent of the
number of bit clocks per frame, and therefore other data formats
are possible using the delay values described above. For detailed
timing, see Figure 6.

Figure 2 shows the I

2

S mode. L/RCLK is LO for the left chan-

nel, and HI for the right channel. Data is valid on the rising
edge of BCLK. The MSB is left-justified to an L/RCLK transi­tion but with a single BCLK period delay. The I

2

S mode can be

used to accept any number of bits up to 24.
Figure 3 shows the left-justified mode. L/RCLK is HI for the

left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left-justified to an L/RCLK
transition, with no MSB delay. The left-justified mode can
accept any word length up to 24 bits.

Figure 4 shows the DSP serial port mode. L/RCLK must pulse
HI for at least one bit clock period before the MSB of the left
channel is valid, and L/RCLK must pulse HI again for at least
one bit clock period before the MSB of the right channel is
valid. Data is valid on the falling edge of BCLK. The DSP serial
port mode can be used with any word length up to 24 bits.

BCLK

L/RCLK

SDATA

LEFT-JUSTIFIED

MODE

SDATA

2

I

S-JUSTIFIED

MODE

SDATA

RIGHT-JUSTIFIED

MODE

t

DBH

t

DBL

t

DLS

t

DDS

MSB

t

DDH

8-BIT CLOCKS

(24-BIT DATA)

12-BIT CLOCKS

(20-BIT DATA)

16-BIT CLOCKS

(16-BIT DATA)

t

DBP

MSB-1

t

DDS

MSB

t

DDH

t

DDS

MSB

t

DDH

t

DDS

LSB

t

DDH

Figure 6. Serial Data Port Timing

REV. A

–7–

AD1853

Table II.

Nominal Input Internal Sigma-Delta

Chip Mode Allowable Master Clock Frequencies Sample Rate Clock Rate

INT8× Mode 256 × F
INT4× Mode 128 × FS, 192 × FS, 256 × FS, 384 × FS, 512 × F
INT2× Mode 64 × FS, 96 × FS, 128 × FS, 192 × FS, 256 × F

, 384 × FS, 512 × FS, 768 × FS, 1024 × F

S

S

S

S

48 kHz 128 × F
96 kHz 64 × F
192 kHz 32 × F

S

S

S

In this mode, it is the responsibility of the DSP to ensure that
the left data is transmitted with the first LRCLK pulse, and that
synchronism is maintained from that point forward.

Note that the AD1853 is capable of a 32 × F

BCLK frequency

S

“packed mode” where the MSB is left-justified to an L/RCLK
transition, and the LSB is right-justified to the opposite L/RCLK
transition. L/RCLK is HI for the left channel, and LO for the
right channel. Data is valid on the rising edge of BCLK. Packed
mode can be used when the AD1853 is programmed in right­justified or left-justified mode. Packed mode is shown is Figure 5.

Master Clock Auto-Divide Feature

The AD1853 has a circuit that autodetects the relationship
between master clock and the incoming serial data, and inter­nally sets the correct divide ratio to run the interpolator and
modulator. The allowable frequencies for each mode are shown
above.

Serial Control Port

The AD1853 serial control port is SPI-compatible. SPI (Serial
Peripheral Interface) is an industry standard serial port protocol.
The write-only serial control port gives the user access to: select
input mode, soft reset, soft de-emphasis, channel specific at­tenuation and mute (both channels at once). The SPI port is a
3-wire interface with serial data (CDATA), serial bit clock
(CCLK), and data latch (CLATCH). The data is clocked
into an internal shift register on the rising edge of CCLK.
The serial data should change on the falling edge of CCLK and
be stable on the rising edge of CCLK. The rising edge of

CLATCH is used internally to latch the parallel data from the
serial-to-parallel converter. This rising edge should be aligned
with the falling edge of the last CCLK pulse in the 16-bit frame.
The CCLK can run continuously between transactions.

The serial control data is 16-bit MSB first, and is unsigned. Bits
0 and 1 are used to select 1 of 3 registers (control, volume left,
and volume right). The remaining 14 bits (bits 15:2) are used to
carry the data for the selected register. If a volume register is
selected, then the upper 14 bits are used to multiply the digital
input signal by the control word, which is interpreted as an
unsigned number (for example, 11111111111111 is 0 dB, and
01111111111111 is –6 dB, etc.). The default volume control
words on power-up are all 1s (0 dB). The control register only
uses bits 11:2 to carry data; the upper bits (15:12) should al­ways be written with zeroes, as several test modes are decoded
from these upper bits. The control register defaults on power-up
to 8× interpolation mode, 24-bit right-justified serial mode,
unmuted, and no de-emphasis filter. The intent with these reset
defaults is to enable AD1853 applications without requiring the
use of the serial control port. For those users that do not use the
serial control port, it is still possible to mute the AD1853 output
by using the MUTE pin (Pin 23) signal.

Note that the serial control port timing is asynchronous to the
serial data port timing. Changes made to the attenuator level
will be updated on the next edge of the LRCLK after CLATCH
write pulse as shown in Figure 6.

CDATA

CCLK

CLATCH

t

CHD

D15

t

CCH

t

CCL

t

CSU

D14

D0

t

CLH

t

CLL

Figure 7. Serial Control Port Timing

–8–

REV. A

t

CCH

t

CCL

t

CSU

t

CHD

t

CLL

t

CLH

AD1853

Table III. Digital Timing

Min Units

CCLK HI Pulsewidth 40 ns
CCLK LOW Pulsewidth 40 ns
CDATA Setup Time 10 ns
CDATA Hold Time 10 ns
CLATCH LOW Pulsewidth 10 ns
CLATCH HI Pulsewidth 10 ns

SPI REGISTER DEFINITIONS

The SPI port allows flexible control of many chip parameters.
It is organized around three registers; a LEFT-CHANNEL
VOLUME register, a RIGHT-CHANNEL VOLUME register
and a CONTROL register. Each WRITE operation to the
AD1853 SPI control port requires 16 bits of serial data in
MSB-first format. The bottom two bits are used to select one
of three registers, and the top 14 bits are then written to that
register. This allows a write to one of the three registers in a
single 16-bit transaction.

The SPI CCLK signal is used to clock in the data. The incom­ing data should change on the falling edge of this signal. At the
end of the 16 CCLK periods, the CLATCH signal should rise
to latch the data internally into the AD1853.

Register Addresses

The lowest two bits of the 16-bit input word are decoded as
follows to set the register into which the upper 14 bits will be
written.

Bit 1 Bit 0 Register

0 0 Volume Left
1 0 Volume Right
0 1 Control Register

VOLUME LEFT and VOLUME RIGHT Registers

A write operation to the left or right volume registers will acti­vate the “auto-ramp” clickless volume control feature of the
AD1853. This feature works as follows. The upper 10 bits of
the volume control word will be incremented or decremented by
1 at a rate equal to the input sample rate. The bottom 4 bits are
not fed into the auto-ramp circuit and thus take effect immedi­ately. This arrangement gives a worst-case ramp time of about
1024/F

for step changes of more than 60 dB, which has been

S

determined by listening tests to be optimal in terms of pre­venting the perception of a “click” sound on large volume
changes. See Figure 8 for a graphical description of how the
volume changes as a function of time.

The 14-bit volume control word is used to multiply the signal,
and therefore the control characteristic is linear, not dB. A con­stant dB/step characteristic can be obtained by using a lookup
table in the microprocessor that is writing to the SPI port.

LEVEL – dB

0

–60

0

VOLUME REQUEST REGISTER

ACTUAL VOLUME REGISTER

REV. A

–9–

–60

20ms

Figure 8. Smooth Volume Control

TIME

AD1853

Control Register

The following table shows the functions of the control register. The control register is addressed by having a “01” in the bottom 2 bits
of the 16-bit SPI word. The top 14 bits are then used for the control register.

Bit 11 Bit 10 Bit 9:8 Bit 7 Bit 6 Bit 5:4 Bit 3:2

INT2× Mode INT4× Mode Number of Soft Reset. Soft Mute OR’d Serial Mode OR’d De-Emphasis Filter
OR’d with Pin. OR’d with Pin. Bits in Right- Default = 0 with Pin. with Mode Pins. Select.
Default = 0 Default = 0 Justified Serial Default = 0 IDPMI:IDPM0 0:0 No Filter

Mode. 0:0 Right-Justified 0:1 44.1 kHz Filter
0:0 = 24 0:1 I
0:1 = 20 1:0 Left-Justified 1:1 48 kHz Filter
1:0 = 16 1:1 DSP Mode Default = 0.0
Default = 0:0 Default = 0:0

2

S 1:0 32 kHz Filter

Mute

The AD1853 offers two methods of muting the analog output.
By asserting the MUTE (Pin 23) signal HI, both the left and
right channel are muted. As an alternative, the user can assert
the mute bit in the serial control register (Bit 6) HI. The AD1853
has been designed to minimize pops and clicks when muting
and unmuting the device by automatically “ramping” the gain
up or down. When the device is unmuted, the volume returns to
the value set in the volume register.

Analog Attenuation

The AD1853 also offers the choice of using IREF (Pin 10) to
attenuate by up to 50 dB in the analog domain. This feature can
be used as an analog volume control. It is also a convenient
place to add a compressor/limiter gain control signal.

Output Drive, Buffering and Loading

The AD1853 analog output stage is able to drive a 1 kΩ (in
series with 2 nF) load. The analog outputs are usually ac
coupled with a 10 µF capacitor.

Figures 9–14 show the calculated frequency response of the
digital interpolation filters. Figures 15–27 show the performance
of the AD1853 as measured by an Audio Precision System 2
Cascade. For the wideband plots, the noise floor shown in the

De-Emphasis

The AD1853 has a built-in de-emphasis filter that can be used
to decode CDs that have been encoded with the standard
“Redbook” 50 µs/15 µs emphasis response curve. Three curves
are available; one each for 32 kHz, 44.1 kHz and 48 kHz sam­pling rates. The external “DEEMP” pin (Pin 9) turns on the

44.1 kHz de-emphasis filter. The other filters may be selected
by writing to control Bits 2 and 3 in the control register. If the
SPI port is used to control the de-emphasis filter, the external
DEEMP pin should be tied LO.

Control Signals

The IDPM0 and IDPM1 control inputs are normally con­nected HI or LO to establish the operating state of the AD1853.
They can be changed dynamically (and asynchronously to
LRCLK and the master clock), but it is possible that a click
or pop sound may result during the transition from one serial
mode to another. If possible, the AD1853 should be placed in
mute before such a change is made.

plots is higher than the actual noise floor of the AD1853. This is
caused by the higher noise floor of the “High Bandwidth” ADC
used in the Audio Precision measurement system. The two-tone
test shown in Figure 18 is per the SMPTE standard for measur­ing Intermodulation Distortion.

0.001

0.0008

0.0006

0.0004

0.0002

0

dB

–0.0002

–0.0004

–0.0006

–0.0008

–0.001

0

21012141620

468 18

FREQUENCY – kHz

Figure 9. Passband Response 8× Mode, 48 kHz Sample
Rate

0

–20

–40

–60

–80

–100

ATTENUATION – dB

–120

–140

–160

0 150 20050 100 250 300 350

FREQUENCY – kHz

Figure 10. Complete Response, 8× Mode, 48 kHz
Sample Rate

–10–

REV. A

Typical Performance Characteristics–

AD1853

0.5

0.4

0.3

0.2

0.1

0

dB

–0.1

–0.2

–0.3

–0.4

–0.5

5 10152025303540

–10

FREQUENCY – kHz

Figure 11. 44 kHz Passband Response 4× Mode, 96 kHz
Sample Rate

2.0

1.5

1.0

0.5

0

–20

–40

–60

–80

dB

–100

–120

–140

–160

50 100 250

0

150 200

FREQUENCY – kHz

300

Figure 14. Complete Response, 4× Mode, 96 kHz
Sample Rate

0

–20

–40

–60

0

dB

–0.5

–1.0

–1.5

–2.0

10 20 30 40 50 60 70 80

0

FREQUENCY – kHz

Figure 12. 88 kHz Passband Response 2× Mode, 192 kHz
Sample Rate

–50

–60

–70

–80

dBr

–90

–100

–110

–120

10

100 1k 10k

FREQUENCY – Hz

Figure 13. THD vs. Frequency Input @ –3 dBFS, SR 48 kHz

–80

dB

–100

–120

–140

–160

0 150 20050 100 250

FREQUENCY – kHz

Figure 15. Complete Response, 2× Mode, 192 kHz
Sample Rate

0

–10

–20

–30

–40

–50

dB

–60

–70

–80

–90

–100

–110

–120 –100 –80 –60 –40 –20 0

dBFS

Figure 16. THD + N Ratio vs. Amplitude Input 1 kHz,
SR 48 kHz, 24-Bit

REV. A

–11–

AD1853

2

0

–2

–4

dBr

–6

–8

–10

–12

10

100 1k 10k

FREQUENCY – Hz

Figure 17. Normal De-Emphasis Frequency Response
Input @ –10 dBFS, SR 48 kHz

–10

–30

–50

–70

dBr

–90

–110

–130

–150

0246810121416182022

FREQUENCY – kHz

Figure 18. SMPTE/DIN 4:1 IMD 60 Hz/7 kHz @ 0 dBFS

–90

–100

–110

–120

dBr

–130

–140

–150

–160

0246810121416182022

FREQUENCY – kHz

Figure 20. Noise Floor for Zero Input, SR 48 kHz,
SNR –117 dBFS A-Weighted

0

–10

–20

–30

–40

–50

–60

–70

dBr

–80

–90

–100

–110

–120

–130

–140

–150

0 2 4 6 8 10 12 14 16 18 20 22

FREQUENCY – kHz

Figure 21. Input 0 dBFS @ 1 kHz, BW 10 Hz to 22 kHz,
SR 48 kHz, THD+N 104 dBFS

0

–20

–40

–60

dBr

–80

–100

–120

–140

–140 –120 –100 –60 –40 –20 0–80

dBFS

Figure 19. Linearity vs. Amplitude Input 200 Hz,
SR 48 kHz, 24-Bit Word

–12–

–50

–60

–70

–80

–90

–100

dBr

–110

–120

–130

–140

–150

–160

0246810121416182022

FREQUENCY – kHz

Figure 22. Dynamic Range for 1 kHz @ –60 dBFS,
116 dB, Triangular Dithered Input

REV. A

AD1853

–60

–70

–80

dBr

–90

–100

10

100 1k 10k

FREQUENCY – Hz

Figure 23. Power Supply Rejection vs. Frequency

5 V dc + 100 mV p-p ac

AV

DD

0

–10

–20

–30

–40

–50

–60

–70

dBr

–80

–90

–100

–110

–120

–130

–140

40 60 80 100

FREQUENCY – kHz

12020

Figure 24. Wideband Plot, 15 kHz Input, 8× Interpolation,
SR 48 kHz

0

–10
–20

–30

–40
–50

–60

–70
–80

dBr

–90
–100

–110

–120
–130

–140

–150

–160

10 15 20 25

305

35 40 45 50 55 60 65 70 75 80

FREQUENCY – kHz

Figure 26. Wideband Plot, 25 kHz Input, 2× Interpolation,
SR 192 kHz

0

–10

–20

–30

–40

–50

–60

–70

–80

dBr

–90
–100

–110

–120
–130

–140

–150

–160

10 15 20 25

35 40 45 50 55 60 65 70 75 80

305

FREQUENCY – kHz

Figure 27. Wideband Plot, 75 kHz Input, 2× Interpolation,
SR 192 kHz

0

–10

–20

–30

–40

–50

–60

–70

dBr

–80

–90

–100

–110

–120

–130

–140

40 60 80 100

FREQUENCY – kHz

12020

Figure 25. Wideband Plot, 37 kHz Input, 4× Interpolation,
SR 96 kHz

REV. A

–13–

AD1853

STEREO MODE OUTPUT FILTER

DVDD

HDR2

1

EXT SDATA

EXT

L/RCLK

EXT

SCLK

EXT

MCLK

EXT I/F

IN

SPDIF/EXT

I/F

SELECT

SPNIF

IN

TOSLINK

IN

OFF

DEEMPH

R24
100

10k

C37
47pF

DVDD

R11

10k

10

S2A

1

J1

1

0

R1
75

DVDD

C4

100nF

DVDD

U1

TORX173

SHLD DGND

DVDD

R16
10k

ON

7

S2D

4

NOTE:

= DGND

= AGND

R12

SPDIF/EXT

FB1
600Z

R2

3.40k

OUT

R25
100

R13

10k

C35
47pF

SIGNAL

SOURCE

S1

500mVp-p

1k

R3
750

C24

47nF

ON

MUTE

C1

10nF

C2

10nF

R4

R10
10k

OFF

6
5

R26
100

C36
47pF

C5

100nF

S2E

10k

VA+

RXP

RXN

FILT

AGND

EXT C

R14

CS8414-CS

I/F

DVDD

FB2
600Z

VD+

SDATA

FSYNC

U2

C0/E0

Ca/E1

Cb/E2

Cd/F1

CSI2/FCK

DGND

DEEMPH

MUTE

R27
100

C34
47pF

100nF

SCK

MCK

M0

M1

M2

M3

CBL

VERF

ERF

Cc/F0

Ce/F2

SEL

HDR1

R15

10k

C6

C

U

DVDD

1

CDATA

CCLK

CLATCH

MCLK

EXT MCLK

SCLK

EXT

L/RCLK

EXT

SDATA

EXT

F

S

64F

S

256F

S

R19

10k

VREF

PREEMPH

DVDD

DGND

R7
10k

DVDD

R17
10k

9

IDPM0

S2B S2C

2

DVDD

U4

PALCE22V10-J

CLK/I0

I1

I/O9

I2

I/O8

I3

I/O7

I4

I/O6

I5

I/O5

I6

I/O4

I7

I/O3

I8

I/O2

I9

I/O1

I10

I/O0

I11

R23

DS4

274

3

R9
10k

VERF

U3A

74HC00D

1

2

R8
10k

Q1
2N2222

C11
100nF

DVDD

DVDD

R18
10k

8

IDPM1

3

MCLK

CLATCH

CCLK

CDATA

ZR

ZL

RST

ZL

ZR

U3B

74HC00D

4

5

HDR3 FN 12

44/48 0 0
96 1 0
192 0 1
NO 1 1

DVDD

R5

R6

10k

10k

U2 DATA SOURCE

DVDD

C9

100nF

DVDD AVDD

AD1853JRS

INT4

INT2

SDATA
L/RCLK

BCLK

MCLK

IDPM0

IDPM1

DEEMP

MUTE

CLATCH

CCLK

CDATA

ZEROR

ZEROL

RST

DGND

DGND

U3D

74HC00D

12

13

R22

274

6

SAMPLE RATE

MODE

HDR3

2

I

S SERIAL

DATA MODE

DEEMPH OFF

MUTE OFF

AVDD

C8

100nF

U5

OUTR+

OUTR–

OUTL+

OUTL–

FILTR

IREF

FILTB

FCR

AGND

FB3

600Z

C10

100nF

R20

274

11

U3C

74HC00D

9

10

8

DVDD

DS3
DEEMPH

#98107-02-3 REV. 1.1

10
1
2
3
4
5

ROUT+

ROUT–

LOUT+

LOUT–

V

REF

+2.7V

C26

10F

C56
100nF

2.67k

AGND

SET Ib = 1mA

DVDD

DS1
ZERO
LEFT

R21

274

DVDD

S2A
S2B
S2C
S2D
S2E

+

–

R28

DS2
ZERO
RIGHT

C12
100nF

Figure 28. Digital Receiver, MUX and AD1853 DAC

–14–

REV. A

ROUT+

ROUT–

V

REF

+2.7V

LOUT+

LOUT–

C57

220pF

NP0

+

C7

100nF

*NOT POPULATED

C58

220pF

NP0

–

R52

402

C25
10F

R53

402

C46

330pF, NP0

C52*
NP

C53*
NP

R49

4.12k

C48

330pF, NP0

C54*
NP

C55*
NP

R51

4.12k

R48

4.12k

–AV

SS

C23

100nF

U6A

C21

100nF

+AV

CC

U6B

C47

330pF, NP0

R50

4.12k

–AV

EE

C22

100nF

U7A

C20

100nF

+AV

CC

U7B

C49

330pF, NP0

OP275

OP275

OP275

OP275

OUTPUT BUFFERS AND LP FILTERS

R30

R31

R32

C38
220pF
NP0

C39
220pF
NP0

C40
220pF
NP0

C41
220pF
NP0

U8B

OP275

–AV

U8A

+AV

R33

2.74k

R35

2.74k

R37

2.74k

R39

2.74k

R34

2.74k

C43
680pF
NP0

C42
680pF
NP0

R36

2.74k

R38

2.74k

C45
680pF
NP0

C44
680pF
NP0

R40

2.74k

R29

2.94k

2.94k

2.94k

2.94k

R41

604

C50

2.2nF
NP0

GAUSSIAN FILTER RESPONSE
–3dB CORNER FREQUENCY: 75kHz

SS

C18

100nF

R42

604

OP275

C19

100nF

CC

C51

2.2nF

NP0

R43

49.9k

R44

49.9k

J2

1

0

J3

1

0

AD1853

RIGHT
OUT

LEFT
OUT

RESET GENERATOR

DVDD

C17

100nF

ADM707AR

PFI

MR

NOTE:

RESET

S3

V

CC

U10

RESET

RESET

PFO

GND

= DGND

= AGND

VOLTAGE REGULATORS AND SUPPLY FILTERING

J6

RST

+15V dc

CR2

1SMB15AT3

0V

AGND

–15V dc

+9V dc

TO

+15V dc

1SMB15AT3

0V

DGND

J7

J8

J4

J5

C15

100nF

CR3

1N4001

CR1

FB4
600Z

FB5

600Z

C27

10F

+

–

C30
10F

ADP3303-5.0

IN

IN

ERR

SD

+

–

C13
100nF

U11

OUT

OUT

NR

GND

V

IN

U9

LM317

V

GND

OUT

+

–

C28
10F

+5V REG

Figure 29. DAC Output LP Filter, Power and Reset

C16

100nF

C3
10nF

R45
243

R46
715

+

C32
10F

–

R47

332

+

C31
10F

–

AGND

+

C33
10F

–

+5V REG

C14
100nF

+

–

DS5

POWER

C29
10F

DGND

+AV

AVDD

–AV

DVDD

CC

SS

REV. A

–15–

AD1853

PIN 12

LOUT+

PIN 13

LOUT–

PIN 17

ROUT+

PIN 16

ROUT–

V

REF

+2.78V

100nF

I/V CONVERTERS AND LP FILTER

R9*

2.87k

C6

68pF, NP0

R11

100

U2

AD797

U3

AD797

C7

R10*

2.87k

R12

100

68pF, NP0

C15

C8

+

10F

–

TANT

NOTE:

= AGND

GAUSSIAN FILTER RESPONSE
–3dB CORNER FREQUENCY: 75kHz

R4

2.74k

R3

2.74k

R5

2.74k

2.74k

+AV

–AV

C4
680pF
NP0

C3
680pF
NP0

R6

CC

SS

R1

2.94k

R2

2.94k

C1
220pF
NP0

R7

U1

AD797

C2
220pF
NP0

NOTES:

1. R9, R10 MUST BE LOW NOISE TYPES.
METAL FILM IS RECOMMENDED.

2. RIGHT CHANNEL DIGITAL DATA MUST BE INVERTED.

C10
100nF

C9
100nF

C12
100nF

C11
100nF

604

C14
100nF

C13
100nF

C5

2.2nF
NP0

C16

+

10F

–

TANT

+

–

C17
10F

TANT

R8

49.9k

J2

J3

J4

J1

1

0

+16.5V dc

0V
AGND

–16.5V dc

OUT
6Vrms

C3503a–8–4/99

0.311 (7.9)

0.301 (7.64)

0.078 (1.98)

0.068 (1.73)

0.008 (0.203)

0.002 (0.050)

Figure 30. Mono Application Circuit

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead Shrink Small Outline Package (SSOP)

(RS-28)

0.407 (10.34)

0.397 (10.08)

28 15

0.212 (5.38)

0.205 (5.21)

141

PIN 1

0.0256
(0.65)

BSC

0.015 (0.38)

0.010 (0.25)

0.066 (1.67)

SEATING

PLANE

0.07 (1.79)

0.009 (0.229)

0.005 (0.127)

8°
0°

0.03 (0.762)

0.022 (0.558)

PRINTED IN U.S.A.

–16–

REV. A