Analog Devices AD1848KST, AD1848KP Datasheet

Parallel-Port 16-Bit

a

FEATURES
Single-Chip Integrated ∑∆ Digital Audio Stereo Codec
Supports the Microsoft Windows Sound System®
Multiple Channels of Stereo Input
Analog and Digital Signal Mixing
Programmable Gain and Attenuation
On-Chip Signal Filters

Digital Interpolation

Analog Output Low-Pass
Sample Rates from 5.5 kHz to 48 kHz
68-Lead PLCC and 68-Lead TQFP Packages
Operation from +5 V Supplies
Byte-Wide Parallel Interface to ISA and EISA Buses
Supports One or Two DMA Channels and

Programmed I/O

PRODUCT OVERVIEW

The Parallel-Port AD1848K SoundPort® Stereo Codec inte­grates the key audio data conversion and control functions into
a single integrated circuit. The AD1848K is intended to provide
a complete, single-chip audio solution for business audio and
multimedia applications requiring operation from a single +5 V

SoundPort is a registered trademark of Analog Devices, Inc.

SoundPort Stereo Codec

AD1848K

supply. It provides a direct, byte-wide interface to both ISA
(“AT”) and EISA computer buses for simplified implementa­tion on a computer motherboard or add-in card. The AD1848K
generates enable and direction controls for IC buffers such as
74_245.

The AD1848K SoundPort Stereo Codec supports a DMA re­quest/grant architecture for transferring data with the host com­puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control
register accesses and for applications lacking DMA control. Two
input control lines support mixed direct and indirect addressing
of twenty-one internal control registers over this asynchronous
interface.

External circuit requirements are limited to a minimal number
of low cost support components. Anti-imaging DAC output fil­ters are incorporated on-chip. Dynamic range exceeds 80 dB
over the 20 kHz audio band. Sample rates from 5.5 kHz to
48 kHz are supported from external crystals.

The Codec includes a stereo pair of ∑∆ analog-to-digital
converters and a stereo pair of ∑∆ digital-to-analog converters.
Inputs to the ADC can be selected from four stereo pairs of

(Continued on page 9)

FUNCTIONAL BLOCK DIAGRAM

DIGITAL
SUPPLY

L

R

ANALOG

FILTER

ANALOG

FILTER

GAIN

GAIN

REFERENCE

20

dB

∑

ATTEN/

MUTE

ATTEN/

MUTE

MUX

∑∆ A/D

CONVERTER

∑∆ A/D

CONVERTER

∑∆ D/A

CONVERTER

∑∆ D/A

CONVERTER

2.25V

ANALOG

L_LINE

R_LINE

L_MIC

R_MIC

L_AUX1

R_AUX1

L_OUT

R_OUT

L_AUX2
R_AUX2

ANALOG

SUPPLY

GAIN/ATTEN/MUTE

L

R

∑

GAIN/ATTEN/MUTE

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

CRYSTALS

2

2

OSCILLATORS

16

16

DIGITAL

INTERPOL

INTERPOL

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

ATTENUATE

ATTENUATE

∑

MIX

∑

CONTROL

REGS

POWER DOWN

µ/
A

P

L

A

A

R

W

A
L
L
E
L

P
O

µ/

R

A

T

L
A
W

2

8

2

2

DIGITAL

PLAYBACK REQ
PLAYBACK ACK
CAPTURE REQ

CAPTURE ACK

ADR1:0

DATA7:0

CS

WR
RD
BUS DRIVER

CONTROL

HOST DMA

INTERRUPT
EXTERNAL

CONTROL

AD1848K–SPECIFICA TIONS

STANDARD TEST CONDITIONS UNLESS
OTHERWISE NOTED

Temperature 25 °C
Digital Supply (V
Analog Supply (V
Word Rate (F

) 5.0 V

DD

) 5.0 V

CC

) 48 kHz

S

Input Signal 1008 Hz
Analog Output Passband 20 Hz to 20 kHz
ADC FFT Size 2048
DAC FFT Size 8192
V

IH

V

IL

V

OH

V

OL

ANALOG INPUT

2.4 V

0.8 V

2.4 V

0.4 V

DAC Input Conditions

Post-Autocalibrated
0 dB Attenuation
–2.0 dB Relative to Full Scale
16-Bit Linear Mode
No Output Load
Mute Off

ADC Input Conditions

Post-Autocalibrated
0 dB Gain
–3.0 dB Relative to Full Scale
Line Input
16-Bit Linear Mode

Min Typ Max Units

Input Voltage (RMS Values Assume Sine Wave Input)

Line 1 V rms

2.6 2.8 3.0 V p-p

Mic with +20 dB Gain (MGE = 1) 0.1 V rms

0.26 0.28 0.3 V p-p

Mic with 0 dB Gain (MGE = 0) 1 V rms

2.6 2.8 3.0 V p-p
Input Impedance 20 kΩ
Input Capacitance 15 pF

PROGRAMMABLE GAIN AMPLIFIER—ADC

Min Typ Max Units

Step Size (0 dB to 22.5 dB) 1.3 1.5 1.7 dB

(All Steps Tested, –30 dB Input)

PGA Gain Range Span* 21.5 22.5 23.5 dB

AUXILIARY INPUT ANALOG AMPLIFIERS/ATTENUATORS

Min Typ Max Units

Step Size (+12.0 dB to –33.0 dB) 1.3 1.5 1.7 dB

(All Steps Tested, –14.5 dB Input)

Auxiliary Gain/Attenuation Range Span* 45.5 46.5 47.5 dB

–2–

REV. 0

DIGITAL DECIMATION AND INTERPOLATION FILTERS*

Min Max Units

AD1848K

Passband 0 0.45 3 F

S

Hz
Passband Ripple ±0.1 dB
Transition Band 0.45 3 F
Stopband 0.55 3 F

S
S

0.55 3 F

S

Hz

∞ Hz
Stopband Rejection 74 dB
Group Delay 30/F

S

Group Delay Variation Over Passband 0.0 µs

ANALOG-TO-DIGITAL CONVERTERS

Min Typ Max Units

Resolution (No Missing Codes from 16 Bits

±10 LSB Ramp Around Midscale)*

Dynamic Range (–60 dB Input, 80 86 dB

THD+N Referenced to Full Scale)

THD+N (Referenced to Full Scale) 0.022 %

–77 –73 dB
Signal-to-Intermodulation Distortion* 90 dB
ADC Crosstalk*

Line Inputs (Input L, Ground R, Read R; –80 dB
Input R, Ground L, Read L)
Line to MIC (Input LINE, Ground and –80 dB
Select MIC, Read Both Channels)
Line to AUX1 –80 dB

Line to AUX2 –80 dB
Gain Error (Full-Scale Span Relative to Nominal) ±5%
Interchannel Gain Mismatch ±0.5 dB

(Difference of Gain Errors)
ADC Offset Error 50 LSBs

DIGITAL-TO-ANALOG CONVERTERS

Min Typ Max Units

Resolution* 16 Bits
Dynamic Range (–60 dB Input, 80 87 dB

THD+N Referenced to Full Scale)
THD+N (Referenced to Full Scale) 0.02 %

–76 –74 dB
Signal-to-Intermodulation Distortion* 90 dB
Gain Error (Full-Scale Span Relative to Nominal) ±5%
Interchannel Gain Mismatch ±0.5 dB

(Difference of Gain Errors)

DAC Crosstalk* (Input L, Zero R, Measure –80 dB

R_OUT; Input R, Zero L, Measure L_OUT)

Total Out-of-Band Energy* –45 dB

(Measured from 0.55 × F

to 100 kHz)

S

Audible Out-of-Band Energy* –70 dB

(Measured from 0.55 × F

to 22 kHz,

S

All Selectable Sampling Frequencies)

*Guaranteed Not Tested.
Specifications subject to change without notice.

REV. 0

–3–

AD1848K

DAC ATTENUATOR

Min Typ Max Units

Step Size (0 dB to –34.5 dB) 1.3 1.5 1.7 dB
Step Size (–60 dB to –94.5 dB)* 1.0 1.5 2.0 dB
Output Attenuation Range Span* 93.5 94.5 95.5 dB

ANALOG OUTPUT

Min Typ Max Units

Full-Scale Output Voltage 0.707 Vrms

1.85 2.0 2.1 V p-p
Output Impedance 600 Ω
External Load Impedance 10 kΩ
Output Capacitance 15 pF
External Load Capacitance 100 pF
V

REF

V

Current Drive 100 µA

REF

V

Output Impedance 4 kΩ

REF

Mute Attenuation of 0 dB –80 dB

Fundamental* (OUT)

Mute Click 5mV

(|Muted Output Minus Unmuted
Midscale DAC Output|)

2.10 2.25 2.40 V

SYSTEM SPECIFICATIONS

Min Typ Max Units

Peak-to-Peak Frequency Response Ripple* 1.0 dB

(Line In to Line Out)
Differential Nonlinearity* ±1 Bit
Phase Linearity Deviation* 5 Degrees

STATIC DIGITAL SPECIFICATIONS

Min Max Units

High Level Input Voltage (V

)

IH

Digital Inputs 2.4 (VD+) + 0 3 V

XTAL1/2I 2.4 (VD+) + 0 3 V
Low Level Input Voltage (V
High Level Output Voltage (V
Low Level Output Voltage (V

) –0.3 0.8 V

IL

) at IOH = –2 mA 2.4 V

OH

) at IOL = 2 mA 0.4 V

OL

Input Leakage Current –10 10 µA

(GO/NOGO Tested)
Output Leakage Current –10 10 µA

(GO/NOGO Tested)

–4–

REV. 0

AD1848K

TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE AND V

= VCC = 5.0 V 65%)

DD

Min Max Units

WR/RD Strobe Width (t
WR/RD Rising to WR/RD Falling (t

Write Data Setup to

RD Falling to Valid Read Data (t
CS Setup to WR/RD Falling (t
CS Hold from WR/RD Rising (t

Adr Setup to
Adr Hold from

WR/RD Falling (t

WR/RD Rising (t
DAK Rising to WR/RD Falling (t
DAK Falling to WR/RD Rising (t
DAK Setup to WR/RD Falling (t

Data Hold from
Data Hold from
DRQ Hold from

RD Rising (t
WR Rising (t

WR/RD Falling (t
DAK Hold from WR Rising (t
DAK Hold from RD Rising (t
DBEN/DBDIR delay from WR/RD Falling (t

) 110 ns

STW

WR Rising (t

RDDV

CSSU

CSHD

ADSU

ADHD

SUDK1
SUDK2

DKSU

DHD1

DHD2

DKHDa

DKHDb

) 110 ns

BWND

)22ns

WDSU

)3070ns

)10ns

)0ns

)10ns

)10ns

)60ns
)0ns

)25ns

)020ns

)15ns

)025ns

DRHD

)50ns
)50ns

)030ns

DBDL

POWER SUPPLY

Min Max Units

Power Supply Range – Analog 4.75 5.25 V
Power Supply Range – 5 V Digital 4.75 5.25 V
Power Supply Current – 5 V Operating 120 mA

(5 V Supplies, 10 kΩ Load)
Analog Supply Current – 5 V Operating (10 kΩ Load) 65 mA
Digital Supply Current – 5 V Operating (10 kΩ Load) 55 mA
Digital Power Supply Current – Power Down 1 mA
Analog Power Supply Current – Power Down 1 mA
Power Dissipation – 5 V Operating 600 mW

(Current • Nominal Supplies)
Power Dissipation – Power Down

(Current • Nominal Supplies) 10 mW
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)* 40 dB F

(At Both Analog and Digital Supply Pins, Both ADCs

and DACs)

S

CLOCK SPECIFICATIONS*

Min Max Units

Input Clock Frequency 27 MHz
Recommended Clock Duty Cycle Tolerance ±10 %
Initialization Time

16.9344 MHz Crystal Selected 70 ms

24.576 MHz Crystal Selected 90 ms

*Guaranteed, not tested
Specifications subject to change without notice.

REV. 0

–5–

AD1848K

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

ORDERING GUIDE

Min Max Units

Power Supplies

Digital (V
Analog (V

) –0.3 6.0 V

DD

) –0.3 6.0 V

CC

Input Current

(Except Supply Pins) ±10.0 mA

Model Range Description Option

AD1848KP –40°C to +85°C 68-Lead PLCC P-68A
AD1848KST –40°C to +85°C 64-Lead TQFP ST-64

Temperature Package Package

Analog Input Voltage (Signal Pins) –0.3 (VA+) + 0.3 V
Digital Input Voltage (Signal Pins) –0.3 (VD+) + 0.3 V
Ambient Temperature (Operating) –40 +85 °C
Storage Temperature –65 +150 °C
ESD Tolerance (Human Body

Model per Method 3015.2
of MIL-STD-883B) 1000 V

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1848K features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

68-Lead Plastic Leaded Chip Carrier Pinout

64-Lead Thin Quad Flatpack Pinout

ADR0
CDAK

CDRQ
PDAK

PDRQ

V

GNDD

XTAL1I

XTAL1O

V

GNDD

XTAL2I

XTAL2O

PWRDWN

V

GNDD

R_FILT

10
11

12

13
14
15

DD

16
17
18
19

DD

20

21
22
23
24

DD

25
26

NC = NO CONNECT

ADR1

R_LINE

GNDD

R_MIC

DD

V

L_MIC

DATA0

L_LINE

DATA3

GNDD

DD

V

DATA1

DATA2

AD1848K

TOP VIEW

31 3230292827 36

CC

V

(2.25V)

REF

V

_F (BYPASS)
V

GNDA

REF

L_FILT

DATA4

67 66 6568123 63 62 6164546789

37 38 39353433

CC

V

DATA5

GNDA

DATA7

DATA6

L_AUX2

L_AUX1

40

GNDD

41 42

L_OUT

DBEN

R_OUT

DBDIR

WR

43

R_AUX1

R_AUX2

DD

DATA2

DATA1

DATA0

GNDD

ADR1

V

60

RD

59

CS
XCTL1

58
57

INT

56

XCTL0

55

NC

54

V

DD

53

GNDD

52

NC

51

NC

50

NC

49

NC
NC

48

47

NC
NC

46

V

45

DD

44

GNDD

ADR0
CDAK
CDRQ

PDAK
PDRQ

GNDD

XTAL1I

XTAL1O

GNDD

XTAL2I

XTAL2O

PWRDWN

GNDD

V

DD

V

DD

V

DD

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

L_MIC

R_MIC

R_FILT

R_LINE

NC = NO CONNECT

L_LINE

L_FILT

GNDD

DATA3

V

56 55 54 53 52 51 50 4964 63 62 61 60 59 58 57

AD1848K

TOP VIEW

(2.25V)

REF

V

_F (BYPASS)

REF

V

DD

GNDA

DATA4

CC

V

DATA5

CC

V

DATA6

GNDA

DATA7

L_AUX2

DBEN

GNDD

L_OUT

L_AUX1

DBDIR

R_OUT

4748RD
46
45
44
43
42
41
40
39
38
37
36
35
34
33

WR

CS
XCTL1
INT
XCTL0
NC
V

DD

GNDD
NC
NC
NC
V

DD

GNDD
R_AUX2
R_AUX1

–6–

REV. 0

AD1848K

PIN DESCRIPTION

Parallel Interface
Pin Name PLCC TQFP I/O Description

CDRQ 12 3 O Capture Data Request. The assertion of this signal indicates that the Codec has a cap-

tured audio sample from the ADC ready for transfer. This signal will remain asserted un­til all the bytes from the capture buffer have been transferred.

CDAK 11 2 I Capture Data Acknowledge. The assertion of this active LO signal indicates that the RD

cycle occurring is a DMA read from the capture buffer.

PDRQ 14 5 O Playback Data Request. The assertion of this signal indicates that the Codec is ready for

more DAC playback data. The signal will remain asserted until all the bytes needed for a
playback sample have been transferred.

PDAK 13 4 I Playback Data Acknowledge. The assertion of this active LO signal indicates that the WR

cycle occurring is a DMA write to the playback buffer.

ADR1:0 9 & 10 1 & 64 I Codec Addresses. These address pins are asserted by the Codec interface logic during a

control register/PIO access. The state of these address lines determine which register is
accessed.

RD 60 47 I Read Command Strobe. This active LO signal defines a read cycle from the Codec. The

cycle may be a read from the control/PIO registers, or the cycles could be a read from the
Codec’s DMA sample registers.

WR 61 48 I Write Command Strobe. This active LO signal indicates a write cycle to the Codec. The

cycle may be a write to the control/PIO registers, or the cycle could be a write to the
Codec’s DMA sample registers.

CS 59 46 I AD1848K Chip Select. The Codec will not respond to any control/PIO cycle accesses

unless this active LO signal is LO. This signal is ignored during DMA transfers.

DATA7:0 3–6 & 52–55 & I/O Data Bus. These pins transfer data and control information between the Codec and the

65–68 58–61 host.

DBEN 63 50 O Data Bus Enable. This pin enables the external bus drivers. This signal is normally HI.

For control register/PIO cycles,

DBEN = (WR or RD) and CS

For DMA cycles,

DBEN = (WR or RD) and (PDAK or CDAK)

DBDIR 62 49 O Data Bus Direction. This pin controls the direction of the data bus transceiver. HI

enables writes from the host to the AD1848K; LO enables reads from the AD1848K to
the host bus. This signal is normally HI.

For control register/PIO cycles,

DBDIR =

For DMA cycles,

DBDIR = RD and (PDAK or CDAK)

RD and CS

REV. 0

–7–

AD1848K

Analog Signals
Pin Name PLCC TQFP I/O Description

L_LINE 30 21 I Left Line Input. Line level input for the left channel.
R_LINE 27 18 I Right Line Input. Line level input for the right channel.
L_MIC 29 20 I Left Microphone Input. Microphone input for the left channel. This signal

can be either line level or –20 dB from line level.

R_MIC 28 19 I Right Microphone Input. Microphone input for the right channel. This

signal can be either line level or –20 dB from line level.
L_AUX1 39 30 I Left Auxiliary #1 Line Input
R_AUX1 42 33 I Right Auxiliary #1 Line Input
L_AUX2 38 29 I Left Auxiliary #2 Line Input
R_AUX2 43 34 I Right Auxiliary #2 Line Input
L_OUT 40 31 O Left Line Level Output
R_OUT 41 32 O Right Line Level Output

Miscellaneous
Pin Name PLCC TQFP I/O Description

XTAL1I 17 8 I 24.576 MHz Crystal #1 Input
XTAL1O 18 9 O 24.576 MHz Crystal #1 Output
XTAL2I 21 12 I 16.9344 MHz Crystal #2 Input
XTAL2O 22 13 O 16.9344 MHz Crystal #2 Output
PWRDWN 23 14 I Power-Down Signal. Active LO control places AD1848K in its lowest

power consumption mode. All sections of the AD1848K, including the

digital interface, are shut down and consume minimal power.
INT 57 44 O Host Interrupt Pin. This signal is used to notify the host that the DMA

Current Count Register has underflowed.
XCTL1:O 56 & 58 43 & 45 O External Control. These signals reflect the current status of register bits

inside the AD1848K. They can be used for signaling or to control external

logic.
V

REF

V

_F 33 24 I Voltage Reference Filter. Voltage reference filter point for external

REF

L_FILT 31 22 I Left Channel Filter Input. This pin requires a 1.0 µF capacitor to analog

R_FILT 26 17 I Right Channel Filter Input. This pin requires a 1.0 µF capacitor to analog

N/C 46–52, 55 37–39, 42 No Connect. Do not connect.

32 23 O Voltage Reference. Nominal 2.25 volt reference available for dc-coupling

and level-shifting. V

should not be used where it will sink or source

REF

current.

bypassing only.

ground for proper operation.

ground for proper operation.

Power Supplies
Pin Name PLCC TQFP I/O Description

V

CC

35 & 36 26 & 27 I Analog Supply Voltage (+5 V)
GNDA 34 & 37 25 & 28 I Analog Ground
V

DD

1, 7, 15, 19, 6, 10, 15, 36, I Digital Supply Voltage (+5 V)

24, 45, 54 41, 56
GNDD 2, 8, 16, 20, 7, 11, 16, 35, I Digital Ground

25, 44, 53, 64 40, 51, 63

–8–

REV. 0

AD1848K

(Continued from page 1)

analog signals: line, microphone (“mic”), auxiliary (“aux”) #1,
and post-mixed DAC output. The microphone inputs can pass
through optional 20 dB gain blocks. A software-controlled pro­grammable gain stage allows independent gain for each channel
going into the ADC. The ADCs’ output can be digitally mixed
with the DACs’ input.

AD1848K

CS

WR

RD

DATA7:0

DBDIR

DBEN

PDRQ

CDRQ

PDAK

CDAK

INT

ADDRESS

DECODE

A1
A0

DIR
G

7
4

2
4
5

8

B

AEN

18

SA19:2
SA1
SA0
IOWC
IORC

8

DATA7:0

ISA BUS

A

DRQ<X>
DRQ<Y>
DAK<X>
DAK<Y>
IRQ<Z>

Figure 1. Interface to ISA Bus

The pair of 16-bit outputs from the ADCs is available over a
byte-wide bidirectional interface that also supports 16-bit digital
input to the DACs and control information. The AD1848K can
accept and generate 16-bit twos-complement PCM linear digital
data, 8-bit unsigned magnitude PCM linear data, and 8-bit
µ-law or A-law companded digital data.

The ∑∆ DACs are preceded by a digital interpolation filter. An
attenuator provides independent user volume control over each
DAC channel. Nyquist images and shaped quantization noise
are removed from the DACs’ analog stereo output by on-chip
switched-capacitor and continuous-time filters. Two stereo pairs
of auxiliary line-level inputs can also be mixed in the analog do­main with the DAC output.

AUDIO FUNCTIONAL DESCRIPTION

This section overviews the functionality of the AD1848K and is
intended as a general introduction to the capabilities of the de­vice. As much as possible, detailed reference information has
been placed in “Control Registers” and other sections. The user
is not expected to refer repeatedly to this section.

Analog Inputs

The AD1848K SoundPort Stereo Codec accepts stereo
line-level and mic-level inputs. LINE, MIC, and AUX1 inputs
and post-mixed DAC output analog stereo signals are multi­plexed to the internal programmable gain amplifier stage
(PGA). Each channel of the mic inputs can be amplified by

+20 dB prior to the PGA to compensate for the voltage swing
difference between line levels and typical condenser micro­phones. Alternatively, the mic inputs can bypass the +20 dB
fixed gain block and go straight to the input multiplexer.

The PGA following the input multiplexer allows independent se­lectable gains for each channel from 0 to 22.5 dB in +1.5 dB
steps. The Codec can operate either in a global stereo mode or
in a global mono mode with left channel inputs appearing at
both channel outputs.

Analog Mixing

AUX1 and AUX2 analog stereo signals can be mixed in the ana­log domain with the DAC output. Each channel of each auxil­iary analog input can be independently gained/attenuated from
+12 dB to –34.5 dB in –1.5 dB steps or completely muted. The
post mixed DAC output is available on OUT externally and as
an input to the ADCs.

Even if the AD1848K is not playing back data from its DACs,
the analog mix function can still be active.

Analog-to-Digital Datapath

The AD1848K ∑∆ ADCs incorporate a fourth order modulator.
A single pole of passive filtering is all that is required for
anti-aliasing the analog input due to the ADC’s high 64 times
oversampling ratio. The ADCs include linear phase digital deci­mation filters that low-pass filter the input to 0.45 × F

(“FS” is

S

the word rate or “sampling frequency.”) ADC input overrange
conditions will cause register bits to be set that can be read.

Digital-to-Analog Datapath

The ∑∆ DACs contain a programmable attenuator and a low­pass digital interpolation filter. The anti-imaging interpolation
filter nominally oversamples by 64 and digitally filters the higher
frequency images. The interpolation ratio is increased at low
sample rates to ensure that the shaped quantization noise is
inaudible. This feature of the AD1848K represents an improve­ment over the earlier AD1848J. The attenuator allows indepen­dent control of each DAC channel from 0 dB to –94.5 dB in

1.5 dB steps plus full mute. The DACs’ ∑∆ noise shapers also
oversample by 64 and convert the signal to a single bit stream.
The DAC outputs are then filtered in the analog domain by a
combination of switched-capacitor and continuous-time filters.
They remove the very high frequency components of the DAC
bitstream output. No external components are required. Phase
linearity at the analog output is achieved by internally compen­sating for the group delay variation of the analog output filters.

Changes in DAC output attenuation take effect only on zero
crossings of the digital signal, thereby eliminating “zipper”
noise. Each channel has its own independent zero-crossing de­tector and attenuator change control circuitry. A timer guarantees
that requested volume changes will occur even in the absence of
an input signal that changes sign. The time-out period is 8 milli­seconds at a 48 kHz sampling rate and 48 milliseconds at an
8 kHz sampling rate. (Time out [ms] ≈ 384/F

[kHz].)

S

REV. 0

–9–