Analog Devices AD1819B Datasheet

a

AC’97 SoundPort® Codec

AD1819B

AC’97 FEATURES
Fully Compliant AC’97 Analog I/O Component
48-Terminal LQFP Package
Multibit ⌺⌬ Converter Architecture for Improved

S/N Ratio >90 dB
16-Bit Stereo Full-Duplex Codec
Four Analog Line-Level Stereo Inputs for Connection

from LINE, CD, VIDEO, and AUX
Two Analog Line-Level Mono Inputs for Speakerphone

and PC BEEP
Mono MIC Input Switchable from Two External

Sources
High Quality CD Input with Ground Sense
Stereo Line Level Output
Mono Output for Speakerphone
Power Management Support

FUNCTIONAL BLOCK DIAGRAM

AD1819B

MIC1
MIC2

LINE_IN

AUX

CD

VIDEO

PHONE_IN

LINE_OUT_L

MONO_OUT

LINE_OUT_R

PC_BEEP

0dB/
20dB

MV

MV

MV

G
A

S

M

PHAT

S

S

STEREO

S

S

A
M

PHAT

S

STEREO

ENHANCED FEATURES
Support for Multiple Codec Communications
DSP 16-Bit Serial Port Format
Variable 7 kHz to 48 kHz Sampling Rate with 1 Hz

Supports Modem Sample Rates and Filtering
Phat™ Stereo 3D Stereo Enhancement
VHDL and Verilog Models of Serial Port Available

G

G
A
M

S S

S S S S

G = GAIN
A = ATTENUATE
M = MUTE
MV = MASTER VOLUME

G
A
M

G

A

A

M

M

S

S

S

Resolution

G
A
M

S

S

PGA

SELECTOR

PGA

G
A
M

G
A
M

CS1

CS0

MASTER/SLAVE
SYNCHRONIZER

16-BIT
SD A/D

CONVERTER

16-BIT

SD A/D

CONVERTER

SAMPLE

RATE

GENERATORS

16-BIT

SD D/A

CONVERTER

16-BIT

SD D/A

CONVERTER

OSCILLATORS

XTALO

CHAIN_IN

XTALI

CHAIN_CLK

RESET

SYNC

BIT_CLK

AC LINK

SDATA_OUT

SDATA_IN

SoundPort is a registered trademark of Analog Devices, Inc.
Phat is a trademark of Analog Devices, Inc.

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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD1819B

PRODUCT OVERVIEW

The AD1819B SoundPort Codec is designed to meet all require­ments of the Audio Codec ’97, Component Specification, Revision

1.03, © 1996, Intel Corporation, found at www.Intel.com. In
addition, the AD1819B supports multiple codec configurations
(up to three per AC-Link), a DSP serial mode, variable sample
rates, modem sample rates and filtering, and built-in Phat Ste­reo 3D enhancement.

The AD1819B is an analog front end for high performance PC
audio, modem, or DSP applications. The AC’97 architecture
defines a 2-chip audio solution comprising a digital audio con­troller, plus a high quality analog component that includes
Digital-to-Analog Converters (DACs), Analog-to-Digital Con­verters (ADCs) mixer and I/O.

The main architectural features of the AD1819B are the high

quality analog mixer section, two channels of Σ∆ ADC conver­sion, two channels of Σ∆ DAC conversion and Data Direct

Scrambling (D

2

S) rate generators. The AD1819B’s left channel
ADC and DAC are compatible for modem applications support­ing irrational sample rates and modem filtering requirements.

FUNCTIONAL DESCRIPTION

This section overviews the functionality of the AD1819B and is
intended as a general introduction to the capabilities of the
device. Detailed reference information may be found in the
descriptions of the Indexed Control Registers.

Analog Inputs

The codec contains a stereo pair of Σ∆ ADCs. Inputs to the

ADC may be selected from the following analog signals: tele­phony (PHONE_IN), mono microphone (MIC1 or MIC2),
stereo line (LINE_IN), auxiliary line input (AUX), stereo CD
ROM (CD), stereo audio from a video source (VIDEO) and
post-mixed stereo or mono line output (LINE_OUT).

Analog Mixing

PHONE_IN, MIC1 or MIC2, LINE_IN, AUX, CD and
VIDEO can be mixed in the analog domain with the stereo
output from the DACs. Each channel of the stereo analog in­puts may be independently gained or attenuated from +12 dB
to –34.5 dB in 1.5 dB steps. The summing path for the mono
inputs (PHONE_IN, MIC1, and MIC2 to LINE_OUT) dupli­cates mono channel data on both the left and right LINE_OUT.
Additionally, the PC attention signal (PC_BEEP) may be
mixed with the line output. A switch allows the output of the
DACs to bypass the Phat Stereo 3D enhancement.

Analog-to-Digital Signal Path

The selector sends left and right channel signals to the program­mable gain amplifier (PGA). The PGA following the selector
allows independent gain for each channel entering the ADC
from 0 dB to +22.5 dB in 1.5 dB steps.

Each channel of the ADC is independent, and can process
left and right channel data at different sample rates. All pro­grammed sample rates from 7 kHz to 48 kHz have a resolution
of 1 Hz. The AD1819B also supports irrational V.34 sample
rates.

Sample Rates and D2S

The AD1819B default mode sets the codec to operate at 48 kHz
sample rates. The converter pairs may process left and right
channel data at different sample rates. The AD1819B sample
rate generator allows the codec to instantaneously change and
process sample rates from 7 kHz to 48 kHz with a resolution of
1 Hz. The in-band integrated noise and distortion artifacts in­troduced by rate conversions are below –90 dB. The AD1819B
uses a 4-bit D/A structure and Data Directed Scrambling (D

2

S)
to enhance noise immunity on motherboards and in PC enclo­sures, and to suppress idle tones below the device’s quantization
noise floor. The D

2

S process pushes noise and distortion arti­facts caused by errors in the multibit D/A conversion process to
frequencies beyond the audible range of the human ear and then
filters them.

Digital-to-Analog Signal Path

The analog output of the DAC may be gained or attenuated
from +12 dB to –34.5 dB in 1.5 dB steps, and summed with any
of the analog input signals. The summed analog signal enters
the Master Volume stage where each channel of the mixer out­put may be attenuated from 0 dB to –46.5 dB in 1.5 dB steps or
muted.

Host-Based Echo Cancellation Support

The AD1819B supports time correlated I/O data format by
presenting mic data on the left channel of the ADC and the
mono summation of left and right output on the right channel.
The ADC is splittable; left and right ADC data can be sampled
at different rates.

Telephony Modem Support

The AD1819B contains a V.34-capable analog front end for
supporting host-based and data pump modems. The modem
DAC typical dynamic range is 90 dB over a 4.2 kHz analog
output passband where F

= 12.8 kHz. The left channel of the

S

ADC and DAC may be used to convert modem data at the same
sample rate in the range between 7 kHz and 48 kHz. All pro­grammed sample rates have a resolution of 1 Hz. The AD1819B
supports irrational V.34 sample rates with 8/7 and 10/7 select­able sample rate multiplier coefficients.

Differences Between the AD1819A and AD1819B

The voltage reference (V

) of the AD1819B remains active

REF

while RESET is asserted. This eliminates the audible artifacts
associated with the RESET LO to HI transitions that can
occur during a Windows boot (power-up) or Windows warm
restart (reset).

–2–

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SPECIFICATIONS

STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED

AD1819B

DAC Test Conditions

Temperature 25 °C Calibrated

Digital Supply (V
Analog Supply (V
Sample Rate (F

) 5.0 V 0 dB Attenuation

DD

) 5.0 V Input 0 dB

CC

) 48 kHz 10 kΩ Output Load

S

Input Signal 1008 Hz Mute Off
Analog Output Passband 20 Hz to 20 kHz

(AC-Link) 2.0 V

V

IH

(AC-Link) 0.8 V

V

IL

(CS0, CS1, CHAIN_IN) 4.0 V

V

IH

(CHAIN_CLK) 1.0 V

V

IL

ANALOG INPUT

ADC Test Conditions

Calibrated
0 dB Gain
Input –3 dB Relative to Full Scale
Line Input Selected

Parameter Min Typ Max Units

Input Voltage (RMS Values Assume Sine Wave Input)

LINE_IN, AUX, CD, VIDEO, PHONE_IN, PC_BEEP 1 V rms

2.83 V p-p

MIC1, MIC2 with +20 dB Gain (M20 = 1) 0.1 V rms

0.283 V p-p

MIC1, MIC2 with 0 dB Gain (M20 = 0) 1 V rms

2.83 V p-p

Input Impedance* 10 kΩ

Input Capacitance* 15 pF

PROGRAMMABLE GAIN AMPLIFIER—ADC

Parameter Min Typ Max Units

Step Size (0 dB to 22.5 dB) 1.5 dB
PGA Gain Range Span 22.5 dB

ANALOG MIXER— INPUT GAIN/AMPLIFIERS/ATTENUATORS

Parameter Min Typ Max Units

Dynamic Range (–60 dB Input THD+N, Referenced to Full Scale, A-Weighted)

CD to LINE_OUT 90 dB
Other to LINE_OUT* 90 dB

Step Size (+12 dB to –34.5 dB): (All Steps Tested)

MIC, LINE_IN, AUX, CD, VIDEO, PHONE_IN, DAC 1.5 dB

Input Gain/Attenuation Range

MIC, LINE_IN, AUX, CD, VIDEO, PHONE_IN, DAC 46.5 dB

Step Size␣ (0 dB to –45 dB): (All Steps Tested)

PC_BEEP 3.0 dB

Input Gain/Attenuation Range: PC_BEEP 45 dB

DIGITAL DECIMATION AND INTERPOLATION FILTERS*

Parameter Min Typ Max Units

Passband 0 0.4 × F

Hz

S

Passband Ripple ±0.09 dB
Transition Band 0.4 × F
Stopband 0.6 × F

S

S

0.6 × F

∞

Hz

S

Hz
Stopband Rejection –74 dB
Group Delay 12/F

S

sec

Group Delay Variation Over Passband 0.0 µs

*Guaranteed, not tested.
Specifications subject to change without notice.

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–3–

AD1819B–SPECIFICATIONS

ANALOG-TO-DIGITAL CONVERTERS

Parameter Min Typ Max Units

Resolution 16 Bits
Total Harmonic Distortion (THD) 0.02 %

–74 dB

Dynamic Range (–60 dB Input THD+N Referenced to Full Scale,

A-Weighted) 84 87 dB
Signal-to-Intermodulation Distortion* (CCIF Method) 85 dB
ADC Crosstalk*

Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) –100 –90 dB

Line to Other –90 –85 dB

Gain Error (Full-Scale Span Relative to Nominal Input Voltage) ±10 %
Interchannel Gain Mismatch (Difference of Gain Errors) ±0.5 dB
ADC Offset Error ±5mV

DIGITAL-TO-ANALOG CONVERTERS

Parameter Min Typ Max Units

Resolution 16 Bits
Total Harmonic Distortion (THD) LINE_OUT 0.02 %

–74 dB

Dynamic Range (–60 dB Input THD+N Referenced to Full Scale,

A-Weighted) 85 90 dB
Signal-to-Intermodulation Distortion* (CCIF Method) 85 dB

Gain Error (Full-Scale Span Relative to Nominal Input Voltage) ±10 %
Interchannel Gain Mismatch (Difference of Gain Errors) ±0.5 dB

DAC Crosstalk* (Input L, Zero R, Measure LINE_OUT_R; Input R, dB

Zero L, Measure LINE_OUT_L) –80 dB

Total Out-of-Band Energy (Measured from 0.6 × F

to 20 kHz)* –40 dB

S

MASTER VOLUME

Parameter Min Typ Max Units

Step Size (0 dB to –46.5 dB)

LINE_OUT_L, LINE_OUT_R, MONO_OUT 1.5 dB
Output Attenuation Range Span 46.5 dB
Mute Attenuation of 0 dB Fundamental* 75 dB

ANALOG OUTPUT

Parameter Min Typ Max Units

Full-Scale Output Voltage 1 V rms

2.83 V p-p

Output Impedance* 800 Ω
External Load Impedance 10 kΩ

Output Capacitance* 15 pF
External Load Capacitance 100 pF
V

REF

V

Current Drive 100 µA

REF

V

REFOUT

V

Current Drive 5mA

REFOUT

2.00 2.25 2.50 V

2.25 V

Mute Click (Muted Output Minus Unmuted Midscale DAC Output)* ±5mV

*Guaranteed, not tested.
Specifications subject to change without notice.

–4–

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AD1819B

STATIC DIGITAL SPECIFICATIONS

Parameter Min Typ Max Units

High-Level Input Voltage (V
Low-Level Input Voltage (V
High-Level Output Voltage (V
Low-Level Output Voltage (V

): Digital Inputs 0.4 × DV

IH

) 0.2 × DV

IL

), I

OH

OL

= 2 mA 0.5 × DV

OH

), I

= 2 mA 0.2 × DV

OL

DD

DD

Input Leakage Current –10 10 µA
Output Leakage Current –10 10 µA

POWER SUPPLY

Parameter Min Typ Max Units

Power Supply Range—Analog 4.5 5.5 V
Power Supply Range—Digital 4.5 5.5 V
Power Supply Current 120 mA
Power Dissipation 600 mW
Analog Supply Current 60 mA
Digital Supply Current 60 mA
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*

(At Both Analog and Digital Supply Pins, Both ADCs and DACs) –40 dB

CLOCK SPECIFICATIONS*

Parameter Min Typ Max Units

Input Clock Frequency 24.576 MHz
Recommended Clock Duty Cycle 40 50 60 %

DD

DD

V
V
V
V

POWER-DOWN STATES

Parameter Set Bits Min Typ Max Units

ADCs and Input Mux Power-Down PR0 110 mA
DACs Power-Down PR1 100 mA
Analog Mixer Power-Down (V
Analog Mixer Power-Down (V

REF

REF

and V

and V

On) PR1, PR2 54 mA

REFOUT

Off) PR0, PR1, PR3 47 mA

REFOUT

Digital Interface Power-Down* PR4 120 mA
Internal Clocks Disabled* PR0, PR1, PR4, PR5 85 mA
ADC and DAC Power-Down PR0, PR1 85 mA

Standby Mode* PR0, PR1, PR2, PR4, PR5 55 mA

V

REF

Total Power-Down PR0, PR1, PR2, PR3,

PR4, PR5 220 µA

RESET (Low) 250 µA

*Guaranteed, not tested.
Specifications subject to change without notice.

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–5–

AD1819B

TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)

Parameter Symbol Min Typ Max Units

RESET Active Low Pulsewidth t
RESET Inactive to BIT_CLK Start-Up Delay t

SYNC Active High Pulsewidth t
SYNC Low Pulsewidth t
SYNC Inactive to BIT_CLK Start-Up Delay t

RST_LOW

RST2CLK

SYNC_HIGH

SYNC_LOW

SYNC2CLK

BIT_CLK Frequency 12.288 MHz
BIT_CLK Period t

CLK_PERIOD

BIT_CLK Output Jitter* 750 ps
BIT_CLK High Pulsewidth t
BIT_CLK Low Pulsewidth t

CLK_HIGH

CLK_LOW

SYNC Frequency 48.0 kHz
SYNC Period t
Setup to Falling Edge of BIT_CLK t
Hold from Falling Edge of BIT_CLK t
BIT_CLK Rise Time t
BIT_CLK Fall Time t
SYNC Rise Time t
SYNC Fall Time t
SDATA_IN Rise Time t
SDATA_IN Fall Time t
SDATA_OUT Rise Time t
SDATA_OUT Fall Time t
End of Slot 2 to BIT_CLK, SDATA_IN Low t

SYNC_PERIOD

SETUP

HOLD

RISE CLK

FALL CLK

RISE SYNC

FALL SYNC

RISE DIN

FALL DIN

RISE DOUT

FALL DOUT

S2_PDOWN

Setup to Trailing Edge of RESET (Applies to

SYNC, SDATA_OUT) t

Rising Edge of RESET to HI-Z Delay t

*Output Jitter is directly dependent on crystal input jitter.

SETUP2RST

OFF

1.0 µs

162.8 ns

0.0814 1.3 µs

19.5 µs

162.8 ns

81.4 ns

32.56 40.7 48.84 ns

32.56 40.7 48.84 ns

20.8 µs

15.0 ns

15.0 ns
4ns
4ns
4ns
4ns
4ns
4ns
4ns
4ns

1.0 µs

15 ns

25 ns

RESET

BIT_CLK

SYNC

BIT_CLK

t

RST_LOW

Figure 1. Cold Reset

t

SYNC_HIGH

Figure 2. Warm Reset

BIT_CLK

SYNC

t

CLK_HIGH

Figure 3. Clock Timing

t

CLK_PERIOD

t

SYNC_HIGH

t

SYNC_PERIOD

t

RST2CLK

t

RST2CLK

t

CLK_LOW

t

SYNC_LOW

–6–

REV. 0

BIT_CLK

BIT_CLK

SDATA_OUT

SYNC

SDATA_IN

SLOT 1

SLOT 2

WRITE

TO 0x26

DATA

PR4

DON’T

CARE

t

S2_PDOWN

NOTE: BIT_CLK NOT TO SCALE

RESET

SDATA_OUT

HI-Z

t

SETUP2RST

t

OFF

SDATA_IN, BIT_CLK

WARNING!

ESD SENSITIVE DEVICE

SYNC

SDATA_OUT

t

SETUP

t

HOLD

Figure 4. Data Setup and Hold

AD1819B

BIT_CLK

SYNC

SDATA_IN

SDATA_OUT

t

RISECLK

t

RISESYNC

t

RISEDIN

t

RISEDOUT

t

FALLCLK

t

FALLSYNC

t

FALLDIN

t

FALLDOUT

Figure 5. Signal Rise and Fall Time

ABSOLUTE MAXIMUM RATINGS*

Parameter Min Max Units

Power Supplies
␣ ␣ Analog (AV
␣ ␣ Digital (DV

) –0.3 6.0 V

DD

) –0.3 6.0 V

DD

Input Current (Except Supply Pins) ±10.0 mA

Analog Input Voltage (Signal Pins) –0.3 AV
Digital Input Voltage (Signal Pins) –0.3 DV

+ 0.3 V

DD

+ 0.3 V

DD

Ambient Temperature (Operating) –40 +85 °C
Storage Temperature –65 +150 °C

*Stresses greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Figure 6. AC-Link, Link Low Power Mode Timing

Figure 7. ATE Test Mode

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*

AD1819BJST –40°C to +85°C 48-Terminal LQFP ST-48

*ST = Thin Quad Flatpack.

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating

= T

T

AMB

= Case Temperature in °C

T

CASE

= Power Dissipation in W

P

D

= Thermal Resistance (Case-to-Ambient)

θ

CA

= Thermal Resistance (Junction-to-Ambient)

θ

JA

= Thermal Resistance (Junction-to-Case)

θ

JC

CASE

– (P

D

× θ

CA

)

Package ␪

JA

LQFP 76.2°C/W 17°C/W 59.2°C/W

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1819B features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–7–

␪

JC

␪

CA

AD1819B

PIN CONFIGURATION

48-Terminal LQFP

(ST-48)

DV

DD1

XTL_IN

XTL_OUT

DV

SS1

SDATA_OUT

BIT_CLK

DV

SS2

SDATA_IN

DV

DD2

SYNC

RESET

PC_BEEP

CHAIN_CLK

CHAIN_INNCCS0NCNCNCNC

CS1

48 47 46 45 44 39 38 3743 42 41 40

1

PIN 1

2

IDENTIFIER

3
4
5
6
7
8

9
10
11
12

13 14 15 16 17 18 19 20 21 22 23 24

PHONE_IN

NC = NO CONNECT

AUX_L

AUX_R

AD1819B

TOP VIEW

(Not to Scale)

CD_L

VIDEO_R

VIDEO_L

SS2

AV

CD_GND

CD_R

MIC1

DD2

AV

MIC2

LINE_IN_L

MONO_OUT

LINE_OUT_R

36
35

LINE_OUT_L
CX3D

34
33

RX3D
FILT_L

32
31

FILT_R
AFILT2

30
29

AFILT1

28

V

REFOUT

27

V

REF

AV

26
25

AV

LINE_IN_R

SS1
DD1

PIN FUNCTION DESCRIPTIONS

Digital I/O

Pin Name LQFP I/O Description

XTL_IN 2 I 24.576 MHz Crystal or Clock Input
XTL_OUT 3 O 24.576 MHz Crystal Output
SDATA_OUT 5 I Serial Data Output. Serial, Time Division Multiplexed, AD1819B Input Stream
BIT_CLK 6 O/I* Bit Clock Input, 12.288 MHz Serial Data Clock. Daisy Chain Output Clock
SDATA_IN 8 O Serial Data Input. Serial, Time Division Multiplexed, AD1819B Output Stream
SYNC 10 I 48 kHz Fixed Rate Sample Sync Clock
RESET 11 I Reset. AC-Link Master Hardware Reset

*Input if the AD1819B is configured as Slave 1 or Slave 2.

Daisy Chain Connections

Pin Name LQFP I/O Description

CS0 45 I Daisy Chain Codec Select
CS1 46 I Daisy Chain Codec Select
CHAIN_IN 47 I Daisy Chain Data Input
CHAIN_CLK 48 I/O* 24.576 MHz Buffered Clock Input/Output

*Output when configured as Master. Input when configured as Slave 1 or Slave 2.

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AD1819B

Analog I/O

These signals connect the AD1819B component to analog sources and sinks, including microphones and speakers.

Pin Name LQFP I/O Description

PC_BEEP 12 I PC Beep. PC Speaker Beep Pass-Through
PHONE_IN 13 I Phone. From Telephony Subsystem Speakerphone or Handset
AUX_L 14 I Auxiliary Input Left Channel
AUX_R 15 I Auxiliary Input Right Channel
VIDEO_L 16 I Video Audio Left Channel
VIDEO_R 17 I Video Audio Right Channel
CD_L 18 I CD Audio Left Channel
CD_GND 19 I CD Audio Analog Ground Sense for Differential CD Input
CD_R 20 I CD Audio Right Channel
MIC1 21 I Microphone 1. Desktop Microphone Input
MIC2 22 I Microphone 2. Second Microphone Input
LINE_IN_L 23 I Line In Left Channel
LINE_IN_R 24 I Line In Right Channel
LINE_OUT_L 35 O Line Out Left Channel
LINE_OUT_R 36 O Line Out Right Channel
MONO_OUT 37 O Monaural Output to Telephony Subsystem Speakerphone

Filter/Reference

Pin Name LQFP I/O Description

V

REF

V

REFOUT

AFILT1 29 O Antialiasing Filter Capacitor—ADC Right Channel
AFILT2 30 O Antialiasing Filter Capacitor—ADC Left Channel
FILT_R 31 O AC-Coupling Filter Capacitor—ADC Right Channel
FILT_L 32 O AC-Coupling Filter Capacitor—ADC Left Channel
RX3D 33 O 3D Phat Stereo Enhancement—Capacitor
CX3D 34 I 3D Phat Stereo Enhancement—Capacitor

27 O Voltage Reference Filter
28 O Voltage Reference Output 5 mA Drive (Intended for Mic Bias)

Power and Ground Signals

Pin Name LQFP I/O Description

DV

DD1

DV

SS1

DV

SS2

DV

DD2

AV

DD1

AV

SS1

AV

DD2

AV

SS2

No Connects

1 I Digital VDD—5.0 V
4 I Digital GND
7 I Digital GND
9 I Digital VDD—5.0 V
25 I Analog VDD—5.0 V
26 I Analog GND
38 I Analog VDD—5.0 V
42 I Analog GND

Pin Name LQFP I/O Description

NC 39 No Connect
NC 40 No Connect
NC 41 No Connect
NC 43 No Connect
NC 44 No Connect

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–9–