Analog Devices AD1819 Service Manual

a

CS

AC ’97 SoundPort® Codec

AD1819

AC '97 FEATURES
Fully Compliant AC ’97 Analog I/O Component
48-Terminal TQFP Package
Multibit SD Converter Architecture for Improved

S/N Ratio >90 dB
16-Bit Stereo Full-Duplex Codec
Four Analog Line-Level Stereo Inputs for Connection

from LINE, CD, VIDEO and AUX
Two Analog Line-Level Mono Inputs for Speakerphone

and PC BEEP
Mono MIC Input Switchable from Two External

Sources
High Quality CD Input with Ground Sense
Stereo Line Level Output
Mono Output for Speakerphone
Power Management Support

FUNCTIONAL BLOCK DIAGRAM

AD1819

MIC1
MIC2

LINE_IN

AUX

CD

VIDEO

PHONE_IN

LINE_OUT_L

MONO_OUT

LINE_OUT_R

PC_BEEP

0dB/
20dB

MV

MV

MV

G
A

S

M

S

PHAT

S

STEREO

S

PHAT

S

S

A
M

STEREO

ENHANCED FEATURES
Support for Multiple Codec Communications
DSP 16-Bit Serial Port Format
Variable 7 kHz to 48 kHz Sampling Rate with 1 Hz

Supports Modem Sample Rates and Filtering
Phat™ Stereo 3D Stereo Enhancement

G

G
A
M

S S S

S S S S

G = GAIN
A = ATTENUATE
M = MUTE
MV = MASTER VOLUME

G
A
M

G

A

A

M

M

S

S

Resolution

G
A
M

S

S

PGA

SELECTOR

PGA

G
A
M

G
A
M

1

CS0

MASTER/SLAVE
SYNCHRONIZER

16-BIT
SD A/D

CONVERTER

16-BIT
SD A/D

CONVERTER

SAMPLE

RATE

GENERATORS

16-BIT
SD D/A

CONVERTER

16-BIT

SD D/A

CONVERTER

OSCILLATORS

XTALO

CHAIN_IN

XTALI

CHAIN_CLK

RESET

SYNC

BIT_CLK

AC LINK

SDATA_OUT

SDATA_IN

SoundPort is a registered trademark of Analog Devices, Inc.
Phat is a trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

AD1819

PRODUCT OVERVIEW

The AD1819 SoundPort Codec is designed to meet all require­ments of the Audio Codec ’97, Component Specification, Revision

1.03, © 1996, Intel Corporation, found at www.Intel.com. In
addition, the AD1819 supports multiple codec configurations
(up to three per AC Link), a DSP serial mode, variable sample
rates, modem sample rates and filtering, and built-in Phat Ste­reo 3D enhancement.

The AD1819 is an analog front end for high performance PC
audio, modem, or DSP applications. The AC ’97 architecture
defines a 2-chip audio solution comprising a digital audio con­troller, plus a high quality analog component that includes
Digital-to-Analog Converters (DACs), Analog-to-Digital Con­verters (ADCs) mixer and I/O.

The main architectural features of the AD1819 are the high
quality analog mixer section, two channels of Σ∆ ADC conver­sion, two channels of Σ∆ DAC conversion and Data Direct
Scrambling (D2S) rate generators. The AD1819’s left channel
ADC and DAC are compatible for modem applications sup­porting irrational sample rates and modem filtering require­ments.

FUNCTIONAL DESCRIPTION

This section overviews the functionality of the AD1819 and is
intended as a general introduction to the capabilities of the
device. Detailed reference information may be found in the
descriptions of the Indexed Control Registers.

Analog Inputs

The codec contains a stereo pair of ∑∆ ADCs. Inputs to the
ADC may be selected from the following analog signals: tele­phony (PHONE_IN), mono microphone (MIC1 or MIC2),
stereo line (LINE_IN), auxiliary line input (AUX), stereo CD
ROM (CD), stereo audio from a video source (VIDEO) and
post-mixed stereo or mono line output (LINE_OUT).

Analog Mixing

PHONE_IN, MIC1 or MIC2, LINE_IN, AUX, CD and
VIDEO can be mixed in the analog domain with the stereo
output from the DACs. Each channel of the stereo analog in­puts may be independently gained or attenuated from +12 dB
to –34.5 dB in 1.5 dB steps. The summing path for t he mono
inputs (PHONE_IN, MIC1, and MIC2 to LINE_OUT) dupli­cates mono channel data on both the left and right LINE_OUT.
Additionally, the PC attention signal (PC_BEEP) may be
mixed with the line output. A switch allows the output of the
DACs to bypass the Phat Stereo 3D enhancement.

Analog-to-Digital Signal Path

The selector sends left and right channel information to the
programmable gain amplifier (PGA). The PGA following the
selector allows independent gain for each channel entering the
ADC from 0 dB to +22.5 dB in 1.5 dB steps.

Each channel of the ADC is independent, and can process
left and right channel data at different sample rates. All pro­grammed sample rates from 7 kHz to 48 kHz have a resolution
of 1 Hz. The AD1819 also supports irrational V.34 sample
rates.

Sample Rates and D2S

The AD1819 default mode sets the codec to operate at 48 kHz
sample rates. The converter pairs may process left and right
channel data at different sample rates. The AD1819 sample rate
generator allows the codec to instantaneously change and pro­cess sample rates from 7 kHz to 48 kHz with a resolution of
1 Hz. The in-band integrated noise and distortion artifacts in­troduced by rate conversions are below –90 dB. The AD1819
uses a 4-bit D/A structure and Data Directed Scrambling (D

2

S)
to enhance noise immunity on motherboards and in PC enclo­sures, and to suppress idle tones below the device’s quantization
noise floor. The D

2

S process pushes noise and distortion arti­facts caused by errors in the multibit D/A conversion process to
frequencies beyond the auditory response of the human ear and
then filters them.

Digital-to-Analog Signal Path

The analog output of the DAC may be gained or attenuated
from +12 dB to –34.5 dB in 1.5 dB steps, and summed with any
of the analog input signals. The summed analog signal enters
the Master Volume stage where each channel of the mixer out­put may be attenuated from 0 dB to –46.5 dB in 1.5 dB steps or
muted.

Host-Based Echo Cancellation Support

The AD1819 supports time correlated I/O data format by pre­senting mic data on the left channel of the ADC and the mono
summation of left and right output on the right channel. The
ADC is splittable; left and right ADC data can be sampled at
different rates.

Telephony Modem Support

The AD1819 contains a V.34-capable analog front end for sup­porting host-based and data pump modems. The modem DAC
typical dynamic range is 90 dB over a 4.2 kHz analog output
passband where F

= 12.8 kHz. The left channel of the ADC

S

and DAC may be used to convert modem data at the same
sample rate in the range between 7 kHz and 48 kHz. All pro­grammed sample rates have a resolution of 1 Hz. The AD1819
supports irrational V.34 sample rates with 8/7 and 10/7 select­able multiplier coefficients.

–2–

REV. 0

SPECIFICATIONS

STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED

AD1819

DAC Test Conditions
Temperature 25 °C Calibrated
Digital Supply (V
Analog Supply (V
Sample Rate (F

) 5.0 V 0 dB Attenuation

DD

) 5.0 V Input 0 dB

CC

) 48 kHz 10 kΩ Output Load

S

Input Signal 1008 Hz Mute Off
Analog Output Passband 20 Hz to 20 kHz

(AC Link) 2.0 V

V

IH

(AC Link) 0.8 V

V

IL

(CS0, CS1, CHAIN_IN) 4.0 V

V

IH

(CHAIN_CLK) 1.0 V

V

IL

ANALOG INPUT

ADC Test Conditions

Calibrated
0 dB Gain
Input –3 dB Relative to Full Scale
Line Input Selected

Parameter Min Typ Max Units

Input Voltage (RMS Values Assume Sine Wave Input)

LINE_IN, AUX, CD, VIDEO, PHONE_IN, PC_BEEP 1 V rms

2.83 V p-p

MIC1, MIC2 with +20 dB Gain (M20 = 1) 0.1 V rms

0.283 V p-p

MIC1, MIC2 with 0 dB Gain (M20 = 0) 1 V rms

2.83 V p-p
Input Impedance* 10 kΩ
Input Capacitance* 15 pF

PROGRAMMABLE GAIN AMPLIFIER—ADC

Parameter Min Typ Max Units

Step Size (0 dB to 22.5 dB) 1.5 dB
PGA Gain Range Span 22.5 dB

ANALOG MIXER— INPUT GAIN/AMPLIFIERS/ATTENUATORS

Parameter Min Typ Max Units

Dynamic Range (–60 dB Input THD+N, Referenced to Full Scale, A-Weighted)

CD to LINE_OUT 90 dB
Other to LINE_OUT 90 dB

Step Size (+12 dB to –34.5 dB): (All Steps Tested)

MIC, LINE_IN, AUX, CD, VIDEO, PHONE_IN, DAC 1.5 dB

Input Gain/Attenuation Range

MIC, LINE_IN, AUX, CD, VIDEO, PHONE_IN, DAC 46.5 dB

Step Size (0 dB to –45 dB): (All Steps Tested)

PC_BEEP 3.0 dB

Input Gain/Attenuation Range: PC_BEEP 45 dB

DIGITAL DECIMATION AND INTERPOLATION FILTERS*

Parameter Min Typ Max Units

Passband 0 0.4 × F

Hz

S

Passband Ripple ±0.09 dB
Transition Band 0.4 × F
Stopband 0.6 × F

S
S

0.6 × F
∞ Hz

Hz

S

Stopband Rejection –74 dB
Group Delay 12/F

S

sec

Group Delay Variation Over Passband 0.0 µs

*Guaranteed, not tested.
Specifications subject to change without notice.

REV. 0

–3–

AD1819–SPECIFICA TIONS

ANALOG-TO-DIGITAL CONVERTERS

Parameter Min Typ Max Units

Resolution 16 Bits
Total Harmonic Distortion (THD) 0.02 %

–74 dB

Dynamic Range (–60 dB Input THD+N Referenced to Full Scale,

A-Weighted) 84 87 dB
Signal-to-Intermodulation Distortion* (CCIF Method) 85 dB
ADC Crosstalk*

Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) –100 –90 dB

Line to Other –90 –85 dB
Gain Error (Full-Scale Span Relative to Nominal Input Voltage) ±10 %
Interchannel Gain Mismatch (Difference of Gain Errors) ±0.5 dB
ADC Offset Error ±5mV

DIGITAL-TO-ANALOG CONVERTERS

Parameter Min Typ Max Units

Resolution 16 Bits
Total Harmonic Distortion (THD) LINE_OUT 0.02 %

–74 dB

Dynamic Range (–60 dB Input THD+N Referenced to Full Scale,

A-Weighted) 85 90 dB
Signal-to-Intermodulation Distortion* (CCIF Method) 85 dB
Gain Error (Full-Scale Span Relative to Nominal Input Voltage) ±10 %
Interchannel Gain Mismatch (Difference of Gain Errors) ±0.5 dB
DAC Crosstalk* (Input L, Zero R, Measure LINE_OUT_R; Input R, dB

Zero L, Measure LINE_OUT_L) –80 dB
Total Out-of-Band Energy (Measured from 0.6 × FS to 20 kHz)* –40 dB

MASTER VOLUME

Parameter Min Typ Max Units

Step Size (0 dB to –46.5 dB)

LINE_OUT_L, LINE_OUT_R, MONO_OUT 1.5 dB
Output Attenuation Range Span* 46.5 dB
Mute Attenuation of 0 dB Fundamental* 75 dB

ANALOG OUTPUT

Parameter Min Typ Max Units

Full-Scale Output Voltage 1 V rms

2.83 V p-p
Output Impedance* 800 Ω
External Load Impedance 10 kΩ
Output Capacitance* 15 pF
External Load Capacitance 100 pF
V

REF

Current Drive 100 µA

V

REF

V

REFOUT

V

Current Drive 5mA

REFOUT

2.00 2.25 2.50 V

2.25 V
Mute Click (Muted Output Minus Unmuted Midscale DAC Output) ±5mV

*Guaranteed, not tested.
Specifications subject to change without notice.

–4–

REV. 0

AD1819

STATIC DIGITAL SPECIFICATIONS

Parameter Min Typ Max Units

High-Level Input Voltage (V
Low-Level Input Voltage (V
High-Level Output Voltage (V
Low-Level Output Voltage (V

): Digital Inputs 0.4 × DV

IH

) 0.2 × DV

IL

), IOH = 2 mA 0.5 × DV

OH

), IOL = 2 mA 0.2 × DV

OL

DD

DD

Input Leakage Current –10 10 µA
Output Leakage Current –10 10 µA

POWER SUPPLY

Parameter Min Typ Max Units

Power Supply Range—Analog 4.5 5.5 V
Power Supply Range—Digital 4.5 5.5 V
Power Supply Current 120 mA
Power Dissipation 600 mW
Analog Supply Current 60 mA
Digital Supply Current 60 mA
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*

(At Both Analog and Digital Supply Pins, Both ADCs and DACs) 40 dB

CLOCK SPECIFICATIONS*

Parameter Min Typ Max Units

Input Clock Frequency 24.576 MHz
Recommended Clock Duty Cycle 40 50 60 %

DD

DD

V
V
V
V

POWER-DOWN STATES

Parameter Set Bits Min Typ Max Units

ADCs and Input Mux Power-Down PR0 110 mA
DACs Power-Down PR1 100 mA
Analog Mixer Power-Down (V
Analog Mixer Power-Down (V

REF
REF

and V

and V

On) PR1, PR2 54 mA

REFOUT

Off) PR0, PR1, PR3 47 mA

REFOUT

Digital Interface Power-Down PR4 120 mA
Internal Clocks Disabled PR0, PR1, PR4, PR5 85 mA
ADC and DAC Power-Down PR0, PR1 85 mA

Standby Mode PR0, PR1, PR2, PR4, PR5 55 mA

V

REF

Total Power-Down PR0, PR1, PR2, PR3,

PR4, PR5 220 µA

RESET 250 µA

*Guaranteed, not tested.
Specifications subject to change without notice.

REV. 0

–5–

AD1819

TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)

Parameter Symbol Min Typ Max Units

RESET Active Low Pulse Width t
RESET Inactive to BIT_CLK Start-Up Delay t

SYNC Active High Pulse Width t
SYNC Low Pulse Width t
SYNC Inactive to BIT_CLK Start-Up Delay t

RST_LOW
RST2CLK
SYNC_HIGH
SYNC_LOW
SYNC2CLK

BIT_CLK Frequency 12.288 MHz
BIT_CLK Period t

CLK_PERIOD

BIT_CLK Output Jitter* 750 ps
BIT_CLK High Pulse Width t
BIT_CLK Low Pulse Width t

CLK_HIGH
CLK_LOW

SYNC Frequency 48.0 kHz
SYNC Period t
Setup to Falling Edge of BIT_CLK t
Hold from Falling Edge of BIT_CLK t
BIT_CLK Rise Time t
BIT_CLK Fall Time t
SYNC Rise Time t
SYNC Fall Time t
SDATA_IN Rise Time t
SDATA_IN Fall Time t
SDATA_OUT Rise Time t
SDATA_OUT Fall Time t
End of Slot 2 to BIT_CLK, SDATA_IN Low t

SYNC_PERIOD
SETUP
HOLD
RISE CLK
FALL CLK
RISE SYNC
FALL SYNC
RISE DIN
FALL DIN
RISE DOUT
FALL DOUT
S2_PDOWN

Setup to Trailing Edge of RESET (Applies to

SYNC, SDATA_OUT) t

Rising Edge of RESET to HI-Z Delay t

*Output Jitter is directly dependent on crystal input jitter.

RESET

SETUP2RST
OFF

t

RST_LOW

t

RST2CLK

1.0 µs

162.8 ns

0.0814 1.3 µs

19.5 µs

162.8 ns

81.4 ns

32.56 40.7 48.84 ns

32.56 40.7 48.84 ns

20.8 µs

15.0 ns

15.0 ns
4ns
4ns
4ns
4ns
4ns
4ns
4ns
4ns

1.0 µs

15 ns

25 ns

BIT_CLK

SYNC

BIT_CLK

Figure 1. Cold Reset

t

SYNC_HIGH

Figure 2. Warm Reset

BIT_CLK

SYNC

t

CLK_HIGH

Figure 3. Clock Timing

t

CLK_PERIOD

t

SYNC_HIGH

t

SYNC_PERIOD

t

RST2CLK

t

CLK_LOW

t

SYNC_LOW

–6–

REV. 0

BIT_CLK

BIT_CLK

SDATA_OUT

SYNC

SDATA_IN

SLOT 1

SLOT 2

WRITE

TO 0x20

DATA

PR4

DON'T

CARE

t

S2_PDOWN

NOTE: BIT_CLK NOT TO SCALE

RESET

SDATA_OUT

HI-Z

t

SETUP2RST

t

OFF

SDATA_IN, BIT_CLK

WARNING!

ESD SENSITIVE DEVICE

SYNC

SDATA_OUT

SDATA_IN

SDATA_OUT

t

SETUP

t

HOLD

Figure 4. Data Setup and Hold

BIT_CLK

SYNC

t

RISECLK

t

RISESYNC

t

RISEDIN

t

RISEDOUT

t

FALLCLK

t

FALLSYNC

t

FALLDIN

t

FALLDOUT

Figure 5. Signal Rise and Fall Time

AD1819

Figure 6. AC Link, Link Low Power Mode Timing

Figure 7. ATE Test Mode

ABSOLUTE MAXIMUM RATINGS*

Parameter Min Max Units

Power Supplies

Analog (AV
Digital (DV

) –0.3 6.0 V

DD

) –0.3 6.0 V

DD

Input Current (Except Supply Pins) ±10.0 mA
Analog Input Voltage (Signal Pins) –0.3 AV
Digital Input Voltage (Signal Pins) –0.3 DV

+ 0.3 V

DD

+ 0.3 V

DD

Ambient Temperature (Operating) –40 +85 °C
Storage Temperature –65 +150 °C

*Stresses greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Model Range Description Option*

AD1819JST –40°C to +85°C 48-Terminal TQFP ST-48

*ST = Thin Quad Flatpack.

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating

= T

T
T
P

θ
θ
θ

AMB

CASE
D
CA
JA
JC

CASE

= Case Temperature in °C

= Power Dissipation in W

= Thermal Resistance (Case-to-Ambient)
= Thermal Resistance (Junction-to-Ambient)
= Thermal Resistance (Junction-to-Case)

Package u

ORDERING GUIDE

Temperature Package Package

– (PD × θCA)

JA

TQFP 76.2°C/W 17°C/W 59.2°C/W

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1819 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

u

JC

u

CA

REV. 0

–7–

AD1819

PIN CONFIGURATION

48-Terminal TQFP

(ST-48)

DV

DD1

XTL_IN

XTL_OUT

DV

SS1

SDATA_OUT

BIT_CLK

DV

SS2

SDATA_IN

DV

DD2

SYNC

RESET

PC_BEEP

CHAIN_INNCCS0NCNC

CS1

CHAIN_CLK

48 47 46 45 44 39 38 3743 42 41 40

1

PIN 1

2

IDENTIFIER

3
4

5
6
7
8
9

10
11

12

13 14 15 16 17 18 19 20 21 22 23 24

PHONE_IN

NC = NO CONNECT

AUX_L

AUX_R

AD1819

TOP VIEW

(Not to Scale)

CD_L

VIDEO_L

VIDEO_R

SS2

AV

CD_R

CD_GND

NC

MIC1

DD2

NC

AV

MIC2

LINE_IN_L

MONO_OUT

LINE_OUT_R

36
35

LINE_OUT_L
CX3D

34
33

RX3D
FILT_L

32
31

FILT_R
AFILT2

30
29

AFILT1

28

V

REFOUT

27

V

REF

AV

26
25

AV

LINE_IN_R

SS1
DD1

PIN FUNCTION DESCRIPTION
Digital I/O

Pin Name TQFP I/O Description

XTL_IN 2 I 24.576 MHz Crystal or Clock Input
XTL_OUT 3 O 24.576 MHz Crystal Output
SDATA_OUT 5 I Serial Data Output. Serial, Time Division Multiplexed, AD1819 Input Stream
BIT_CLK 6 O/I* Bit Clock Input, 12.288 MHz Serial Data Clock. Daisy Chain Output Clock
SDATA_IN 8 O Serial Data Input. Serial, Time Division Multiplexed, AD1819 Output Stream
SYNC 10 I 48 kHz Fixed Rate Sample Sync Clock
RESET 11 I Reset. AD1819 Master Hardware Reset

*Input if the AD1819 is configured as Slave 1 or Slave 2.

Daisy Chain Connections

Pin Name TQFP I/O Description

CS0 45 I Daisy Chain Codec Select
CS1 46 I Daisy Chain Codec Select
CHAIN_IN 47 I Daisy Chain Data Input
CHAIN_CLK 48 I/O* 24.576 MHz Buffered Clock Input/Output

*Output when configured as Master. Input when configured as Slave 1 or Slave 2.

–8–

REV. 0

AD1819

Analog I/O

These signals connect the AD1819 component to analog sources and sinks, including microphones and speakers.

Pin Name TQFP I/O Description

PC_BEEP 12 I PC Beep. PC Speaker Beep Pass-Through
PHONE_IN 13 I Phone. From Telephony Subsystem Speakerphone or Handset
AUX_L 14 I Auxiliary Input Left Channel
AUX_R 15 I Auxiliary Input Right Channel
VIDEO_L 16 I Video Audio Left Channel
VIDEO_R 17 I Video Audio Right Channel
CD_L 18 I CD Audio Left Channel
CD_GND 19 I CD Audio Analog Ground Sense for Differential CD Input
CD_R 20 I CD Audio Right Channel
MIC1 21 I Microphone 1. Desktop Microphone Input
MIC2 22 I Microphone 2. Second Microphone Input
LINE_IN_L 23 I Line In Left Channel
LINE_IN_R 24 I Line In Right Channel
LINE_OUT_L 35 O Line Out Left Channel
LINE_OUT_R 36 O Line Out Right Channel
MONO_OUT 37 O Monaural Output to Telephony Subsystem Speakerphone

Filter/Reference

Pin Name TQFP I/O Description

V

REF

V

REFOUT

AFILT1 29 O Antialiasing Filter Capacitor—ADC Channel
AFILT2 30 O Antialiasing Filter Capacitor—ADC Channel
FILT_R 31 O AC-Coupling Filter Capacitor—ADC Left
FILT_L 32 O AC-Coupling Filter Capacitor—ADC Right
RX3D 33 O 3D Phat Stereo Enhancement—Resistor
CX3D 34 I 3D Phat Stereo Enhancement—Capacitor

27 O Voltage Reference Filter
28 O Voltage Reference Output 5 mA Drive (Intended for Mic Bias)

Power and Ground Signals

Pin Name TQFP I/O Description

DV

DD1

DV

SS1

DV

SS2

DV

DD2

AV

DD1

AV

SS1

AV

DD2

AV

SS2

No Connects

1 I Digital VDD—5.0 V
4 I Digital GND
7 I Digital GND
9 I Digital VDD—5.0 V
25 I Analog VDD—5.0 V
26 I Analog GND
38 I Analog VDD—5.0 V
42 I Analog GND

Pin Name TQFP I/O Description

NC 39 No Connect
NC 40 No Connect
NC 41 No Connect
NC 43 No Connect
NC 44 No Connect

REV. 0

–9–

AD1819

MIC1
MIC2

LINE_IN

AUX

VIDEO

PHONE_IN

LINE_OUT_L

MONO_OUT

LINE_OUT_R

0x20

0dB/20dB
M20 0x0E

STEREO MIX (L)

MONO MIX

STEREO MIX (R)

LS/RS (0)

LS (4)
RS (4)

GM 0x1C

LIM

LS (3)

IM

RS (3)
LS (1)

RS (1)
LS (2)

RS (2)

GM 0x1C

LS/RS (7)

RIM

LS (5)

IM
LS/RS (6)
RS (5)

GM 0X1C
LIM
IM

S
E
L
E
C
T
O
R

GM 0X1C
RIM
IM

16-BIT

SD ADC

16-BIT

SD ADC

0X74

RESET

MS

CD

0x1A

SYNC

BIT_CLK

AC LINK

SDATA_OUT

SDATA_IN

M 0x02
MM

M 0x06
MMM

M 0x02
MM

A 0x02
LMV

A 0x06
MMV

A 0x02
RMV

0
1

MIX 0x20

S

GA 0x0C

PHV

M 0x0C
PHM

S

GA 0x0E
MCV

M 0x0E

MCM

3D 0x22

S

DP

S

LLV
RLA

M 0x10

LM

S S

LAV
RAV

M 0x16

AM

GA 0x16

GA 0x10

S

3D 0x22

SS

DP

S

GA 0x12
LCV

RCV

M 0x12

CM

S

GA 0x14
LVV

RVV

M 0x14

VM

S

SR0 0x78

SR1 0x7A

GAM 0x18
LOV

OM

0x20
POP

SS SS

GAM 0x18
ROV

OM

16-BIT

SD DAC

16-BIT

SD DAC

LPBK

0x20

PC_BEEP

GA 0x0A

PCV

M 0x0A

PCM

G = GAIN
A = ATTENUATE
M = MUTE
MV = MASTER VOLUME

Figure 8. Block Diagram Register Map

OSCILLATORS

XTLO XTLI

–10–

REV. 0

AD1819

Indexed Control Registers

geR

emaN51D41D31D21D11D01D9D8D7D6D5D4D3D2D1D0DtluafeD

muN

h00teseRX4ES3ES2ES1ES0ES9DI8DI7DI6DI5DI4DI3DI2DI1DI0DIh0040

h20emuloVretsaMMMX 5VML4VML3VML2VML1VML0VMLXX5VMR4VMR3VMR2VMR1VMR0VMRh0008

h40devreseR XXX X XXXXXXXXXX XX X

h60onoMemuloVretsaMMMM XX X XXXXXX 5VMM4VMM2VMM2VMM1VMM0VMMh0008

h80devreseR XXX X XXXXXXXXXXXX X

hA0emuloVpeeBCPMCP XX X XXXXXXX 3VCP2VCP1VCP0VCPX h0008

hC0emuloVenohPMHP XX X XXXXXXX 4VHP3VHP2VHP1VHP0VHPh8008

hE0emuloVciMMCM XX X XXXXX 02MX 4VCM3VCM2VCM1VCM0VCMh8008

h01emuloVNI_ENILMLXX 4VLL3VLL2VLL1VLL0VLLXXX4VLR3VLR2VLR1VLR0VLRh8088

Line In Volume

h21emuloVDCMVCXX 4VCL3VCL2VCL1VCL0VCLXXX4VCR3VCR2VCR1VCR0VCRh8088

h41emuloVoediVMVXX 4VVL3VVL2VVL1VVL0VVLXXX4VVR3VVR2VVR1VVR0VVRh8088

h61emuloVxuAMAXX 4VAL3VAL2VAL1VAL0VALXXX4VAR3VAR2VAR1VAR0VARh8088

h81loVtuOMCPMOXX 4VOL3VOL2VOL1VOL0VOLXXX4VOR3VOR2VOR1VOR0VORh8088

hA1tceleSdroceR XXX X X 2SL1SL0SL XXXXX 2SR1SR0SRh0000

hC1niaGdroceRMIXXX 3MIL2MIL1MIL0MIL XXXX 3MIR2MIR1MIR0MIRh0008

hE1devreseR XXX X XXXXXXXXXX XX X

h02esopruPlareneGPOPXD3XXXXIMSMKBPL XXXXXXX h0000

h22lortnoCD3 XXX X XXXXXXXX 3PD2PD1PD0PDh0000

h42devreseR XXX X XXXXXXXXXXXX X

h62tatS/rtnoCnwoD-rewoPXX5RP4RP3RP2RP1RP0RP XXXX FERLNACADCDAh0000

h82devreseR XXX X XXXXXXXXXX XX X

h27devreseR XXX X XXXXXXXXXX XX X

TOLS

MGER

MGER

MGER

EQRD

QRLD

QRLD

h47noitarugifnoClaireS

h67stiBlortnoCcsiMZCADXXXXRSLDXRSLA

h870etaRelpmaS510RS410RS310RS210RS110RS010RS90RS80RS70RS60RS50RS40RS30RS20RS10RS00RSh08BB

hA71etaRelpmaS511RS411RS311RS211RS111RS011RS91RS81RS71RS61RS51RS41RS31RS21RS11RS01RSh08BB

hC71DIrodneV7F6F5F4F3F2F1F0F7S6S5S4S3S2S1S0Sh4414

hE72DIrodneV7T6T5T4T3T2T1T0T7VER6VER5VER4VER3VER2VER1VER0VERhxx35

61

2

1

0

N

2

1

QRLD

XXXXX

0

DOM

1XRS

7D0

8XRS

7D

NE

XX RSRDXRSRAh0000

QRRD

2

QRRD

1

QRRD

0

NOTES

1. All registers not shown and bits containing an X are reserved.

2. Odd register addresses are aliased to the next lower even address.

3. Reserved registers should not be written.

4. Zeros should be written to reserved bits.

h0007

REV. 0

–11–

AD1819

Reset (Index 00h)

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Note: Writing any value to this register performs a register reset, which cause all registers to revert to their default values (except
74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo
Enhancement.

ID [9:0] Identify Capability. The ID decodes the capabilities of AD1819 on the following:

Bit Function AD1819*

ID0 Dedicated Mic PCM in Channel 0
ID1 Modem Line Codec Support 0
ID2 Bass and Treble Control 0
ID3 Simulated Stereo (Mono to Stereo) 0
ID4 Headphone Out Support 0
ID5 Loudness (Bass Boost) Support 0
ID6 18-Bit DAC Resolution 0
ID7 20-Bit DAC Resolution 0
ID8 18-Bit ADC Resolution 0
ID9 20-Bit ADC Resolution 0

*The AD1819 contains none of the optional features identified by these bits.

SE [4:0] Stereo Enhancement. The 3D stereo enhancement identifies the Analog Devices 3D Phat Stereo enhancement

(00001)

Master Volume (Index 02h)

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RMV [4:0] Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from

0 dB to a maximum attenuation of –46.5 dB.
RMV5 Right Master Volume Maximum Attenuation. Forces RMV [4:0] to all “1s,” –46.5 dB.
LMV [4:0] Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from

0 dB to a maximum attenuation of –46.5 dB.
LMV5 Left Master Volume Maximum Attenuation. Forces LMV [4:0] to all “1s,” –46.5 dB.
MM Master Volume Mute. When this bit is set to “1,” the left and right channels are muted.

MM xMV5 . . . xMV0 Function

0 00 0000 0 dB Attenuation

0 01 1111 –46.5 dB Attenuation

0 1x xxxx –46.5 dB Attenuation

1 xx xxxx ∞ dB Attenuation

Master Volume Mono (Index 06h)

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MMV [4:0] Mono Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from

0 dB to a maximum attenuation of –46.5 dB.
MMV5 Mono Master Volume Maximum Attenuation –46.5 dB.
MMM Mono Master Volume Mute. When this bit is set to “1,” the channel is muted.

–12–

REV. 0

AD1819

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geR

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MMM MMV5 . . . MMV0 Function

0 00 0000 0 dB Attenuation
0 01 1111 –46.5 dB Attenuation
0 1x xxxx –46.5 dB Attenuation
1 xx xxxx ∞ dB Attenuation

PC Beep (Index 0Ah)

PCV [3:0] PC Beep Volume Control. The least significant bit represents 3 dB attenuation. This register controls the output

from 0 dB to a maximum attenuation of –45 dB. The PC Beep is routed to the Left and Right Line outputs even
when AD1819 is in a RESET State. This is so that Power-On Self Test (POST) codes can be heard by the user in
case of a hardware problem with the PC.

PCM PC Beep Mute. When this bit is set to “1,” the channel is muted.

PCM PCV3 . . . PCV0 Function

0 0000 0 dB Attenuation
0 1111 –45 dB Attenuation
1 xxxx –∞ dB Attenuation

Phone Volume (Index 0Ch)

PHV [4:0] Phone Volume. Allows setting the Phone Volume Attenuator in 32 steps. The LSB represents 1.5 dB, and the

range is +12 dB to –34 dB. The default value is 0 dB, mute enabled.

PHM Phone Mute. When this bit is set to “1,” the channel is muted.

Mic Volume (Index 0Eh)

MCV [4:0] Mic Volume Gain. Allows setting the Mic Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the

range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
M20 Microphone +20 dB Gain Block

0 = Disabled; Gain = 0 dB.
1 = Enabled; Gain = +20 dB.

MCM Mic Mute. When this bit is set to “1,” the channel is muted.

Line In Volume (Index 10h)

RLV [4:0] Right Line In Volume. Allows setting the Line In right channel attenuator in 32 steps. The LSB represents

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

LLV [4:0] Left Line In Volume. Allows setting the Line In left channel attenuator in 32 steps. The LSB represents

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

LM Line In Mute. When this bit is set to “1,” the channel is muted.

REV. 0

–13–

AD1819

CD Volume (Index 12h)

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RCV [4:0] Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents

LCV [4:0] Left CD Volume. Allows setting the CD left channel attenuator in 32 steps. The LSB represents

CVM CD Volume Mute. When this bit is set to “1,” the channel is muted.

Video Volume (Index 14h)

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RVV [4:0] Right Video Volume. Allows setting the Video right channel attenuator in 32 steps. The LSB represents

LVV [4:0] Left Video Volume. Allows setting the Video left channel attenuator in 32 steps. The LSB represents

VM Video Mute. When this bit is set to “1,” the channel is muted.

Aux Volume (Index 16h)

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1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

emaN51D41D31D21D11D01D9D8D7D6D5D4D3D2D1D0DtluafeD

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

emaN51D41D31D21D11D01D9D8D7D6D5D4D3D2D1D0DtluafeD

RAV [4:0] Right Aux Volume. Allows setting the Aux right channel attenuator in 32 steps. The LSB represents

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

LAV [4:0] Left Aux Volume. Allows setting the Aux left channel attenuator in 32 steps. The LSB represents

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

AM Aux Mute. When this bit is set to “1,” the channel is muted.

PCM Out Volume (Index 18h)

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ROV [4:0] Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 steps. The LSB represents

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

LOV [4:0] Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 steps. The LSB represents

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

OM PCM Out Volume Mute. When this bit is set to “1,” the channel is muted.

Volume Table (Index 0Ch to 18h)

Mute x4 . . . x0 Function

0 00000 +12 dB Gain
0 01000 0 dB Gain
0 11111 –34.5 dB Gain
1 xxxxx –∞ dB Gain

–14–

REV. 0

Record Select Control (Index 1Ah)

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RS [2:0] Right Record Select.
LS [2:0] Left Record Select.

Used to select the record source independently for right and left. See table for legend.
The default value is 0000h, which corresponds to Mic in.

AD1819

RS2 . . . RS0 Right Record Source

0 MIC
1 CD_R
2 VIDEO_R
3 AUX_R
4 LINE_IN_R
5 Stereo Mix (R)
6 Mono Mix
7 PHONE_IN

LS2 . . . LS0 Left Record Source

0 MIC
1 CD_L
2 VIDEO_L
3 AUX_L
4 LINE_IN_L
5 Stereo Mix (L)
6 Mono Mix
7 PHONE_IN

Record Gain (Index 1Ch)

RIM [3:0] Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB.
LIM [3:0] Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB.
IM Input Mute. 0 = Unmuted, 1 = Muted or –∞ dB gain.

IM xIM3 . . . xIM0 Function

0 1111 +22.5 dB Gain
0 0000 0 dB Gain
1 xxxxx –∞ dB Gain

General Purpose (Index 20h)

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LPBK Loopback Control. ADC/DAC digital loopback mode.
MS MIC Select.

0 = MIC1.
1 = MIC2.

REV. 0

–15–

AD1819

MIX Mono Output Select.

0 = Mix.

1 = Mic.
3D Phat Stereo Enhancement.

0 = Phat Stereo is off.

1 = Phat Stereo is on.
POP PCM Output Path. The POP bit controls the optional PCM out 3D bypass path (the pre- and post-

3D PCM outpaths are mutually exclusive).

0 = Pre-3D.

1 = Post-3D.

The register should be read before writing to generate a mask for only the bit(s) that need to be changed. The

default value is 0000h.

3D Control (Index 22h)

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DP [2:0] Depth Control. Sets 3D “Depth” Phat Stereo enhancement according to table below.

DP3 . . . DP0 Depth

00%
1 6.67%

14 93.33%
15 100%

Power-Down Control/Status (Index 26h)

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Ready Bits: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indi-

cate the status for the AD1819 subsections. If the bit is a one then that subsection is “ready.” Ready is defined as

the subsection able to perform in its nominal state.
ADC ADC section ready to transmit data.
DAC DAC section ready to accept data.
ANL Analog gainuators, attenuators, and mixers ready.
REF Voltage References, V

REF

and V

up to nominal level.

REFOUT

PR [5:0] Power-Down Bits. The first three bits are to be used individually rather than in combination with each other. The

last bit PR3 can be used in combination with PR2 or by itself.

Power-Down State Set Bits

ADCs and Input Mux Power-Down PR0
DACs Power-Down PR1
Analog Mixer Power-Down (V
Analog Mixer Power-Down (V

REF
REF

and V

and V

On) PR1, PR2

REFOUT

Off) PR0, PR1, PR3

REFOUT

AC-Link Interface Power-Down PR4
Internal Clocks Disabled PR0, PR1, PR4, PR5
ADC and DAC Power-Down PR0, PR1

Standby Mode PR0, PR1, PR2, PR4, PR5

V

REF

Total Power-Down PR0, PR1, PR2, PR3, PR4, PR5

–16–

REV. 0

AD1819

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TOLS

61

MGER

2

MGER

1

MGER

0

EQRD

N

QRLD

2

QRLD

1

QRLD

0

XXXXX

QRRD

2

QRRD

1

QRRD

0

h0007

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Serial Configuration (Index 74h)

DRRQ0 Master AC ’97 Codec DAC Right Request.
DRRQ1 Slave 1 Codec DAC Right Request.
DRRQ2 Slave 2 Codec DAC Right Request.
DLRQ0 Master AC ’97 Codec DAC Left Request.
DLRQ1 Slave 1 Codec DAC Left Request.
DLRQ2 Slave 2 Codec DAC Left Request.
DRQEN Fills idle status slots with DAC request reads, and stuffs DAC requests into LSB of output address slot. (AC Link

Slot 1.)
REGM0 Master Codec Register Mask.
REGM1 Slave 1 Codec Register Mask.
REGM2 Slave 2 Codec Register Mask.
SLOT16 Enable 16-Bit Slots.

If your system uses only a single AD1819, you can ignore the register mask and the slave 1/slave 2 request bits. If

you write to this register, write ones to all of the register mask bits. The DxRQx bits are read-only.

The codec asserts the DxRQx bit when the corresponding DAC channel can accept data in the next frame. These

bits are snapshots of the codec state taken when the current frame began (effectively, on the rising edge of SYNC),

but they also take notice of DAC samples sent in the current frame.

If you set the DRQEN bit, the AD1819 will fill all otherwise unused AC Link status address and data slots with

the contents of register 74h. That makes it somewhat simpler to access the information, because you don’t need to

continually issue AC Link read commands to get the register contents.

Also, the DAC requests are reflected in Slot 1, Bits (11 . . . 6). These bits are active Low.

SLOT16 makes all AC Link slots 16 bits in length, formatted into 16 slots.

Miscellaneous Control Bits (Index 76h)

ARSR ADC Right Sample Generator Select. Connects right ADC channel to SR0 or SR1.

0 = SR0 Selected.

1 = SR1 Selected.
DRSR DAC Right Sample Generator Select. Connects right DAC channel to SR0 or SR1.

0 = SR0 Selected.

1 = SR1 Selected.
SRX8D7 Multiply SR1 Rate by 8/7.
SRX10D7 Multiply SR1 Rate by 10/7. SRX10D7 and SRX8D7 are mutually exclusive; SRX10D7 has priority if both are set.
MODEN Modem Filter Enable (left channel only). Change only when DACs are inactive.
ALSR ADC Left Sample Generator Select. Connects left ADC channel to SR0 or SR1.

0 = SR0 Selected.

1 = SR1 Selected.
DLSR DAC Left Sample Generator Select. Connects left DAC channel to SR0 or SR1.

0 = SR0 Selected.

1 = SR1 Selected.
DACZ Zero-Fill (vs. repeat sample) if DAC is starved.

REV. 0

–17–

AD1819

Sample Rate 0 (Index 78h)

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SR0 [15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)

in 1 Hz increments. The resultant sample rate value may be multiplied by 8/7 and 10/7 (SRX8D7 and SRX10D7
in register 0x76h). Programming a value greater than 48 kHz or less than 7kHz may cause unpredictable results.

Sample Rate 1 (Index 7Ah)

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SR1 [15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)

in 1 Hz increments. The sample rate may be multiplied by 8/7 or 10/7 by setting Bits D6 and D5 in Register 76h.

Vendor ID (Index 7Ch–7Eh)

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S [7:0] This register is ASCII encoded to “A.”
F [7:0] This register is ASCII encoded to “D.”

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T [7:0] This register is ASCII encoded to “S.”
REV [7:0] Revision Register field contains the revision number.

These bits are read-only and should be verified before accessing vendor-defined features.

DIGITAL INTERFACE
AD1819 AC Link Digital Serial Interface Protocol

The AD1819 incorporates an AC ’97 5-pin digital serial interface that links it to a digital controller. AC Link is a bidirectional, fixed
rate, serial PCM digital stream. It handles multiple input, and output audio streams, as well as control register accesses employing a
time division multiplexed (TDM) scheme. The AC Link architecture divides each audio frame into 12 outgoing and 12 incoming
data streams, up to 20-bit sample resolution. The AD1819 uses 16-bit samples. The data streams include:

AC ’97 Protocol

• TAG 1 Input and Output

• Control 2 Output Slots

Control Register Write Port

• Status 2 Input Slots

Control Register Read Port

• PCM Playback 2 Output Slots

2-Channel Composite PCM Output Stream

• PCM Record Data 2 Input Slots

2-Channel Composite PCM Input Stream

Synchronization of all AC Link data transactions is signaled by the AC ’97 controller. The AD1819 drives the serial bit clock onto
AC Link, which the AC ’97 controller then qualifies with a synchronization signal to construct audio frames.

SYNC, which is fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK) by 256. The BIT_CLK is fixed at

12.288 MHz. AC Link serial data is updated on each rising edge of BIT_CLK. The receiver of AC Link data, the AD1819 for outgoing
data and the AC ’97 controller for incoming data, samples each serial bit on the falling edge of BIT_CLK. SYNC may remain high
for a minimum of 1 BIT_CLK up to a maximum duration of 16 BIT_CLKs at the beginning of each audio frame. The first 16 bits of
the audio frame is defined as the “Tag Phase.” The remainder of the audio frame is the “Data Phase.” The AD1819 uses SYNC to
define the beginning of the audio frame.

–18–

REV. 0

AD1819

The AC Link protocol provides for a special 16-bit time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time
slot within the current audio frame. A “1” in a given bit position of Slot 0 indicates that the corresponding time slot within the cur­rent audio frame has been assigned to a data stream, and contains valid data. If a slot is “tagged” invalid, it is the responsibility of the
source of the data, (AD1819 for the input stream, AC ’97 controller for the output stream), to stuff all bit positions with 0s during
that slot’s active time. The AD1819 stuffs all invalid slots with zeros and ignores invalid input slots.

Additionally, for power savings, all clock sync and data signals can be halted.
For multiple codec operations, the AD1819 supports an enhanced mode for communicating with up to two additional codecs. The

Slave 1 AD1819 codec uses Slots 5 and 6, while Slave 2 uses Slots 7 and 8 as shown in the following diagram.

ENHANCED MODE

SLOT # ....

SYNC

OUTGOING STREAMS

INCOMING STREAMS

PHASE

AC Link Audio Output Frame (SDATA_OUT)

The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting AD1819’s DAC
inputs and control registers. As briefly mentioned earlier, each audio output frame supports up to twelve 20-bit outgoing data time
slots. Slot 0 is a special reserved time slot containing 16 bits that are used for AC Link protocol infrastructure.

Within Slot 0 the first bit is a global bit (SDATA_OUT Slot 0, Bit 15), which flags the validity for the entire audio frame. If the
“Valid Frame” bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. The next 12-bit
positions sampled by AC ’97 indicate which of the corresponding 12 time slots contain valid data. In this way input DAC data
streams of differing sample rates can be transmitted across AC Link at its fixed 48 kHz audio frame rate. The following diagram
illustrates the time-slot-based AC Link protocol.

123456789101112

CMD

CMD

PCM

TAG RSRVD

ADR

DATA

STATUS

STATUS

TAG RSRVD RSRVD

TAG

ADR

DATA

LEFT

PCM

LEFT

PCM

RIGHT

PCM

RIGHT

PCM

LEFT

PCM

LEFT

SLAVE 1

PCM

RIGHT

PCM

RIGHT

DATA PHASE

PCM

LEFT

PCM

LEFT

SLAVE 2

PCM

RIGHT

PCM

RIGHT

RSRVD

Figure 9. Standard Bidirectional Audio Frame

RSRVD

RSRVD

RSRVD

RSRVD

SYNC

BIT_CLK

SDATA_IN

END OF PREVIOUS

AUDIO FRAME

TAG PHASE

12.2888MHz

CODEC
READY

81.4ns

SLOT(1) SLOT(2)

(1) = TIME SLOT CONTAINS VALID PCM DATA

SLOT(12)

TIME SLOT "VALID"

BITS

20.8ms (48kHz)

"0" "0" "0" 19 0 1900019 19

SLOT 1 SLOT 2 SLOT 3 SLOT 12

DATA PHASE

Figure 10. AC Link Audio Output Frame

A new audio output frame begins with a low-to-high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On
the immediately following falling edge of BIT_CLK, the AD1819 samples the assertion of SYNC. This falling edge marks the time
when both sides of AC Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC ’97 controller tran­sitions SDATA_OUT into the first bit position of Slot 0 (Valid Frame Bit). Each new bit position is presented to AC Link on a rising
edge of BIT_CLK, and subsequently sampled by AD1819 on the following falling edge of BIT_CLK. This sequence ensures that
data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.

REV. 0

–19–

AD1819

AD1819 SAMPLES SYNC ASSERTION HERE

SYNC

BIT_CLK

SDATA_OUT

END OF PREVIOUS

AUDIO FRAME

Figure 11. Start of an Audio Output Frame

SDATA_OUT’s composite stream is MSB justified (MSB first) with all nonvalid slots’ bit positions stuffed with 0s by the
AC ’97 controller. The AD1819 ignores invalid slots.

In the event that there are less than 20 valid bits within an assigned and valid time slot, the AC ’97 controller always stuffs all trailing
nonvalid bit positions of the 20-bit slot with 0s. The AD1819 ignores unused bits.

As an example, consider an 8-bit sample stream being played out to one of AD1819’s DACs. The first 8-bit positions are presented
to the DAC (MSB justified), followed by the next 12 bit positions, which are stuffed with 0s by the AC ’97 controller.

When mono audio sample streams are output from the AC ’97 controller, it is necessary that BOTH left and right stream time slots
be filled with the same data.

Slot 1: Command Address Port

The command port is used to control features and request status (see Audio Input Frame Slots l and 2) for AD1819 functions in­cluding, but not limited to, mixer settings and power management (refer to the control register section of this specification).

The control interface architecture supports up to sixty-four 16-bit read/write registers, addressable on even byte boundaries. Only the
even registers (00h, 02h, etc.) are valid, odd register (01h, 03h, etc.) accesses are discouraged (defaulting to the preceding even byte
boundary—i.e., a read to 01h will return the 16-bit contents of 00h). Note that shadowing of the control register file on the AC ’97
controller is an option left open to the implementation of the AC ’97 controller. The AD1819’s control register file is readable as
well as writable. Odd register addresses are mapped to the preceding even register address.

Audio output frame Slot 1 communicates control register address, and write/read command information to AD1819.

Command Address Port Bit Assignments:

Bit (19) Read/Write Command (1 = Read, 0 = Write)
Bit (18:12) Control Register Index (64 16-Bit Locations, Addressed On Even Byte Boundaries)
Bit (11:0) Reserved (Stuffed with 0s)
The first bit (MSB) sampled by the AD1819 indicates whether the current control transaction is a read or a write operation. The

following 7-bit positions communicate the targeted control register address. The trailing 12-bit positions within the slot are reserved.

Slot 2: Command Data Port

The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a
write cycle (as indicated by Slot 1, Bit 19).

Bit (19:4) Control Register Write Data (Stuffed with 0s If Current Operation Is Not a Write)
Bit (3:0) Reserved (Stuffed with 0s)
If the current command port operation is not a write, the entire slot time should be stuffed with 0s by the AC ’97 controller.

Slot 3: PCM Playback Left Channel

Audio output frame Slot 3 is the composite digital audio left playback stream. In a typical “Games Compatible” PC this slot is com­posed of standard PCM (.wav) output samples digitally mixed (on the AC ’97 controller or host processor) with music synthesis
output samples. If a sample stream of resolution less than 20 bits is transferred, the AC ’97 controller should stuff all trailing
nonvalid bit positions within this time slot with 0s.

Slot 4: PCM Playback Right Channel

Audio output frame Slot 4 is the composite digital audio right playback stream. In a typical “Games Compatible” PC this slot is
composed of standard PCM (.wav) output samples digitally mixed (on the AC ’97 controller or host processor) with music synthesis
output samples. If a sample stream of resolution less than 20 bits is transferred, the AC ’97 controller should stuff all trailing nonvalid bit
positions within this time slot with 0s.

AC '97 CONTROLLER SAMPLES
FIRST SDATA_OUT BIT OF FRAME HERE

VALID

SLOT (1) SLOT (2)

FRAME

–20–

REV. 0

AD1819

Slot 5–Slot 8: Multicodec Communication

• Slot 5 Slave 1 PCM Playback Left Channel

• Slot 6 Slave 1 PCM Playback Right Channel

• Slot 7 Slave 2 PCM Playback Left Channel

• Slot 8 Slave 2 PCM Playback Right Channel

Slot 6–Slot 12: Reserved

Audio output frame Slot 6 to Slot 12 are reserved for future use and should always be stuffed with 0s by the digital controller.

AC Link Audio Input Frame (SDATA_IN)

The audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AC ’97 controller.
As is the case for audio output frame, each AC Link audio input frame consists of twelve 20-bit time slots. Slot 0 is a special reserved
time slot containing 16 bits used for AC Link protocol infrastructure.

Within Slot 0 the first bit is a global bit (SDATA_IN Slot 0, Bit 15) which flags whether or not AD1819 is in the “Codec Ready”
state. If the “Codec Ready” bit is a 0, this indicates that AD1819 is not ready for normal operation. This condition is normal follow­ing the deassertion of power-on reset, for example, while AD1819’s voltage references settle. When the AC Link “Codec Ready”
indicator bit is a 1, it indicates that the AC Link and AD1819 control and status registers are in a fully operational state and all sub­sections are ready.

Prior to any attempts at putting AD1819 into operation the AC ’97 controller should poll the first bit in the audio input frame
(SDATA_IN Slot 0, Bit 15) for an indication that the AD1819 has asserted “Codec Ready.” Once the AD1819 is sampled, “Codec
Ready” is asserted the next 12-bit positions sampled by the AC ’97 controller indicate which of the corresponding 12 time slots are
assigned to input data streams and that they contain valid data. The following diagram illustrates the time-slot-based AC Link protocol.

SYNC

BIT_CLK

SDATA_IN

END OF PREVIOUS

AUDIO FRAME

TAG PHASE

CODEC

READY

12.288MHz

81.4ns

SLOT(1) SLOT(2)

(1) = TIME SLOT CONTAINS VALID PCM DATA

SLOT(12)

TIME SLOT "VALID"

BITS

20.8ms (48kHz)

"0" "0" "0" 19 0 1900019 19

SLOT 1 SLOT 2 SLOT 3 SLOT 12

DATA PHASE

Figure 12. AC Link Audio Input Frame

A new audio input frame begins with a low-to-high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On
the immediately following falling edge of BIT_CLK, AD1819 samples the assertion of SYNC. This falling edge marks the time when
both sides of AC Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, AD1819 transitions SDATA_IN
into the first bit position of Slot 0 (“Codec Ready” bit). Each new bit position is presented to AC Link on a rising edge of BIT_CLK, and
subsequently sampled by the AC ’97 controller on the following falling edge of BIT_CLK. This sequence ensures that data transi­tions, and subsequent sample points for both incoming and outgoing data streams, are time aligned.

AD1819 SAMPLES SYNC ASSERTION HERE

SYNC

BIT_CLK

SDATA_IN

AC '97 CONTROLLER SAMPLES
FIRST SDATA_IN BIT OF FRAME HERE

CODEC

SLOT (1) SLOT (2)

READY

END OF PREVIOUS

AUDIO FRAME

Figure 13. Start of an Audio Input Frame

SDATA_IN’s composite stream is MSB justified (MSB first) with all nonvalid bit positions (for assigned and/or unassigned time
slots) stuffed with 0s by AD1819. (SDATA_IN data should be sampled on the falling edges of BIT_CLK.)

Slot 0: Tag Phase SDATA_IN

The AD1819 is capable of sampling data from 7 kHz to 48 kHz with a resolution of 1 kHz. To enable a sample rate other than the
default 48 kHz, set the DRQEN bit (Register 74h Bit 11). This allows DAC request bits to be output on the SDATA_IN stream.
The digital controller should monitor the ADC valid bits to determine when the codec has valid data ready to send (these are low
active).

REV. 0

–21–

AD1819

TAG Phase Bit Assignments:

Bit (15) Codec Ready
Bit (14) Slot 1 Valid
Bit (13) Slot 2 Valid
Bit (12) Slot 3 Valid/ADC Left Data Is Valid on Slot 3
Bit (11) Slot 4 Valid/ADC Right Data Is Valid on Slot 4
Bit (10) Slot 5 Valid/ADC Left Data Slave 1 Valid on Slot 5
Bit (9) Slot 6 Valid/ADC Right Data Slave 1 Valid on Slot 6
Bit (8) Slot 7 Valid/ADC Left Data Slave 2 Valid on Slot 7
Bit (7) Slot 8 Valid/ADC Right Data Slave 2 Valid on Slot 8
Bit (6:0) Not Used

Slot 1: Status Address Port

The status port is used to monitor status for AD1819 functions including, but not limited to, mixer settings and power management.
Audio input frame Slot 1’s stream echoes the control register index, for historical reference, for the data to be returned in Slot 2

(assuming that Slots 1 and 2 had been tagged “valid” by AD1819 during Slot 0).

Status Address Port Bit Assignments:

Bit (19) RESERVED (Stuffed with 0)
Bit (18:12) Control Register Index (Echo of Register Index for Which Data Is Being Returned)
Bit (11) DAC Request Slot 3 (0 = Request, 1 = No Request)
Bit (10) DAC Request Slot 4 (0 = Request, 1 = No Request)
Bit (9) DAC Request Slot 5 (0 = Request, 1 = No Request); Slave 1
Bit (8) DAC Request Slot 6 (0 = Request, 1 = No Request); Slave 1
Bit (7) DAC Request Slot 7 (0 = Request, 1 = No Request); Slave 2
Bit (6) DAC Request Slot 8 (0 = Request, 1 = No Request); Slave 2
Bit (5:0) RESERVED (Stuffed with 0s)

The first bit (MSB) generated by AD1819 is always stuffed with a 0. The following 7-bit positions communicate the associated con­trol register address, and the trailing 12-bit positions are stuffed with 0s by AD1819.

Slot 2: Status Data Port

The status data port delivers 16-bit control register read data.
Bit (19:4) Control Register Read Data (Stuffed with 0s If Tagged “Invalid” by AD1819)
Bit (3:0) RESERVED (Stuffed with 0s)
If Slot 2 is tagged “invalid” by AD1819, the entire slot will be stuffed with 0s by AD1819.

Slot 3: PCM Record Left Channel

Audio input frame Slot 3 is the left channel output of AD1819’s input MUX, post-ADC.
AD1819 ships out its ADC output data (MSB first), and stuffs the trailing nonvalid bit positions with 0s to fill out its 20-bit time slot.

Slot 4: PCM Record Right Channel

Audio input frame Slot 4 is the right channel output of AD1819’s input MUX, post-ADC.
AD1819 ships out its ADC output data (MSB first), and stuffs the trailing nonvalid bit positions with 0s to fill out its 20-bit time slot.

Slot 5–Slot 8: Multicodec Communication

• Slot 5 Slave 1 PCM Record Left Channel

• Slot 6 Slave 1 PCM Record Right Channel

• Slot 7 Slave 2 PCM Record Left Channel

• Slot 8 Slave 2 PCM Record Right Channel

Slot 9–Slot 12: Reserved

Audio input frame Slots 9–12 are reserved for future use and are always stuffed with 0s by AD1819.

AC Link Low Power Mode

The AC Link signals can be placed in a low power mode. When AD1819’s Power-Down Register (26h) is programmed to the
appropriate value, both BIT_CLK and SDATA_IN will be brought to a logic low voltage level.

–22–

REV. 0

SYNC

BIT_CLK

AD1819

SDATA_OUT

SDATA_IN

SLOT 12

PREVIOUS

FRAME

SLOT 12

PREVIOUS

FRAME

NOTE:
BIT_CLK NOT TO SCALE

TAG

TAG

WRITE TO

0x26

DATA

PR4

Figure 14. AC Link Power-Down Timing

BIT_CLK and SDATA_IN are transitioned low immediately1 following the decode of the write to the Power-Down Register (26h)
with PR4. When the AC ’97 controller driver is at the point where it is ready to program the AC Link into its low power mode, Slots
(1 and 2) must be the only valid stream in the audio output frame

2

.
The AC ’97 controller should also drive SYNC and SDATA_OUT low after programming AD1819 to this low power “halted” mode.
Once AD1819 has been instructed to halt BIT_CLK, a special “wake-up” protocol must be used to bring the AC Link to the active

mode, since normal audio output and input frames can not be communicated in the absence of BIT_CLK.

Waking up the AC Link

There are two methods for bringing the AC Link out of a low power, halted mode. Regardless of the method, it is the AC ’97
controller that performs the wake-up task.

AC Link protocol provides for a “Cold AC ’97 Reset,” and a “Warm AC ’97 Reset.” The current power-down state would
ultimately dictate which form of AC ’97 reset is appropriate. Unless a “cold” or “register” reset (a write to the Reset Register) is
performed, wherein the AD1819 registers are initialized to their default values, registers are required to keep state during all power­down modes. The Serial Configuration Register (0x74) maintains state during a register reset.

Once powered down, reactivation of the AC Link via reassertion of the SYNC signal may be immediate. When the AD1819 powers
up, it indicates readiness via the Codec Ready Bit (Input Slot 0, Bit 15).

Cold AC ’97 Reset

A cold reset is achieved by asserting RESET for at least the minimum specified time. By driving RESET, BIT_CLK and SDATA_OUT
will be activated, and all AD1819 control registers will be initialized to their default power-on reset values.

RESET is an asynchronous AD1819 input.

Warm AC ’97 Reset

A warm AC ’97 reset will reactivate the AC Link without altering the current AD1819 register values. A warm reset is signaled
by driving SYNC high for a minimum of 1 µs in the absence of BIT_CLK.

Within normal audio frames SYNC is a synchronous AD1819 input. In the absence of BIT_CLK, however, SYNC is treated as an
asynchronous input used in the generation of a warm reset to the AD1819.

REV. 0

–23–

AD1819

MULTIPLE CODE CONFIGURATION
Setting Up Multiple Codecs

The AD1819 may be used with up to two additional AD1819
codecs. In order to configure the codecs as Master, Slave 1 or
Slave 2, refer to the following table.

CS1 CS0 Configuration

0 0 Slave 1 Codec
0 1 Slave 2 Codec
1 0 Master Codec
1 1 AC ’97 Mode Codec

0 = Ground; 1 = VDD.

XTALI pin on the Slave Codecs “must” be tied to ground and
the CHAIN_IN pin “must” be tied to ground on the last codec
Slave 1 (on a 2-codec design) or SLAVE 2 (on a 3-codec de­sign). See Figures 9 and 10.

Configure the Codec Resources

Programing REGM (2:0) bits in the Serial Configuration Regis­ter (74h) allows the digital controller read write access to all the
internal registers on each codec according to the following table.

REGM2 REGM1 REGM0 Read Write

00 0xx
0 0 1 Master Master
0 1 0 Slave 1 Slave 1
0 1 1 Master Master, Slave 1
1 0 0 Slave 2 Slave 2
1 0 1 Master Master, Slave 2
1 1 0 Slave 1 Slave 1, Slave 2
1 1 1 Master Master, Slave 1, Slave 2

–24–

REV. 0

APPLICATIONS CIRCUITS

The AD1819 has been designed to require a minimum number
of external circuitry. The recommended applications circuits are
shown in Figures 15–18. Reference designs for the AD1819 are
available and may be obtained by contacting your local Analog
Devices’ sales representative or authorized distributor. Example
shell programs for establishing a communications path between
the AD1819 and an ADSP-21xx are also available.

AD1819

1.37kV

4.99kV

10kV

100nF

10kV10kV

1mF

1mF

1mF

1mF

1mF

1mF

1mF

1mF

100nF

1mF

1mF

1mF

1mF

1mF

1mF

1mF

+5AV

PC_BEEP

LINE_IN_R
LINE_IN_L

MIC1

MIC2

CD_R

CD_L

CD_GND

VIDEO_L

VIDEO_R

AUX_L
AUX_R

PHONE_IN

7

MONO_OUT

36

LINE_OUT_R

LINE_OUT_L

AFILT1 AFILT2 FILT_L

270pF

NP0

270pF
NP0

DD

10mF TANT

100nF

AV

DD2AVSS2

FILT_R CX3D RX3D

1mF

1mF

+5AV

DD

10mF TANT

100nF

AV

DD1AVSS

34

100nF

AD1819

33

C9
47nF
NP0

10mF TANT

100nF

DV

SS1DVDD1

V

REFOUTVREF

28

2.25Vdc
100nF

+5DV

DD

DV

27

10mF

TANT

+5DV

DD

10mF TANT

100nF

SS2DVDD2

SDATA_OUT

SDATA_IN

BIT_CLK

CHAIN_IN

CHAIN_CLK

XTAL_IN XTAL_OUT

24.576MHz

22pF

NP0

RESET

SYNC

CS0
CS1

22pF
NP0

47

48

CONTROLLER

DV

DD

DIGITAL

REV. 0

600Z

CHASSIS GROUND

ANALOG GROUND DIGITAL GROUND

Figure 15. Recommended One Codec Application Circuit

–25–

AD1819

XTAL_IN

22pF

NP0

XTAL_IN

AD1819

MASTER

24.576MHz

AD1819

SLAVE 1

RESET

SDATA_OUT

SDATA_IN

SYNC

BIT_CLK

CHAIN_IN

CHAIN_CLK

XTAL_OUT

22pF
NP0

RESET

SDATA_OUT

SDATA_IN

SYNC

BIT_CLK

CHAIN_IN

CHAIN_CLK

XTAL_OUT

CS0
CS1

CS0
CS1

DV

RESET

SDATA_OUT
SDATA_IN
SYNC
BIT_CLK

DD

FL0
DT0
DR0
RFS0
SCLK0

SPORT0

DIGITAL

CONTROLLER

(ADSP-2181)

AD1819

SLAVE 2

XTAL_IN

RESET

SDATA_OUT

SDATA_IN

SYNC

BIT_CLK

CHAIN_IN

CHAIN_CLK

XTAL_OUT

CS0
CS1

DV

DD

Figure 16. Three Codec System Example

–26–

REV. 0

AD1819

XTAL_IN

22pF

NP0

XTAL_IN

AD1819

MASTER

24.576MHz

AD1819

SLAVE 1

RESET

SDATA_OUT

SDATA_IN

SYNC

BIT_CLK

CS0
CS1

CHAIN_IN

CHAIN_CLK

XTAL_OUT

22pF
NP0

RESET

SDATA_OUT

SDATA_IN

SYNC

BIT_CLK

CS0
CS1

CHAIN_IN

CHAIN_CLK

XTAL_OUT

DV

RESET

SDATA_OUT
SDATA_IN
SYNC
BIT_CLK

DD

FL0
DT0
DR0
RFS0
SCLK0

SPORT0

DIGITAL

CONTROLLER

(ADSP-2181)

Figure 17. Two Codec System Example

2.21kV*

MIC

INPUT

.

10mV RMS

(mean)

200Hz < FREQUENCY RESPONSE < 5kHz @ –3dB

NOTES:
*MAY NEED TO OPTIMIZE TO SUIT MICROPHONE
**SELECT MIC1 AND MAX GAIN 20dB +12dB for 10mV
RMS MICROPHONE OUTPUT.

FB

100V

100pF

Figure 18. Microphone Input

10nF*

100nF

NC

AD1819

V

REFOUT

MIC1**

MIC2

REV. 0

–27–

AD1819

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

48-Terminal TQFP

(ST-48)

0.030 (0.75)

0.018 (0.45)

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0° – 7°

0.063 (1.60) MAX

0.030 (0.75)

0.057 (1.45)

0.018 (0.45)

0.053 (1.35)

0° MIN

0.007 (0.18)

0.004 (0.09)

0.354 (9.00) BSC

0.276 (7.0) BSC

48

1

(PINS DOWN)

12

13

0.019 (0.5)
BSC

TOP VIEW

37

24

0.011 (0.27)

0.006 (0.17)

36

25

0.276 (7.0) BSC

0.354 (9.00) BSC

C3097–2–10/97

–28–

PRINTED IN U.S.A.

REV. 0