Complete, High Speed
16-Bit A/D Converters
AD1376/AD1377
FEATURES
Complete 16-Bit Converters with Reference and Clock
ⴞ0.003% Maximum Nonlinearity
No Missing Codes to 14 Bits over Temperature
Fast Conversion
17 s to 16 Bits (AD1376)
10 s to 16 Bits (AD1377)
Short Cycle Capability
Parallel Outputs
Low Power
645 mW Typical (AD1376)
585 mW Typical (AD1377)
Industry-Standard Pinout
GENERAL DESCRIPTION
The AD1376/AD1377 are high resolution, 16-bit analog-todigital converters with internal reference, clock, and
laser-trimmed thin-film applications resistors. They are
packaged in compact 32-lead, ceramic seam sealed (hermetic), dual-in-line packages (DIP). Thin-film scaling
resistors provide bipolar input ranges of ±2.5 V, ±5 V, ±10 V
and unipolar input ranges of 0 V to +5 V, 0 V to +10 V, and
0 V to +20 V.
Digital output data is provided in parallel form with corresponding clock and status outputs. All digital inputs and
outputs are TTL compatible.
FUNCTIONAL BLOCK DIAGRAM
For the AD1376, the serial output function is nonfunctional after date code 0111. For the AD1377, the serial
output function is nonfunctional after date code 0210. The
user option of applying external clock on the CONVERT
START pin to slow down the internally set conversion time
is no longer available for either part.
PRODUCT HIGHLIGHTS
1. The AD1376/AD1377 provides 16-bit resolution with a
maximum linearity error of ±0.003% (1/2 LSB
25°C.
2. AD1376 conversion time is 14 µs (typical) short
cycled to 14 bits, and 16 µs to 16 bits.
3. AD1377 conversion time is 8 µs (typical) short cycled
to 14 bits, and 9 µs to 16 bits.
4. Two binary codes are available on the digital output.
They are CSB (complementary straight binary) for
unipolar input voltage ranges and COB (complementary
offset binary) for bipolar input ranges. Complementary
twos complement (CTC) coding may be obtained by
inverting Pin 1 (MSB).
5. The AD1376 and AD1377 include internal reference
and clock, with external clock rate adjust pin, and parallel digital outputs.
) at
14
REV. C
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AD1376/AD1377–SPECIFICATIONS
(typical at TA = 25ⴗC, VS = ⴞ15 V, +5 V, unless otherwise noted.)
Model AD1376JD/AD1377JD AD1376KD/AD1377KD Unit
RESOLUTION 16 (max) 16 (max) Bits
ANALOG INPUTS
Voltage Ranges
Bipolar ± 2.5, ± 5, ± 10 ± 2.5, ± 5, ± 10 V
Unipolar 0 to +5, 0 to +10, 0 to +20 0 to +5, 0 to +10, 0 to +20 V
Impedance (Direct Input)
0 V to +5 V, ±2.5 V 1.88 1.88 kΩ
0 V to +10 V, ±5.0 V 3.75 3.75 kΩ
0 V to +20 V, ±10 V 7.50 7.50 kΩ
DIGITAL INPUTS
1
Convert Command Positive Pulse 50 ns Wide (min) Trailing Edge Initiates Conversion
Logic Loading 1 1 LS TTL Load
TRANSFER CHARACTERISTICS
ACCURACY
Gain Error ± 0.05
Offset Error
Unipolar ± 0.05
2
3
(±0.2 max) ± 0.053 (±0.2 max) %
3
(±0.1 max) ± 0.053 (±0.1 max) % of FSR
Bipolar ± 0.053 (±0.2 max) ± 0.053 (±0.2 max) % of FSR
Linearity Error (Max) ± 0.006 ±0.003 % of FSR
Inherent Quantization Error ± 1/2 ±1/2 LSB
Differential Linearity Error ± 0.003 ±0.003 % of FSR
POWER SUPPLY SENSITIVITY
± 15 V DC (± 0.75 V) 0.0015 0.0015 % of FSR/% ∆V
+5 V DC (± 0.25 V) 0.001 0.001 % of FSR/% ∆V
CONVERSION TIME
5
12 Bits (AD1376) 11.5 (13 max) 11.5 (13 max) µs
14 Bits (AD1376) 13.5 (15 max) 13.5 (15 max) µs
16 Bits (AD1376) 15.5 (17 max) 15.5 (17 max) µs
14 Bits (AD1377) 8.75 max 8.75 max µs
16 Bits (AD1377) 10 max 10 max µs
POWER SUPPLY REQUIREMENTS
Rated Voltage, Analog ± 15, ± 0.5 (max) ± 15, ± 0.5 (max) V dc
Rated Voltage, Digital +5, ± 0.25 (max) +5, ±0.25 (max) V dc
AD1376 Power Consumption 645 (850 max) 645 (850 max) mW
+15 V Supply Drain +16 +16 mA
–15 V Supply Drain –21 –21 mA
+5 V Supply Drain +18 +18 mA
AD1377 Power Consumption 600 (800 max) 600 (800 max) mW
+15 V Supply Drain +10 +10 mA
–15 V Supply Drain –23 –23 mA
+5 V Supply Drain +18 +18 mA
WARM-UP TIME 1 1 minutes
6
DRIFT
Gain ± 15 (max) ±5 (±15 max) ppm/°C
Offset
Unipolar ± 2 (± 4 max) ± 2 (± 4 max) ppm of FSR/°C
Bipolar ± 10 (max) ± 3 (± 10 max) ppm of FSR/°C
Linearity ± 2 (± 3 max) ± 0.3 (± 2 max) ppm of FSR/°C
Guaranteed No Missing Code
Temperature Range 0 to 70 (13 Bits) 0 to 70 (14 Bits) °C
4
S
S
REV. C–2–
AD1376/AD1377
Model AD1376JD/AD1377JD AD1376KD/AD1377KD Unit
DIGITAL OUTPUT
(All Codes Complementary)
Parallel
Output Codes
Unipolar CSB CSB
Bipolar COB, CTC
Output Drive 5 5 LSTTL Loads
Status Logic 1 during Conversion
Status Output Drive 5 (max) 5 (max) LSTTL Loads
Internal Clock
Clock Output Drive 5 (max) 5 (max) LSTTL Loads
Frequency 1040/1750 1040/1750 kHz
TEMPERATURE RANGE
Specification 0 to 70 0 to 70 °C
Operating –25 to +85 –25 to +85 °C
Storage –55 to +125 –55 to +125 °C
NOTES
1
Logic 0 = 0.8 V, max. Logic 1 = 2.0 V, min for inputs. For digital outputs Logic 0 = 0.4 V max. Logic 1 = 2.4 V min.
2
Tested on ± 10 V and 0 V to +10 V ranges.
3
Adjustable to zero.
4
Full-scale range.
5
Guaranteed but not 100% production tested.
6
Conversion time may be shortened with “short cycle” set for lower resolution.
7
CSB–Complementary Straight Binary. COB–Complementary Offset Binary. CTC–Complementary Twos Complement.
8
CTC coding obtained by inverting MSB (Pin 1).
9
With Pin 23, clock rate controls tied to digital ground.
Specifications subject to change without notice.
1
7
8
9
COB, CTC
8
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Logic Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Analog Inputs (Pins 24 and 25) . . . . . . . . . . . . . . . . . . . ± 25 V
Analog Ground to Digital Ground . . . . . . . . . . . . . . . . . ± 0.3 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
DD
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15°C
Lead Temperature (10 sec) . . . . . . . . . . . . . . . . . . . . . . 300°C
*Absolute maximum ratings are limiting values to be applied individually, and
beyond which the service ability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
Temperature Linearity Time Package
Model Range Error (16 Bits) Option*
AD1376JD 0°C to 70°C ± 0.006% 17 µs DH-32E
AD1376KD 0°C to 70°C ± 0.003% 17 µs DH-32E
AD1377JD 0°C to 70°C ± 0.006% 10 µs DH-32E
AD1377KD 0°C to 70°C ± 0.003% 10 µs DH-32E
*DH-32E = Ceramic DIP.
ORDERING GUIDE
Maximum Conversion
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD1376/AD1377 feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. C
–3–
AD1376/AD1377
Figure 1. Linearity Error vs. Temperature
APPLICATIONS
The AD1376/AD1377 are excellent for use in high resolution
applications requiring moderate speed and high accuracy or
stability over commercial (0°C to 70°C) temperature ranges (for
extended temperature ranges, the pin compatible AD1378 is
recommended.) Typical applications include medical and analytic instrumentation, precision measurement for industrial
robotics, automatic test equipment (ATE), multichannel data
acquisition systems, servo control systems, or anywhere wide
dynamic range is required. A proprietary monolithic DAC
and laser-trimmed thin-film resistors guarantee a maximum
nonlinearity of ±0.003% (1/2 LSB
). The converters may be
14
short cycled to achieve faster conversion times—15 µs to 14 bits
for the AD1376 or 8 µs to 14 bits for the AD1377.
DESCRIPTION OF OPERATION
On receipt of a CONVERT START command, the AD1376/
AD1377 converts the voltage at its analog input into an equivalent 16-bit binary number. This conversion is accomplished as
follows: the 16-bit successive approximation register (SAR) has
its 16-bit outputs connected both to the device bit output pins
and to the corresponding bit inputs of the feedback DAC. The
analog input is successively compared to the feedback DAC
output, one hit at a time (MSB first, LSB last). The decision to
keep or reject each bit is then made at the completion of each
bit comparison period, depending on the state of the comparator at that time.
Figure 2. AD1376 Nonlinearity vs. Conversion Time
Figure 3. Gain Drift Error vs. Temperature
GAIN ADJUSTMENT
The gain adjust circuit consists of a 100 ppm/°C potentiometer
connected across ±V
with its slider connected through a 300 kΩ
S
resistor to the gain adjust Pin 29 as shown in Figure 4.
If no external trim adjustment is desired, Pin 27 (OFFSET
ADJ) and Pin 29 (GAIN ADJ) may be left open.
Figure 4. Gain Adjustment Circuit (±0.2% FSR)
OFFSET ADJUSTMENT
The zero adjust circuit consists of a 100 ppm/°C potentiometer
connected across ±V
with its slider connected through a 1.8 MΩ
S
resistor to Comparator Input Pin 27 for all ranges. As shown
in Figure 5, the tolerance of this fixed resistor is not critical,
and a carbon composition type is generally adequate. Using a
carbon composition resistor having a –1200 ppm/°C temperature coefficent contributes a worst-case offset temperature
coefficent of 32 LSB
⫻ 61 ppm/LSB14 ⫻ 1200 ppm/°C =
14
2.3 ppm/°C of FSR, if the OFFSET ADJ potentiometer is set
at either end of its adjustment range. Since the maximum offset
adjustment required is typically no more than ±16 LSB
, use of
14
a carbon composition offset summing resistor typically contributes no more than 1 ppm/°C of FSR offset temperature
coefficent.
REV. C–4–