Datasheet AD13280AZ, AD13280AF, AD13280-PCB, 5962-0053001HXA Datasheet (Analog Devices)

a

Dual Channel, 12-Bit, 80 MSPS A/D Converter

with Analog Input Signal Conditioning

AD13280

FEATURES
Dual, 80 MSPS Minimum Sample Rate

Channel-to-Channel Matching, 1% Gain Error
90 dB Channel-to-Channel Isolation

DC-Coupled Signal Conditioning
80 dB Spurious-Free Dynamic Range
Selectable Bipolar Inputs (1 V and 0.5 V Ranges)
Integral Single-Pole Low-Pass Nyquist Filter
Two’s Complement Output Format

3.3 V Compatible Outputs

1.85 W per Channel
Industrial and Military Grade

APPLICATIONS
Radar Processing (Optimized for I/Q Baseband Operation)
Phased Array Receivers
Multichannel, Multimode Receivers
GPS Antijamming Receivers
Communications Receivers

PRODUCT DESCRIPTION

The AD13280 is a complete dual channel signal processing
solution including on board amplifiers, references, ADCs, and
output termination components to provide optimized system
performance. The AD13280 has on-chip track-and-hold circuitry
and utilizes an innovative multipass architecture to achieve 12-bit,
80 MSPS performance. The AD13280 uses innovative high­density circuit design and laser-trimmed thin-film resistor networks
to achieve exceptional channel matching, impedance control,

and performance while still maintaining excellent isolation,
and providing for significant board area savings.

Multiple options are provided for driving the analog input,
including single-ended, differential, and optional series filtering.
The AD13280 also offers the user a choice of analog input
signal ranges to further minimize additional external signal
conditioning, while still remaining general purpose.

The AD13280 operates with ±5.0 V for the analog signal condi­tioning with a separate 5.0 V supply for the analog-to-digital
conversion, and 3.3 V digital supply for the output stage. Each
channel is completely independent allowing operation with
independent encode and analog inputs, and maintaining mini­mal crosstalk and interference.

The AD13280 is packaged in a 68-lead ceramic gull wing package.
Manufacturing is done on Analog Devices, Inc. MIL-38534
Qualified Manufacturers Line (QML) and components are
available up to Class-H (–40°C to +85°C). The components are
manufactured using Analog Devices, Inc. high-speed comple­mentary bipolar process (XFCB).

PRODUCT HIGHLIGHTS

1. Guaranteed sample rate of 80 MSPS.

2. Input signal conditioning included; gain and impedance match.

3. Single-ended, differential, or off-module filter options.

4. Fully tested/characterized full channel performance.

5. Compatible with 14-bit (up to) 65 MSPS family.

FUNCTIONAL BLOCK DIAGRAM

AMP-IN-A-1

VREF

DROUT

100 OUTPUT TERMINATORS

ENC

12

3

D9A D10A

D11A

(MSB)

AD13280

AMP-OUT-A

A–IN

A+IN

DROUTA

(LSB) D0A

D1A

D2A

D3A

D4A

D5A

D6A

D7A

D8A

AMP-IN-A-2

9

TIMING

ENC

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

AMP-IN-B-2 AMP-IN-B-1

AMP-OUT-B

B+IN

B–IN

DROUTB

TIMING

VREF
DROUT

12

100 OUTPUT TERMINATORS

7

D0B

D1B D3BD2B D4B D5B D6B

(LSB)

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

5

ENC

ENC

D11B (MSB)

D10B

D9B

D8B

D7B

(AVCC = +5 V, AVEE = –5 V, DVCC = +3.3 V; applies to each ADC with Front-End

AD13280–SPECIFICATIONS

Parameter Temp Level Subgroup Min Typ Max Unit

RESOLUTION 12 Bits

DC ACCURACY

No Missing Codes Full IV 12 Guaranteed
Offset Error 25°C I 1 –2.2 ±1.0 +2.2 % FS

Offset Error Channel Match Full VI 1, 2, 3 –1.0 ±0.1 +1.0 %
Gain Error

Gain Error Channel Match 25°C I 1 –1.5 ±0.5 +1.5 %

SINGLE-ENDED ANALOG INPUT

Input Voltage Range

AMP-IN-X-1 Full V ±0.5 V
AMP-IN-X-2 Full V ±1.0 V

Input Resistance

AMP-IN-X-1 Full IV 12 99 100 101 Ω
AMP-IN-X-2 Full IV 12 198 200 202 Ω

Capacitance 25°C V 4.0 7.0 pF
Analog Input Bandwidth

DIFFERENTIAL ANALOG INPUT

Analog Signal Input Range

A+IN to A–IN and B+IN to B–IN

Input Impedance 25°C V 618 Ω
Analog Input Bandwidth Full V 50 MHz

ENCODE INPUT (ENC, ENC)

Differential Input Voltage Full IV 12 0.4 V p-p
Differential Input Resistance 25°CV 10 kΩ
Differential Input Capacitance 25°C V 2.5 pF

SWITCHING PERFORMANCE

Maximum Conversion Rate
Minimum Conversion Rate
Aperture Delay (t
Aperture Delay Matching 25°C IV 12 250 500 ps
Aperture Uncertainty (Jitter) 25°C V 0.3 ps rms
ENCODE Pulsewidth High at Max Conversion Rate 25°C IV 12 4.75 6.25 8 ns
ENCODE Pulsewidth Low at Max Conversion Rate 25°C IV 12 4.75 6.25 8 ns
Output Delay (t
Encode, Rising to Data Ready, Rising Delay Full V 8.5 ns

1, 6

SNR

Analog Input @ 10 MHz 25°C I 4 67.5 70 dBFS

Analog Input @ 21 MHz 25°C I 4 67.5 70 dBFS

Analog Input @ 37 MHz 25°C I 4 63.5 65 dBFS

1, 7

SINAD

Analog Input @ 10 MHz 25°C I 4 67 69 dBFS

Analog Input @ 21 MHz 25°C I 4 65 68.5 dBFS

Analog Input @ 37 MHz 25°C I 4 54.5 59 dBFS

1

2

3

4

1

5

5

)25°C V 1.5 ns

A

) Full V 5 ns

OD

Amplifier unless otherwise noted.)

Test Mil AD13280AZ/BZ

Full VI 2, 3 –2.2 ±1.0 +2.2 % FS

25°C I 1 –3 –1.0 +1 % FS
Full VI 2, 3 –5.0 ±2.0 +5.0 % FS

Max VI 2 –3.0 ± 1.0 +3.0 %
Min VI 3 –5 ±1.0 +5 %

Full V 100 MHz

Full V ±1V

Full VI 4, 5, 6 80 MSPS
Full IV 12 20 MSPS

Min II 6 64.5 dBFS
Max II 5 67.5 dBFS

Min II 6 64 dBFS
Max II 5 67.5 dBFS

Min II 6 61.5 dBFS
Max II 5 63.5 dBFS

Min II 6 63.5 dBFS
Max II 5 67 dBFS

Min II 6 63 dBFS
Max II 5 65 dBFS

Min II 6 53 dBFS
Max II 5 54.5 dBFS

–2–

REV. 0

AD13280

Test Mil AD13280AZ/BZ

Parameter Temp Level Subgroup Min Typ Max Unit

SPURIOUS-FREE DYNAMIC RANGE

Analog Input @ 10 MHz 25°C I 4 75 80 dBFS

Analog Input @ 21 MHz 25°C I 4 68 75 dBFS

Analog Input @ 37 MHz 25°C I 4 56 62 dBFS

SINGLE-ENDED ANALOG INPUT

Passband Ripple to 10 MHz 25°C V 0.05 dB
Passband Ripple to 25 MHz 25°C V 0.1 dB

DIFFERENTIAL ANALOG INPUT

Passband Ripple to 10 MHz 25°C V 0.3 dB
Passband Ripple to 25 MHz 25°C V 0.82 dB

TWO-TONE IMD REJECTION

fIN = 9.1 MHz and 10.1 MHz 25°C I 4 75 80 dBc
f1 and f2 are –7 dB Min II 6 71

f

= 19.1 MHz and 20.7 MHz 25°C V 4 77 dBc

IN

f

and f2 are –7 dB

1

fIN = 36 MHz and 37 MHz 25°C V 4 60 dBc
f1 and f2 are –7 dB

CHANNEL-TO-CHANNEL ISOLATION
TRANSIENT RESPONSE 25°CV 25 ns

DIGITAL OUTPUTS

11

Logic Compatibility CMOS
DVCC = 3.3 V

Logic “1” Voltage Full I 1, 2, 3 2.5 DVCC – 0.2 V
Logic “0” Voltage Full I 1, 2, 3 0.2 0.5 V

DVCC = 5 V

Logic “1” Voltage Full V DVCC – 0.3 V
Logic “0” Voltage Full V 0.35 V

Output Coding Two’s Complement

POWER SUPPLY

AVCC Supply Voltage
I (AVCC) Current Full I 1, 2, 3 310 338 mA
AV

Supply Voltage

EE

I (AVEE) Current Full I 1, 2, 3 38 49 mA
DV

Supply Voltage

CC

12

12

12

I (DVCC) Current Full I 1, 2, 3 34 46 mA
I

(Total) Supply Current per Channel Full I 1, 2, 3 369 433 mA

CC

Power Dissipation (Total) Full I 1, 2, 3 3.72 4.05 W
Power Supply Rejection Ratio (PSRR) Full V 0.01 % FSR/% V

NOTES

1

All ac specifications tested by driving ENCODE and ENCODE differentially. Single-ended input: AMP-IN-X-1 = 1 V p-p, AMP-IN-X-2 = GND.

2

Gain tests are performed on AMP-IN-X-1 input voltage range.

3

Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.

4

For differential input: +IN = 1 V p-p and –IN = 1 V p-p (signals are 180° out of phase). For single-ended input: +IN = 2 V p-p and = –IN = GND.

5

Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%.

6

Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 80 MSPS. SNR
is reported in dBFS, related back to converter full scale.

7

Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 80 MSPS. SINAD is
reported in dBFS, related back to converter full scale.

8

Analog Input signal at –1 dBFS; SFDR is ratio of converter full scale to worst spur.

9

Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product.

10

Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B Channel.

11

Digital output logic levels: DVCC = 3.3 V, C

12

Supply voltage recommended operating range. AVCC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range
AVCC = 5.0 V to 5.25 V.

Specifications subject to change without notice.

1, 8

Min II 6 70
Max II 5 75

Min II 6 67
Max II 5 68

Min II 6 55
Max II 5 56

9

Max II 5 75

10

25°CIV 12 90 dB

Full IV 4.85 5.0 5.25 V

Full IV –5.25 –5.0 –4.75 V

Full IV 3.135 3.3 3.465 V

S

= 10 pF. Capacitive loads > 10 pF will degrade performance.

LOAD

REV. 0

–3–

AD13280

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL

1

AVCC Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V

Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V to 0 V

AV

EE

DV

Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V

CC

Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . V

EE

to V

CC

Analog Input Current . . . . . . . . . . . . . . –10 mA to +10 mA

Digital Input Voltage (ENCODE) . . . . . . . . . . . . . 0 to V

CC

ENCODE, ENCODE Differential Voltage . . . . . . . . 4 V max

Digital Output Current . . . . . . . . . . . . . . –10 mA to +10 mA

ENVIRONMENTAL

2

Operating Temperature (Case) . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 175°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C

Storage Temperature Range (Ambient) . . –65°C to +150°C

NOTES

1

Absolute maximum ratings are limiting values applied individually, and beyond
which the serviceability of the circuit may be impaired. Functional operability is not
necessarily implied. Exposure to absolute maximum rating conditions for an
extended period of time may affect device reliability.

2

Typical thermal impedance for “ES” package: θJC 2.2°C/W; θJA 24.3°C/W.

TEST LEVEL

I 100% Production Tested.
II 100% Production Tested at 25°C, and sample tested at

specified temperatures. AC testing done on sample basis.

III Sample Tested only.

IV Parameter is guaranteed by design and characterization

testing.

V Parameter is a typical value only.
VI 100% production tested with temperature at 25°C: sample

tested at temperature extremes.

68-Lead Ceramic Leaded Chip Carrier

10

AGNDA

11

AV

A

EE

AV

A

12

CC

13

AGNDA

AGNDA

DV

CC

NC

NC

D1A

D2A

D3A

D4A

D5A

DGNDA

14

15

16

A

17

18

19

20

21

22

23

24

25

26

ENCODEA

ENCODEA

D0A(LSB)

NC = NO CONNECT

PIN CONFIGURATION

(ES-68C)

AGNDA

AMP-OUT-A

AMP-IN-A-2

AMP-IN-A-1

9618765 686766656463624321

27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42

D8A

D7A

D6A

DGNDA

AGNDA

A+IN

A–IN

AGNDA

AD13280

TOP VIEW

(Not to Scale)

D9A

D10A

DROUTA

D11A(MSB)

AGNDB

SHIELD

AGNDB

B–IN

B+IN

AMP-OUT-B

AMP-IN-B-1

PIN 1
IDENTIFIER

SHIELD

DROUTB

D0B(LSB)

D2B

D1B

NC

NC

AGNDB

AMP-IN-B-2

60

AGNDB

59

AV

58

AV

57

AGNDB

56

ENCODEB

55

ENCODEB

54

AGNDB

53

DV

52

D11B(MSB)
D10B

51

D9B

50

49

D8B

48

D7B

47

D6B

46

D5B

45

D4B

44

DGNDB

D3B

DGNDB

B

EE

B

CC

B

CC

ORDERING GUIDE

Model Temperature Range (Case) Package Description Package Option

AD13280AZ –25°C to +85°C 68-Lead Ceramic Leaded Chip Carrier ES-68C
AD13280AF –25°C to +85°C 68-Lead Ceramic Leaded Chip Carrier ES-68C

with Nonconductive Tie-Bar

5962-0053001HXA –40°C to +85°C 68-Lead Ceramic Leaded Chip Carrier ES-68C
AD13280/PCB 25°C Evaluation Board with AD13280AZ

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD13280 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–4–

REV. 0

AD13280

PIN FUNCTION DESCRIPTIONS

Pin No. Name Function

1, 35 SHIELD Internal Ground Shield between Channels
2, 3, 9, 10, 13, 16 AGNDA A Channel Analog Ground. A and B grounds should be connected as close to

the device as possible.
4 A–IN Inverting Differential Input (Gain = 1).
5 A+IN Noninverting Differential Input (Gain = 1).
6 AMP-OUT-A Single-Ended Amplifier Output (Gain = 2).
7 AMP-IN-A-1 Analog Input for A Side ADC (Nominally ±0.5 V).
8 AMP-IN-A-2 Analog Input for A Side ADC (Nominally ±1.0 V).
11 AV
12 AV
14 ENCODEA Complement of Encode; Differential Input.
15 ENCODEA Encode Input; Conversion Initiated on Rising Edge.
17 DV
18, 19, 37, 38 NC No Connect.
20–25, 28–33 D0A–D11A Digital Outputs for ADC A. D0 (LSB).
26, 27 DGNDA A Channel Digital Ground.
34 DROUTA Data Ready A Output.
36 DROUTB Data Ready B Output.
39–42, 45–52 D0B–D11B Digital Outputs for ADC B. D0 (LSB).
43, 44 DGNDB B Channel Digital Ground.
53 DV
54, 57, 60, 61, 67, 68 AGNDB B Channel Analog Ground. A and B grounds should be connected as close to the

55 ENCODEB Encode Input; Conversion Initiated on Rising Edge.
56 ENCODEB Complement of Encode; Differential Input.
58 AV
59 AV
62 AMP-IN-B-2 Analog Input for B Side ADC (Nominally ±1.0 V).
63 AMP-IN-B-1 Analog Input for B Side ADC (Nominally ±0.5 V).
64 AMP-OUT-B Single-Ended Amplifier Output (Gain = 2).
65 B+IN Noninverting Differential Input (Gain = 1).
66 B–IN Inverting Differential Input (Gain = 1).

A A Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V).

EE

A A Channel Analog Positive Supply Voltage (Nominally 5.0 V).

CC

A A Channel Digital Positive Supply Voltage (Nominally 5.0 V/ 3.3 V).

CC

B B Channel Digital Positive Supply Voltage (Nominally 5.0 V/ 3.3 V).

CC

device as possible.

B B Channel Analog Positive Supply Voltage (Nominally 5.0 V).

CC

B B Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V).

EE

REV. 0

–5–

AD13280

–Typical Performance Characteristics

dB

–100

–110

–120

–130

dB

–100

–110

–120

–130

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

3

2

0

51015202530

4

FREQUENCY – MHz

TPC 1. Single Tone @ 5 MHz

0

0

51015202530

FREQUENCY – MHz

ENCODE = 80MSPS
A

= 5MHz (–1dBFS)

IN

SNR = 69.4dBFS
SFDR = 81.9dBc

5

6

35 40

ENCODE = 80MSPS
A

= 18MHz (–1dBFS)

IN

SNR = 69.79dBFS
SFDR = 76.81dBc

35 40

dB

–100

–110

–120

–130

dB

–100

–110

–120

–130

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

51015202530

FREQUENCY – MHz

TPC 4. Single Tone @ 10 MHz

0

–10

ENCODE = 80MSPS
A

= 37MHz (–1dBFS)

–20

–30

–40

–50

–60

–70

–80

–90

IN

SNR = 68.38dBFS
SFDR = 57.81dBc

2

6

4

0

51015202530

FREQUENCY – MHz

ENCODE = 80MSPS
A

= 10MHz (–1dBFS)

IN

SNR = 69.19dBFS
SFDR = 79.55dBc

3

2

6

5

3

5

4

35 40

35 40

TPC 2. Single Tone @ 18 MHz

0

–10

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

–130

0

51015202530

FREQUENCY – MHz

TPC 3. Two Tone @ 9 MHz/10 MHz

ENCODE = 80MSPS

A

= 9MHz AND

IN

10MHz (–7dBFS)
SFDR = 82.77dBc

35 40

TPC 5. Single Tone @ 37 MHz

0

ENCODE = 80MSPS
A

IN

20MHz (–7dBFS)
SFDR = 74.41dBc

dB

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

0

51015202530

FREQUENCY – MHz

TPC 6. Two Tone @ 19 MHz/20 MHz

= 19MHz AND

35 40

–6–

REV. 0

3.0

–3

ENCODE = 80MSPS
INL MAX = 0.562 CODES
INL MIN = 0.703 CODES

–2

0

2

3

1

–1

0

512 1024 1536 2048 2560 3072 3584 4096

LSB

2.5

2.0

1.5

1.0

LSB

0.5

–0.5

–1.0

–1

–2

–3

–4

–5

dBFS

–6

–7

–8

–9

–10

ENCODE = 80MSPS
DNL MAX = 0.688 CODES
DNL MIN = 0.385 CODES

0

1024 1536 2048 2560 3072 3584 4096

512

0

TPC 7. Differential Nonlinearity

0

6.0 8.5 11.0 13.5 16.0 18.5 21.0 23.5 26.0

3.5

1.0

FREQUENCY – MHz

ENCODE = 80MSPS
ROLL-OFF = 0.0459dB

AD13280

TPC 9. Integral Nonlinearity

TPC 8. Passband Ripple to 25 MHz

REV. 0

–7–

AD13280

DEFINITION OF SPECIFICATIONS
Analog Bandwidth

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

Aperture Delay

The delay between a differential crossing of ENCODE and
ENCODE command and the instant at which the analog input
is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci­tance and differential input impedances are measured with a
network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to the
converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage from the other pin,
which is 180 degrees out of phase. Peak-to-peak differential is
computed by rotating the inputs phase 180 degrees and taking
the peak measurement again. The difference is then computed
between both peak measurements.

Differential Nonlinearity

The deviation of any code from an ideal 1 LSB step.

Encode Pulsewidth/Duty Cycle

Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic “1” state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. At a given clock
rate, these specs define an acceptable Encode duty cycle.

Harmonic Distortion

The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.

Integral Nonlinearity

The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a differential crossing of ENCODE and
ENCODE command and the time when all output data bits are
within valid logic levels.

Overvoltage Recovery Time

The amount of time required for the converter to recover to

0.02% accuracy after an analog input signal of the specified
percentage of full scale is reduced to midscale.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in
power supply voltage.

Signal-to-Noise-and-Distortion (SINAD)

The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo­nents, including harmonics but excluding dc. May be reported
in dB (i.e., degrades as signal level is lowered) or in dBFS
(always related back to converter full scale).

Signal-to-Noise Ratio (without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo­nents, excluding the first five harmonics and dc. May be reported
in dB (i.e., degrades as signal level is lowered) or in dBFS
(always related back to converter full scale).

Spurious-Free Dynamic Range

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo­nent may or may not be a harmonic.

Transient Response

The time required for the converter to achieve 0.02% accuracy
when a one-half full-scale step function is applied to the ana­log input.

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.

A

ENC, ENC

D[11:0]

DRY

t

A

N

IN

t

ENC

N

N+1

N+2

ENCH

N+1

t

ENCL

N+2 N+3 N+4

t

E_DR

t

N–3N–2N–1N

N+3

N+4

t

OD

Figure 1. Timing Diagram

–8–

REV. 0

AD13280

ENCODE

AMP-IN-X-1

AMP-IN-X-2

100

TO AD8037

100

Figure 2. Single-Ended Input Stage

LOADS

AV

AV

CC

CC

10k

10k

LOADS

AV

CC

10k

10k

Figure 3. ENCODE Inputs

DV

CC

CURRENT MIRROR

DV

CC

V

REF

DR OUT

CURRENT MIRROR

Figure 4. Digital Output Stage

DV

CC

CURRENT MIRROR

THEORY OF OPERATION

The AD13280 is a high-dynamic range 12-bit, 80 MHz pipeline
delay (three pipelines) analog-to-digital converter. The custom
analog input section provides input ranges of 1 V and 2 V p-p
and input impedance configurations of 50 Ω, 100 Ω, and 200 Ω.

The AD13280 employs four monolithic ADI components per
channel (AD8037, AD8138, AD8031, and a custom ADC IC),
along with multiple passive resistor networks and decoupling

AV

CC

capacitors to fully integrate a complete 12-bit analog-to-digital
converter.

ENCODE

In the single-ended input configuration the input signal is passed
through a precision laser trimmed resistor divider allowing
the user to externally select operation with a full-scale signal of
±0.5 V, or ±1.0 V by choosing the proper input terminal for the
application. The result of the resistor divider is to apply a full­scale input approximately 0.4 V to the noninverting input of the
internal AD8037 amplifier.

The AD13280 analog input includes an AD8037 amplifier featur­ing an innovative architecture that maximizes the dynamic range
capability on the amplifiers’ inputs and outputs. The AD8037
amplifier provides a high input impedance and gain for driving
the AD8138 in a single-ended to differential amplifier configura­tion. The AD8138 has a –3 dB bandwidth at 300 MHz and
delivers a differential signal with the lowest harmonic distortion
available in a differential amplifier. The AD8138 differential
outputs help balance the differential inputs to the custom ADC
maximizing the performance of the device.

The AD8031 provides the buffer for the internal reference analog­to-digital converter. The internal reference voltage of the custom
ADC is designed to track the offsets and drifts and is used to
ensure matching over an extended temperature range of operation.
The reference voltage is connected to the output common-mode
input on the AD8138. This reference voltage sets the output
common mode on the AD8138 at 2.4 V, which is the midsupply
level for the ADC.

The custom ADC has complementary analog input pins, AIN
and AIN. Each analog input is centered at 2.4 V and should
swing ±0.55 V around this reference. Since AIN and AIN are
180 degrees out of phase, the differential analog input signal is

2.2 V peak-to-peak. Both analog inputs are buffered prior to the
first track-and-hold.

The custom ADC digital outputs drive 100 Ω series resistors (Fig­ure 5). The result is a 12-bit parallel digital CMOS-compatible
word, coded as two’s complement.

REV. 0

DV

CC

V

REF

CURRENT MIRROR

100

Figure 5. Digital Output Stage

D0–D11

USING THE SINGLE-ENDED INPUT

The AD13280 has been designed with the user’s ease of opera­tion in mind. Multiple input configurations have been included
on-board to allow the user a choice of input signal levels and
input impedance. The standard inputs are ±0.5 V and 1.0 V.
The user can select the input impedance of the AD13280 on any
input by using the other inputs as alternate locations for the
GND. The following chart summarizes the impedance options
available at each input location.

AMP-IN-X-1 = 100 Ω when AMP-IN-X-2 is open.
AMP-IN-X-1 = 50 Ω when AMP-IN-X-2 is shorted to GND.
AMP-IN-X-2 = 200 Ω when AMP-IN-X-1 is open.

Each channel has two analog inputs AMP-IN-A-1 and AMP­IN-A-2 or AMP-IN-B-1 and AMP-IN-B-2. Use AMP-IN-A-1

–9–

AD13280

or AMP-IN-B-1 when an input of ±0.5 V full scale is desired. Use
AMP-IN-A-2 or AMP-IN-B-2 when ±1 V full scale is desired.
Each channel has an AMP-OUT which must be tied to either a
noninverting or inverting input of a differential amplifier with the
remaining input grounded. For example, Side A, AMP-OUT-A
(Pin 6) must be tied to A+IN (Pin 5) with A–IN (Pin 5) tied to
ground for noninverting operation or AMP-OUT-A (Pin 6) tied
to A–IN (Pin 4) with A+IN (Pin 5) tied to ground for inverting
operation.

USING THE DIFFERENTIAL INPUT

Each channel of the AD13280 was designed with two optional
differential inputs, A+IN, A–IN and B+IN, B–IN. The inputs
provide system designers with the ability to bypass the AD8037
amplifier and drive the AD8138 directly. The AD8138 differen­tial ADC driver can be deployed in either a single-ended or
differential input configuration. The differential analog inputs
have a nominal input impedance of 620 Ω and nominal full­scale input range of 1.2 V p-p. The AD8138 amplifier drives a
differential filter and the custom analog-to-digital converter. The
differential input configuration provides the lowest even-order
harmonics and signal-to-noise (SNR) performance improvement
of up to 3 dB (SNR = 73 dBFS). Exceptional care was taken in
the layout of the differential input signal paths. The differential
input transmission line characteristics are matched and balanced.
Equal attention to system level signal paths must be provided in
order to realize significant performance improvements.

APPLYING THE AD13280
Encoding the AD13280

The AD13280 encode signal must be a high quality, extremely
low phase noise source, to prevent degradation of performance.
Maintaining 12-bit accuracy at 80 MSPS places a premium on
encode clock phase noise. SNR performance can easily degrade
3 dB to 4 dB with 37 MHz input signals when using a high-jitter
clock source. See Analog Devices’ Application Note AN-501,
“Aperture Uncertainty and ADC System Performance” for
complete details. For optimum performance, the AD13280 must
be clocked differentially. The encode signal is usually ac-coupled
into the ENCODE and ENCODE pins via a transformer or
capacitors. These pins are biased internally and require no addi­tional bias.

Shown below is one preferred method for clocking the AD13280.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD13280 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to the other portions of the AD13280, and limits the
noise presented to the ENCODE inputs. A crystal clock oscillator
can also be used to drive the RF transformer if an appropriate
limited resistor (typically 100 Ω) is placed in the series with
the primary.

CLOCK

SOURCE

0.1F
100



T1-4T

ENCODE

AD13280

HSMS2812

DIODES

ENCODE

If a low jitter ECL/PECL clock is available, another option is to
ac-couple a differential ECL/PECL signal to the encode input
pins as shown below. A device that offers excellent jitter perfor­mance is the MC100LVEL16 (or same family) from Motorola.

VT

ECL/

PECL

0.1F

0.1F

VT

ENCODE

AD13280

ENCODE

Figure 7. Differential ECL for Encode

Jitter Consideration

The signal-to-noise ratio (SNR) for any ADC can be predicted.
When normalized to ADC codes, Equation 1 accurately predicts
the SNR based on three terms. These are jitter, average DNL
error, and thermal noise. Each of these terms contributes to the
noise within the converter.

/

12







ε

+

1

()

SNR f t

=×

f

ANALOG

t

J RMS



20

– log ( )




= analog input frequency

= rms jitter of the encode (rms sum of encode

+×× × +

π






2



N

2





ANALOG RMS



V

NOISE RMS

2

J




2









N

2

(1)






source and internal encode circuitry)

ε = average DNL of the ADC (typically 0.50 LSB)

N = Number of bits in the ADC

V

NOISE RMS

= V rms noise referred to the analog input of the

ADC (typically 5 LSB)

For a 12-bit analog-to-digital converter like the AD13280, aper­ture jitter can greatly affect the SNR performance as the analog
frequency is increased. The chart below shows a family of curves
that demonstrates the expected SNR performance of the AD13280
as jitter increases. The chart is derived from the above equation.

For a complete discussion of aperture jitter, please consult Ana­log Devices’ Application Note AN-501, “Aperture Uncertainty
and ADC System Performance.”

71

70

69

68

67

66

65

64

SNR – –dBFS

63

62

61

60

59

58

0.0

0.2

0.4

0.6

1.0

1.4

1.2

0.8

CLOCK JITTER – ps

1.6

1.8

2.0

2.2

2.4

2.6

2.8

AIN = 5MHz

AIN = 10MHz

AIN = 20MHz

AIN = 37MHz

3.0

3.2

3.4

3.6

3.8

4.0

Figure 8. SNR vs. Jitter

Figure 6. Crystal Clock Oscillator—Differential Encode

–10–

REV. 0

AD13280

Power Supplies

Care should be taken when selecting a power source. Linear sup­plies are strongly recommended. Switching supplies tend to have
radiated components that may be “received” by the AD13280.
Each of the power supply pins should be decoupled as closely as
possible to the package, using 0.1 µF chip capacitors.

The AD13280 has separate digital and analog power supply
pins. The analog supplies are denoted AV
supply pins are denoted DV

. AVCC and DVCC should be

CC

and the digital

CC

separate power supplies because the fast digital output swings
can couple switching current back into the analog supplies.
Note that AV
is specified for DV

must be held within 5% of 5 V. The AD13280

CC

= 3.3 V as this is a common supply for

CC

digital ASICs.

Output Loading

Care must be taken when designing the data receivers for the
AD13280. The digital outputs drive an internal series resistor
(e.g., 100 Ω) followed by a gate like 75LCX574. To minimize
capacitive loading, there should be only one gate on each output
pin. An example of this is shown in the evaluation board sche­matic shown in Figure 9. The digital outputs of the AD13280
have a constant output slew rate of 1 V/ns. A typical CMOS
gate combined with a PCB trace will have a load of approxi­mately 10 pF. Therefore, as each bit switches, 10 mA (10 pF ×
1 V ÷ 1 ns) of dynamic current per bit will flow in or out of the
device. A full-scale transition can cause up to 120 mA (12 bits ×
10 mA/bit) of transient current through the output stages.
These switching currents are confined between ground and the

pin. Standard TTL gates should be avoided since they

DV

CC

can appreciably add to the dynamic switching currents of the
AD13280. It should also be noted that extra capacitive loading
will increase output timing and invalidate timing specifications.
Digital output timing is guaranteed with 10 pF loads.

LAYOUT INFORMATION

The schematic of the evaluation board (Figure 10) represents a
typical implementation of the AD13280. The pinout of the
AD13280 is very straightforward and facilitates ease of use and
the implementation of high-frequency/high-resolution design
practices. It is recommended that high-quality ceramic chip
capacitors be used to decouple each supply pin to ground directly
at the device. All capacitors can be standard high-quality ceramic
chip capacitors.

Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the ADC through a resistor network to eliminate
the need to externally isolate the device from the receiving gate.

EVALUATION BOARD

The AD13280 evaluation board (Figure 9) is designed to
provide optimal performance for evaluation of the AD13280
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD13280. The board requires an analog input signal, encode
clock, and power supply inputs. The clock is buffered on-board
to provide clocks for the latches. The digital outputs and out
clocks are available at the standard 40-pin connectors J1 and J2.

Power to the analog supply pins is connected via banana jacks.
The analog supply powers the associated components and the
analog section of the AD13280. The digital outputs of the
AD13280 are powered via banana jacks with 3.3 V. Contact the
factory if additional layout or applications assistance is required.

REV. 0

Figure 9. Evaluation Board Mechanical Layout

–11–

AD13280

Bill of Materials List for Evaluation Board

Qty. Component Name Ref/Des Value Description Manufacturing Part No.

2 74LCX16373MTD U7, U8 Latch 74LCX16373MTD (Fairchild)
1 AD13280AZ U1 AD13280 AD13280AZ
2 ADP3330 U5, U6 Regulator ADP3330ART-3.3RL7
10 BJACK BJ1–BJ10 Banana Jacks 108-0740-001 (Johnson Components)
2 BRES0805 R41, R53 25 Ω 0805 SM Resistor ERJ-6GEYJ 240V
4 BRES0805 R38, R39, R55, R56 33 kΩ 0805 SM Resistor ERJ-6GEYJ 333V
28 CAP2 C1, C2, C5–C10, 0.1 µF 0805 SM Capacitor GRM 40X7R104K025BL

C12, C16–C18,
C20–C26, C28,
C30–C38

2 CAP2 C13, C27 0.47 µF 0805 SM Capacitor VJ1206U474MFXMB
2 H40DM J1, J2 2 × 20 40 Pin Male Connector TSW-120-08-G-D
6 IND2 L1–L6 47 Ω SM Inductor 2743019447
4 MC10EL16 U2, U4, U9, U11 Clock Drivers MC1016EP16D
2 MC100ELT23 U4, U10 ECL/TTL Clock Drivers SY100ELT23L
8 POLCAP2 C3, C4, C11, C14, 10 µF Tantalum Polar Caps T491C106M016A57280

4 RES2 R47–R50 0 Ω 0805 SM Resistor ERJ-6GEY OR 00V
6 RES2 R1, R2, R5, R7, R8, R54 50 Ω 0805 SM Resistor ERJ-6GEYJ 510V
36 RES2 R3, R4, R6, R9, R12–R15, 100 Ω 0805 SM Resistor ERJ-6GEYJ 101V

12 SMA J3–J14 SMA Connectors 142-0701-201
4 Standoff Standoff 313-2477-016 (Johnson Components)
4 Screws Screws (Standoff) MPMS 004 0005 PH (Building Fasteners)
1 PCB AD13280 Eval Board (Rev. B) GS03361

C15, C19, C29, C30

R19–R28, R31–R36, R37,
R42, R43, R44–R46 R51, R52

–12–

REV. 0

AD13280

–5VAA

0.1F

AGNDA

+5VAA

C35

0.1F

AGNDA

OUT 3.3VDA

C36

0.1F

DGNDA

J13

SMA

AGNDA

C9

C34

0.1F

C10

0.1F

AGNDA

J9

SMA

J3

SMA

J4

SMA

AGNDA

AGNDA

AGNDA

AGNDA

ENCAB

ENCA

AGNDA

NC0A

NC1A

D0A

D1A

D2A

D3A

D4A

D5A

DGNDA

NC = NO CONNECT

E51

E69 E70

AGNDA

10

AGNDA

11

–5VAA

12

+5VAA

13

AGNDA

14

ENCAB

15

ENCA

16

AGNDA

17

+3VDA

18

NC

19

NC

20

D0A(LSB)

21

D1A

22

D2A

23

D3A

24

D4A

25

D5A

26

DGNDA

E68

AGNDA

E50

E75

E73

E49

987654321

E71

E72

E74

E77

A–IN

A+IN

OUT A

IN A 2

AGNDA

AMP

AMP

AMP IN A 1

AGNDA

E66

LIDA

E76

AGNDA

E67

AGNDB

E83

E81

E79

E78

E80

E82

AGNDB

E84

B–IN

B+IN

OUT B

AMP

68676665646362

AGNDB

SHIELD

U1

AD13280

NC0B

NC1B

DRBOUT

D0B(LSBB)

D1B

D1B

D0B

DGNDB

D10A

D10A

D11A(MSBA)

D11A

LIDB

E48

DRAOUT

SHIELD

DRBOUTNCNC

E65

E40

D9A

D8A

D7A

D6A

DGNDA

2728293031323334353637383940414243

D9A

D8A

D7A

D6A

DGNDA

DRAOUT

E56 E55

DGNDA

AMP IN B 1

D2B

D2B

E53

E52

61

IN B 2

AGNDB

AMP

D11B(MSB)

D3B

DGNDB

D3B

DGNDB

E54

AGNDB

AGNDB

–5.2VAB

+5VAB

AGNDB

ENCBB

ENCB

AGNDB

+3.3VDB

D10B

D9B

D8B

D7B

D6B

D5B

D4B

DGNDB

E86E85

J7

SMA

AGNDB

60

AGNDB

59

58

57

AGNDB

56

ENCBB

55

ENCB

54

AGNDB

53

52

D11B

51

D10B

50

D9B

49

D8B

48

D7B

47

D6B

46

D5B

45

D4B

44

DGNDB

J14

SMA

AGNDB

J8

SMA

AGNDB

J6

SMA

AGNDB

–5VAB

C33

0.1F

AGNDB

C17

0.1F

AGNDB

OUT 3.3VDB

C18

0.1F

DGNDB

+5VAB

C38

0.1F

C37

0.1F

REV. 0

BJ10

C29

10F

BJ9

C30

10F

+3VDA

1

+3VD B

1

C62

0.1F

C16

0.1F

@100MHz

U7

DGNDA

@100MHz

U8

DGNDB

47

20%

L1

47

20%

L2

DUT 3.3VDA

DUT 3.3VDB

BJ6

10F

BJ5

10F

AGNDB

+3VAA

1

C3

AGNDA

+5VAB

1

C4

47

20% @100MHz

L3

U1

C20

0.1F

AGNDA

47

20%@100MHz

U1

L4

C21

0.1F

AGNDB

+5VAA

+5VAB

Figure 10a. Evaluation Board

–13–

BJ2

C11

10F

BJ1

C19

10F

–5VAA

1

AGNDA

–5VAB

1

AGNDB

47

20%@100MHz

U1

L5

C32

0.1F

AGNDA

47

20%@100MHz

U1

L6

C31

0.1F

–5VAA

–5VAB

AGNDB

AD13280

DGNDA

R47
0

R48
0

DGNDA

NC0A

NC1A

DUT 3.3VDA

LSB D0A

D1A

DGNDA

D2A

D3A

D4A

D5A

DGNDA

D6A

D7A

DUT 3.3VDA

D8A

D9A

DGNDA

D10A

MSB D11A

R7

50

LATCHA

E58

LE2

25

115

26

114

27

GND

28

113

29

112

30

VCC

31

111

32

110

33

GND

34

19

35

18

36

17

37

16

38

GND

39

15

40

14

41

VCC

42

13

43

12

44

GND

45

11

46

10

47

LE1 OE1

48

74LCX16374

U8

B10A

B9A
B8A
B7A

B6A
B5A

R5

B4A

B3A
B2A
B1A

F3A
F2A

F1A
F0A

DGNDA

H40DM

1
2
3
4

5
6

7
8
9

10
11

12

13
14
15
16
17

18
19

20

J1

40
39
38
37

36
35

34
33
32
31

30
29

28
27
26
25
24

23
22

21

DGNDA

OE2

O15

O14

GND

O13

O12

VCC

O11

O10

GND

O9

O8

O7
O6

GND

O5

O4

VCC

O3

O2

GND

O1

O0

DGNDA

24

23

22

DGNDA

21

20

19

DUT 3.3VDA

18

17

16

DGNDA

15

14

13

12
11

DGNDA

10

9

8

DUT 3.3VDA

7

6

5

DGNDA

4

3

2

DGNDA

1

R18, DNI

R17, DNI

R40, DNI

R44, DNI

R45, 100

R46, 100

R15, 100

R14, 100

R13, 100

R15, 100

R24, 100

R23, 100

R22, 100

R21, 100

R20, 100

R19, 100

F0A

F1A

F2A
F3A

B0A (LSB)

B1A

B2A

B3A

B4A

B5A

B6A

B7A

B8A

B9A

B10A

B11A (MSB)

3.3VDA

C15

10F

E60

DGNDA

E61

BUFLATA

MSB B11A

50

E59

DRAOUT

LSB B0A

R49

R50

0

DGNDB

0

DGNDB

NC0B

NC1B

DUT 3.3VDB

LSB D0B

D1B

DGNDB

D2B

D3B

D4B

D5B

DGNDB

D6B

D7B

DUT 3.3VDB

D8B

D9B

DGNDB

D10B

MSB D11B

R8

50

LATCHB

E57

LE2

25

115

26

114

27

GND

28

113

29

112

30

VCC

31

111

32

110

33

GND

34

19

35

18

36

17

37

16

38

GND

39

15

40

14

41

VCC

42

13

43

12

44

GND

45

11

46

10

47

LE1 OE1

48

74LCX16374

U7

DGNDB

OE2

O15

O14

GND

O13

O12

VCC

O11

O10

GND

O9

O8

O7
O6

GND

O5

O4

VCC

O3

O2

GND

O1

O0

24

23

22

21

20

19

18

17

16

15

14

13

12
11

10

9

8

7

6

5

4

3

2

1

DGNDB

DUT 3.3VDB

R28, 100

R27, 100

DGNDB

R26, 100

R12, 100

R25, 100

DGNDB

R36, 100

R35, 100

DUT 3.3VDB

R34, 100

R33, 100

DGNDB

R32, 100

R31, 100

DGNDB

R11, DNI

R10, DNI

R30, DNI

R29, DNI

R9, 100

F0B

F1B

F2B
F3B

B0B (LSB)

B1B

B2B

B3B

B4B

B5B

B6B

B7B

B8B

B9B

B10B

B11B (MSB)

Figure 10b. Evaluation Board

3.3VDB

C14

10F

DGNDB

E63 E62

MSB B11B

E64

DRAOUT

BUFLATB

B10B

B9B
B8B
B7B

B6B
B5B

R2

B4B

50

B3B
B2B
B1B

LSB B0B

F3B
F2B
F1B
F0B

DGNDB

H40DN

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

J2

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

DGNDB

–14–

REV. 0

J5

ENCODE

SMA

AGNDA

J12

SMA

AGNDA

AGNDA

C1

0.1F

R1
50

C2

0.1F

R41
25

+5VAA

NC = NO CONNECT

DGNDA

R55

33k

1

2

3

4

NC = NO CONNECT

NC

D

U3

DB

VBB

MC10EL16

VCC

Q

QB

VEE

1

NC

2

D

3

DB

4

VBB

8

7

6

5

3

ERR

2

IN

5

SD

VCC

U2

VEE

MC10EL16

R56

33k

C6

0.47F

+3.3VDA

DGNDA

U5

5

NR

ADP3330

4

AGNDA

8

7

Q

6

QB

5

AGNDA

100

OUT

GND

C13

0.47F

AGNDA

R4

DGNDA

1

R3
100

AGNDA

R42
100

+3.3VA

R43

100

AGNDA

0.47F

1

2

3

4

NC = NO CONNECT

VCC

NC

Q0

D

U4

Q1

DB

VEE

VBB

MC100EPT23

0.1F

0.1F

C5

8

7

6

5

C7

C8

ENCAB

ENCA

+3.3VDA

DGNDA

DGND

LATCHA
E23

E19
BUFLATA

AD13280

BJ3

1

BJ4

1

BJ7

1

DGNDB

BJ8

1

DGNDA

DGNDA DGNDB

DGNDA DGNDB

AGNDB

AGNDA

DGNDB

DGNDA

E15E7E16

E12

E11
E39E8E47

J10

ENCODE

SMA

AGNDB

J11

SMA

AGNDB

R53

25

AGNDB

C22

0.1F

R54
50

C23

0.1F

+5VAB

NC = NO CONNECT

DGNDB

R39

33k

1

2

3

4

NC = NO CONNECT

NC

D

U9

DB

VBB

MC10EL16

VCC

Q

QB

VEE

1

NC

2

D

3

DB

4

VBB

8

7

6

5

3

ERR

2

5

SD

VCC

U11

VEE

MC10EL16

R38

33k

C25

0.47F

+3.3VDB

DGNDB

5

NR

ADP3330

U6

IN

GND

4

AGNDB

8

7

Q

6

QB

5

DGNDB

100

OUT

C27

0.47F

AGNDB

R6

DGNDB

1

R37
100

AGNDB

R52
100

+3.3VB

R51

100

AGNDA

0.1F

1

2

3

4

NC = NO CONNECT

VCC

NC

Q0

D

U10

Q1

DB

VEE

VBB

MC100EPT23

0.1F

0.1F

C26

8

7

6

5

C24

C28

+3.3VDA

DGNDB

ENCBB

ENCB

DGNDB

LATCHB

E24

E22

BUFLATB

E17

E18

E27

E28

E25

E26

E21

E20

E32

E31

E44

E43

E42

E41

E10

E9

E33

E34

E6

E5

DGNDA AGNDA

E38

E37

E29

E30

E1

E2

E36

E35

E14

E13

E45E3E46

E4

DGNDB AGNDB

SO1

SO4
SO5

SO2

SO6

SO3

REV. 0

Figure 10c. Evaluation Board

–15–

AD13280

Figure 11a. Top Silk

Figure 11b. Top Layer

–16–

REV. 0

Figure 11c. GND1

AD13280

REV. 0

Figure 11d. GND2

–17–

AD13280

Figure 11e. Bottom Silk

Figure 11f. Bottom Layer

–18–

REV. 0

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

68-Lead Ceramic Leaded Chip Carrier

(ES-68C)

AD13280

0.010 (0.25)

0.008 (0.20)

0.007 (0.18)

1.070

(27.18)

MIN

0.060 (1.52)

0.050 (1.27)

0.040 (1.02)

0.235 (5.97)
MAX

0.175 (4.45)
MAX

0.800

(20.32)

BSC

DETAIL A

61

9

60

PIN 1

10

0.055 (1.40)

0.050 (1.27)

0.045 (1.14)

0.960 (24.38)

0.950 (24.13) SQ

0.940 (23.88)

TOP VIEW

(PINS DOWN)

0.020 (0.508)

0.017 (0.432)

0.014 (0.356)

44

43

27

26

1.190 (30.23)

1.180 (29.97) SQ

1.170 (29.72)

REV. 0

–19–

AD13280

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

68-Lead Ceramic Leaded Chip Carrier With Non-Conductive Tie-Bar

(ES-68C)

0.960 (24.38)

0.950 (24.13) SQ

0.940 (23.88)

2.000
(8.89)

TYP

0.235 (5.97)
MAX

0.350

(8.89)

TYP

0.040 (1.02)
 45

PIN 1

TOP VIEW

(PINS DOWN)

0.800 (20.32)
BSC

DETAIL A

0.010 (0.254)

0.015 (0.3)
 45

3 PLS

0.040 (1.02) R
TYP

0.010 (0.25)

0.008 (0.20)

0.007 (0.18)

0.055 (1.40)

0.050 (1.27)

0.045 (1.14)

0.020 (0.508)

0.017 (0.432)

0.014 (0.356)

0.175 (4.45)
MAX

C02386–2.5–4/01(0)

0.050 (1.27)

0.020 (0.508)

DETAIL A

–20–

30

PRINTED IN U.S.A.

REV. 0