ANALOG DEVICES AD13280 Service Manual

Dual-Channel, 12-Bit, 80 MSPS ADC

A

FEATURES

Dual 80 MSPS, minimum sample rate Channel-to-channel matching, ±1% gain error 90 dB channel-to-channel isolation DC-coupled signal conditioning 80 dB spurious-free dynamic range Selectable bipolar inputs (±1 V and ±0.5 V ranges) Integral single-pole, low-pass Nyquist filter Twos complement output format

3.3 V compatible outputs

1.85 W per channel

FUNCTIONAL BLOCK DIAGRAM

AMP-IN-A-1

VREF

DROUT

100Ω OUTPUT TERMINATORS

TIMING

12

AMP-OUT-A

A–IN

A+IN

DROUTA

D0A (LSB)

D1A

D2A

D3A

D4A

D5A

D6A

D7A

D8A

AMP-IN-A-2

9

with Analog Input Signal

Conditioning

AD13280

APPLICATIONS

Radar processing (optimized for I/Q baseband operation) Phased array receivers Multichannel, multimode receivers GPS antijamming receivers Communications receivers

PRODUCT HIGHLIGHTS

1. Guaranteed sample rate of 80 MSPS.

2. Input signal conditioning; gain and impedance match.

3. Single-ended, differential, or off-module filter option.

4. Fully tested/characterized full channel performance.

MP-IN-B-2AMP-IN-B-1

AMP-OUT-B

B+IN

AD13280

TIMING

VREF

DROUT

12

100Ω OUTPUT TERMINATORS

3

7

5

B–IN

DROUTB

ENCODEB

D11B (MSB)

D10B

D9B

D8B

D7B

ENCODEAENCODEA

D9A D10A D11A

(MSB)

D0B

D1B D3BD2B D4B D5B D6B

(LSB)

02386-001

Figure 1.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD13280

REVISION HISTORY

4/08—Rev. B to Rev. C

Updated Outline Dimensions....................................................... 25

Changes to the Ordering Guide.................................................... 26

11/05—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Features and Product Highlights ............................... 1

Changes to General Description .................................................... 3

Changes to Table 1............................................................................ 4

Changes to Figure 3.......................................................................... 8

Changes to Theory of Operation.................................................. 14

Changes to Equation 1................................................................... 15

Changes to Table 5.......................................................................... 18

Changes to Figure 21...................................................................... 19

Changes to Figure 22...................................................................... 20

Changes to Figure 23...................................................................... 21

Changes to Figure 28 and Figure 29............................................. 24

Updated Outline Dimensions....................................................... 25

Changes to the Ordering Guide.................................................... 26

8/02—Rev. 0 to Rev. A

Edits to Specifications.......................................................................2

Packages Updated........................................................................... 19

Rev. C | Page 2 of 28

AD13280

GENERAL DESCRIPTION

The AD13280 is a complete, dual-channel, signal processing solution that includes on-board amplifiers, references, ADCs, and output termination components to provide optimized system performance. The AD13280 has on-chip track-and-hold circuitry and uses an innovative multipass architecture to achieve 12-bit, 80 MSPS performance. The AD13280 uses innovative high density circuit design and laser-trimmed thin-film resistor networks to achieve exceptional channel matching, impedance control, and performance while maintaining excellent isolation and providing for significant board area savings.

Multiple options are provided for driving the analog input, including single-ended, differential, and optional series filtering. The AD13280 also offers users a choice of analog input

signal ranges to further minimize additional external signal conditioning, while remaining general purpose.

The AD13280 operates with ±5.0 V for the analog signal conditioning with a separate 5.0 V supply for the analog-to-digital conversion and 3.3 V digital supply for the output stage. Each channel is completely independent, allowing operation with independent encode and analog inputs and maintaining minimal crosstalk and interference.

The AD13280 is available in a 68-lead, ceramic gull wing package. The components are manufactured using the Analog Devices, Inc., high speed complementary bipolar process (XFCB).

Rev. C | Page 3 of 28

AD13280

SPECIFICATIONS

AVCC = +5 V, AVEE = −5 V, DVCC = +3.3 V; applies to each ADC with front-end amplifier, unless otherwise noted.

Table 1.

AD13280AZ Parameter Temperature Test Level Min Typ Max Unit

RESOLUTION 12 Bits DC ACCURACY

No Missing Codes Full IV Guaranteed

Offset Error 25°C I −2.2 ±1.0 +2.2 % FS Full VI −2.2 ±1.0 +2.2 % FS

Offset Error Channel Match Full VI −1.0 ±0.1 +1.0 %

Gain Error

Full VI −5.0 ±2.0 +5.0 % FS

Gain Error Channel Match 25°C I −1.5 ±0.5 +1.5 % Max VI −3.0 ±1.0 +3.0 % Min VI −5 ±1.0 +5 % SINGLE-ENDED ANALOG INPUT

Input Voltage Range

AMP-IN-X-1 Full V ±0.5 V AMP-IN-X-2 Full V ±1.0 V

Input Resistance

AMP-IN-X-1 Full IV 99 100 101 Ω

AMP-IN-X-2 Full IV 198 200 202 Ω Capacitance 25°C V 4.0 7.0 pF Analog Input Bandwidth

DIFFERENTIAL ANALOG INPUT

Analog Signal Input Range

A+IN to A–IN and B+IN to B−IN Input Impedance 25°C V 618 Ω Analog Input Bandwidth Full V 50 MHz

ENCODE INPUT (ENCODE, ENCODE)

Differential Input Voltage Full IV 0.4 V p-p Differential Input Resistance 25°C V 10 kΩ Differential Input Capacitance 25°C V 2.5 pF

SWITCHING PERFORMANCE

Maximum Conversion Rate Minimum Conversion Rate Aperture Delay (tA) 25°C V 0.9 ns Aperture Delay Matching 25°C IV 250 500 ps Aperture Uncertainty (Jitter) 25°C V 0.3 ps rms ENCODE Pulse Width High at Max Conversion Rate 25°C IV 4.75 6.25 8 ns ENCODE Pulse Width Low at Max Conversion Rate 25°C IV 4.75 6.25 8 ns

Output Delay (tOD) Full V 5 ns

Encode, Rising to Data Ready, Rising Delay Full V 8.5 ns

1, 6

SNR

Analog Input @ 10 MHz 25°C I 66.5 70 dBFS

Min II 64.5 dBFS Max II 66.3 dBFS

Analog Input @ 21 MHz 25°C I 66.5 70 dBFS

Min II 64 dBFS Max II 66.3 dBFS

1

2

3

4

1

5

25°C I −3 −1.0 +1 % FS

Full V 143 MHz

Full V ±1 V

Full VI 80 MSPS Full IV 30 MSPS

Rev. C | Page 4 of 28

AD13280

AD13280AZ

Parameter Temperature Test Level Min Typ Max Unit

Analog Input @ 37 MHz 25°C I 63 65 dBFS

Min II 61.5 dBFS

Max II 63 dBFS

1, 7

SINAD

Min II 53 dBFS

Max II 54 dBFS

SPURIOUS-FREE DYNAMIC RANGE

Min II 55

Max II 55

SINGLE-ENDED ANALOG INPUT

DIFFERENTIAL ANALOG INPUT

TWO-TONE IMD REJECTION9

CHANNEL-TO-CHANNEL ISOLATION10 25°C IV 90 dB

TRANSIENT RESPONSE 25°C V 25 ns

DIGITAL OUTPUTS11

POWER SUPPLY

Analog Input @ 10 MHz 25°C I 66 69 dBFS Min II 63.5 dBFS Max II 66 dBFS Analog Input @ 21 MHz 25°C I 64 68.5 dBFS Min II 63 dBFS Max II 64 dBFS Analog Input @ 37 MHz 25°C I 54 59 dBFS

1, 8

Analog Input @ 10 MHz 25°C I 75 80 dBFS Min II 70 Max II 75 Analog Input @ 21 MHz 25°C I 68 75 dBFS Min II 67 Max II 67 Analog Input @ 37 MHz 25°C I 56 62 dBFS

Pass-Band Ripple to 10 MHz 25°C V 0.07 dB Pass-Band Ripple to 25 MHz 25°C V 0.12 dB

Pass-Band Ripple to 10 MHz 25°C V 0.3 dB Pass-Band Ripple to 25 MHz 25°C V 0.82 dB

fIN = 9.1 MHz and 10.1 MHz (f1 and f2 are −7 dBFS) 25°C I 75 80 dBc Min II 71 Max II 74 fIN = 19.1 MHz and 20.7 MHz (f1 and f2 are −7 dBFS) 25°C V 77 dBc fIN = 36 MHz and 37 MHz (f1 and f2 are −7 dBFS) 25°C V 60 dBc

Logic Compatibility CMOS DVCC = 3.3 V Logic 1 Voltage Full I 2.5 DVCC − 0.2 V Logic 0 Voltage Full I 0.2 0.5 V DVCC = 5 V Logic 1 Voltage Full V DVCC − 0.3 V Logic 0 Voltage Full V 0.35 V Output Coding Twos complement

AVCC Supply Voltage12 Full IV 4.85 5.0 5.25 V I (AVCC) Current Full I 313 364 mA AVEE Supply Voltage12 Full IV −5.25 −5.0 −4.75 V I (AVEE) Current Full I 38 49 mA DVCC Supply Voltage12 Full IV 3.135 3.3 3.465 V

Rev. C | Page 5 of 28

AD13280

AD13280AZ Parameter Temperature Test Level Min Typ Max Unit

I (DVCC) Current Full I 34 46 mA ICC (Total) Supply Current per Channel Full I 375 459 mA Power Dissipation (Total) Full I 3.7 4.3 W Power Supply Rejection Ratio (PSRR) Full V 0.01 % FSR/% VS

1

All ac specifications tested by driving ENCODE and

2

Gain tests are performed on the AMP-IN-x-1 input voltage range.

3

Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.

4

For differential input: +IN = 1 V p-p and −IN = 1 V p-p (signals are 180 Ω out of phase). For single-ended input: +IN = 2 V p-p and –IN = GND.

5

Minimum and maximum conversion rates allow for variation in encode duty cycle of 50% ± 5%.

6

Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 80 MSPS. SNR is

reported in dBFS, related back to converter full scale.

7

Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 80 MSPS. SINAD is

reported in dBFS, related back to converter full scale.

8

Analog input signal at –1 dBFS; SFDR is the ratio of converter full scale to worst spur.

9

Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third-order intermodulation product.

10

Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel.

11

Digital output logic levels: DVCC = 3.3 V, C

12

Supply voltage recommended operating range. AVCC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V.

TIMING DIAGRAM

t

A

N

A

IN

ENCODE

differentially. Single-ended input: AMP-IN-x-1 = 1 V p-p, AMP-IN-x-2 = GND.

= 10 pF. Capacitive loads >10 pF degrades performance.

LOAD

N + 1

N + 2

N + 3

ENCODE, ENCODE

D[11:0]

DRY

t

ENC

N N+1 N+2 N+3 N + 4

t

ENCH

N – 3 N – 2 N – 1

t

ENCL

t

E_DR

N + 4

t

OD

N

Figure 2.

2386-012

Rev. C | Page 6 of 28

AD13280

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Ratings

ELECTRICAL1

AVCC Voltage 0 V to 7 V AVEE Voltage −7 V to 0 V DVCC Voltage 0 V to 7 V Analog Input Voltage VEE to VCC Analog Input Current −10 mA to +10 mA Digital Input Voltage (ENCODE) 0 to VCC ENCODE, ENCODE Differential Voltage Digital Output Current −10 mA to +10 mA

ENVIRONMENTAL1

Operating Temperature Range (Case) −40°C to +85°C Maximum Junction Temperature 175°C Lead Temperature (Soldering, 10 sec) 300°C Storage Temperature Range (Ambient) −65°C to +150°C

1

Typical thermal impedance for ES package: θJC 2.2°C/W; θJA 24.3°C/W.

4 V max

Stresses above those listed under Absolute Maximum Ratings

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% production tested at 25°C, and sample tested

at specified temperatures. AC testing done on a sample basis.

III. Sample tested only.

IV. Parameter guaranteed by design and characterization

testing.

V. Parameter is a typical value only.

VI. 100% production tested with temperature at 25°C, and

sample tested at temperature extremes.

ESD CAUTION

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. C | Page 7 of 28

AD13280

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

B

CC

D11B (MSB)

AGNDB

DV

AD13280

TOP VIEW

A

NC

CC

DV

AGNDA

D10B

ENCODEB

(Not to Scale)

ENCODEA

NC = NO CONNECT

NC

D9B

D0A (LSB)

D8B

D1A

D7B

D2A

D6B

D3A

D5B

D4A

D4B

D5A

444546474849505160 59 58 57 56 55 54 53 52

DGNDB

DGNDA

43

DGNDB

42

D3B

41

D2B

40

D1B

39

D0B (LSB) NC

38

37

NC

36

DROUTB

35

SHIELD

34

DROUTA

33

D11A (MSB)

32

D10A

31

D9A

30

D8A

29

D7A

28

D6A

27

DGNDA

02386-002

AGNDB AMP-IN-B-2

AMP-IN-B-1

MP-OUT-B

B+IN

B–IN

AGNDB

SHIELD

AGNDA

A–IN

A+IN

AMP-OUT-A

AMP-IN-A-1

AMP-IN-A-2

AGNDA

B

EE

CC

AGNDB

AV

AGNDB

AV

61

62

63

64

65

66

67

68

1

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10 2611 12 13 14 15 16 17 18 19 20 21 22 23 24 25

A

EE

CC

AV

AGNDA

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1, 35 SHIELD Internal Ground Shield Between Channels. 2, 3, 9, 10, 13, 16 AGNDA A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. 4 A−IN Inverting Differential Input (Gain = +1). 5 A+IN Noninverting Differential Input (Gain = +1). 6 AMP-OUT-A Single-Ended Amplifier Output (Gain = +2). 7 AMP-IN-A-1 Analog Input for A Side ADC (Nominally ±0.5 V ). 8 AMP-IN-A-2 Analog Input for A Side ADC (Nominally ±1.0 V ). 11 AVEEA A Channel Analog Negative Supply Voltage (Nominally −5.0 V or −5.2 V). 12 AVCCA A Channel Analog Positive Supply Voltage (Nominally +5.0 V). 14

ENCODEA

Complement of ENCODEA. Differential input.

15 ENCODEA Encode Input. Conversion initiated on rising edge. 17 DVCCA A Channel Digital Positive Supply Voltage (Nominally +5.0 V/+3.3 V). 18, 19, 37, 38 NC No Connect. 20 to 25, 28 to 33

D0A to

Digital Outputs for ADC A. D0 (LSB).

D11A 26, 27 DGNDA A Channel Digital Ground. 34 DROUTA Data Ready A Output. 36 DROUTB Data Ready B Output. 39 to 42, 45 to 52

D0B to

Digital Outputs for ADC B. D0 (LSB).

D11B 43, 44 DGNDB B Channel Digital Ground. 53 DVCCB B Channel Digital Positive Supply Voltage (Nominally +5.0 V/+3.3 V).

Rev. C | Page 8 of 28

AD13280

Pin No. Mnemonic Description

54, 57, 60, 61, 67, 68 AGNDB B Channel Analog Ground. A and B grounds should be connected as close to the device as possible. 55 ENCODEB Encode Input. Conversion initiated on rising edge. 56 58 AVCCB B Channel Analog Positive Supply Voltage (Nominally +5.0 V). 59 AVEEB B Channel Analog Negative Supply Voltage (Nominally −5.0 V or −5.2 V). 62 AMP-IN-B-2 Analog Input for B Side ADC (Nominally ±1.0 V). 63 AMP-IN-B-1 Analog Input for B Side ADC (Nominally ±0.5 V). 64 AMP-OUT-B Single-Ended Amplifier Output (Gain = +2). 65 B+IN Noninverting Differential Input (Gain = +1). 66 B−IN Inverting Differential Input (Gain = +1).

ENCODEB

Complement of ENCODEB. Differential input.

Rev. C | Page 9 of 28

ANALOG DEVICES AD13280 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

TIMING DIAGRAM

ABSOLUTE MAXIMUM RATINGS

EXPLANATION OF TEST LEVELS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS