ANALOG DEVICES AD12401 Service Manual

www.BDTIC.com/ADI

12-Bit, 400 MSPS A/D Converter

FEATURES

Up to 400 MSPS sample rate SNR of 63 dBFS @128 MHz SFDR of 70 dBFS @128 MHz VSWR of 1:1.5 High or low gain grades Wideband ac-coupled input signal conditioning Enhanced spurious-free dynamic range Single-ended or differential ENCODE signal LVDS output levels Twos complement output data

APPLICATIONS

Communications test equipment Radar and satellite subsystems Phased array antennas, digital beams Multichannel, multimode receivers Secure communications Wireless and wired broadband communications Wideband carrier frequency systems

GENERAL DESCRIPTION

The AD12401 is a 12-bit analog-to-digital converter (ADC) with a transformer-coupled analog input and digital postprocessing for enhanced SFDR. The product operates at up to 400 MSPS conversion rate with outstanding dynamic performance in wideband carrier systems.

The AD12401 requires a 3.7 V analog supply and 3.3 V and

1.5 V dig that can be differential or single ended. No external reference is required.

The AD12401 package style is an enclosed 2.9" × 2.6" × 0.6" m temperature range.

ital supplies, and provides a flexible ENCODE signal

odule. Performance is rated over a 0°C to 60°C case

AD12401

FUNCTIONAL BLOCK DIAGRAM

AD12401

ADC

A

POST-

A

IN

CLK DISTRIBUTION

ADC

B

CLOCK DISTRIBUTION

DIVIDE BY 2

ENC ENC

Figure 1.

PRODUCT HIGHLIGHTS

1. Guaranteed sample rate up to 400 MSPS.

2. I

nput signal conditioning with optimized dynamic

performance to 175 MHz.

3. H

igh and low gain grades available.

4. A

dditional performance options available (sample rates >400 MSPS or second Nyquist zone operation); contact sales.

5. Propr

ietary Advanced Filter Bank (AFB™) digital post-

processing from V Corp Technologies, Inc.

PROCESSING

OROUT

DATA READY A

DA0–DA11

DB0–DB11

DR_EN

DATA READY B

005649-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD12401

www.BDTIC.com/ADI

REVISION HISTORY

4/06—Rev. 0 to Rev. A

Changes to Features and Product Highlights ............................... 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Table 4............................................................................ 6

Changes to Table 7............................................................................ 9

Changes to Figure 5........................................................................ 10

Changes to Table 9.......................................................................... 11

Added Gain Select Section ............................................................ 20

Added H/L_GAIN Section............................................................ 21

Changes to Figure 25...................................................................... 23

Changes to the Ordering Guide.................................................... 28

7/05—Revision 0: Initial Version

Ordering Guide .......................................................................... 28

Rev. A | Page 2 of 28

AD12401

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SPECIFICATIONS

DC SPECIFICATIONS

VA = 3.7 V, VC = 3.3 V, VD = 1.5 V, 0°C ≤ T

Table 1.

AD12401-xxxKWS AD12401-xxxJWS Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit

RESOLUTION 12 Bits ACCURACY

No Missing Codes Full IV Guaranteed Offset Error Full I −12 +12 −12 +12 LSB Gain Error @ 10 MHz Full I −10 +10 −10 +10 %FS Differential Nonlinearity (DNL) 60°C V ±0.3 ±0.3 LSB Integral Nonlinearity (INL) 60°C V ±0.5 ±0.5 LSB

TEMPERATURE DRIFT

Gain Error 60°C V 0.02 0.02 %/°C

ANALOG INPUT (AIN)

Full-Scale Input Voltage Range 60°C V 3.2 1.6 V p-p Flatness (10 MHz to 175 MHz) Full IV 0.5 1 0.5 1 dB Input VSWR, 50 Ω (300 kHz to 175 MHz) 60°C V 1.5 1.5 Analog Input Bandwidth 60°C V 480 480 MHz

POWER SUPPLY

Supply Voltage

VA Full IV 3.6 3.8 3.6 3.8 V VC Full IV 3.2 3.4 3.2 3.4 V VD Full IV 1.45 1.55 1.45 1.55 V

Supply Current

IVA (VA = 3.7 V) Full I 0.95 1.2 0.95 1.2 A IVC (VC = 3.3 V) Full I 400 500 400 500 mA IVD (VD = 1.5 V) Full I 0.8 1.2 0.8 1.2 A

Total Power Dissipation Full I 5.7 6.8 5.7 6.8 W

ENCODE INPUTS

Differential Inputs (ENC, ENC)

Input Voltage Full IV 0.4 0.4 V Input Resistance 60°C V 100 100 Ω Input Capacitance 60°C V 35 35 pF Common-Mode Voltage 60°C V ±3 ±3 V

Single-Ended Inputs (ENC)

Input Voltage Full IV 0.4 2 0.4 2 V p-p Input Resistance 60°C V 50 50 Ω

LOGIC INPUTS (RESET)

Logic 1 Voltage Full IV 2.0 2.0 V Logic 0 Voltage Full IV 0.8 0.8 V Source I Sink I

LOGIC INPUTS (DR_EN)

Logic 1 Voltage Full IV 1.7 1.7 V Logic 0 Voltage Full IV 0.7 0.7 V Source I Sink I

1

2

IH

IL

IH

IL

≤ 60°C, unless otherwise noted.

CASE

60°C IV 3.4 6 3.4 6 mA 60°C IV 0.9 1 0.9 1 mA

60°C IV 20 50 20 50 μA 60°C IV 30 160 30 160 μA

Rev. A | Page 3 of 28

AD12401

www.BDTIC.com/ADI

AD12401-xxxKWS AD12401-xxxJWS Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit

LOGIC OUTPUTS (DRA, DRB, OUTPUT BITS)

Differential Output Voltage Full IV 247 350 454 247 350 454 mV

Output Common-Mode Voltage Full IV 1.125 1.25 1.375 1.125 1.25 1.375 V

Output High Voltage 60°C IV 1.602 1.602 V

Output Low Voltage 60°C IV 0.898 0.898 V

1

Tested using input frequency of 70 MHz (see Figure 17).

2

Refer to Table 8 for logic convention on all logic inputs.

3

Digital output logic levels: VC = 3.3 V, C

LOAD

AC SPECIFICATIONS1—ENCODE = 400 MSPS

VA = 3.7 V, VC = 3.3 V, VD = 1.5 V, ENCODE = 400 MSPS, 0°C ≤ T

Table 2.

AD12401-400KWS AD12401-400JWS Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

SNR

Analog Input 10 MHz Full I 62 64 60 62 dBFS @ −1.0 dBFS 70 MHz Full I 61.5 63.5 59.5 61.5 dBFS

128 MHz Full I 60 63 58 61 dBFS

2

SINAD

Analog Input 10 MHz Full I 59 63.5 57 61.5 dBFS @ −1.0 dBFS 70 MHz Full I 58.5 63 56.5 61 dBFS

Spurious-Free Dynamic Range

Analog Input 10 MHz Full I 69 85 69 85 dBFS @ −1.0 dBFS 70 MHz Full I 69 80 69 80 dBFS

Image Spur

Analog Input 10 MHz Full I 60 75 60 75 dBFS @ −1.0 dBFS 70 MHz Full I 60 72 60 72 dBFS

Offset Spur

Analog Input @ −1.0 dBFS 60°C V 65 65 dBFS

Two-Tone IMD

F1, F2 @ −6 dBFS 60°C V −75 −75 dBc

ANALOG INPUT

Frequency Range Full IV 10 175 10 175 MHz DIGITAL INPUT (DR_EN)

Minimum Time (Low) Full IV 5.0 5.0 ns SWITCHING SPECIFICATIONS

Conversion Rate

Encode Pulse Width High (tEH)

Encode Pulse Width Low (tEL)

175 MHz Full I 60 62.5 57.5 60.5 dBFS

128 MHz Full I 57.5 61.5 55.5 59.5 dBFS 175 MHz Full I 55 60 53 58 dBFS

3

128 MHz Full I 66 72 66 72 dBFS 175 MHz Full I 62 68 62 68 dBFS

4

128 MHz Full I 60 66 60 66 dBFS 175 MHz Full I 57 63 57 63 dBFS

4

5

6

1

3

= 8 pF, 2.5 V LVDS, RT = 100 Ω.

Full IV 396 400 404 396 400 404 MSPS 60°C V 1.25 1.25 ns 60°C V 1.25 1.25 ns

≤ 60°C, unless otherwise noted.

CASE

Rev. A | Page 4 of 28

AD12401

www.BDTIC.com/ADI

AD12401-400KWS AD12401-400JWS Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit

DIGITAL OUTPUT PARAMETERS

Valid Time (tV) Full IV 3.9 3.9 ns Propagation Delay (tPD) 60°C V 8.7 8.7 ns Rise Time, tR (20% to 80%) 60°C V 0.3 0.3 ns Fall Time, tF (20% to 80%) 60°C V 0.3 0.3 ns DR Propagation Delay (t Data to DR Skew (t Pipeline Latency

7

Start-Up Time Full IV 29 44 87 29 44 87 ms

Postprocessing Configuration Time Full IV 2.8 2.8 sec APERTURE DELAY (tA) 60°C V 2.3 2.3 ns APERTURE UNCERTAINTY (Jitter, tJ) 60°C V 0.4 0.4 ps rms

1

All ac specifications tested with a single-ended, 2.0 V p-p encode on ENCODE and

2

The image spur is included in the SINAD measurement.

3

The image spur is not included in the SFDR specification.

4

The image spur is at fS/2 – AIN; the offset spur is at fS/2.

5

F1 = 70 MHz, F2 = 73 MHz.

6

Parts are tested with 400 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design

for encode 400 MSPS ± 1%.

7

Pipeline latency is exactly 74 cycles with an additional tPD required for data to emerge.

) 60°C V 11.2 11.2 ns

EDR

− tPD) 60°C V 2.5 2.5 ns

EDR

Full IV 74 74 Cycles

ENCODE

floating.

AC SPECIFICATIONS1—ENCODE = 360 MSPS

VA = 3.7 V, VC = 3.3 V, VD = 1.5 V, encode = 360 MSPS, 0°C ≤ T

Table 3.

AD12401-360KWS Parameter Case Temp Test Level Min Typ Max Unit

DYNAMIC PERFORMANCE

SNR

Analog Input 10 MHz Full I 62 64 dBFS @ −1.0 dBFS 70 MHz Full I 61.5 63.5 dBFS

128 MHz Full I 60 63 dBFS

2

SINAD

Analog Input 10 MHz Full I 59 63.5 dBFS @ −1.0 dBFS 70 MHz Full I 58.5 63 dBFS

128 MHz Full I 57.5 61.5 dBFS

Spurious-Free Dynamic Range

3

Analog Input 10 MHz Full I 69 85 dBFS @ −1.0 dBFS 70 MHz Full I 69 80 dBFS

128 MHz Full I 66 72 dBFS

Image Spur

4

Analog Input 10 MHz Full I 60 75 dBFS @ −1.0 dBFS 70 MHz Full I 60 72 dBFS

128 MHz Full I 60 66 dBFS

Offset Spur

4

Analog Input @ −1.0 dBFS 60°C V 65 dBFS

Two-Tone IMD

5

F1, F2 @ −6 dBFS 60°C V −75 dBc

ANALOG INPUT

Frequency Range Full IV 10 160 MHz DIGITAL INPUT (DR_EN)

Minimum Time (Low) Full IV 5.6 ns

≤ 60°C, unless otherwise noted.

CASE

Rev. A | Page 5 of 28

AD12401

www.BDTIC.com/ADI

AD12401-360KWS Parameter Case Temp Test Level Min Typ Max Unit

SWITCHING SPECIFICATIONS

Conversion Rate Encode Pulse Width High (tEH) Encode Pulse Width Low (tEL)

DIGITAL OUTPUT PARAMETERS

Valid Time (tV) Full IV 4.5 ns Propagation Delay (tPD) 60°C V 8.7 ns Rise Time, tR (20% to 80%) 60°C V 0.3 ns Fall Time, tF (20% to 80%) 60°C V 0.3 ns DR Propagation Delay (t Data to DR Skew (t Pipeline Latency Start-Up Time Full IV 29 44 87 ms

Postprocessing Configuration Time Full IV 3.1 sec APERTURE DELAY (tA) 60°C V 2.3 ns APERTURE UNCERTAINTY (Jitter, tJ) 60°C V 0.4 ps rms

1

All ac specifications tested with a single-ended, 2.0 V p-p encode on ENCODE and

2

The image spur is included in the SINAD specification.

3

The image spur is not included in the SFDR specification.

4

The image spur is at fS/2 – AIN; the offset spur is at fS/2.

5

F1 = 70 MHz, F2 = 73 MHz.

6

Parts are tested with 360 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design

for encode 360 MSPS ± 1%.

7

Pipeline latency is exactly 74 cycles with an additional tPD required for data to emerge.

6

1

) 60°C V 11.5 ns

EDR

− tPD) 60°C V 2.8 ns

EDR

7

Full IV 356 360 364 MSPS 60°C V 1.38 ns 60°C V 1.38 ns

Full IV 74 Cycles

ENCODE

floating.

AC SPECIFICATIONS1—ENCODE = 326 MSPS

VA = 3.7 V, VC = 3.3 V, VD = 1.5 V, ENCODE = 326 MSPS, 0°C ≤ T

Table 4.

AD12401-326KWS AD12401-326JWS Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

SNR

Analog Input 10 MHz Full I 62 64 60 62 dBFS @ −1.0 dBFS 70 MHz Full I 61.5 63.5 59.5 61.5 dBFS

128 MHz Full I 60 63 58 61 dBFS

2

SINAD

Analog Input 10 MHz Full I 59 63.5 57 61.5 dBFS @ −1.0 dBFS 70 MHz Full I 58.5 63 56.5 61 dBFS

128 MHz Full I 57.5 61.5 55.5 59.5 dBFS

Spurious-Free Dynamic Range

3

Analog Input 10 MHz Full I 69 85 69 85 dBFS @ −1.0 dBFS 70 MHz Full I 69 80 69 80 dBFS

128 MHz Full I 66 72 66 72 dBFS

Image Spur

4

Analog Input 10 MHz Full I 60 75 60 75 dBFS @ −1.0 dBFS 70 MHz Full I 60 72 60 72 dBFS 128 MHz Full I 60 66 60 66 dBFS

Offset Spur

5

Analog Input @ −1.0 dBFS 60°C V 65 65 dBFS

Two-Tone IMD

5

F1, F2 @ −6 dBFS 60°C V −75 −75 dBc

≤ 60°C, unless otherwise noted.

CASE

Rev. A | Page 6 of 28

AD12401

www.BDTIC.com/ADI

AD12401-326KWS AD12401-326JWS Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit

ANALOG INPUT

Frequency Range Full IV 10 140 10 140 MHz

DIGITAL INPUT (DR_EN)

Minimum Time (Low) Full IV 6.2 6.2 ns

SWITCHING SPECIFICATIONS

Conversion Rate Encode Pulse Width High (tEH) Encode Pulse Width Low (tEL)

DIGITAL OUTPUT PARAMETERS

Valid Time (tV) Full IV 5.0 5.0 ns Propagation Delay (tPD) 60°C V 8.7 8.7 ns Rise Time, tR (20% to 80%) 60°C V 0.3 0.3 ns Fall Time, tF (20% to 80%) 60°C V 0.3 0.3 ns DR Propagation Delay (t Data to DR Skew (t Pipeline Latency Start-Up Time Full IV 29 44 87 29 44 87 ms

Postprocessing Configuration Time Full IV 3.4 3.4 sec APERTURE DELAY (tA) 60°C V 2.3 2.3 ns APERTURE UNCERTAINTY (Jitter, tJ) 60°C V 0.4 0.4 ps rms

1

All ac specifications tested with a single-ended, 2.0 V p-p encode on ENCODE and

2

The image spur is included in the SINAD measurement.

3

The image spur is not included in the SFDR specification.

4

The image spur is at fS/2 − AIN; the offset spur is at fS/2.

5

F1 = 70 MHz, F2 = 73 MHz.

6

Parts are tested with 326 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design

for encode 326 MSPS ±1%.

7

Pipeline latency is exactly 74 cycles with an additional tPD required for data to emerge.

6

1

) 60°C V 11.8 11.8 ns

EDR

− tPD) 60°C V 3.1 3.1 ns

EDR

7

Full IV 323 326 329 323 326 329 MSPS 60°C V 1.53 1.53 ns 60°C V 1.53 1.53 ns

Full IV 74 74 Cycles

ENCODE

floating.

Rev. A | Page 7 of 28

AD12401

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Value

VA to AGND 5 V VC to DGND 4 V VD to DGND 1.6 V max Analog Input Voltage 6 V (dc) Analog Input Power 18 dBm (ac) ENCODE Input Voltage 6 V (dc) ENCODE Input Power 12 dBm (ac) Logic Inputs −0.3 V to +4 V Storage Temperature Range, Ambient −65°C to +150°C Operating Temperature Range 0°C to 60°C

EXPLANATION OF TEST LEVELS

Table 6.

Level Description

I 100% production tested. II 100% production tested at 25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI

100% production tested at 25°C; guaranteed by design and charac production tested at temperature extremes for military devices.

Stresses above those listed under Absolute Maximum Ratings

y cause permanent damage to the device. This is a stress

ma rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

terization testing for industrial temperature range; 100%

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 8 of 28

AD12401

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Table 7. Output Coding (Twos Complement)

A

(V)

IN

Code KWS JWS Digital Output

4095 +1.6 +0.8 0111 1111 1111

. . . .

2048 0 0 0000 0000 0000 2047 −0.000781 to +0.0003905 1111 1111 1111

. . . .

0 −1.6 to +0.8 1000 0000 0000

N

ENC

400MHZ

DATA OUT A

N– 1

t

EL

t

EH

N + 1

N + 2

N + 3

1/f

S

74 CLOCK CYCLES

N – 74

N – 73

Table 8. Option Pin List with Necessary Associated Circuitry

Logic Pin Name

RESET

Active High

Lev

Typ e

el

Default Lev

Associated Circuitry

el

Within Part

Low LVTTL High 3.74 kΩ Pull-Up

DR_EN High LVTTL High Weak Pull-Up (>16 kΩ)

3.3V

100Ω

PECL

DRIVER

05649-002

ENCODE

3.3V

Figure 2. ENCODE Equivalent Circuit

N

N + 2

1

N + 4 N + 6 N + 8

DRA DRA

DATA OUT B

DRB DRB

DR_EN

NOTES

1. DATA LOST DUE TO ASSERTION OF DR_EN. LATENCY OF 74 ENCODE CLOCK CYCLES BEFORE DATA VALID.

2. IF A SINGLE-ENDED SINE WAVE IS USED FOR ENCODE, USE THE ZERO CROSSING POINT (AC-COUPLED) AS THE 50% POINT AND APPLY THE SAME TIMING INFORMATION.

3. THE DR_EN PIN IS USED TO SYNCHRONIZE THE COLLECTION OF DATA INTO EXTERNAL BUFFER MEMORIES. THE DR_EN PIN CAN BE APPLIED SYNCHRONOUSLY OR ASYNCHRONOUSLY TO THE AD12401. IF APPLIED ASYNCHRONOUSLY, DR_EN MUST BE HELD LOW FOR A MINIMUM OF 5ns TO ENSURE CORRECT OPERATION. THE FUNCTION SHUTS OFF DRA AND DRB UNTIL THE DR_EN PIN IS SET HIGH AGAIN. DRA AND DRB RESUME ON THE NEXT VALID DRA AFTER DR_EN IS RETURNED HIGH. IF THIS FEATURE IS NOT REQUIRED, TIE THIS PIN TO 3.3V THROUGH A 3.74kΩ RESISTOR OR LEAVE IT FLOATING.

N + 1

N + 3 N + 5 N + 7

1

Figure 3. Timing Diagram

t

EDR

ENC

DATA OUT

DR

t

PD

t

VD

Figure 4. Highlighted Timing Diagram

05649-004

05649-003

Rev. A | Page 9 of 28

ANALOG DEVICES AD12401 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

EXPLANATION OF TEST LEVELS

ESD CAUTION