Analog Devices AD538SD, AD538BD, AD538AD, AD539SE-883B, AD539SD-883B Datasheet

REV. C

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a

AD538

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

Real-Time Analog

Computational Unit (ACU)

FUNCTIONAL BLOCK DIAGRAM

25kV

25kV

LOG

RATIO

100V

25kV

25kV

ANTILOG

LOG

OUTPUT

100V

AD538

INTERNAL
VOLTAGE

REFERENCE

I

V

O

I

Z

V

Z

B

+10V

–V

S

+V

S

+2V

I

Y

A

D

I

X

V

X

C

PWR
GND

SIGNAL
GND

V

Y

118

17

16

15

14

13

12

11

10

2

3

4

5

6

7

8

9

FEATURES

V

OUT

= VY

V

Z

V

X











m

Transfer Function

Wide Dynamic Range (Denominator) –1000:1
Simultaneous Multiplication and Division
Resistor-Programmable Powers and Roots
No External Trims Required
Low Input Offsets <100 ␮V
Low Error ⴞ0.25% of Reading (100:1 Range)
+2 V and +10 V On-Chip References
Monolithic Construction

APPLICATIONS
One- or Two-Quadrant Mult/Div
Log Ratio Computation
Squaring/Square Rooting
Trigonometric Function Approximations
Linearization Via Curve Fitting
Precision AGC
Power Functions

PRODUCT DESCRIPTION

The AD538 is a monolithic real-time computational circuit that
provides precision analog multiplication, division and exponen­tiation. The combination of low input and output offset voltages
and excellent linearity results in accurate computation over an
unusually wide input dynamic range. Laser wafer trimming makes
multiplication and division with errors as low as 0.25% of read-

ing possible, while typical output offsets of 100 µV or less add to

the overall off-the-shelf performance level. Real-time analog
signal processing is further enhanced by the device’s 400 kHz
bandwidth.

The AD538’s overall transfer function is VO = VY (VZ/VX)m.
Programming a particular function is via pin strapping. No
external components are required for one-quadrant (positive
input) multiplication and division. Two-quadrant (bipolar
numerator) division is possible with the use of external level
shifting and scaling resistors. The desired scale factor for both
multiplication and division can be set using the on-chip +2 V or
+10 V references, or controlled externally to provide simulta­neous multiplication and division. Exponentiation with an m
value from 0.2 to 5 can be implemented with the addition of
one or two external resistors.

Direct log ratio computation is possible by using only the log
ratio and output sections of the chip. Access to the multiple
summing junctions adds further to the AD538’s flexibility.

Finally, a wide power supply range of ±4.5 V to ±18 V allows
operation from standard ±5 V, ±12 V and ±15 V supplies.

The AD538 is available in two accuracy grades (A and B) over

the industrial (–25°C to +85°C) temperature range and one
grade (S) over the military (–55°C to +125°C) temperature

range. The device is packaged in an 18-lead TO-118 hermetic
side-brazed ceramic DIP. A-grade chips are also available.

PRODUCT HIGHLIGHTS

1. Real-time analog multiplication, division and exponentiation.

2. High accuracy analog division with a wide input dynamic
range.

3. On-chip +2 V or +10 V scaling reference voltages.

4. Both voltage and current (summing) input modes.

5. Monolithic construction with lower cost and higher reliability
than hybrid and modular circuits.

–2–

REV. C

AD538–SPECIFICATIONS

AD538AD AD538BD AD538SD

Parameters Conditions Min Typ Max Min Typ Max Min Typ Max Units

MULTIPLIER DIVIDER
PERFORMANCE

Nominal Transfer
Function

10 V ≥ V

X

, VY, V

Z

≥ 0V

O

= V

Y

V

Z

V

X











m

VO = Vy

V

Z

V

X











m

VO = V

Y

V

Z

V

X











m

400 µA ≥ I

X

, IY, I

Z

≥ 0VO = 25 kΩ × I

Y

I

Z

I

X











m

V

O

= 25 kΩ × I

Y

I

Z

I

X











m

V

O

= 25 kΩ × I

Y

I

Z

I

X











m

Total Error Terms 100 mV ≤ VX ≤ 10 V ±0.5 ⴞ1 ±0.25 ⴞ0.5 ± 0.5 ⴞ1 % of Reading +

100:1 Input Range

1

100 mV ≤ VY ≤ 10 V ±200 ⴞ500 ±100 ⴞ250 ±200 ⴞ500 µV
100 mV ≤ VZ ≤ 10 V

V

Z

≤ 10 V

X

, m = 1.0

TA = T

MIN

to T

MAX

±1 ⴞ2 ±0.5 ⴞ1 ±1.25 ⴞ2.5 % of Reading +
±450 ⴞ750 ±350 ⴞ500 ±750 ⴞ1000 µV

Wide Dynamic Range

2

10 mV ≤ VX ≤ 10 V ±1 ⴞ2 ±0.5 ⴞ1 ±1 ⴞ2 % of Reading +
1 mV ≤ VY ≤ 10 V ±200 ⴞ500 ±100 ⴞ250 ±200 ⴞ500 µV +
0 mV ≤ VZ ≤ 10 V ±100 ⴞ250 ±750 ⴞ150 ±200 ⴞ250 µV × (V

Y

+ VZ)/V

X

V

Z

≤ 10 V

X

, m = 1.0

TA = T

MIN

to T

MAX

±1 ⴞ3 ±1 ⴞ2 ±2 ⴞ4 % of Reading +
±450 ⴞ750 ±350 ⴞ500 ±750 ⴞ1000 µV +
±450 ⴞ750 ±350 ⴞ500 ±750 ⴞ1000 µV × (V

Y

+ VZ)/V

X

Exponent (m) Range TA = T

MIN

to T

MAX

0.2 5 0.2 5 0.2 5

OUTPUT

CHARACTERISTICS

Offset Voltage V

Y

= 0, V

C

= –600 mV ±200 ⴞ500 ±100 ⴞ250 ±200 ⴞ500 µV

TA = T

MIN

to T

MAX

±450 ⴞ750 ±350 ⴞ500 ±750 ⴞ1000 µV

Output Voltage Swing R

L

= 2 kΩ –11 +11 –11 +11 –11 +11 V

Output Current 5 10 5 10 5 10 mA

FREQUENCY RESPONSE

Slew Rate 1.4 1.4 1.4 V/µs
Small Signal Bandwidth 100 mV ≤ 10 V

Y

, VZ, 400 400 400 kHz

V

X

≤ 10 V

VOLTAGE REFERENCE

Accuracy V

REF

= 10 V or 2 V ±25 ⴞ50 ±15 ⴞ25 ±25 ⴞ50 mV

Additional Error TA = T

MIN

or T

MAX

±20 ⴞ30 ± 20 ⴞ30 ±30 ⴞ50 mV

Output Current V

REF

= 10 V to 2 V 1 2.5 1 2.5 1 2.5 mA

Power Supply Rejection

+2 V = V

REF

±4.5 V ≤ VS ≤ ± 18 V 300 600 300 600 300 600 µV/V

+10 V = V

REF

±13 V ≤ VS ≤ ±18 V 200 500 200 500 200 500 µV/V

POWER SUPPLY

Rated R

L

= 2 kΩ±15 ± 15 ±15 V

Operating Range

3

ⴞ4.5 ⴞ18 ⴞ4.5 ⴞ18 ⴞ4.5 ⴞ18 V

PSRR ±4.5 V < VS < ±18 V 0.5 0.1 0.05 0.1 0.5 0.1 %/V

VX = VY = VZ = 1 V
V

OUT

= 1 V

Quiescent Current 4.5 7 4.5 7 4.5 7 mA

TEMPERATURE RANGE

Rated –25 +85 –25 +85 –55 +125 °C
Storage –65 +150 –65 +150 –65 +150 °C

PACKAGE OPTIONS

Ceramic (D-18) AD538AD AD538BD AD538SD

AD538SD/883B

Chips AD538ACHIPS

NOTES

1

Over the 100 mV to 10 V operating range total error is the sum of a percent of reading term and an output offset. With this input dynamic range the input offset
contribution to total error is negligible compared to the percent of reading error. Thus, it is specified indirectly as a part of the percent of reading error.

2

The most accurate representation of total error with low level inputs is the summation of a percent of reading term, an output offset and an input offset multiplied by
the incremental gain (VY + VZ) VX.

3

When using supplies below ±13 V, the 10 V reference pin must be connected to the 2 V pin in order for the AD538 to operate correctly.

Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

(VS = ⴞ15 V, TA = +25ⴗC unless otherwise noted)

AD538

–3–

REV. C

RE-EXAMINATION OF MULTIPLIER/DIVIDER
ACCURACY

Traditionally, the “accuracy” (actually the errors) of analog
multipliers and dividers have been specified in terms of percent
of full scale. Thus specified, a 1% multiplier error with a 10 V
full-scale output would mean a worst case error of +100 mV at
“any” level within its designated output range. While this type
of error specification is easy to test evaluate, and interpret, it can
leave the user guessing as to how useful the multiplier actually is
at low output levels, those approaching the specified error limit
(in this case) 100 mV.

The AD538’s error sources do not follow the percent of full­scale approach to specification, thus it more optimally fits the
needs of the very wide dynamic range applications for which it is
best suited. Rather than as a percent of full scale, the AD538’s
error as a multiplier or divider for a 100:1 (100 mV to 10 V)
input range is specified as the sum of two error components: a
percent of reading (ideal output) term plus a fixed output offset.
Following this format the AD538AD, operating as a multiplier

or divider with inputs down to 100 mV, has a maximum error of

±1% of reading ±500 µV. Some sample total error calculations

for both grades over the 100:1 input range are illustrated in the
chart below. This error specification format is a familiar one to
designers and users of digital voltmeters where error is specified

as a percent of reading ± a certain number of digits on the meter

readout.

For operation as a multiplier or divider over a wider dynamic
range (>100:1), the AD538 has a more detailed error specifica­tion that is the sum of three components: a percent of reading
term, an output offset term and an input offset term for the
V

Y/VX

log ratio section. A sample application of this specifica-

tion, taken from Table I, for the AD538AD with V

Y

= 1 V, VZ =

100 mV and V

X

= 10 mV would yield a maximum error of

±2.0% of reading ±500 µV ±(1 V + 100 mV)/10 mV × 250 µV
or ±2.0% of reading ±500 µV ± 27.5 mV. This example illus-

trates that with very low level inputs the AD538’s incremental
gain (V

Y

+ VZ)/VX has increased to make the input offset contri-

bution to error substantial.

Table I. Sample Error Calculation Chart (Worst Case)

V

Y

V

Z

V

X

Ideal Total Offset % of Reading Total Error Total Error Summation
Input Input Input Output Error Term Error Term Summation as a % of the Ideal
(in V) (in V) (in V) (in V) (in mV) (in mV) (in mV) Output

100:1 10 10 10 10 0.5 (AD) 100 (AD) 100.5 (AD) 1.0 (AD)

INPUT 0.25 (BD) 50 (BD) 50.25 (BD) 0.5 (BD)

RANGE

Total Error = 10 0.1 0.1 10 0.5 (AD) 100 (AD) 100.5 (AD) 1.0 (AD)

±% rdg 0.25 (BD) 50 (BD) 50.25 (BD) 0.5 (BD)

±Output V

OS

1 1 1 1 0.5 (AD) 10 (AD) 10.5 (AD) 1.05 (AD)

0.25 (BD) 5 (BD) 5.25 (BD) 0.5 (BD)

0.1 0.1 0.1 0.1 0.5 (AD) 1 (AD) 1.5 (AD) 1.5 (AD)

0.25 (BD) 0.5 (BD) 0.75 (BD) 0.75 (BD)

WIDE 1 0.10 0.01 10 28 (AD) 200 (AD) 228 (AD) 2.28 (AD)

DYNAMIC 16.75 (BD) 100 (BD) 116.75 (BD) 1.17 (BD)

RANGE

Total Error = 10 0.05 2 0.25 1.76 (AD) 5 (AD) 6.76 (AD) 2.7 (AD)

±% rdg 1 (BD) 2.5 (BD) 3.5 (BD) 1.4 (BD)

±Output V

OS

±Input VOS × 5 0.01 0.01 5 125.75 (AD) 100 (AD) 225.75 (AD) 4.52 (AD)

(V

Y

+ VZ)/V

X

75.4 (BD) 50 (BD) 125.4 (BD) 2.51 (BD)

10 0.01 0.1 1 25.53 (AD) 20 (AD) 45.53 (AD) 4.55 (AD)

15.27 (BD) 10 (BD) 25.27 (BD) 2.53 (BD)

AD538

–4–

REV. C

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD538AD –25°C to +85°C Side-Brazed Ceramic DIP D-18
AD538BD –25°C to +85°C Side-Brazed Ceramic DIP D-18
AD538ACHIPS –25°C to +85°C Chips
AD538SD –55°C to +125°C Side-Brazed Ceramic DIP D-18
AD538SD/883B –55°C to +125°C Side-Brazed Ceramic DIP D-18

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 250 mW

Output Short Circuit-to-Ground . . . . . . . . . . . . . . . Indefinite

Input Voltages V

X

, VY, VZ . . . . . . . . . . . . . (+VS – 1 V), –1 V

Input Currents I

X

, IY, IZ, IO . . . . . . . . . . . . . . . . . . . . . . 1 mA

Operating Temperature Range . . . . . . . . . . . –25°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature, Storage . . . . . . . . . . . . . . 60 sec, +300°C

Thermal Resistance

θ

JC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35°C/W

θ

JA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W

PIN CONFIGURATION

1
2

18
17

5
6
7

14
13
12

3
4

16
15

8

11

910

I

Z

V

Z

A
D

+2V
+V

S

–V

S

PWR GND
C

B

+10V

I

X

V

O

I

Y

IV

Y

SIGNAL GND

V

X

AD538

TOP VIEW

(Not to Scale)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD538 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE