Datasheet AD7982 Datasheet (ANALOG DEIVCES)

18-Bit, 1 MSPS PulSAR 7.0 mW

V

V

±

www.BDTIC.com/ADI

FEATURES

18-bit resolution with no missing codes
Throughput: 1 MSPS
Low power dissipation

7.0 mW at 1 MSPS

70 μW at 10 kSPS
INL: ±1 LSB typical, ±2 LSB maximum
Dynamic range: 99 dB
True differential analog input range: ±V

0 V to V

with V

REF

between 2.5 V to 5.0 V

REF

Allows use of any input range

Easy to drive with the ADA4941
No pipeline delay
Single-supply 2.5 V operation with

interface
Serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Ability to daisy-chain multiple ADCs and busy indicator
10-lead package: MSOP (MSOP-8 size) and 3 mm × 3 mm QFN

(LFCSP

), SOT-23 size

APPLICATIONS

Battery-powered equipment
Data acquisition systems
Medical instruments
Seismic data acquisition systems

REF

1.8 V/2.5 V/3 V/5 V logic

ADC in MSOP/QFN

AD7982

APPLICATION DIAGRAM EXAMPLE

2.5V TO 5

10V, ±5V, ..

ADA4941

GENERAL DESCRIPTION

The AD7982 is an 18-bit, successive approximation, analog-to­digital converter (ADC) that operates from a single power supply,
VDD. It contains a low power, high speed, 18-bit sampling ADC
and a versatile serial interface port. On the CNV rising edge,
the AD7982 samples the voltage difference between the IN+
and IN− pins. The voltages on these pins usually swing in
opposite phases between 0 V and V
REF, is applied externally and can be set independent of the
supply voltage, VDD. Its power scales linearly with throughput.

The SPI-compatible serial interface also features the ability,
usin

g the SDI input, to daisy-chain several ADCs on a single
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply.

REF

IN+

AD7982

IN–

GND

Figure 1.

2.5

VIO

VDD

SDI

SCK

SDO

CNV

. The reference voltage,

REF

1.8V TO 5V

3- OR 4-WI RE
INTERFACE
(SPI, CS
DAISY CHAIN)

06513-001

The AD7982 is available in a 10-lead MSOP or a 10-lead QFN
(LFCS

P) with operation specified from −40°C to +85°C.

Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR® ADCs

Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver

18-Bit True Differential AD7691 AD7690 AD7982 ADA4941
AD7984 ADA4841
16-Bit True Differential AD7684 AD7687 AD7688 ADA4941
AD7693 ADA4841
16-Bit Pseudo Differential AD7680 AD7685 AD7686 AD7980 ADA4841
AD7683 AD7694
14-Bit Pseudo Differential AD7940 AD7942 AD7946 ADA4841

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

AD7982

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TABLE OF CONTENTS

Features .............................................................................................. 1

Driver Amplifier Choice ........................................................... 14

Applications....................................................................................... 1

Application Diagram Example........................................................1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ...........................7

Te r mi n ol o g y ...................................................................................... 8

Typical Performance Characteristics............................................. 9

Theory of Operation ...................................................................... 12

Circuit Information.................................................................... 12

Converter Operation.................................................................. 12

Typical Con ne ction Diag ram ................................................... 13

Analog Inputs.............................................................................. 14

Single-to-Differential Driver .................................................... 15

Voltage Reference Input ............................................................ 15

Power Supply............................................................................... 15

Digital Interface.......................................................................... 16

CS

Mode, 3-Wire Without Busy Indicator .............................17

CS

Mode, 3-Wire with Busy Indicator.................................... 18

CS

Mode, 4-Wire Without Busy Indicator .............................19

CS

Mode, 4-Wire with Busy Indicator.................................... 20

Chain Mode Without Busy Indicator...................................... 21

Chain Mode with Busy Indicator............................................. 22

Application Hints ........................................................................... 23

Layout ..........................................................................................23

Evaluating AD7982 Performance............................................. 23

Outline Dimensions .......................................................................24

Ordering Guide .......................................................................... 24

REVISION HISTORY

10/07—Rev. 0 to Rev. A

Changes to Table 1 and Layout....................................................... 1

Changes to Table 2............................................................................ 3

Changes to Layout............................................................................ 5

Changes to Layout............................................................................ 6

Changes to Figure 5.......................................................................... 7

Changes to Figure 18 and Figure 20............................................. 11

Changes to Figure 23...................................................................... 13

Changers to Figure 26.................................................................... 15

Changes to Digital Interface Section............................................ 16

Changes to Figure 38...................................................................... 21

Changes to Figure 40...................................................................... 22

Updated Outline Dimensions....................................................... 24

Changes to Ordering Guide.......................................................... 24

3/07—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD7982

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SPECIFICATIONS

VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = −40°C to +85°C, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

RESOLUTION 18 Bits
ANALOG INPUT

Voltage Range IN+ − IN− −V

REF

Absolute Input Voltage IN+, IN− −0.1 V
Common-Mode Input Range IN+, IN− V

× 0.475 V

REF

Analog Input CMRR fIN = 450 kHz 67 dB
Leakage Current at 25°C Acquisition phase 200 nA
Input Impedance See the Analog Inputs section

ACCURACY

No Missing Codes 18 Bits
Differential Linearity Error −0.85 ±0.5 +1.5 LSB
Integral Linearity Error −2 ±1 +2 LSB
Transition Noise REF = 5 V 1.05 LSB
Gain Error, T

MIN

to T

MAX

2

−0.023 +0.004 +0.023 % of FS
Gain Error Temperature Drift ±1 ppm/°C
Zero Error, T

MIN

to T

MAX

2

±100 +700 μV
Zero Temperature Drift 0.5 ppm/°C
Power Supply Rejection Ratio VDD = 2.5 V ± 5% 90 dB

THROUGHPUT

Conversion Rate 0 1 MSPS
Transient Response Full-scale step 290 ns

AC ACCURACY

Dynamic Range V
V
Oversampled Dynamic Range

4

Signal-to-Noise fIN = 1 kHz, V
f

= 5 V 97 99 dB

REF

= 2.5 V 93 dB

REF

FO = 1 kSPS 129 dB

= 5 V, TA = 25°C 95.5 98 dB

REF

= 1 kHz, V

IN

= 2.5 V, TA = 25°C 92.5 dB

REF

Spurious-Free Dynamic Range fIN = 10 kHz −115 dB
Total Harmonic Distortion
Signal-to-(Noise + Distortion) fIN = 1 kHz, V

1

LSB means least significant bit. With the ±5 V input range, 1 LSB is 38.15 μV.

2

See Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.

3

All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

4

Dynamic range is obtained by oversampling the ADC running at a throughput Fs of 1 MSPS followed by postdigital filtering with an output word rate of FO.

5

Tested fully in production at fIN = 1 kHz.

5

fIN = 10 kHz −120 dB

= 5 V, TA = 25°C 97 dB

REF

+V

× 0.5 V

REF

REF

+ 0.1 V

REF

× 0.525 V

REF

V

1

1

1

3

3

3

3

3

3

3

3

Rev. A | Page 3 of 24

AD7982

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VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = −40°C to +85°C, unless otherwise noted.

Table 3.

Parameter Conditions Min Typ Max Unit

REFERENCE

Voltage Range 2.4 5.1 V
Load Current 1 MSPS, REF = 5 V 350 μA

SAMPLING DYNAMICS

−3 dB Input Bandwidth 10 MHz
Aperture Delay VDD = 2.5 V 2 ns

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format Serial 18 bits, twos complement
Pipeline Delay

VOL I
VOH I

POWER SUPPLIES

VDD 2.375 2.5 2.625 V
VIO Specified performance 2.3 5.5 V
VIO Range 1.8 5.5 V
Standby Current

1, 2

Power Dissipation 10 kSPS throughput 70 86 μW
1 MSPS throughput 7.0 8.6 mW
Energy per Conversion 7.0 nJ/sample

TEMPERATURE RANGE

3

Specified Performance T

1

With all digital inputs forced to VIO or GND as required.

2

During acquisition phase.

3

Contact an Analog Devices, Inc. sales representative for the extended temperature range.

VIO > 3 V –0.3 +0.3 × VIO V
VIO > 3 V 0.7 × VIO VIO + 0.3 V
VIO ≤ 3 V –0.3 +0.1 × VIO V
VIO ≤ 3 V 0.9 × VIO VIO + 0.3 V

−1 +1 μA

−1 +1 μA

Conversion results available immediately

ter completed conversion

af

= +500 μA 0.4 V

SINK

= −500 μA VIO − 0.3 V

SOURCE

VDD and VIO = 2.5 V, 25°C 0.35 μA

MIN

to T

MAX

−40 +85 °C

Rev. A | Page 4 of 24

AD7982

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TIMING SPECIFICATIONS

CONV

ACQ

CYC

t

CNVH

t

SCK

SCK

SCKL

SCKH

HSDO

DSDO

t

EN

t

DIS

SSDICNV

t

HSDICNV

HSDICNV

SSCKCNV

HSCKCNV

SSDISCK

HSDISCK

DSDOSDI

1

500 710 ns
290 ns
1000 ns
10 ns

4.5 ns

4.5 ns
3 ns

20 ns
5 ns
2 ns
0 ns
5 ns
5 ns
2 ns
3 ns
15 ns

TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted.

Table 4.

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time Between Conversions t
CNV Pulse Width (CS Mode)

SCK Period (CS Mode)

VIO Above 4.5 V 10.5 ns
VIO Above 3 V 12 ns
VIO Above 2.7 V 13 ns
VIO Above 2.3 V 15 ns

SCK Period (Chain Mode) t

VIO Above 4.5 V 11.5 ns
VIO Above 3 V 13 ns
VIO Above 2.7 V 14 ns
VIO Above 2.3 V 16 ns

SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t

VIO Above 4.5 V 9.5 ns
VIO Above 3 V 11 ns
VIO Above 2.7 V 12 ns
VIO Above 2.3 V 14 ns

CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO Above 3 V 10 ns
VIO Above 2.3 V 15 ns

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge t
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode) t
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with Busy Indicator) t

1

See Figure 2 and Figure 3 for load conditions.

500µA I

TO SDO

20pF

C

L

500µA I

Figure 2. Load Circuit for Di

OL

1.4V

OH

06513-002

gital Interface Timing

1

X% VIO

t

DELAY

V

IH

V

IL

1

FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VI O > 3.0V, X = 70, AND Y = 30.

2

MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS

SPECIFICATIONS IN TABLE 3.

Figure 3. Voltage Levels for Timing

Rev. A | Page 5 of 24

1

Y% VIO

t

DELAY

2

2

2

V

IH

2

V

IL

06513-003

AD7982

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ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs

IN+, IN− to GND

Supply Voltage

REF, VIO to GND −0.3 V to +6.0 V
VDD to GND −0.3 V to +3.0 V

VDD to VIO +3 V to −6 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance

10-Lead MSOP 200°C/W

10-Lead QFN (LFCSP_WD) 48.7°C/W
θJC Thermal Impedance

10-Lead MSOP 44°C/W

10-Lead QFN (LFCSP_WD) 2.96°C/W
Lead Temperatures

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

1

See the Analog Inputs section for an explanation of IN+ and IN−.

1

−0.3 V to V
or ±130 mA

+ 0.3 V

REF

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 6 of 24

AD7982

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

REF

VDD

2

AD7982

IN+

3

TOP VIEW

(Not to Scale)

IN–

4

GND

5

Figure 4. 10-Lead MSOP Pin Configuration

10

VIO

SDI

9

SCK

8

SDO

7

CNV

6

06513-004

1REF

2VDD

AD7982

3IN+

TOP VIEW

4IN–

5GND

Figure 5. 10-Lead QFN (LFCSP) Pin Configuration

10 VIO

9SDI

8SCK

7SDO

6 CNV

06513-005

Table 6. Pin Function Descriptions

Pin
No. Mnemonic Type

1 REF AI

1

Description

Reference Input Voltage. The REF range is 2.4 V to 5.1 V

. This pin is referred to the GND pin and should

be decoupled closely to the GND pin with a 10 μF capacitor.
2 VDD P Power Supply.
3 IN+ AI Differential Positive Analog Input.
4 IN− AI Differential Negative Analog Input.
5 GND P Power Supply Ground.
6 CNV DI

Convert Input. This input has multiple functions. On its leading

selects the interface mode of the part: chain mode or CS

edge, it initiates the conversions and

mode. In CS mode, the SDO pin is enabled

when CNV is low. In chain mode, the data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:

Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to

daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is

output on SDO with a delay of 18 SCK cycles.

CS

mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator
feature is enabled.

10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).

1

AI = analog input, DI = digital input, DO = digital output, and P = power.

Rev. A | Page 7 of 24

AD7982

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TERMINOLOGY

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line

wn from negative full scale through positive full scale. The

dra
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maxim

um deviation from this ideal value. It is often specified in

terms of resolution for which no missing codes are guaranteed.

Zero Error

Zero error is the difference between the ideal midscale voltage,
t

hat is, 0 V, from the actual voltage producing the midscale

output code, that is, 0 LSB.

Gain Error

The first transition (from 100 ... 00 to 100 ... 01) should occur at
a leve

l ½ LSB above nominal negative full scale (−4.999981 V
for the ±5 V range). The last transition (from 011 … 10 to
011 … 11) should occur for an analog voltage 1½ LSB below
the nominal full scale (+4.999943 V for the ±5 V range). The
gain error is the deviation of the difference between the actual
level of the last transition and the actual level of the first transition
from the difference between the ideal levels.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels (dB), between the rms
a

mplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave
in

put. It is related to SINAD as follows

ENOB = (SINA

and is expressed in bits.

Noise-Free Code Resolution

Noise-free code resolution is the number of bits beyond which it is

possible to distinctly resolve individual codes. It is calculated as

im

Noise-Free Code Resolution = lo

and is expressed in bits.

− 1.76)/6.02

D

dB

g

(2N/Peak-to-Peak Noise)

2

Figure 22).

Effective Resolution

Effective resolution is calculated as

Effective Resolution = log

and is expressed in bits.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic
co

mponents to the rms value of a full-scale input signal and is

expressed in decibels.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to
th

e total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels. It is
measured with a signal at −60 dBF so that it includes all noise
sources and DNL artifacts.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the

ms sum of all other spectral components below the Nyquist

r
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to

e rms sum of all other spectral components that are less than

th
the Nyquist frequency, including harmonics but excluding dc.
The value of SINAD is expressed in decibels.

Aperture Delay

Aperture delay is the measure of the acquisition performance

nd is the time between the rising edge of the CNV input and

a
when the input signal is held for a conversion.

Transi ent Res p ons e

Transient response is the time required for the ADC to accurately
acq

uire its input after a full-scale step function is applied.

(2N/RMS Input Noise)

2

Rev. A | Page 8 of 24

AD7982

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TYPICAL PERFORMANCE CHARACTERISTICS

VDD = 2.5 V, REF = 5.0 V, VIO = 3.3 V.

2.0

1.5

1.0

POSITIVE INL: +0.79 LSB
NEGATIVE INL: –0.68 LSB

2.0

1.5

1.0

POSITIVE INL: +0.46 LSB
NEGATIVE INL: –0.49 LSB

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

–2.0

0 65536 131072 196608 262144

CODE

Figure 6. Integral Nonlinearity vs. Code

60000

29064

7795

CODE IN HEX

50975

32476

9064

881

43

50000

40000

30000

COUNTS

20000

10000

745

29

00

0

3FFF0 3FFF2 3FFF4 3FFF6 3FFF8 3FFFA 3FFFC

Figure 7. Histogram of a DC Input at the Code Center

0.5

0

DNL (LSB)

–0.5

–1.0

–1.5

–2.0

06513-006

0 65536 1310 72 196608 262144

CODE

06513-009

Figure 9. Differential Nonlinearity vs. Code

50000

45000

40000

35000

30000

25000

COUNTS

20000

15000

10000

5000

0

0

06513-007

007

0

01234 56789A D

145

16682

2793

44806

43239

CODE IN HEX

20013

3158

222

70 0

CB

06513-010

Figure 10. Histogram of a DC Input at the Code Transition

0

–20

–40

–60

–80

–100

–120

–140

AMPLITUDE (dB OF F ULL SCALE )

–160

–180

0 100 200 300 400 500

FREQUENCY (kHz)

f

= 1MSPS

S

f

= 2kHz

IN

SNR = 97.3dB
THD = –121.8dB
SFDR = 120.2dB
SINAD = 97.3d B

Figure 8. FFT Plot

06513-008

100

99

98

97

96

95

94

93

92

SNR (dB REFERRED T O FULL SCALE)

91

90

–10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0

Figure 11. SNR vs. Input Level

Rev. A | Page 9 of 24

INPUT LEVEL (dB)

06513-032

AD7982

–

–

–

www.BDTIC.com/ADI

100

18

100

130

95

90

SNR, SINAD (d B)

85

80

2.25 2.75 3.25 3.75 4.25 4. 75 5.25

SNR, SINAD

ENOB

REFERENCE VOL TAGE (V)

Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage

100

98

96

SNR (dB)

94

–105

17

–110

16

ENOB (Bits)

15

14

06513-034

–115

THD (dB)

–120

–125

–130

2.25 2.75 3.25 3. 75 4.25 4.75 5.25

SFDR

THD

REFERENCE VOL TAGE (V)

125

120

115

110

105

100

SFDR (dB)

06513-033

Figure 15. THD, SFDR vs. Reference Voltage

115

–117

–119

THD (dB)

–121

92

90

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

Figure 13. SNR vs. Temperature

100

95

90

SINAD (dB)

85

80

0.1 1 10 100 1000
FREQUENCY (kHz)

Figure 14. SINAD vs. Frequency

–123

–125

06513-042

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

06513-041

Figure 16. THD vs. Temperature

80

–85

–90

–95

–100

–105

THD (dB)

–110

–115

–120

–125

06513-031

0.1 1 1 0 100 1000
FREQUENCY (kHz)

06513-030

Figure 17. THD vs. Frequency

Rev. A | Page 10 of 24

AD7982

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1.4

1.2

I

VDD

1.4

1.2

I

VDD

1.0

0.8

0.6

0.4

OPERATING CURRENTS (mA)

0.2

0

2.375 2.525 2.575 2.625

2.425 2.475

I

REF

I

VIO

SUPPLY VOLTAGE (V)

Figure 18. Operating Currents vs. Supply Voltage

8

7

6

5

4

3

2

POWER-DOW N CURRENTS (µA)

1

I

VDD

+ I

VIO

1.0

0.8

0.6

0.4

OPERATING CURRENTS (mA)

0.2

0

06513-036

–55 –35 –15 5 25

I

REF

I

VIO

TEMPERATURE ( °C)

45 65 85 105 125

06513-035

Figure 20. Operating Currents vs. Temperature

0
–55 –35 –15 5 25

Figure 19. Power-Down Currents vs. Temperature

TEMPERATURE ( °C)

45 65 85 105 125

06513-038

Rev. A | Page 11 of 24

AD7982

G

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THEORY OF OPERATION

IN+

SWITCHES CONTROL

SW+

MSB

REF

ND

MSB

LSB

CC2C65,536C 4C131,072C

COMP

CC2C65,536C 4C131,072C

SW–

LSB

CONTROL

LOGIC

CNV

BUSY

OUTPUT CODE

IN–

Figure 21. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7982 is a fast, low power, single-supply, precise, 18-bit
ADC using a successive approximation architecture.

The AD7982 is capable of converting 1,000,000 samples per
s

econd (1 MSPS) and powers down between conversions. When
operating at 10 kSPS, for example, it typically consumes 70 μW,
making it ideal for battery-powered applications.

The AD7982 provides the user with an on-chip track-and-hold
an

d does not exhibit any pipeline delay or latency, making it

ideal for multiple multiplexed channel applications.

The AD7982 can be interfaced to any 1.8 V to 5 V digital logic

mily. It is available in a 10-lead MSOP or a tiny 10-lead QFN

fa
(LFCSP) that allows space savings and flexible configurations.

It is pin-for-pin-compatible with the 16-bit AD7980.

CONVERTER OPERATION

The AD7982 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified

chematic of the ADC. The capacitive DAC consists of two

s
identical arrays of 18 binary-weighted capacitors, which are
connected to the two comparator inputs.

06513-011

During the acquisition phase, terminals of the array tied to the
in

put of the comparator are connected to GND via SW+ and
SW−. All independent switches are connected to the analog
inputs. Therefore, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated. When the
conversion phase begins, SW+ and SW− are opened first. The
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the inputs IN+ and IN− captured at the end of the
acquisition phase is applied to the comparator inputs, causing
the comparator to become unbalanced. By switching each
element of the capacitor array between GND and REF, the
comparator input varies by binary-weighted voltage steps
(V

/2, V

REF

REF

/4 ... V

/262,144). The control logic toggles these

REF

switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase, and the control logic
generates the ADC output code and a busy signal indicator.

Because the AD7982 has an on-board conversion clock, the
s

erial clock, SCK, is not required for the conversion process.

Rev. A | Page 12 of 24

AD7982

V

www.BDTIC.com/ADI

Transfer Functions

The ideal transfer characteristic for the AD7982 is shown in
Figure 22 and Tabl e 7.

011. ..111

011...110

011...101

ADC CODE (TWO S COMPLEMENT)

100...010

100...001

100...000

–FSR

–FSR + 1 LSB

–FSR + 0.5 L SB

ANALOG INPUT

+FSR – 1.5 L SB

+FSR – 1 LS B

Figure 22. ADC Ideal Transfer Function

1

REF

0 TO VREF

REF TO 0

ADA4841

2, 3

V+

V+

V–

V+

V–

10µF

20Ω

2.7nF

4

20Ω

2.7nF

4

06513-012

2

IN+

IN–

Table 7. Output Codes and Ideal Input Voltages

Description

Analog Input
V

= 5 V

REF

Digital Output
C

FSR – 1 LSB +4.999962 V 0x1FFFF
Midscale + 1 LSB +38.15 μV 0x00001
Midscale 0 V 0x00000
Midscale – 1 LSB −38.15 μV 0x3FFFF
–FSR + 1 LSB −4.999962 V 0x20001
–FSR −5 V 0x20000

1

This is also the code for an overranged analog input (V

2

This is also the code for an underranged analog input (V

− V

IN+

TYPICAL CONNECTION DIAGRAM

Figure 23 shows an example of the recommended connection
diagram for the AD7982 when multiple supplies are available.

2.5V

1.8V TO 5V

3-WIRE INT ERFACE

REF VDD VIO

AD7982

GND

100nF

100nF

SDI

SCK

SDO

CNV

ode (Hex)

1

2

above V

IN−

− V

below V

IN+

IN−

− V

REF

GND

GND

).

).

NOTES

1

SEE VOLT AGE REFERENCE INPUT SECTI ON FOR REFERENCE SELECTI ON.

2

C

IS USUALLY A 10µF CERAMI C CAPACITOR (X 5R).

REF

SEE RECOMME NDED LAYOUT FIGURE 41 AND F IGURE 42.

3

SEE DRIVER AMPLIFIER CHOICE SECTION.

4

OPTIONAL FILTER. SEE ANALOG INPUT SECTION.

06513-013

Figure 23. Typical Application Diagram with Multiple Supplies

Rev. A | Page 13 of 24

AD7982

www.BDTIC.com/ADI

ANALOG INPUTS

Figure 24 shows an equivalent circuit of the input structure of
the AD7982.

The two diodes, D1 and D2, provide ESD protection for the
a

nalog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal does not exceed the reference input
voltage (REF) by more than 0.3 V. If the analog input signal
exceeds this level, the diodes become forward biased and start
conducting current. These diodes can handle a forward-biased
current of 130 mA maximum. However, if the supplies of the
input buffer (for example, the supplies of the ADA4841 in
Figure 23) are different from those of the REF, the analog input
s

ignal may eventually exceed the supply rails by more than

0.3 V. In such a case (for example, an input buffer with a short­circuit), the current limitation can be used to protect the part.

REF

D1

IN+ OR IN–

GND

Figure 24. Equivalent Analog Input Circuit

C

PIN

D2

C

IN

R

IN

06513-014

When the source impedance of the driving circuit is low, the
AD7982

can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The
dc performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency.

DRIVER AMPLIFIER CHOICE

Although the AD7982 is easy to drive, the driver amplifier must
meet the following requirements:

• The noise generated by the driver amplifier must be kept

as low as possible to preserve the SNR and transition noise
performance of the AD7982. The noise from the driver is
filtered by the AD7982 analog input circuit’s 1-pole, low­pass filter made by R
one is used. Because the typical noise of the AD7982 is
40 μV rms, the SNR degradation due to the amplifier is

SNR

LOSS

=

and CIN or by the external filter, if

IN

⎛
⎜

⎜

log20

⎜
⎜
⎝

40

40

π

+

3dB

−

2

⎞
⎟

⎟
⎟

22

)(

Nef

⎟

N

⎠

The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.

90

85

80

75

CMRR (dB)

70

65

60

1 10 100 1000 10000

Figure 25. Analog Input CMRR vs. Frequency

FREQUENCY (kHz)

06513-040

During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of Capacitor C
of R

and CIN. C

IN

and the network formed by the series connection

PIN

is primarily the pin capacitance. RIN is typically

PIN

400 Ω and is a lumped component composed of serial resistors
and the on resistance of the switches. C

is typically 30 pF and

IN

is mainly the ADC sampling capacitor.

During the sampling phase, where the switches are closed, the

put impedance is limited to C

in

. RIN and CIN make a 1-pole,

PIN

low-pass filter that reduces undesirable aliasing effects and
limits noise.

Rev. A | Page 14 of 24

where:

is the input bandwidth, in megahertz, of the AD7982

f

–3dB

(10 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).

e

is the equivalent input noise voltage of the op amp, in

N

nV/√Hz.

r ac applications, the driver should have a THD perfor-

• Fo

mance commensurate with the AD7982.

or multichannel multiplexed applications, the driver

• F

amplifier and the AD7982 analog input circuit must settle
for a full-scale step onto the capacitor array at an 18-bit level
(0.0004%, 4 ppm). In the data sheet of the amplifier,
settling at 0.1% to 0.01% is more commonly specified. This
may differ significantly from the settling time at an 18-bit
level and should be verified prior to driver selection.

Table 8. Recommended Driver Amplifiers

Amplifier Typical Application

ADA4941 Very low noise, low power, single to differential
ADA4841 Very low noise, small, and low power
AD8021 Very low noise and high frequency
AD8022 Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8655 5 V single supply, low noise
AD8605, AD8615 5 V single supply, low power

AD7982

A

www.BDTIC.com/ADI

SINGLE-TO-DIFFERENTIAL DRIVER

For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4941 single-ended-to-differential
driver allows for a differential input to the part. The schematic
is shown in Figure 26.

R1 and R2 set the attenuation ratio between the input range and
t

he ADC range (V
the desired input resistance, signal bandwidth, antialiasing, and
noise contribution. For example, for the ±10 V range with a 4 kΩ
impedance, R2 = 1 kΩ and R1 = 4 kΩ.

). R1, R2, and CF are chosen depending on

REF

POWER SUPPLY

The AD7982 uses two power supply pins: a core supply (VDD) and
a digital input/output interface supply (VIO). VIO allows direct
interface with any logic between 1.8 V and 5.5 V. To reduce the
number of supplies needed, VIO and VDD can be tied together.
The AD7982 is independent of power supply sequencing between
VIO and VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in

95

90

Figure 27.

R3 and R4 set the common mode on the IN− input, and R5 and R6

et the common mode on the IN+ input of the ADC. The common

s
mode should be close to V

/2. For example, for the ±10 V range

REF

with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 = 10.5 kΩ,
and R6 = 9.76 kΩ.

R6

R4

+5.2V

REF

IN

FB

R1

–0.2V

ADA4941

R2

C

F

OUTN

OUTP

Figure 26. Single-Ended-to-D

10µF

20Ω

2.7nF

2.7nF

20Ω

IN+

IN–

ifferential Driver Circuit

REF

AD7982

GND

+5V REF

+2.5V

VDD

±10V,

±5V, ..

R5

R3

100nF

100nF

VOLTAGE REFERENCE INPUT

The AD7982 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.

When REF is driven by a very low impedance source (for
exa

mple, a reference buffer using the AD8031 or the AD8605),
a 10 μF (X5R
for optimum performance.

, 0805 size) ceramic chip capacitor is appropriate

85

80

75

PSRR (dB)

70

65

60

1 10 100 1000

FREQUENCY (kHz)

06513-039

Figure 27. PSRR vs. Frequency

To ensure optimum performance, VDD should be roughly half
of REF, the voltage reference input. For example, if REF is 5.0 V,
VDD should be set to 2.5 V (±5%).

The AD7982 powers down automatically at the end of each

nversion phase; therefore, the power scales linearly with the

co

06513-015

sampling rate. This makes the part ideal for low sampling rates
(even of a few hertz) and low battery-powered applications.

10.000

1.000

I

VDD

I

I

REF

VIO

TING CURRENTS (mA)

OPER

0.100

0.010

If an unbuffered reference voltage is used, the decoupling value
dep

ends on the reference used. For instance, a 22 μF (X5R,

0.001
10000 1000000

1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift

ADR43x reference.

Figure 28. Operating Currents vs. Sampling Rate

If desired, a reference decoupling capacitor with values as small
as 2.2 μF ca

n be used with a minimal impact on performance,

especially DNL.

Regardless, there is no need for an additional lower value ceramic

upling capacitor (for example, 100 nF) between the REF

deco
and GND pins.

Rev. A | Page 15 of 24

100000

SAMPLING RATE (SPS)

06513-037

AD7982

www.BDTIC.com/ADI

DIGITAL INTERFACE

Although the AD7982 has a reduced number of pins, it offers
flexibility in its serial interface modes.

When in
digital hosts, and DSPs. In this mode, the AD7982 can use
either a 3-wire or 4-wire interface. A 3-wire interface using the
CNV, SCK, and SDO signals minimizes wiring connections
useful, for instance, in isolated applications. A 4-wire interface
using the SDI, CNV, SCK, and SDO signals allows CNV, which
initiates the conversions, to be independent of the readback
timing (SDI). This is useful in low jitter sampling or
simultaneous sampling applications.

When in chain mode, the AD7982 provides a daisy-chain feature
usin
data line similar to a shift register.

CS

mode, the AD7982 is compatible with SPI, QSPI,

g the SDI input for cascading multiple ADCs on a single

The mode in which the part operates depends on the SDI level

CS

w

hen the CNV rising edge occurs. The
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.

In either mode, the AD7982 offers the option of forcing a start
b

it in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must timeout
the maximum conversion time prior to readback.

The busy indicator feature is enabled

CS

mode if CNV or SDI is low when the ADC

the

• In

conversion ends (see Figure 32 and Figure 36).

• I

n the chain mode if SCK is high during the CNV rising

edge (see

Figure 40).

mode is selected if

Rev. A | Page 16 of 24

AD7982

www.BDTIC.com/ADI

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when a single AD7982 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 29, and the corresponding timing is given in
Figure 30.

With SDI tied to VIO, a rising edge on CNV initiates a

CS

co

nversion, selects the
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for instance, to bring CNV low to select other SPI devices, such
as analog multiplexers; however, CNV must be returned high
before the minimum conversion time elapses and then held

mode, and forces SDO to high

high for the maximum possible conversion time to avoid the
generation of the busy signal indicator. When the conversion is
complete, the AD7982 enters the acquisition phase and powers
down. When CNV goes low, the MSB is output onto SDO. The
remaining data bits are clocked by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the 18

th

SCK falling edge or when
CNV goes high (whichever occurs first), SDO returns to high
impedance.

CONVERT

DIGITAL HOST

DATA IN

CLK

06513-016

Figure 29.

VIO

CS

Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)

CNV

SDI SDO

AD7982

SCK

SDI = 1

t

CYC

t

CNVH

CNV

SCK

SDO

t

CONV

CONVERSIONACQUISITION

Figure 30.

123 161718

t

HSDO

t

EN

D17 D16 D15 D1 D0

CS

Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)

t

ACQ

ACQUISIT ION

t

DSDO

t

SCKL

t

SCKH

t

SCK

t

DIS

06513-017

Rev. A | Page 17 of 24

AD7982

www.BDTIC.com/ADI

CS MODE, 3-WIRE WITH BUSY INDICATOR

This mode is usually used when a single AD7982 is connected
to an SPI-compatible digital host having an interrupt input.

The connection diagram is shown in Figure 31, and the

orresponding timing is given in Figure 32.

c

With SDI tied to VIO, a rising edge on CNV initiates a

CS

co

nversion, selects the
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.

mode, and forces SDO to high

VIO

SDI SDO

AD7982

CNV

When the conversion is complete, SDO goes from high
i

mpedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7982 then
enters the acquisition phase and powers down. The data bits are
then clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 19

th

SCK falling edge
or when CNV goes high (whichever occurs first), SDO returns
to high impedance.

If multiple AD7982s are selected at the same time, the SDO
o

utput pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.

CONVERT

VIO

DIGITAL HOST

47kΩ

DATA IN

IRQ

CLK

06513-018

Figure 31.

SCK

CS

Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)

SDI = 1

t

CYC

t

CNVH

CNV

SCK

SDO

t

CONV

CONVERSIONACQUISITION

Figure 32.

1 2 3 17 18 19

t

HSDO

D17 D16 D1 D0

CS

Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)

t

ACQ

ACQUISIT ION

t

DSDO

t

SCKL

t

SCKH

t

SCK

t

DIS

06513-019

Rev. A | Page 18 of 24

AD7982

www.BDTIC.com/ADI

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when multiple AD7982s are
connected to an SPI-compatible digital host.

A connection diagram example using two AD7982s is shown in
Figure 33, and the corresponding timing is given in Figure 34.

With SDI high, a rising edge on CNV initiates a conversion,

CS

lects the

se
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion

mode, and forces SDO to high impedance. In this

time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7982 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate, provided it has an acceptable hold time.
After the 18

th

SCK falling edge or when SDI goes high (whichever
occurs first), SDO returns to high impedance and another
AD7982 can be read.

CS2
CS1
CONVERT

CNV

SDI SDO

AD7982

SCK

Figure 33.

CS

Mode, 4-Wire Without Busy Indicator Connection Diagram

CNV

SDI SDO

AD7982

SCK

DIGITAL HOST

DATA IN
CLK

06513-020

t

CYC

CNV

t

ACQ

ACQUISITI ON

19 2018

D0 D17 D16

t

DIS

06513-021

t

SDI(CS1)

SDI(CS2)

SCK

SDO

SSDICNV

t

HSDICNV

t

CONV

CONVERSIONACQUISITI ON

t

SCK

t

SCKL

t

DSDO

16 17

t

SCKH

D1

123 343536

t

t

EN

HSDO

D17 D16 D15 D1 D0

CS

Figure 34.

Mode, 4-Wire Without Busy Indicator Serial Interface Timing

Rev. A | Page 19 of 24

AD7982

www.BDTIC.com/ADI

CS MODE, 4-WIRE WITH BUSY INDICATOR

This mode is usually used when a single AD7982 is connected
to an SPI-compatible digital host with an interrupt input and
when it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This independence is particularly important in
applications where low jitter on CNV is desired.

The connection diagram is shown in Figure 35, and the

orresponding timing is given in Figure 36.

c

With SDI high, a rising edge on CNV initiates a conversion,

CS

se

lects the
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be

mode, and forces SDO to high impedance. In this

CNV

SDI SDO

AD7982

used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7982
then enters the acquisition phase and powers down. The data
bits are then clocked out, MSB first, by subsequent SCK falling
edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 19

th

SCK falling edge or
SDI going high (whichever occurs first), SDO returns to high
impedance.

CS1
CONVERT

VIO

DIGITAL HOST

47kΩ

DATA IN

IRQ

CLK

06513-022

Figure 35.

SCK

CS

Mode, 4-Wire with Busy Indicator Connection Diagram

t

CYC

CNV

t

ACQ

ACQUISITION

t

SCKL

t

SCKH

t

SCK

t

DIS

06513-023

SDI

SCK

SDO

t

SSDICNV

t

HSDICNV

CONVERSIONACQUISITI ON

t

CONV

t

EN

Figure 36.

1 2 3 171819

t

HSDO

t

DSDO

D17 D16 D1 D0

CS

Mode, 4-Wire with Busy Indicator Serial Interface Timing

Rev. A | Page 20 of 24

AD7982

www.BDTIC.com/ADI

CHAIN MODE WITHOUT BUSY INDICATOR

This mode can be used to daisy-chain multiple AD7982s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.

A connection diagram example using two AD7982s is shown in
Figure 37, and the corresponding timing is given in Figure 38.

When SDI and CNV are low, SDO is driven low. With SCK low,
a r

ising edge on CNV initiates a conversion, selects the chain

mode, and disables the busy indicator. In this mode, CNV is

held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7982 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7982s in the chain, provided the
digital host has an acceptable hold time. The maximum conversion
rate may be reduced due to the total readback time.

CONVERT

CNV

SDI SDO

AD7982

A

SCK

CNV

SDI SDO

AD7982

B

SCK

DIGITAL HOST

DATA IN

CLK

6513-024

Figure 37. Chain Mode Without Busy Indicator Connection Diagram

SDIA = 0

CNV

SCK

t

HSCKCNV

SDOA = SDI

SDO

t

CONV

CONVERSIO NACQUISITION

t

t

SSCKCNV

1 2 3 343536

t

t

EN

B

t

HSDO

t

DSDO

B

SSDISCK

DA17 DA16 DA15

DB17 DB16 DB15 DA1DB1DB0DA17 DA16

SCKL

t

Figure 38. Chain Mode Without Busy Indicator Serial Interface Timing

16 17

HSDISCK

t

CYC

ACQUISITION

t

SCK

DA1

t

t

SCKH

DA0

ACQ

19 2018

DA0

06513-025

Rev. A | Page 21 of 24

AD7982

www.BDTIC.com/ADI

CHAIN MODE WITH BUSY INDICATOR

This mode can also be used to daisy-chain multiple AD7982s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.

A connection diagram example using three AD7982s is shown
in Figure 39, and the corresponding timing is given in Figure 40.

When SDI and CNV are low, SDO is driven low. With SCK
hig

h, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the

subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7982 ADC labeled C in

iven high. This transition on SDO can be used as a busy indicator

dr

Figure 39) is

to trigger the data readback controlled by the digital host. The
AD7982 then enters the acquisition phase and powers down.
The data bits stored in the internal shift register are clocked out,
MSB first, by subsequent SCK falling edges. For each ADC, SDI
feeds the input of the internal shift register and is clocked by the
SCK falling edge. Each ADC in the chain outputs its data MSB
first, and 18 × N + 1 clocks are required to read back the N ADCs.
Although the rising edge can be used to capture the data, a digital
host using the SCK falling edge allows a faster reading rate and
consequently more AD7982s in the chain, provided the digital
host has an acceptable hold time.

CONVERT

CNV = SDI

ACQUISIT ION

SCK

t

HSCKCNV

SDOA = SDI

= SDI

SDO

B

SDO

SDI SDO

A

t

CONV

CONVERSI ON

t

SSCKCNV

t

EN

B

t

DSDOSDI

C

t

DSDOSDI

C

CNV

AD7982

A

SCK

Figure 39. Chain Mode with Busy I

t

123 39 53 54

t

SSDISCK

DA17 DA16 DA15

t

HSDO

t

DSDO

DB17 DB16 DB15 DA1DB1DB0DA17 DA16

DC17 DC16 DC15 DA1DA0DC1DC0D

CNV

SDI SDO

AD7982

B

SCK

t

SCKH

SCK

417

t

HSDISCK

DA1

t

SCKL

CNV

SDI SDO

AD7982

C

SCK

ndicator Connection Diagram

t

CYC

t

ACQ

ACQUISITION

19 3818

DA0

21 35 3620

37

DA0

1DB0DA17DB17 DB16

D

B

Figure 40. Chain Mode with Busy Indicator Serial Interface Timing

DIGITAL HOST

DATA IN

IRQ

CLK

16

A

t

DSDOSDI

t

DSDOSDI

t

DSDOSDI

06513-026

55

06513-027

Rev. A | Page 22 of 24

AD7982

www.BDTIC.com/ADI

APPLICATION HINTS

LAYOUT

The printed circuit board that houses the AD7982 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7982, with its analog signals on the left side and its digital
signals on the right side, eases this task.

Avoid running digital lines under the device because these

uple noise onto the die, unless a ground plane under the

co
AD7982 is used as a shield. Fast switching signals, such as CNV
or clocks, should not run near analog signal paths. Crossover of
digital and analog signals should be avoided.

At least one ground plane should be used. It can be common or

plit between the digital and analog sections. In the latter case,

s
the planes should be joined underneath the AD7982s.

The AD7982 voltage reference input REF has a dynamic input

pedance and should be decoupled with minimal parasitic

im
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.

Figure 41. Example Layout of the AD7982 (Top Layer)

AD7982

06513-028

Finally, the power supplies VDD and VIO of the AD7982

hould be decoupled with ceramic capacitors, typically 100 nF,

s
placed close to the AD7982 and connected using short, wide
traces to provide low impedance paths and to reduce the effect
of glitches on the power supply lines.

An example of layout following these rules is shown in
Figure 41 and Figure 42.

EVALUATING AD7982 PERFORMANCE

Other recommended layouts for the AD7982 are outlined
in the documentation of the evaluation board for the AD7982
(EVAL-AD7982CBZ). The evaluation board package includes
a f

ully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the

EVAL-CONTROL BRD3.

Figure 42. Example Layout of the AD7982 (Bottom Layer)

06513-029

Rev. A | Page 23 of 24

AD7982

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

3.10

3.00

2.90

6

10

3.10

3.00

2.90

1

PIN 1

0.50 BSC

0.95

0.85

0.75

0.15

0.33

0.05

0.17

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 43. 10-Lead Mini Small Outline Package [MSOP]

3.00

BSC SQ

5.15

4.90

4.65

5

1.10 MAX

SEATING
PLANE

(R

M-10)

0.23

0.08

8°
0°

Dimensions shown in millimeters

0.30

0.23

0.18

0.80

0.60

0.40

0.50 BSC

PIN 1 INDEX

AREA

0.80

0.75

0.70

SEATING

PLANE

TOP VIEW

0.80 MAX

0.55 NOM

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

5

EXPOSED

(BOTTOM VIEW)

4

PAD

2.48

2.38

2.23

8

1.74

1.64

1.49

1

P

N

1

I

R

A

O

T

N

I

D

C

I

)

9

1

.

R

0

(

062507-B

Figure 44. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)]

3

mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Ordering Quantity Branding

AD7982BRMZ
AD7982BRMZRL7
AD7982BCPZ
AD7982BCPZ-RL7
AD7982BCPZ-RL
EVAL-AD7982CBZ
EVAL-CONTROL BRD3Z3 Controller Board

1

Z = RoHS compliant part.

2

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes.

3

This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator.

©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06513–0–10/07(A)

1

1

1

1

1

1, 2

−40°C to +85°C 10-Lead MSOP RM-10 Tube, 50 C5F

−40°C to +85°C 10-Lead MSOP RM-10 Reel, 1000 C5F

−40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 Tube, 75 C5F

−40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 Reel, 1000 C5F

−40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 Reel, 5000 C5F
Evaluation Board

Rev. A | Page 24 of 24