Datasheet AD7767 Datasheet (ANALOG DEIVCES)

24-Bit, 8.5 mW, 109 dB,

www.BDTIC.com/ADI

FEATURES

Oversampled successive approximation (SAR) architecture
High performance ac and dc accuracy, low power

115.5

dB dynamic range, 32 kSPS (AD7767-2)

112.5 dB dynamic range, 64 kSPS (AD7767-1)
dB dynamic range, 128 kSPS (AD7767)

109.5

−118 dB THD

Exceptionally low power

, 32 kSPS (AD7767-2)

8.5 mW

10.5 mW, 64 kSPS (AD7767-1)

15 mW, 128 kSPS (AD7767)

High dc accuracy

24 bits

, no missing codes (NMC)

INL: ±3 ppm (typical), ±7.6 ppm (maximum)

Low temperature drift

Zero error drif
Gain error drift: 0.0075% FS

On-chip low-pass FIR filter

Linear phase r
Pass-band ripple: ±0.005 dB
Stop-band attenuation: 100 dB

2.5 V supply with 1.8 V/2.5 V/3 V/3.6 V logic interface options
Flexible interfacing options

S

ynchronization of multiple devices

Daisy chain capability
Power-down function
Temperature range: −40°C to +105°C

APPLICATIONS

Low power PCI/USB data acquisition systems
Low power wireless acquisition systems
Vibration analysis
Instrumentation
High precision medical acquisition

V

REF+

V

IN+

V

IN–

REFGND

t: 15 nV/°C

esponse

FUNCTIONAL BLOCK DIAGRAM

AVDDAGND MCLK DV

SUCCESSIVE-

APPROXIMATION

ADC

AD7767/
AD7767-1/
AD7767-2

SCLK DRDY SDO SDI

Figure 1.

DDVDRIVE

SERIAL INT ERFACE

CONTROL L OGIC

DIGITAL

FIR FILTER

AND

DGND

SYNC/PD

CS

06859-001

128/64/32 kSPS ADCs

AD7767

GENERAL DESCRIPTION

The AD7767/AD7767-1/AD7767-2 are high performance
24-bit oversampled SAR analog-to-digital converters (ADC).
The AD7767/AD7767-1/AD7767-2 combine the benefits of a
large dynamic range and input bandwidth, consuming 15 mW,

10.5 mW, and 8.5 mW power, respectively, all contained in a
16-lead TSSOP package.

Ideal for ultralow power data acquisition (such as PCI- and
US

B-based systems), the AD7767/AD7767-1/AD7767-2
provide 24-bit resolution. The combination of exceptional SNR,
wide dynamic range, and outstanding dc accuracy make the
AD7767/AD7767-1/AD7767-2 ideally suited for measuring
small signal changes over a wide dynamic range. This is
particularly suitable for applications where small changes on the
input are measured on larger ac or dc signals. In such an
application, the AD7767/AD7767-1/AD7767-2 accurately
gather both ac and dc information.

The AD7767/AD7767-1/AD7767-2 include an on-board digital

ilter (complete with linear phase response) that acts to elimi-

f
nate out-of-band noise by filtering the oversampled input
voltage. The oversampled architecture also reduces front-end
antialias requirements. Other features of the AD7767 include a
SYNC

/PD (synchronization/power-down) pin, allowing the
synchronization of multiple AD7767 devices. The addition of
an SDI pin provides the option of daisy chaining multiple
AD7767 devices.

The AD7767/AD7767-1/AD7767-2 operate from a 2.5 V supply

sing a 5 V reference. The devices operate from −40°C to +105°C.

u

RELATED DEVICES

Table 1. 24-Bit Analog-to-Digital Converters

Part No. Description

AD7760 2.5 MSPS, 100 dB dynamic range1, on-board differential

AD7762/
AD7763

AD7764

AD7765

AD7766
AD7766-1
AD7766-2

1

Dynamic range at maximum output data rate.

amp and reference buffer, parallel, variable decimation
625 kSPS, 109 dB dynamic range

amp and reference buffer, parallel/serial, variable
decimation

312 kSPS, 109 dB dynamic range
amp and reference buffer, variable decimation (pin)

156 kSPS, 112 dB dynamic range
amp and reference buffer, variable decimation (pin)

128 kSPS, 109.5 dB
64 kSPS 112.5 dB
32 kSPS, 115.5 dB

1

, 15 mW, 16-bit INL, serial interface

1

,10.5 mW, 16-bit INL, serial interface

1

, 8.5 mW, 16-bit INL, serial interface

1

, on-board differential

1

, on-board differential

1

, on-board differential

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

AD7767

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Timing Diagrams.......................................................................... 6

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 15

AD7767/AD7767-1/AD7767-2 Transfer Function................ 15

Converter Operation.................................................................. 15

Analog Input Structure.............................................................. 16

Supply and Reference Voltages................................................. 16

AD7767 Interface ........................................................................... 17

Initial Power-Up......................................................................... 17

Reading Data............................................................................... 17

Power-Down, Reset, and Synchronization ............................. 17

Daisy Chaining ............................................................................... 18

Reading Data in Daisy Chain Mode........................................ 18

Choosing the SCLK Frequency ................................................ 18

Daisy Chain Mode Configuration and Timing Diagrams.... 19

Driving the AD7767....................................................................... 20

Differential Signal Source ......................................................... 20

Single-Ended Signal Source ...................................................... 20

Antialiasing ................................................................................. 21

Power Dissipation....................................................................... 21

V

Input Signal....................................................................... 22

REF+

Multiplexing Analog Input Channels...................................... 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 23

REVISION HISTORY

8/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD7767

www.BDTIC.com/ADI

SPECIFICATIONS

AVDD = DVDD = 2.5 V ± 5%, V
unless otherwise noted.

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

OUTPUT DATA RATE

AD7767 Decimate by 8 128 kHz
AD7767-1 Decimate by 16 64 kHz
AD7767-2 Decimate by 32 32 kHz

ANALOG INPUT

1

Differential Input Voltage V
Absolute Input Voltage V

V

Common-Mode Input Voltage V
Input Capacitance 22 pF

DYNAMIC PERFORMANCE

AD7767 Decimate by 8, ODR = 128 kHz

Dynamic Range

2

Signal-to-Noise Ratio (SNR)
Spurious Free Dynamic Range (SFDR)2Full-scale input amplitude, 1 kHz tone −128 −116 dB
Total Harmonic Distortion (THD)2 Full-scale input amplitude, 1 kHz tone −118 −105 dB
Intermodulation Distortion (IMD)2

AD7767-1 Decimate by 16, ODR = 64 kHz

Dynamic Range

2

Signal-to-Noise Ratio (SNR)
Spurious Free Dynamic Range (SFDR)2Full-scale input amplitude, 1 kHz tone −128 −116 dB
Total Harmonic Distortion (THD)
Intermodulation Distortion (IMD)

AD7767-2 Decimate by 32, ODR = 32 kHz

Dynamic Range

2

Signal-to-Noise Ratio (SNR)
Spurious Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Intermodulation Distortion (IMD)

DC ACCURACY1 For all devices

Resolution No missing codes 24 Bits
Differential Nonlinearity
Integral Nonlinearity
Zero Error
Gain Error
Zero Error Drift
Gain Error Drift

2

2

2

2

2

2

Common-Mode Rejection Ratio

= 1.8 V to 3.6 V, V

DRIVE

2

2

2

2

2

2

2

2

2

= 5 V, MCLK = 1 MHz, common-mode input = V

REF

/2, TA = −40°C to +105°C,

REF

− V

IN+

IN+

IN−

±V

IN−

−0.1 +V

−0.1 +V
/2 − 5% V

REF

/2 V

REF

V p-p

REF

+ 0.1 V

REF

+ 0.1 V

REF

/2 + 5% V

REF

Shorted inputs 108 109.5 dB
Full-scale input amplitude, 1 kHz tone 107 108.5 dB

Tone A = 49.7 kHz, Tone B = 53 kHz
Second-order terms −133 dB
Third-order terms −109 dB

Shorted inputs 111 112.5 dB
Full-scale input amplitude, 1 kHz tone 110 111.5 dB

Full-scale input amplitude, 1 kHz tone −118 −105 dB
Tone A = 24.7 kHz, Tone B = 25.3 kHz dB
Second-order terms −133 dB
Third-order terms −108 dB

Shorted inputs 114 115.5 dB
Full-scale input amplitude, 1 kHz tone 112 113.5 dB
Full-scale input amplitude, 1 kHz tone −128 −116 dB
Full-scale input amplitude, 1 kHz tone −118 −105 dB
Tone A = 11.7 kHz, Tone B = 12.3 kHz dB
Second-order terms −137 dB
Third-order terms −108 dB

Guaranteed monotonic to 24 bits
18-bit linearity 3 ±7.6 ppm
20 V

0.0075 0.075 % FS
15 nV/°C

0.4 ppm/°C
50 Hz tone −110 dB

Rev. 0 | Page 3 of 24

AD7767

www.BDTIC.com/ADI

Parameter Test Conditions/Comments Min Typ Max Unit

DIGITAL FILTER RESPONSE

Group Delay
Settling Time (Latency) Complete settling 74/ODR µs
Pass-Band Ripple
Pass Band

−3 dB Bandwidth
Stop Band Frequency
Stop-Band Attenuation

REFERENCE INPUT

V

Input Voltage +2.4 2 × AVDD V

REF+

DIGITAL INPUTS (Logic Levels)

VIL −0.3
VIH 0.7 × V
Input Leakage Current ±1 A/pin
Input Capacitance 5 pF
Master Clock Rate 1.024 MHz
Serial Clock Rate 1/t8 Hz

DIGITAL OUTPUTS

Data Format

VOL I
VOH I

POWER REQUIREMENTS

AVDD ± 5% +2.5 V
DVDD ± 5% +2.5 V
V

+1.7 +2.5 +3.6 V

DRIVE

CURRENT SPECIFICATIONS MCLK = 1.024 MHz

AD7767 (Operational Current) 128 kHz output data rate

AIDD 1.3 1.5 mA
DIDD 3.9 4.8 mA
I

0.35 0.425 mA

REF

AD7767-1 (Operational Current) 64 kHz output data rate

AIDD 1.3 1.5 mA
DIDD 2.2 2.85 mA
I

0.35 0.425 mA

REF

AD7767-2 (Operational Current) 32 kHz output data rate

AIDD 1.3 1.5 mA
DIDD 1.37 1.86 mA
I

0.35 0.425 mA

REF

Static Current (MCLK Stopped) For all devices

AIDD 0.9 1 mA
DIDD 1 93 A

Power-Down Mode Current For all devices

AIDD 0.1 6 A
DIDD 1 93 A

POWER DISSIPATION MCLK = 1.024 MHz

AD7767 (Operational Power) 128 kHz output data rate 15 18 mW
AD7767-1 (Operational Power) 64 kHz output data rate 10.5 13 mW
AD7767-2 (Operational Power) 32 kHz output data rate 8.5 10.5 mW

1

Specifications for all devices, AD7767, AD7767-1, and AD7767-2.

2

See the Terminology section.

1

1

1

1

37/ODR µs

±0.005 dB

0.453 × ODR Hz

0.49 × ODR Hz

0.547 × ODR Hz
100 dB

0.3 × V

V

DRIVE

DRIVE

V

DRIVE

+ 0.3 V

Serial 24 bits, twos complement (MSB
first)

= +500 A 0.4 V

SINK

= −500 µA V

1

SOURCE

– 0.3 V

DRIVE

Rev. 0 | Page 4 of 24

AD7767

www.BDTIC.com/ADI

TIMING SPECIFICATIONS

AVDD = DVDD = 2.5 V ± 5%, V
unless otherwise noted

1

Table 3.

Parameter Limit at T

DRDY Operation

t1 510 ns typ

2

t

2

t3 900 ns max MCLK low pulse width
t4

t5

3

t

READ

3

t

DRDY

Read Operation

t6 0 ns min
t7 6 ns max
t8

t9 10 ns min SCLK falling edge to data valid hold time (V
t10 10 ns min SCLK high pulse width
t11 10 ns min SCLK low pulse width
t

1/t8 min Minimum SCLK period

SCLK

t12 6 ns max
t13 0 ns min

Read Operation with CS Low

t14 0 ns min
t15 0 ns max

Daisy Chain Operation

t16 1 ns min SDI valid to SCLK falling edge setup time
t17 2 ns max SCLK falling edge to SDI valid hold time

SYNC/PD Operation

t18 1 ns typ
t19 20 ns typ
t20 1 ns min
t21 510 ns typ

3

t

SETTLING

1

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.7 V.

2

t2 and t3 allow a ~90% to 10% duty cycle to be used for the MCLK input where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum

MCLK frequency is 1.024 MHz.

3

n = 1 for AD7767, n = 2 for the AD7767-1, n = 4 for the AD7767-2.

= 1.7 V to 3.6 V, V

DRIVE

MIN

, T

MAX

= 5 V, common-mode input = V

REF

Unit Description

/2, TA = −40°C (T

REF

MCLK rising edge to DRDY

falling edge

100 ns min MCLK high pulse width

265 ns typ
128 ns typ
71 ns t
294 ns typ
435 ns typ
492 ns t

t − t5

DRDY

n × 8 × t

ns typ

MCLK

ns typ

MCLK rising edge to DRDY
MCLK rising edge to DRDY

yp

MCLK rising edge to DRDY

pulse width (AD7767)

DRDY

pulse width (AD7767-1)

DRDY

yp

pulse width (AD7767-2)

DRDY

low period, read data during this period

DRDY

period

DRDY

falling edge to CS setup time

DRDY

falling edge to SDO three-state disabled

CS

rising edge (AD7767)
rising edge (AD7767-1)
rising edge (AD7767-2)

60 ns max Data access time after SCLK falling edge (V
50 ns max Data access time after SCLK falling edge (V
25 ns max Data access time after SCLK falling edge (V
24 ns max Data access time after SCLK falling edge (V

Bus relinquish time after CS

rising edge to DRDY rising edge

CS

rising edge

falling edge to data valid setup time

DRDY

rising edge to data valid hold time

DRDY

/PD falling edge to MCLK rising edge

SYNC

rising edge going into SYNC/PD

falling edge coming out of SYNC/PD

592 × (n + 2) t

MCLK rising edge to DRDY

/PD rising edge to MCLK rising edge

SYNC
MCLK rising edge to DRDY

Filter settling time after a reset or power-down

MCLK

DRIVE

DRIVE

DRIVE

DRIVE

DRIVE

MIN

= 1.7 V)
= 2.3 V)
= 2.7 V)
= 3.0 V)

= 3.6 V)

) to +105°C (T

MAX

),

Rev. 0 | Page 5 of 24

AD7767

www.BDTIC.com/ADI

TIMING DIAGRAMS

t

2

MCLK

DRDY

Figure 2.

DRDY

vs. MCLK Timing Diagram, n = 1 for AD7767 (Decimate by 8), n = 2 for AD7767-1 (Decimate by 16), n = 4 for AD7767-2 (Decimate by 32)

1

t

3

t

1

t

READ

8 × n 8 × n1

t

4

t

5

t

DRDY

t

DRDY

t

5

06859-002

DRDY

SCLK

SDO

CS

t

6

t

10

1 23

t

t

7

8

t

9

D22MSB D21 D20 D1 LSB

Figure 3. Serial Timing Diagram, Reading Data Using

t

READ

t

13

t

11

t

12

06859-003

CS

CS = 0

t

DRDY

DRDY

SCLK

t

14

1 23 24

t

8

t

READ

t

10

t

t

9

11

t

15

SDO

DATA

INVALID

MSB D22 D21 D20 D1 LSB

CS

Figure 4. Serial Timing Diagram, Reading Data Setting

Logic Low

Rev. 0 | Page 6 of 24

DATA

INVALID

06859-004

AD7767

S

www.BDTIC.com/ADI

MCLK (I)

YNC/PD (I)

DRDY (O)

DOUT (O)

PART IN POWER-DOWN

ABCD

t

18

t

19

PART OUT OF POWER-DOWN

FILTER RESET

t

20

INVALID DATA VALID DATAVALID DATA

Figure 5. Reset, Synchronization, and Power-Down Timing Diagram

BEGINS SAMPL ING

t

SETTLING

t

21

06859-005

Rev. 0 | Page 7 of 24

AD7767

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

AV

to AGND −0.3 V to +3 V

DD

DVDD to DGND −0.3 V to +3 V
AVDD to DVDD −0.3 V to +0.3 V
V

to REFGND −0.3 V to +7 V

REF+

REFGND to AGND −0.3 V to + 0.3 V
V

to DGND −0.3 V to +6 V

DRIVE

V

to AGND −0.3 V to V

IN+, VIN–

Digital Inputs to DGND −0.3 V to V
Digital Outputs to DGND −0.3 V to V
AGND to DGND −0.3 V to +0.3 V
Input Current to Any Pin Except

Supplies

Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSSOP Package

θ
θ

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

ESD 1 kV

1

Transient currents of up to 100 mA do not cause SCR latch-up.

1

Thermal Impedance 150.4°C/W

JA

Thermal Impedance 27.6°C/W

JC

±10 mA

+0.3 V

REF

DRIVE

DRIVE

+ 0.3 V
+ 0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 8 of 24

AD7767

S

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AV

V

REF+

REFGND

V

IN+

V

IN–

AGND

YNC/PD

DV

DD

DD

1

2

AD7767/

3

AD767-1/

4

AD7767-2

TOP VIEW

5

(Not to S cale)

6

7

8

16

CS

15

SDI

14

MCLK

13

SCLK

12

DRDY

11

DGND

10

SDO

9

V

DRIVE

06859-006

Figure 6. 16-Lead TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 AVDD +2.5 V Analog Power Supply.
2 V

REF+

3 REFGND

Reference Input for the AD7767. An external reference must be applied to this input pin. The V

input can range

REF+

from 2.4 V to 5 V. The reference voltage input is independent of the voltage magnitude applied to the AV
Reference Ground. Ground connection for the reference voltage. The input reference voltage (V

) should be

REF+

DD

pin.

decoupled to this pin.
4 V
5 V

Positive Input of the Differential Analog Input.

IN+

Negative Input of the Differential Analog Input.

IN−

6 AGND Power Supply Ground for Analog Circuitry.
7

/PD Synchronization and Power-Down Input Pin. This pin has dual functionality. It can be used to synchronize multiple

SYNC

AD7767 devices and/or put the AD7767 device into power-down mode. See the Power-Down, Reset, and

Synchr

onization section for further details.
8 DVDD Digital Power Supply Input. This pin can be connected directly to V
9 V

DRIVE

Logic Power Supply Input, +1.8 V to +3.6 V. The voltage supplied at this pin determines the operating voltage of

DRIVE

.

the digital logic interface.

10 SDO

Serial Data Output (SDO). The conversion result from the AD7767 is output on the SD

O pin as a 24-bit, twos

complement, MSB first, serial data stream.
11 DGND Digital Logic Power Supply Ground.
12

DRDY

Data Ready Output. A falling edge on the DRDY signal indicates that a new conversion data result is available in the

output register of the AD7767. See the AD7767 Interface section for further details.
13 SCLK

Serial Clock Input. The SCLK input provides the serial clock f

or all serial data transfers with the AD7767 device. See

the AD7767 Interface section for further details.
14 MCLK Master Clock Input. The AD7767 sampling frequency is equal to the MCLK frequency.
15 SDI Serial Data Input. This is the daisy chain input of the AD7767. See the Daisy Chaining section for further details.
16

CS

Chip Select Input. The CS input selects the AD7767 device and acts as an enable on the SDO pin. In cases where CS

is used, the MSB of the conversion result is clocked onto the SDO line on the CS

falling edge. The CS input allows
multiple AD7767 devices to share the same SDO line. This allows the user to select the appropriate device by
supplying it with a logic low CS

signal, which enables the SDO pin of the device concerned. See the AD7767

Interface section for further details.

Rev. 0 | Page 9 of 24

AD7767

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = DVDD = 2.5 V ± 5%, V
otherwise noted. All FFTs were generated using 8192 samples using a 4-term Blackman-Harris window.

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

0 8k 16k 24k 32k 40k 48k 56k 64k

Figure 7. AD7767 FFT, 1 kHz, −0.5 dB Input Tone

= 1.8 V to 3.6 V, V

DRIVE

FREQUENCY (Hz)

= 5 V, MCLK = 1 MHz, common-mode input = V

REF

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

0 8k 16k 24k 32k 40k 48k 56k 64k

06859-101

Figure 10. AD7767 FFT, 1 kHz, −6 dB Input Tone

/2. TA = 25°C, unless

REF

FREQUENCY (Hz)

06859-104

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

0 4k 8k 12k 16k 20k 24k 28k 32k

FREQUENCY (Hz)

Figure 8. AD7767-1 FFT, 1 kHz, −0.5 dB Input Tone

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

0 16k12k8k4k

FREQUENCY (Hz)

Figure 9. AD7767-2 FFT, 1 kHz, −0.5 dB Input Tone

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

0 4k 8k 12k 16k 20k 24k 28k 32k

06859-102

06859-103

Figure 11. AD7767-1 FFT, 1 k

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

0 16k12k8k4k

Figure 12. AD7767-2 FFT, 1 k

FREQUENCY (Hz)

Hz, −6 dB Input Tone

FREQUENCY (Hz)

Hz, −6 dB Input Tone

06859-105

06859-106

Rev. 0 | Page 10 of 24

AD7767

www.BDTIC.com/ADI

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

0 8k 16k 24k 32k 40k 48k 56k 64k

FREQUENCY (Hz)

Figure 13. AD7767 FFT, 1 kHz, −60 dB Input Tone

06859-107

0

TONE A: 49.7kHz
TONE B: 50.3kHz

–20

SECOND-ORDER I MD = –133.71d B
THIRD-ORDER IMD = –109.05d B

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

0 8k 16k 24k 32k 40k 48k 56k 64k

Figure 16. AD7767 IMD FFT, 50

FREQUENCY (Hz)

kHz Center Frequency

06859-110

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

0 4k 8k 12k 16k 20k 24k 28k 32k

FREQUENCY (Hz)

Figure 14. AD7767-1 FFT, 1 kHz, −60 dB Input Tone

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

0 16k12k8k4k

FREQUENCY (Hz)

Figure 15. AD7767-2 FFT, 1 kHz, −60 dB Input Tone

0

TONE A: 24.7kHz
TONE B: 25.3kHz

–20

SECOND-ORDER IMD = –133.33d B
THIRD-ORDER IMD = –108.15d B

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

0 4k 8k 12k 16k 20k 24k 28k 32k

06859-108

FREQUENCY (Hz)

06859-111

Figure 17. AD7767-1 IMD FFT, 25 kHz Center Frequency

0

TONE A: 11.7kHz
TONE B: 12.3kHz

–20

SECOND-ORDER I MD = –137.96d B
THIRD-ORDER I MD = –108.1d B

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

0 16k12k8k4k

06859-109

FREQUENCY (Hz)

06859-112

Figure 18. AD7767-2 IMD FFT, 12 kHz Center Frequency

Rev. 0 | Page 11 of 24

AD7767

–

www.BDTIC.com/ADI

110

–112

–114

–116

–118

–120

THD (dB)

–122

–124

–126

–128

–130

01

AD7767-1

FREQUENCY (Hz)

AD7767

AD7767-2

M

900k800k700k600k500k400k300k200k100k

06859-113

Figure 19. AD7767/AD7767-1/AD7767-2 THD vs. MCLK Frequency

120

115

DYNAMIC RANGE

OPEN INPUTS

FULL-S CALE 921Hz

f

(Hz)

NOISE

CMRR (dB)

110

105

100

95

90

0 60k50k40k30k20k10k

Figure 22. AD7767 CMRR vs. Common-Mode Ripple Frequency

06859-116

115

114

113

112

111

SNR (dB)

110

109

108

107

01

AD7767-2

AD7767-1

AD7767

FREQUENCY (Hz)

M

900k800k700k600k500k400k300k200k100k

06859-114

OCCURRENCE

200

180

160

140

120

100

80

60

40

20

0

8388493

Figure 20. AD7767/AD7767-1/AD7767-2 SNR and THD vs. MCLK Frequency

150

140

130

PSRR (dB)

120

DV

DD

AV

DD

V

DRIVE

OCCURRENCE

250

200

150

100

8388497

8388501

8388505

8388509

8388513

8388517

8388521

8388525

8388529

8388533

8388537

8388541

8388545

8388549

8388553

8388557

8388561

8388565

8388569

CODES

Figure 23. AD7767 24-Bit Histogram

MAX = 8388637
MIN = 8388493
SPREAD = 145

8388573

8388577

8388581

8388585

8388589

8388593

8388597

8388601

8388605

8388609

MAX = 8388507
MIN = 8388608
SPREAD = 102 CODES

8388613

8388617

8388621

8388625

8388629

8388633

8388637

06859-118

110

100

0 60k50k40k30k20k10k

f

(Hz)

NOISE

06859-117

Figure 21. AD7767 Power Supply Sensitivity vs. Supply Ripple Frequency with

Dec

oupling Capacitors

50

0

8388508

8388512

8388516

8388520

8388524

8388528

8388532

8388536

8388540

Figure 24. AD7767-1 24-Bit Histogram

Rev. 0 | Page 12 of 24

8388544

8388548

8388552

8388556

8388560

8388564

8388568

8388572

8388576

8388580

8388584

8388588

8388592

8388596

8388600

8388604

CODES

8388608

06859-119

AD7767

www.BDTIC.com/ADI

INL (ppm)

3.80

3.04

2.28

1.52

0.76

–0.76

–1.52

–2.28

–3.04

–3.80

0

0

2097152

4194304

6291456

24-BIT CODES

LOW TEMPERATURE

NOMINAL T EMPERATURE

HIGH TEMPE RATURE

8388608

10485760

Figure 27. AD7767/AD7767-1/AD7767-2, 24-Bit INL

12582912

14680064

16777216

8388556

8388559

8388562

8388565

MAX = 8388593
MIN = 8388526
SPREAD = 69 CODES

8388568

8388571

8388574

8388577

8388580

8388583

8388586

8388589

8388592

06859-120

350

300

250

200

150

OCCURRENCE

100

50

0

8388526

8388529

8388532

8388535

8388538

8388541

8388544

8388547

8388550

8388553

CODES

Figure 25. AD7767-2 24-Bit Histogram

6859-122

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL (LSBs)

–0.4

–0.6

–0.8

–1.0

0

2097152

4194304

6291456

24-BIT CODES

8388608

10485760

12582912

14680064

16777216

6859-121

Figure 26. AD7767/AD7767-1/AD7767-2, 24-Bit DNL

Rev. 0 | Page 13 of 24

AD7767

www.BDTIC.com/ADI

TERMINOLOGY

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
r

ms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of harmonics to the fundamen-

. For the AD7767, it is defined as

tal

22222

++++

VVVVV

65432

()

THD

where:

V

is the rms amplitude of the fundamental.

1

V

, V3, V4, V5, and V6 are the rms amplitudes of the second to

2

the sixth harmonics.

Nonharmonic Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of the rms signal amplitude to the rms value

f the peak spurious spectral component, excluding harmonics.

o

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to
t

he rms noise measured with the inputs shorted together. The

value for the dynamic range is expressed in decibels.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa
a

nd fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb, where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to 0. For example,
the second-order terms include (fa + fb) and (fa − fb), and the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and
(fa − 2fb).

The AD7767 is tested using the CCIF standard, where two input

requencies near the top end of the input bandwidth are used.

f

In this case, the second-order terms are usually distanced in
f

requency from the original sine waves, and the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification, where it is the ratio of the rms

log20dB

=

V

1

sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in decibels.

Integral Nonlinearity (INL)

INL is the maximum deviation from a straight line passing
th

rough the endpoints of the ADC transfer function.

Differential Nonlinearity (DNL)

DNL is the difference between the measured and the ideal
1 LS

B change between any two adjacent codes in the ADC.

Zero Error

Zero error is the difference between the ideal midscale input

oltage (when both inputs are shorted together) and the actual

v
voltage producing the midscale output code.

Zero Error Drift

Zero error drift is the change in the actual zero error value due
t

o a temperature change of 1°C. It is expressed as a percentage

of full scale at room temperature.

Gain Error

The first transition (from 100…000 to 100…001) should occur

an analog voltage ½ LSB above the nominal negative full

for
scale. The last transition (from 011…110 to 011…111) should
occur for an analog voltage 1½ LSB below the nominal full
scale. The gain error is the deviation of the difference between
the actual level of the last transition and the actual level of the
first transition, from the difference between the ideal levels.

Gain Error Drift

Gain error drift is the change in the actual gain error value due

o a temperature change of 1°C. It is expressed as a percentage

t
of full scale at room temperature.

Common-Mode Rejection Ratio (CMRR)

CMRR is defined as the ratio of the power in the ADC output
a

t full-scale frequency f to the power of a 100 mV sine wave
applied to the common-mode voltage of the V
inputs at frequency fs.

CMRR (dB) = 10 log(Pf/Pfs)

where Pf i
Pfs is the power at the frequency fs in the ADC output.

s the power at the frequency f in the ADC output and

IN+

and V

IN−

Rev. 0 | Page 14 of 24

AD7767

S

www.BDTIC.com/ADI

THEORY OF OPERATION

The AD7767/AD7767-1/AD7767-2 operate using a fully
differential analog input applied to a successive approximation
(SAR) core. The output of the oversampled SAR is filtered using
a linear phase digital FIR filter. The fully filtered data is output
in a serial format, with the MSB being clocked out first.

AD7767/AD7767-1/AD7767-2 TRANSFER FUNCTION

The conversion results of the AD7767/AD7767-1/AD7767-2 are
output in a twos complement, 24-bit serial format. The fully
differential inputs V

IN+

and V

are scaled by the AD7767/

IN−

AD7767-1/AD7767-2 relative to the reference voltage input
(V

), as shown in Figure 28.

REF+

24 BITS

TWOS

COMPLEMENT

011...111

011...110

000...010

000...001

000...000

111...111

24-BIT OUT PUT

111...110

100...001

100...000

V

= 0V V

IN+

= V

V

Figure 28. AD7767/AD7767-1/AD7767-2 Transfer Function

– 1LSB V

IN–

REF

V

REF

V

=

IN+

2

V

REF

V

=

IN–

2

IN+

= V

– 1LSB

REF

= 0V

IN–

CONVERTER OPERATION

Internally, the input waveform applied to the SAR core is
converted and an equivalent digital word is output to the digital
filter at a rate equal to MCLK. By employing oversampling, the
quantization noise of the converter is spread across a wide
bandwidth from 0 to f
contained in the signal band of interest is reduced (see
Figure 29).

BAND OF INTEREST

This means that the noise energy

MCLK.

QUANTIZAT ION NOISE

Figure 29. Quantization Noise

f

MCLK/2

06859-213

06859-012

The digital filtering that follows the converter output acts to
remove the out-of-band quantization noise (see Figure 30). This
als

o has the effect of reducing the data rate from f

input of the filter to f

MCLK

/8, f

MCLK

/16, or f

MCLK

/32 at the digital

MCLK

at the

output, depending on which model of the device is being used.

The digital filter consists of three separate filter blocks. Figure 31
s

hows the three constituent blocks of the filter. The order of
decimation of the first filter block is set as 2, 4, or 8. The
remaining sections both operate in decimate by 2.

DIGITAL FILTER

DATA

TREAM

STAGE 1 STAGE 2

SINC FILTER FIR FILTER FIR FILTER

DEC × (2 × n) DEC × 2 DEC × 2

(n =

1 for AD7767, n = 2 for AD7767-1, n = 4 for AD7767-2)

Figure 31. FIR Filter Stages

STAGE 3

SDO

Tabl e 6 shows the three available models of the AD7767, listing
the change in output data rate relative to the order of decimation
rate implemented. This brings into focus the trade-off that
exists between extra filtering and reduction in bandwidth,
whereby using a filter option with a larger decimation rate
increases the noise performance while decreasing the usable
input bandwidth.

Table 6. AD7767 Models

Model Decimation Rate Output Data Rate (ODR)

AD7767 8 128 kHz
AD7767-1 16 64 kHz
AD7767-2 32 32 kHz

Note that the output data rates shown in Tab le 6 are realized
when using the maximum MCLK input frequency of 1.024 MHz.
The output data rate scales linearly with the MCLK frequency,
as does the digital power dissipated in the device.

The settling time of the filter implemented on the AD7767,
AD7767-1, and

AD7767-2 is related to the length of the filter
employed. The response of the filter in the time domain sets the
filter settling time.
AD7767/AD77

Table 7 shows the filter settling times of the

67-1/AD7767-2.

The frequency responses of the digital filters on the AD7767,
AD7767-1, and

nd Figure 34, respectively. At the Nyquist frequency (output

a
d

ata rate/2), the digital filter provides 6 dB of attenuation. In each

AD7767-2 are shown in Figure 32, Figure 33,

case, the filter provides stop-band attenuation of 100 dB and
pass-band ripple of ±0.005 dB.

06859-019

DIGITAL FILT ER CUTOFF FREQUENCY

f

BAND OF INTEREST

Figure 30. Digital Filter Cutoff Frequency

MCLK/2

6859-214

Rev. 0 | Page 15 of 24

AD7767

V

V

V

www.BDTIC.com/ADI

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

0 128k112k96k80k64k48k32k16k

FREQUENCY (Hz)

06859-216

Figure 32. AD7767 Digital Filter Frequency Response

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

056k48k40k32k24k16k8k

FREQUENCY (Hz)

64k

06859-217

Figure 33. AD7767-1 Digital Filter Frequency Response

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

028k24k20k16k12k8k4k

FREQUENCY (Hz)

32k

06859-218

Figure 34. AD7767-2 Digital Filter Frequency Response

ANALOG INPUT STRUCTURE

The AD7767/AD7767-1/AD7767-2 are configured as a
differential input structure. A true differential signal is sampled
between the analog inputs V

IN+

and V

, Pin 4 and Pin 5,

IN−

respectively. Using differential inputs provides rejection of
signals that are common to both the V

IN+

and V

IN−

pins.

Figure 35 shows the equivalent analog input circuit of the
AD7767/AD77

67-1/AD7767-2. The two diodes on each of the

differential inputs provide ESD protection for the analog inputs.

REF+

IN+

IN–

GND

GND

D

C1

D

AGND

V

REF+

D

C1

D

AGND

C2

R

IN

C2

R

IN

06859-219

Figure 35. Equivalent Analog Input Structure

Take care to ensure that the analog input signal does not exceed
the reference supply voltage V

by more than 0.3 V as specified

REF+

in the Absolute Maximum Ratings section. The diodes become
fo

rward biased if the input voltage exceeds this limit and start to

conduct current. The diodes can handle 130 mA maximum.

The impedance of the analog inputs can be modeled as a

arallel combination of C1 and the network formed by the

p
series connection of R
dominated by the pin capacitance. R
lumped component of serial resistors and the R

, C1, and C2. The value of C1 is

IN

is typically 1.4 kΩ, the

IN

of the

ON

switches. C2 is typically 22 pF, and its value is dominated by the
sampling capacitor.

SUPPLY AND REFERENCE VOLTAGES

The AD7767/AD7767-1/AD7767-2 operate from a 2.5 V supply
applied to the DV
operate between 1.7 V and 3.6 V. The AD7767/AD7767-1/
AD7767-2 operate from a 5 V reference applied to the V
The recommended reference devices are the ADR445 or

ADR425. The 5 V reference operates both as a reference supply

a

nd as a power supply to the AD7767/AD7767-1/AD7767-2
device. This feature means that the full-scale differential input
range of the AD7767/AD7767-1/AD7767-2 is 10 V. See the
Driving the AD7767 section for details on the maximum input
vol

tage.

, AVDD pins. The interface is specified to

DD

REF+

the

pin.

Rev. 0 | Page 16 of 24

AD7767

www.BDTIC.com/ADI

AD7767 INTERFACE

The AD7767 provides the user with a flexible serial interface,
enabling the user to implement the most desirable interfacing
scheme for their application. The AD7767 interface comprises
seven different signals. Five of these signals are inputs: MCLK,
CS

SYNC/PD

,

DRDY

, SCLK, and SDI. There are two output signals:

and SDO.

INITIAL POWER-UP

On initial power-up, apply a continuous MCLK signal. It is
recommended that the user reset the AD7767 to clear the filters
and ensure correct operation. The reset is completed as described
in

Figure 5, with all events occurring relative to the rising edge

f MCLK. A negative pulse on the

o
reset, and the

output switches to logic high and remains

DRDY

/PD input initiates the

SYNC

high until valid data is available. Following the power-up of the
AD7767 by transitioning the

SYNC

/PD pin to logic high, a
settling time is required before valid data is output by the
device. This settling time, t

, is a function of the MCLK

SETTLING

frequency and the decimation rate. Tabl e 7 lists the settling time

f each of the AD7767 models and should be referenced to

o
Figure 5.

SYNC

Table 7. Filter Settling Time After

Model Decimation Rate t

AD7767 8 594 × (t
AD7767-1 16 1186 × (t
AD7767-2 32 2370 × (t

1

t

is measured from the first MCLK rising edge after the rising edge of

SETTLING

to the falling edge of

SYNC/PD

DRDY

.

/PD

SETTLING

1

MCLK

MCLK

MCLK

+ t21)

+ t21)
+ t21)

READING DATA

The AD7767 outputs its data conversion results in an MSB first,
twos complement, 24-bit format on the serial data output pin
(SDO). MCLK is the master clock, which controls all the AD7767
conversions. The SCLK is the serial clock input for the device.
All data transfers take place with respect to the SCLK signal.

The

data is available to be read from the AD7767. The falling edge of
DRDY
register of the device.

output data is permitted to be read from the SDO pin. The
DRDY
from the device. Ensure that a data read is not attempted during
this period as the output register is being updated.

The AD7767 offers the user the option of using a chip select
in

put signal (
for the SDO pin and allows many AD7767 devices to share the
same serial bus, acting as an instruction signal to each of these

line is used as a status signal to indicate when the

DRDY

indicates that a new data-word is available in the output

stays low during the period that

DRDY

signal returns to logic high to indicate when not to read

CS

) in its data read cycle. The CS signal is a gate

devices indicating permission to use the bus. When
high, the SDO line of the AD7767 is tristated.

There are two distinct patterns that can be initiated to read data

rom the AD7767 device; these are for the cases when the

f
falling edge occurs after the

when the

(when

When the

CS

falling edge occurs before the

CS

is set to logic low).

CS

falling edge occurs after

falling edge and for the case

DRDY

DRDY

DRDY

MSB of the conversion result is available on the SDO line on

CS

this

falling edge. The remaining bits of the conversion result
(MSB-1, MSB-2, and so on) are clocked onto the SDO line by
the falling edges of SCLK that follow the

CS

falling edge. Figure 3

details this interfacing scheme.

CS

When

is tied low, the AD7767 serial interface can operate in
3-wire mode as shown in Figure 4. In this case, the MSB of the
co

nversion result is available on the SDO line on the falling

DRDY

edge of

. The remaining bits of the data conversion result
(MSB-1, MSB-2, and so on) are clocked onto the SDO line by
the subsequent SCLK falling edges.

POWER-DOWN, RESET, AND SYNCHRONIZATION

The AD7767

multiple AD7767 devices. This pin also allows the user to reset
and power down the AD7767 device. These features are
implemented relative to the rising edges of MCLK and are
shown in Figure 5.

To power down, reset, or synchronize a device, the AD7767
SYNC
MCLK, the AD7767 is powered down. The

tions to logic high, indicating that the data in the output register
is no longer valid. The status of the

each subsequent rising edge of MCLK. On the first rising edge
of MCLK after the

taken out of power-down. On the next rising edge, the filter of
the AD7767 is reset. On the following rising edge, the first new
sample is taken.

A settling time, t
valid data is output by the device (as listed in Tab l e 7). The
DRDY
valid data is available on SDO for readback.

SYNC

/PD pin allows the user to synchronize

/PD pin should be taken low. On the first rising edge of

DRDY

/PD pin is checked on

SYNC

/PD pin is taken high, the AD7767 is

SYNC

, from the filter reset, must pass before

SETTLING

output goes logic low after t

to indicate when

SETTLING

CS

is logic

CS

falling edge

falling edge, the

pin transi-

Rev. 0 | Page 17 of 24

AD7767

(

(

)

www.BDTIC.com/ADI

DAISY CHAINING

Daisy chaining devices allows numerous devices to use the same
digital interface lines by cascading the outputs of multiple ADCs
on a single data line. This feature is especially useful for reduc­ing component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a limited
interfacing capacity. Data readback is analogous to clocking a
shift register where data is clocked on the falling edge of SCLK.

The block diagram in Figure 36 shows the way in which devices

ust be connected in order to achieve daisy chain functionality.

m
This scheme operates by passing the output data of the SDO pin
of an AD7767 device to the SDI input of the next AD7767 device
in the chain. The data then continues through the chain until it
is clocked onto the SDO pin of the first device on the chain.

READING DATA IN DAISY CHAIN MODE

An example of a daisy chain of four AD7767 devices is shown in
Figure 36 and Figure 37. In the case illustrated in Figure 36, the

of AD7767 (A) is the output of the full daisy chain. The

output
last device in the chain (AD7767 (D)) has its serial data in (SDI)
pin connected to ground. All the devices in the chain must use

, and

SYNC/PD

signals.

common MCLK, SCLK,

CS

To enable the daisy chain conversion process, apply a common
SYNC

/PD pulse to all devices, synchronizing all the devices in
the chain (see the Power-Down, Reset, and Synchronization
secti

on).

SYNC

After applying a

/PD pulse to all the devices, there is a
delay (as listed in Tab le 7 ) before valid conversion data appears
a

t the output of the chain of devices. As shown in Figure 37,

t

he first conversion result is output from the device labeled
AD7767 (A). This 24-bit conversion result is followed by the
conversion results from the devices B, C, and D, respectively,
with all conversion results output in an MSB first sequence. The
stream of conversion results is clocked through each device in
the chain and is eventually clocked onto the SDO pin of the
AD7767 (A) device. The conversion results of the all the devices
in the chain must be clocked onto the SDO pin of the final

device in the chain while its
illustrated in the example shown where the conversion results
from devices A, B, C, and D are clocked onto SDO (A) in the
time between the falling edge of

DRDY

of

(A).

CHOOSING THE SCLK FREQUENCY

As shown in Figure 36, the number of SCLK falling edges that
occur during the period when
match the number of devices in the chain multiplied by 24 (the
number of bits that must be clocked through onto SDO (A) for
each device).

The period of SCLK (t
length using a known common MCLK frequency must
therefore be established in advance. Note that the maximum
SCLK frequency is governed by t
Specifications table for different V

t

⎡

READ

⎢

24

⎣

t − t

DRDY

⎡

READ

≤

⎢
⎣

CS

×≤K

CS

)

In the case where

t

SCLK

where:

K is the n
t

SCLK

t

READ

umber of AD7767 devices in the chain.

is the period of the SCLK.

equals

In the case where

t

SCLK

where:
K is the n

umber of AD7767 devices in the chain.

Note that the maximum value of SCLK is governed by t
specified in the Timing Specifications table for different V
voltages.

DRDY

signal is active low. This is

DRDY

(A) and the rising edge

DRDY

(A) is active low must

) required for a known daisy chain

SCLK

and is specified in the Timing

8

voltages.

DRIVE

is tied logic low,

⎤

(1)

⎥
⎦

.

5

is used in the daisy chain interface,

++−

tttt

⎤

1376

(2)

24

×

K

⎥
⎦

and is

8

DRIVE

Rev. 0 | Page 18 of 24

AD7767

www.BDTIC.com/ADI

DAISY CHAIN MODE CONFIGURATION AND TIMING DIAGRAMS

SYNC/PD

CS

MCLK

DRDY (A)

SCLK

SDO (A)

SDI (A) = SDO (B)

CS

SCLK

MCLK

SYNC/PD

CS

AD7767

(D)

SDISDI SDO

SCLK

MCLK

Figure 36. AD7767 Daisy Chain Configuration with

1 8 × n

24 ×

t

SCLK

AD7767 (A) AD7767 (B) AD7767 (C) AD7767 (D) AD7767 (A)

AD7767 (B) AD7767 (C) AD7767 (D) AD7767 (B)

SYNC/PD

CS

AD7767

SDI SDO

SCLK

24 ×

t

SCLK

(C)

MCLK

24 ×

CS

SDI SDO

SCLK

t

SCLK

SYNC/PD

AD7767

(B)

MCLK

Four AD7767 Devices

24 ×

t

SCLK

SYNC/PD

CS

DRDY

AD7767

(A)

SDI SDO

SCLK

MCLK

06859-013

SDI (B) = SDO (C)

SDI (C) = SDO (D)

MCLK

DRDY (A)

SDO (A)

SCLK

SDI (A) = SDO (B)

AD7767 (C) AD7767 (D) AD7767 (C)

AD7767 (D) AD7767 (D)

Figure 37. AD7767 Daisy Chain Timing Diagram (n = 1 for AD7767

1

CS

MSB (A) LSB (A) MSB (B) LSB (B) LSB (C)MSB (C)

t

16

t

17

MSB (B) LSB (B) MSB (C) LSB (C) LSB (D)MSB (D)

Figure 38. AD7767 Daisy Chain SDI Setup and Hold Timing

, n = 2 for AD7767-1, n = 4 for AD7767-2) Driving the AD7767

06859-014

06859-015

Rev. 0 | Page 19 of 24

AD7767

V

A

www.BDTIC.com/ADI

DRIVING THE AD7767

The AD7767 must be driven with fully differential inputs. The
common-mode voltage of the differential inputs to the AD7767
device and thus the limits on the differential inputs are set by
the reference voltage V
mode voltage of the AD7767 is V

applied to the device. The common-

REF

/2. Where the AD7767 V

REF

REF+

pin is supplied with a 5 V supply (the ADR445 or ADR425), the
common mode is at 2.5 V. This means that the maximum inputs
that can be applied on the AD7767 differential inputs are a
5 V p-p input around 2.5 V.

V

REF

V

REF

2

0V

V

REF

V

REF

2

0V

V

IN+

V

IN–

06859-016

Figure 39. Maximum Differential Inputs to the AD7767

An analog voltage of 2.5 V supplies the AD7767 AVDD pin.
However, the AD7767 allows the user to apply a reference
voltage of up to 5 V. This provides the user with an increased
full-scale range, offering the user the option of using the
AD7767 with a larger LSB voltage size. Figure 39 shows the
maximum and minimum inputs to the AD7767.

IN+

V

OFFSET

R1

R1 C1

IN

ADA4941-1

FB

R4

R5C3

R2

R2

Figure 41. Driving the AD7767 from a Single-Ended Source

7856

DIS

REF

2× V

DIFFERENTIAL SIGNAL SOURCE

An example of some recommended driving circuitry that can
be employed in conjunction with the AD7767/AD7767-1/
AD7767-2 is shown in Figure 40. Figure 40 shows how the

ADA4841-1 device can be used to drive an input to the AD7767/

AD7767-1/AD7767-2 from a differential source. Each of the
differential paths is driven by an ADA4841-1 device.

499Ω

3.3nF

A

IN+

A

IN–

2× V

499Ω

ADA4841-1

499Ω

3.3nF

499Ω

1kΩ

CM

1kΩ

ADA4841-1

3.3Ω

10nF

3.3Ω

Figure 40. Driving the AD7767 from a Fully Differential Source

SINGLE-ENDED SIGNAL SOURCE

In the case where the AD7767 is being supplied from a single­ended source, the application circuit in Figure 41 can be used to
drive the AD7767 device. Figure 41 shows how the ADA4941-1
single-to-differential amplifier can be used to create a fully
differential input to the AD7767. The single-ended signal input
is applied to the positive input of the ADA4941-1 device.
Arrange the values of the resistor elements to create a 2.5 V
common-mode input to the AD7767/AD7767-1/AD7767-2
device. R3 and C2 default to 3.3 Ω and 10 nF, respectively.

SS–

2.5V

V–

OUT–OUT+

V+

4321

V

SS+

CM

R

FB

C

FB

R3

C2

R3

4

5

V

IN+

AD7767

V

IN–

ADR425

V

AV

1

REF+

2

DD

06859 -018

4

V

5

V

2.5V

AV

IN+

AD7767

V

REF+

IN–

ADR425

1

DD

2

06859-017

Rev. 0 | Page 20 of 24

AD7767

www.BDTIC.com/ADI

ANTIALIASING

The AD7767/AD7767-1/AD7767-2 sample the analog input
at a maximum rate of 1.024 MHz. The on-board digital filter
provides up to 100 dB attenuation of any possible aliasing
frequencies in the range from the beginning of the filter stop
band (0.547 × ODR) to where the image of the digital filter pass
band occurs at MCLK − filter stop band (MCLK − 0.547 × ODR),
which is the first alias point. This is illustrated in

DIGITAL FIL TER 100dB

ANTIALIAS P ROTECTI ON

f

– (0.547 × ODR)

BAND OF INTERE ST

MCLK

FIRST ALIAS POINT

Figure 42. AD7767/AD7767-1/AD7767 Spectrum

Tabl e 8 shows the attenuation achieved by various orders of
front-end antialias filters prior to the AD7767/AD7767-1/
AD7767-2 at the image of the digital filter stop band, which is

1.024 MHz − 0.547 × ODR.

Figure 42.

f

MCLK

DIGITAL FILTER

IMAGE AT

f

MCLK

06859-231

in use. For instance, operating the AD7767 device with an
MCLK of 800 kHz gives an output data rate of 100 kHz due to
the decimate by 8 filtering.

4.5

4.0

3.5

3.0

2.5

2.0

CURRENT (mA)

1.5

1.0

0.5

0

0 1000k900k800k700k600k500k400k300k200k100k

FREQUENCY (Hz)

DI

DD

AI

DD

I

REF

Figure 43. AD7767 Current vs. MCLK Frequency

2.5

06859-226

Table 8. Antialias Filter Order Attenuation at First Alias Point

Attenuation at

Model Filter Order

AD7767

1st 27 dB

1.024 M

Hz – 0.547 × ODR

2nd 50 dB

rd

70 dB

3

AD7767-1

1st 33 dB
2nd 62 dB

rd

89 dB

3

AD7767-2

1st 38 dB
2nd 74 dB

rd

110 dB

3

The AD7764 and AD7765 sigma-delta devices are available to
customers that require extra antialias protection. These devices
sample internally at a rate of 20 MHz to achieve up to a maxi­mum of 156 kHz or 312 kHz output data rate. This means that
the first alias point of these devices when run at the maximum
speeds are 19.921 MHz and 19.843 MHz, respectively.

POWER DISSIPATION

The AD7767/AD7767-1/AD7767-2 offer exceptional perform­ance at ultralow power. Figure 43, Figure 44, and Figure 45

how how the current consumption of the AD7767/AD7767-1/

s
AD7767-2 scales with the MCLK frequency applied to the
device. Both the digital and analog currents scale as the MCLK
frequency is reduced. The actual throughput of each of the
AD7767/AD7767-1/AD7767-2 equals the MCLK frequency
applied divided by the decimation rate employed by the device

2.0

DI

DD

1.5

1.0

CURRENT (mA)

0.5

0

0 1000k900k800k700k600k500k400k300k200k100k

FREQUENCY (Hz)

AI

DD

I

REF

06859-227

Figure 44. AD7767-1 Current vs. MCLK Frequency

1.4

1.2

1.0

0.8

0.6

CURRENT (mA)

0.4

0.2

0

0 1000k900k800k700k600k500k400k300k200k100k

FREQUENCY (Hz)

Figure 45. AD7767-2 Current vs. MCLK Frequency

I

REF

DI

DD

AI

DD

06859-228

Rev. 0 | Page 21 of 24

AD7767

www.BDTIC.com/ADI

V

INPUT SIGNAL

REF+

The AD7767/AD7767-1/AD7767-2 V

pin is supplied with a

REF +

5 V input, which is generated by a low noise voltage reference.
Either the ADR445 or the ADR425 can be used with the AD7767/
AD7767-1

/AD7767-2 device. This reference voltage input also
acts as a power supply to the AD7767/AD7767-1/AD7767-2
device.

The output of the low noise voltage reference does not require a
b

uffer; however, it is important to provide a passive filter network

between the V

pin of the voltage reference and the V

OUT

REF+

input on the ADC. Figure 46 shows a reference signal network
tha

t can be used with both the ADR445 and the ADR425.

The 100 nF capacitor on the output of the ADR445 or ADR425
s

tabilizes the reference output voltage. The series resistor coupled
with the other capacitive values on the reference acts as a low­pass filter.
cir

ADR445

ADR425

Figure 46 shows the optimal reference voltage input

cuit.

100Ω

5V

V

OUT

C39

OR

100nF

Figure 46. AD7767/AD7767-1/AD7767-2 Reference Filtering,

ADR445 or ADR425 Circuit Topology

C40
100µF

C15
10µF

V

REF+

C38
100nF

AD7767/

AD7767-1/

AD7767-2

06859-229

For the capacitor designated C40 in Figure 46, either an
electrolytic or tantalum capacitor can be used. This capacitor
acts as a reservoir of charge. Further decoupling capacitors are
placed as close as possible to the V

REF+

pin.

MULTIPLEXING ANALOG INPUT CHANNELS

The AD7767/AD7767-1/AD7767-2 can be used with a multi­plexer configuration. As per any converter that uses a digital
filtering block, the maximum switching rate, or output data rate
per channel, is a function of the digital filter settling time.

A user multiplexing the analog inputs to a converter that
em

ploys a digital filter must wait the full digital filter settling
time before a valid conversion result is achieved; at this point,
the channel can be switched. After switching the channel, the
full settling time must again be observed before a valid conver­sion result is available and the input is switched once more.

The AD7767 filter settling time equals 74 divided by the output
da

ta rate in use. The maximum switching frequency in a
multiplexed application is therefore 1/(74/ODR), where the
output data rate (ODR) is a function of the applied MCLK
frequency and the decimation rate employed by the device in
question. For example, applying a 1.024 MHz MCLK frequency
to the AD7767 gives a maximum output data rate of 128 kHz,
which in turn allows a 1.729 kHz multiplexer switching rate.

The AD7767-1 and the AD7767-2 employ digital filters with
l

onger settling time to achieve greater precision; thus, the
maximum switching frequency for these devices is 864 Hz and
432 Hz, respectively.

Rev. 0 | Page 22 of 24

AD7767

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

16

4.50

4.40

4.30

PIN 1

0.65

BSC

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 47. 16-Lead Thin Shrink S

9

6.40
BSC

81

1.20
MAX

0.30

0.19

Dimensions shown in millimeters

SEATING
PLANE

(RU-16)

0.20

0.09

mall Outline Package [TSSOP]

8°
0°

0.75

0.60

0.45

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7767BRUZ
AD7767BRUZ-RL7
AD7767BRUZ-1
AD7767BRUZ-1-RL7
AD7767BRUZ-2
AD7767BRUZ-2-RL7
EVAL-AD7767EDZ
EVAL-AD7767-1EDZ
EVAL-AD7767-2EDZ
EVAL-CED1Z

1

Z = RoHS Compliant Part.

1

1

1

1

1

1

−40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

−40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

−40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

1

−40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

−40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

1

−40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

1

1

Evaluation Board
Evaluation Board
Evaluation Board
Converter Evaluation and Development Board

Rev. 0 | Page 23 of 24

AD7767

www.BDTIC.com/ADI

NOTES

©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06859-0-8/07(0)

Rev. 0 | Page 24 of 24