AMX 68000 User Manual

AMX™ 68000 Target Guide

First Printing: April 15, 1994
Last Printing: March 1, 2005

®

Copyright © 1994 - 2005

KADAK Products Ltd.

206 - 1847 West Broadway Avenue

Vancouver, BC, Canada, V6J 1Y5

Phone: [phone]
Fax: [phone]

TECHNICAL SUPPORT

KADAK Products Ltd. is committed to technical support for its software products. Our
programs are designed to be easily incorporated in your systems and every effort has
been made to eliminate errors.

Engineering Change Notices (ECNs) are provided periodically to repair faults or to
improve performance. You will automatically receive these updates during the product's
initial support period. For technical support beyond the initial period, you must purchase
a Technical Support Subscription. Contact KADAK for details. Please keep us inform ed
of the primary user in your company to whom update notices and other pertinent
information should be directed.

Should you require direct technical assistance in your use of this KADAK software
product, engineering support is available by telephone, fax or e-mail. KADAK reserves
the right to charge for technical support services which it deems to be beyond the normal
scope of technical support.

We would be pleased to receive your comments and suggestions concerning this produ ct
and its documentation. Your feedback helps in the continuing product evolution.

AMX 68000 Target Guide

KADAK Products Ltd.

206 - 1847 West Broadway Avenue

Vancouver, BC, Canada, V6J 1Y5

Phone: [phone]
Fax: [phone]
e-mail: [e-mail]

KADAK

i

Copyright © 1994-2005 by KADAK Products Ltd.

All rights reserved.

No part of this publication may be reproduced, transmitted, transcribed,
stored in a retrieval system, or translated into any language or computer
language, in any form or by any means, electronic, mechanical,
magnetic, optical, chemical, manual or otherwise, without the prior
written permission of KADAK Products Ltd., Vancouver, B.C., CANADA.

DISCLAIMER

KADAK Products Ltd. makes no representations or warranties with
respect to the contents hereof and specifically disclaims any implied
warranties of merchantability and fitness for any particular purpose.
Further, KADAK Products Ltd. reserves the right to revise this
publication and to make changes from time to time in the content
hereof without obligation of KADAK Products Ltd. to notify any
person of such revision or changes.

TRADEMARKS

AMX in the stylized form and KwikNet are registered trademarks of KADAK Products Ltd.
AMX, AMX/FS, InSight,
Microsoft, MS-DOS and Windows are registered trademarks of Microsoft Corporation.
All other trademarked names are the property of their respective owners.

ii

KwikLook and KwikPeg are trademarks of KADAK Products Ltd.

KADAK

AMX 68000 Target Guide

AMX 68000 TARGET GUIDE

Table of Contents

Page

1. Getting Started with AMX 68000 1

1.1 Introduction ........................................................................................ 1

1.2 AMX Files .......................................................................................... 2

1.3 AMX Nomenclature ........................................................................... 4

1.4 AMX 68000 Target Specifications ..................................................... 5

1.5 Launch Requirements ......................................................................... 6

2. Program Coding Specifications 9

2.1 Task Trap Handler .............................................................................. 9

2.2 Task Scheduling Hooks ...................................................................... 10

3. The Processor Interrupt System 11

3.1 Operation ............................................................................................ 11

3.2 AMX Vector Table ............................................................................ 13

3.3 AMX Interrupt Priority and NMI ....................................................... 15

3.4 Conforming ISPs ................................................................................ 16

3.5 Nonconforming ISPs .......................................................................... 18

3.6 Processor Vector Initialization ........................................................... 19

4. Target Configuration Module 21

4.1 The Target Configuration Process ...................................................... 21

4.2 Target Configuration Parameters ....................................................... 25

4.3 Interrupt Service Procedure (ISP) Definitions .................................... 29

4.4 Defining a Fast Clock ISP .................................................................. 32

4.5 Null Functions .................................................................................... 34

4.6 ROM Option Parameters .................................................................... 35

5. Clock Drivers 37

5.1 Clock Driver Operation ...................................................................... 37

5.2 Custom Clock Driver ......................................................................... 39

5.3 AMX Clock Drivers ........................................................................... 41

5.3.1 MC683xx TPU Clock Driver .......................................................... 41

5.3.2 MC68360 PIT Clock Driver ............................................................ 42

5.3.3 MC68230 Clock Driver ................................................................... 43

5.3.4 MC68901 Clock Driver ................................................................... 44

AMX 68000 Target Guide

KADAK

iii

AMX 68000 TARGET GUIDE

Table of Contents (Cont'd)

Appendices

Page

Appendix A. Target Parameter File Specification A-1

A.1 Target Parameter File Structure ......................................................... A-1

A.2 Target Parameter File Directives ....................................................... A-3

A.3 Porting the Target Parameter File ......................................................A-11

Appendix B. AMX 68000 Service Procedures B-1

Appendix C. AMX 68000 ROM Option C-1

AMX 68000 TARGET GUIDE

Table of Figures

Page

Figure 1.2-1 AMX Include Files .............................................................. 2

Figure 1.2-2 AMX Assembler Source Files ............................................. 2

Figure 1.2-3 AMX C Source Files ........................................................... 3

Figure 1.4-1 AMX Design Constants ....................................................... 5

Figure 3.2-1 AMX Vector Table and Vector Numbers ............................ 14

Figure 4.1-1 Configuration Manager Screen Layout ................................ 22

Figure A.1-1 AMX Target Parameter File ............................................... A-1

iv rev9

KADAK

AMX 68000 Target Guide

1. Getting Started with AMX 68000

1.1 Introduction

The AMX™ Multitasking Executive is described in the AMX User's Guide. This target
guide describes AMX 68000 which operates on the Motorola MC680xx, MC683xx and
all architecturally compatible processors.

Throughout this manual, the term M68000 refers specifically to the Motorola MC680xx
and MC683xx families of processors and all processors which are exact replic as. When
distinctions are not important, the term M68000 is used to reference any processor which
has the general characteristics of these families. When distinctions are important, the
processors are identified explicitly.

The purpose of this manual is to provide you with the information required to properly
configure and implement an AMX 68000 real-time system. It is assumed that you have
read the AMX User's Guide and are familiar with the architecture of the M68000
processor.

Installation

AMX 68000 is delivered ready for use on a PC or compatible running Microsoft
Windows®. To install AMX, follow the directions in the Installation Guide. All AMX
files required for developing an AMX application will be installed on disk in the
directory of your choice. All AMX source files will also be installed on your disk.

AMX Tool Guides

This manual describes the use of AMX in a tool set independent fashion. References to
specific assemblers, compilers, librarians, linkers, locators and debuggers a re purposely
omitted. For each tool set with which AMX 68000 has been tested by KADAK, a
separate chapter in the AMX Tool Guide is provided.

®

AMX 68000 Target Guide

KADAK

1

1.2 AMX Files

AMX is provided in C source format to ensure that regardless of your development
environment, your ability to use and support AMX is uninhibited. AMX also includes a
small portion programmed in M68000 assembly language.

Figures 1.2-1, 2 and 3 summarize the AMX modules provided with AMX 68000. The
AMX product manifest (file MANIFEST.TXT) is a text file which indicates the current
AMX revision level and lists the AMX modules which are provided with the product.

File Name Module

CJ532 .H Generic include file
CJ532APP.H Custom application definitions
CJ532CC .H C dependent definitions
CJ532EC .H AMX error code definitions
CJ532IF .H C and target interface prototypes
CJ532KC .H Private AMX constants
CJ532KF .H AMX service procedure prototypes
CJ532KP .H Private AMX prototypes
CJ532KS .H Private AMX structure definitions
CJ532KT .H Target processor definitions
CJ532KV .H AMX version specification
CJ532SD .H AMX application structure definitions
CJ532TF .H Target dependent prototypes

CJZZZ .H Copy of generic include file CJ532.H

used for portability

CHxxxxx .H Definitions for common timer (PIT, TPU)

and serial I/O (UART) chips

Figure 1.2-1 AMX Include Files

File Name Module

CJ532K .DEF Private AMX assembly language definitions
CJ532KQ .ASM Private AMX math procedures
CJ532KR .ASM AMX Interrupt Supervisor
CJ532KS .ASM AMX Task Scheduler
CJ532MXA.ASM Message Exchange Manager constants
CJ532TDC.ASM Time/Date Manager constants
CJ532UA .ASM Target processor and C support (part 1)
CJ532UB .ASM Target processor and C support (part 2)

Figure 1.2-2 AMX Assembler Source Files

2

KADAK

AMX 68000 Target Guide

File Name Module

CJ532KA .C Kernel task services
CJ532KB .C General task services

CJ532KBR.C
CJ532KC .C

CJ532KCR.C
CJ532KD .C

CJ532KDR.C
CJ532KE .C
CJ532KF .C Suspend/resume task
CJ532KG .C Time slice services
CJ532KH .C Task status
CJ532KI .C Enter and Exit AMX
CJ532KJ .C General object access
CJ532KK .C AMX Vector Table access
CJ532KL .C Private AMX list manipulation
CJ532KM .C AMX task scheduler hook services
CJ532KX .C AMX Kernel Task

CJ532CL .C Circular List Manager
CJ532LM .C Linked List Manager

CJ532BM .C Buffer Manager
CJ532BMR.C

CJ532EM .C
CJ532EMR.C

CJ532RM .C
CJ532SM .C Semaphore Manager

CJ532SMR.C
CJ532MB .C

CJ532MBR.C
CJ532MF .C
CJ532MM .C Memory Manager

CJ532MMR.C
CJ532MX .C

CJ532MXR.C

Timer Manager
Task management services
Task termination services

Event Manager
Semaphore Manager (resources)

Mailbox Manager
Flush mailbox and message exchange

Message Exchange Manager

CJ532TDA.C
CJ532TDB.C Time/Date formatter

CJ532UF .C Launch and leave AMX
CJ532XTA.C Message exchange task services

CJ532XTB.C Message exchange task termination
CHxxxxxT.C Clock drivers for common timer (PIT, TPU) chips

CHxxxxxS.C Sample drivers for common serial I/O (UART) chips

AMX 68000 Target Guide

Time/Date Manager

Figure 1.2-3 AMX C Source Files

KADAK

3

1.3 AMX Nomenclature

The following nomenclature standards have been adopted throughout the AMX Target
Guide.

Numbers used in this manual are decimal unless otherwise indicated. Hexadecimal
numbers are indicated in the format 0xABCD or $ABCD.

The terminology A(Table XYZ) is used to define addresses. It is read as "the address of
Table XYZ".

Read/write memory is referred to as RAM. Read only memory (non-volatile storage) is
referred to as ROM.

AMX symbol names and reserved words are identified as follows:

cjkkpppp AMX C procedure name pppp for service of class kk
cjxtttt
xttttyyy

AMX structure name of type tttt
Member yyy of an AMX structure of type tttt

CJ_ID
CJ_ERRST Completion status returned by AMX service procedures
CJ_CCPP Procedures use C parameter passing conventions
CJ_ssssss Reserved symbols defined in AMX header files

CJ_ERxxxx AMX Error Code xxxx
CJ_WRxxxx
CJ_FExxxx

CJ532xxx.xxx
CJZZZ.H Generic AMX include file

AMX object identifier (handle)

AMX Warning Code xxxx
AMX Fatal Exit Code xxxx

AMX 68000 filenames

The generic include file CJZZZ.H is a copy of file CJ532.H which includes the subset of
the AMX 68000 header files needed for compilation of your AMX application C code.
By including the file CJZZZ.H in your source modules, your AMX application becomes
readily portable to other target processors.

Throughout this manual code examples are presented in lower case. File names are
shown in upper case. C code assumes that an

int is 32 bits as is common for most C

compilers for the M68000 processor.
Processor registers are referenced using the software names specified by Motorola.

D0, D1, D2, D3, D4, D5, D6, D7
A0, A1, A2, A3, A4, A5, A6, A7
PC, SP = A7

SR =

status register, CC = flags (condition code)

4

KADAK

AMX 68000 Target Guide

1.4 AMX 68000 Target Specifications

AMX 68000 was initially developed and tested using the Motorola MC68020, MC68040
and MC68332 processors on a variety of Motorola evaluation boards. However, the
AMX 68000 design criteria fully encompass the Motorola M68000 processor family
requirements.

AMX uses a set of design constants which vary according to the constraints imposed by
each target processor. When operating on the M68000 processor, these design constants
assume the values listed in Figure 1.4-1.

Symbol Purpose

CJ_CCISIZE Size of integer is 4 bytes (32 bits)

Event group supports 32 event flags per group

CJ_ID AMX id (handle) is a 32 bit unsigned integer
CJ_ERRST AMX error codes are 32 bit signed integers

CJ_MINMSZ Minimum AMX message size is 12 bytes
CJ_MAXMSZ Default AMX message size is 12 bytes
CJ_MINKG Minimum number of AMX message envelopes is 10

CJ_MINKS Minimum Kernel Stack is 256 bytes
CJ_MINIS Minimum Interrupt Stack is 256 bytes
CJ_MINTKS Minimum task storage (including TCB) is 512 bytes

CJ_MINBFS Minimum AMX buffer size is 8 bytes
CJ_MINUMEM Minimum AMX memory block size is 16 bytes
CJ_MINSMEM Minimum AMX memory section size is 128 bytes

Figure 1.4-1 AMX Design Constants

AMX 68000 Target Guide

KADAK

5

1.5 Launch Requirements

The M68000 must be properly configured for use before AMX is launched. The manner
in which this is accomplished will depend on your target hardware implementation and
on the startup code provided with your C compiler.

AMX does not include bootstrap code to initialize the M68000 processor. It is assumed
that you will have a boot ROM present which configures the M68000 for your specific
hardware configuration and begins program execution at the entry to your C startup code.

During development, you may be using a ROM monitor provided by the processor
vendor or by the toolset supplier. The ROM monitor automatically initializes the
processor at power on. The monitor is then used to download your AMX application and
start execution at the entry point to the C startup code. Eventuall y your main C program
is called and AMX can be launched by your call to cjkslaunch.

Once your application has been tested, you may choose to replace the ROM monitor and
the C startup code with your own initialization code. The manner in which you do this is
outside the scope of this manual.

Operating Mode

AMX requires that the processor be set to supervisor mode. The processor is in
supervisor mode when the supervisor/user state bit S is 1 in the status register (SR). This
is the default state when the processor is reset.

Interrupt State

Interrupts can be enabled or disabled on entry to AMX. Set the interrupt priority mask in
the status register to disable (0x0600) or enabl e (0x0000) external interrupts. AMX will
disable interrupts during its startup initialization. AMX will enable interrupts prior to
calling your application Restart Procedures.

If you launch AMX with interrupts enabled, be sure that all interrupt sources are either
disabled or externally masked off. You must not enable or unmask any interrupt source
until you have installed an AMX Interrupt Service Procedure to properly service the
device. This subject is described in more detail in Chapters 3 and 4.

For the MC68020, MC68030, MC68040, MC68060 and architecturally similar
processors, AMX requires that the processor be set to interrupt mode. The processor is
in interrupt mode when the master/interrupt state bit

M is 0 in the status register (SR). This

is the default state when the processor is reset.
Some M68000 processors include a Vector Base Register (VBR) which must be

initialized with the address of the Exception Vector Table. AMX can be configured to do
this initialization at launch time. Alternatively you can initialize the VBR prior to
launching AMX and allow AMX to read the VBR without modifying it.

6

KADAK

AMX 68000 Target Guide

Trace Controls

AMX alters the state of the status re gister (SR) whenev er it enables or di sables interrupts.
When AMX disables interrupts, it also clears the trace control bits (T or T0 an d T1) to 0.
When AMX enables interrupts, the trace control bits remain unaltered. Consequently,
you may not be able to use your debugger to single step trace through private AMX code
sequences.

M68000 Stack Use

The M68000 begins execution in supervisor mode (and interrupt mode for the MC68020,
MC68030, MC68040, MC68060, et al) using the initial interrupt stack specified by
vector number 0 in the Exception Vector Table. Your bootstrap code or C startup code
may switch to an alternate stack. Once AMX is launched, it abandons the startup stack.
AMX only uses the stacks allocated by you in your AMX System Configuration Module.
To accomplish this feat on processors which support multiple stacks, AMX always
executes in the interrupt mode (M = 0 in SR).

Instruction and Data Caching

The MC68020 includes a 256-byte instruction cache but no data cache.
The MC68030 includes a 256-byte instruction cache and a 256-byte data cache.
The MC68040 includes a 4096-byte instruction cache and a 4096-byte data cache.
The MC68060 includes an 8192-byte instruction cache and an 8192-byte data cache.

If your AMX Target Parameter File (see Chapter 4) targets one of these processors, AMX
will automatically flush and enable both caches when AMX is launched. Alternatively,
you can configure AMX to ignore the caches during the launch. AMX provides
procedures which you can use to enable or disable the caches.

For example, if you disable both caches in your main program and configure AMX to
ignore the cache, you can simplify the initial testing of your application or overcome
caching problems which may be encountered if your debugger cannot properly handle
cached operation.

You must be aware that, on processors which utilize an M68000 Memory Mana gement
Unit (MMU), successful cache operation will depend on proper setup of the MMU. For
example, if the MMU does not properly control cach ed access to memory and devices,
you may find that device I/O reads and writes end up being cached, resulting in failure of
the device to operate as expected.

AMX does not manipulate the MMU. If you configure AMX to enable caching during
the launch, then you must ensure that the MMU is properly initialized to meet your
hardware memory addressing specifications prior to launching AMX. The AMX Sample
Program purposely leaves the caches unal tered to avoid possible cache related problems
during your initial use of AMX in your hardware environment.

AMX 68000 Target Guide

KADAK

rev6 7

Memory Management Unit (MMU)

The MC68030, MC68040, MC68LC040 and MC68060 include a Memory Management
Unit (MMU) to support a demand-paged virtual memory environment. AMX does not
support the M68000 memory management unit.

If you are using AMX on the Motorola MC68000, MC68008, MC68010 or MC683xx
processors, this restriction does not apply. These processors do not implement the
M68000 memory management unit and allow direct access to the full 20, 24 or 32-bit
address space supported by the particular processor.

Your AMX application code and data must reside within the memory address ranges
allowed by the particular M68000 processor which you are using. Th e M68000 MMU, if
present, must be setup prior to launching AMX. In most cases, your boot ROM or C
startup code will configure the M68000 MMU for your spe cific hardware configuration
prior to entry to your

main() program.

Warning!

Do not enable the memory caches if the MMU has not been
initialized to provide proper cached access to memory.

Big or Little Endian

AMX 68000 adheres to the big endian model in which the most significant byte of a word
(long) is stored in the lowest byte address.

Be aware that AMX for other processors may be big or little endian. If you intend to port
your AMX application to other processors, then avoid using coding techniques which are
endian dependent.

8

KADAK

AMX 68000 Target Guide

2. Program Coding Specific ations

2.1 Task T rap Handler

AMX 68000 supports task traps for the M68000 zero divide, bounds check and overflow
faults. A zero divide fault occurs if any M68000 instruction attempts an integer division
by zero. A bounds check fault occurs if the M68000
bound violation. An overflow fault occurs if the overflow flag (V) is set in the status
register (SR) at the time an M68000 TRAPV instruction is executed.

The Task Trap Handler can be written as a C procedure with formal parameters.

#include "CJZZZ.H" /* AMX Headers */

void CJ_CCPP traphandler(
struct cjxregs *regp, /* A(Register Structure) */
void *faultfp) /* A(Fault frame) */
{

:
Process the error
:
}

The zero divide, bounds check and overflow exceptions are serviced b y AMX. The state
of each register at the time of the fault is stored on the stack in an AMX register structure

cjxregs. Parameter regp is a pointer to that structure. Structure cjxregs is defined in

AMX header file CJ532KT.H.

CHK instruction detects an array

Interrupts are enabled upon entry to the task trap handler. Note that the SR register copy
in the register array reflects the state of the status register after the exception occurred.

A pointer to the M68000 fault frame is provided as parameter faultfp. This pointer is
the M68000 stack pointer (SP) after the fault has occurred. Fault frame members can be
referenced as described in Chapter 3.1.

The register values in structure

regs can be examined and, in rare circumstances,

modified. If necessary, the fault frame at *faultfp can be modified, with ex treme care,
to force resumption at some other location in the task code. If the task trap handler
returns to AMX, execution will resume at the location determined by the fault frame at

*faultfp with registers set according to the values i n the structure referenced by regp.

Note that the

SR register will be restored according to the value returned in the fault frame

referenced by faultfp.
Since the task trap handler executes in the context of the task in which the exception

occurred, it is free to use all AMX services normally available to tasks. In particular, the
handler can call

cjtkend to end task execution if so desired.

AMX 68000 Target Guide

KADAK

9

2.2 Task Scheduling Hooks

There are four critical points within the AMX Task Scheduler. These critical points
occur when:

a task is started
a task ends
a task is suspended
a task is allowed to resume.

AMX allows a unique application procedure to be provided for each of these critical
points. Pointers to your procedures are installed with a call to procedure cjkshook. You
must provide a separate procedure for each of the four critical points. Since these
procedures execute as part of the AMX Task Sch eduler, their operati on is critical. Th ese
procedures must be coded in assembler using techniques designed to ensure that they
execute as fast as possible.

The AMX Task Scheduler calls each of your procedures with the same calling
conventions.

Upon entry to your scheduling procedures, the following conditions exist:

Interrupts are disabled and must remain so.
The Task Control Block address is in register A1.
The stack pointer in register SP references the task's stack.
The return address is on the stack at (SP).
Registers D0, D1, A0, A1, A2 and A3 are free for use.
Condition code flags in the status register (SR) can be altered.
All other registers must be preserved.

Your procedures receive a pointer to the Task Control Block (TCB) of the task which is
being started, ended, suspended or resumed. If you include AMX header file

CJ532K.DEF in your assembly language module, you can reference the private region

within the TCB reserved for your use as

XTCBUSER(A1).

Your procedures are free to temporarily use the task's stack.

10

KADAK

AMX 68000 Target Guide

3. The Processor Interrupt System

3.1 Operation

The M68000 classifies all internal and external sources of interruption as exceptions.
The processor automatically determines the cause of the exception and then branches
indirectly through entries in the processor Exception Vector Table to an appropriate
exception specific procedure.

The particular procedures which service internal or ex ternal device interrupt requests are
called Interrup t Service Procedures. All other proc edures are referred to as exception
service procedures.

Upon entry to any Interrupt Service Procedure or exception service procedure the
processor state is determined by the particular exception.

Device Interrupt Service

A subset of the exception vectors are reserved for the control of d evices external to, or
embedded in, the processor. These vectors include:

Vector 15 Uninitialized interrupt vector
Vector 24 Spurious interrupt
Vectors 25 Interrupt priority level 1 (lowest)
to
Vector 30 Interrupt priority level 6 (highest)
Vector 31 Interrupt priority level 7 (Non-Maskable)
Vectors 64 User assignable interrupts
to 255

The external interrupt facility is enabled by setting the interrupt mask in the processor
status register (

SR) to 0 thereby enabling interrupts from priority levels 1 to 6. Note that

interrupt priority level 7 cannot be inhibited.
The external interrupt facility is disabled by setting the interrupt mask in the processor

status register (SR) to 6 thereby inhibiting interrupts from priority levels 1 to 6 inclusive.
AMX never sets the processor interrupt mask to 7.

When an interrupt occurs at priority level

n, the processor pushes zero or more words of

processor dependent information on the current stack. The return address (current
Program Counter) and the content of the processor status register are then pushed onto
the current stack. The processor interrupt mask is set to

n thereby disabling all external

interrupts of priority less than or equal to n.
The interrupting device then identifies the interrupt source. In most cases, the device lets

the processor use the interrupt priority level n vector. However, devices can be designed
to present the processor with their own vector number. Any vector number in the range 0
to 255 is possible, but vectors 64 to 255 are reserved for this purpose. Programmable
devices which have not been programmed with their particular vector number usually
respond with vector number 15 signifying an uninitialized interrupt. If no device
responds to the processor's demand for interrupt acknowledgment, the processor uses the
spurious interrupt vector number 24.

AMX 68000 Target Guide

KADAK

11

Default Exception Service Procedures

AMX provides default service procedures for most exceptions. The zero divide, bounds
check and overflow exceptions are serviced by AMX using its Task Trap Handler
mechanism. All other exceptions handled by AMX are treated as fatal. AMX calls a
Fatal Exception Procedure cjksfatalexh in module CJ532UF.C identifying the
exception and the machine state at the time of the exception. If the Fatal Exception
Procedure returns, AMX calls the Fatal Exit Procedure cjksfatal in the same module
with one of the following fatal exit codes:

CJ_FETRAP Fatal exception trap
CJ_FEISPTRAP Task exception trap in ISP
CJ_FETKTRAP Task exception trap occurred:

in a Restart Procedure or
in a Timer Procedure or
in a task with no task trap handler

The Fatal Exception Procedure is written in C as follows. Prior to entry, interrupts are
in the state determined by the particular exception.

#include "CJZZZ.H" /* AMX Headers */

void CJ_CCPP cjksfatalexh(
struct cjxregs *regp, /* A(Register structure) */
int vnum, /* Vector number */
void *faultfp) /* A(Fault frame) */
{

:
Process the error
:
}

The state of each register at the time of the fault is stored on the stack in an AMX register
structure cjxregs. Parameter regp is a pointer to that st ructure. Structure cjxregs is
defined in AMX header file CJ532KT.H.

Note that the

SR register copy in the regist er array reflects the state of the status register

after the exception occurred.
A pointer to the M68000 fault frame is provided as parameter

the M68000 stack pointer (

SP) after the fault has occurred. Fault frame members can be

faultfp. This pointer is

referenced as follows:

*((CJ_T16U *)faultfp) is the SR saved in the fault frame
*((CJ_T32U *)((CJ_T16U *)faultfp + 1))

is the A(fault instruction)

*((CJ_T16U *)faultfp + 3) is the frame format type and vector offset

12

KADAK

AMX 68000 Target Guide

3.2 AMX Vector Table

The M68000 processor provides an Exception Vector Table, often referred to as the
AMX Vector Table, through which device interrupts are vectored and processor faults are
trapped. The position of entries in the table and the vector numbers used to reference
them are dictated by Motorola.

AMX provides a set of cjksixxxx service procedur es t o all ow you to dynamically access
or modify entries in the AMX Vector Table. The Motorola vector numbers must be used
in all calls to these procedures to identify entries in the table.

Device Interrupts

AMX uses the AMX Vector Table to maintain pointers to Inter rupt Service Procedures
for all of the device interrupts to which the processor will respond. AMX does not
provide a default Interrupt Service Procedure for ever y device interrupt. However, AMX
does provide a default exception service procedure for the spurious interrupt (vector
number 24) and the uninitialized interrupt (vector number 15).

Processor Exceptions

AMX maintains entries in the AMX Vector Table for all of the processor exceptions for
which AMX assumes responsibility. These entries in the Vector Table are identified by
Motorola's exception vector numbers which are defined in AMX header file CJ532KT.H.
Figure 3.2-1 summarizes the exception vector mnemonics.

A 32-bit mask in your Target Parameter File is used to specify which of the possible
exceptions you wish AMX to service. The mask bits are defined in Figure 3.2-1. The
AMX Configuration Builder (see Chapter 4) puts a directive in your Target Parameter
File to specify the mask required to meet your configuration requirements.

If an enable mask bit is not defined in Figure 3.2-1 for a particular ex ception, then AMX
will not provide a default exception service procedure for that exception. For example,
AMX does not provide service for the

TRAP n vectors (vector numbers 32 to 47). Hence,

all software traps are available for use by your application.
AMX does not provide default exception service procedures for any of the entries which

Motorola has declared as undefined but reserved.

AMX 68000 Target Guide

KADAK

13

Vector Vector Enable
Name Number Mask Exception

CJ_PRVNRES 0, 1 Reset
CJ_PRVNBE 2 $00000004 Bus error (access fault)
CJ_PRVNAE 3 $00000008 Address error
CJ_PRVNII 4 $00000010 Illegal instruction
CJ_PRVNZD 5 $00000020 Zero divide
CJ_PRVNCH 6 $00000040 CHK instruction trap
CJ_PRVNTV 7 $00000080 TRAPV instruction trap
CJ_PRVNPV 8 $00000100 Privilege violation
CJ_PRVNTR 9 $00000200 Trace
CJ_PRVNLA 10 $00000400 Line 1010 (A) emulator
CJ_PRVNLF 11 $00000800 Line 1111 (F) emulator

12 reserved

CJ_PRVNCP 13 $00002000 Coprocessor protocol violation
CJ_PRVNFE 14 $00004000 Format error (>= 68010)
CJ_PRVNUI 15 $00008000 Uninitialized interrupt

16 to 23 reserved

CJ_PRVNSI 24 $00000002 Spurious interrupt

25 to 31 Level 1 to 7 interrupt autovectors

CJ_PRVNTT 32 to 47 TRAP 0 to 15 Table
CJ_PRVNFPBS 48 $01000000 FP Branch or set on unordered condition

CJ_PRVNFPIN 49 $02000000 FP Inexact result
CJ_PRVNFPDZ 50 $04000000 FP Divide by zero
CJ_PRVNFPUN 51 $08000000 FP Underflow
CJ_PRVNFPOP 52 $10000000 FP Operand Error
CJ_PRVNFPOV 53 $20000000 FP Overflow
CJ_PRVNFPSN 54 $40000000 FP Signalling NAN
CJ_PRVNFPUD 55 $80000000 FP Unimplemented data type

CJ_PRVNMMCF 56 MMU Configuration error
CJ_PRVNMMOP 57 MMU Illegal operation
CJ_PRVNMMAV 58 MMU Access level violation

59 to 63 reserved

64 to 255 User defined

Figure 3.2-1 AMX Vector Table and Vector Numbers

14

KADAK

AMX 68000 Target Guide

3.3 AMX Interrupt Priority and NMI

The M68000 family of processors offers inherent interrupt priority ordering. The AMX
Interrupt Supervisor supports this feature and allows the nesting of interrupts for fast
response to high priority events.

The M68000 interrupt priority mask in the status (SR) register establishes the current
interrupt priority. Tasks run at interrupt priority level 0 with all interrupt sources
enabled. Some interrupts may be specifically disabled by an external interrupt controller.

Tasks must NOT alter the interrupt priority level to any level other than 0 (enabled) or
6 (disabled). Doing so will interfere with the interrupt nesting support provided by
AMX.

Interrupt Service Procedures run at the interrupt priority level dictated by the interrupt
source. An ISP must NOT set the interrupt priority level to any level numerically lower
than the level of the interrupt which it is servicing.

Non-Maskable Interrupt

The Motorola M68000 processor provides a non-maskable priority level 7 interrupt
(NMI). This interrupt cannot be inhibited by software. The processor will respond to
any transition from interrupt request levels 0 to 6 to level 7 by generating a non-maskable
interrupt. When the non-maskable interrupt occurs, the processor automatically saves
zero or more processor dependent parameters, the return address and the processor status
register on the current stack. The processor then vectors to a memory address determined
by the level 7 interrupt autovector (vector number 31) in the Exception Vector Table.

You have complete control over the non-maskable interrupt ISP. Usually, the NMI
interrupt is used to signal a catastrophic event such as a pending loss of power. The NMI
ISP must not use any AMX services. The ISP must process the interrupt in an
application-dependent fashion, restore all registers and return to the point of interruption
if feasible. This ISP must assure that the interrupt facility is restored according to its
state at the time the non-maskable interrupt occurred.

Warning!

Because the occurrence of an NMI interrupt cannot be
controlled, the NMI interrupt can occur at any instant,
including within critical sections of AMX.

Consequently, the NMI ISP cannot use AMX service
procedures for task communication.

AMX 68000 Target Guide

KADAK

15

3.4 Conforming ISP s

A conforming ISP consists of an ISP root and a device Interrupt Handler. The ISP root is
created in your Target Configuration Module by the AMX Configuration Generator using
the information provided in your Target Parameter File (see Chapter 4).

The address of the ISP root must be installed in the AMX Vector Table. You must
provide a Restart Procedure or task which calls AMX procedure cjksivtwr or cjksivtx
to install the ISP root pointer into the AMX Vector Table prior to enabling interrupt
generation by the device.

The ISP root is the actual Interrupt Service Procedure which is executed by the proc essor
when the interrupt occurs. The ISP root calls the AMX Interrupt Supervisor to indicate
that interrupt service has begun.

The ISP root then calls the device Interrupt Handler to dismiss the interrupt request and
service the device. Upon return from the Interrupt Handler, the ISP root informs the
Interrupt Supervisor that the interrupt service is complete. The Interrupt Supervisor
either resumes execution at the point of interruption or invokes the Task Scheduler to
suspend the interrupted task in preparation for a context switch. The path taken is
determined by the actions initiated by your Interrupt Handler.

Interrupt Handlers can be written as C procedures with or without a single 32-bit formal
parameter. The parameter, if needed, is identified in your definition of the ISP root in
your Target Parameter File (see Chapter 4.3).

Upon entry to your Interrupt Handler written in C, the following conditions exist:

Interrupts are enabled at priority n (0 to 6) where n is the priority at which
the interrupt occurred.
The stack pointer in register SP references the AMX Interrupt Stack.

The Interrupt Handler can also be written in assembly language. Use assembly language
if speed of execution is critical. Upon entry to an Interrupt Handler written in assembl y
language, the following conditions exist:

Your Interrupt Handler parameter is in register D1.
The stack pointer in register SP references the AMX Interrupt Stack.
The return address is on the stack at (

SP).

Registers D0, D1, A0 and A1 are free for use.
Condition code flags in the status register (

SR) can be altered.

All other registers must be preserved.

16 rev7

KADAK

AMX 68000 Target Guide

The following examples illustrate how simple an Interrupt Handler can be.

/* The ISP root definition in the Target Parameter File is as follows:*/
/* ...ISPC deviceisp,deviceih,26,0,0 */
/* The ISP root is given the public name deviceisp */
/* The Interrupt Handler is named deviceih */
/* The device interrupts on vector number 26 (level 2) */

void CJ_CCPP deviceih(void)
{

local variables, if required
:
Clear the source of the interrupt request.
Perform all device service.
:
}

/* Assume dcbinfo is some application device control block structure. */
/* Assume deviceXdcb is a structure variable defined as */
/* "struct dcbinfo deviceXdcb;". */
/* */
/* The ISP root definition in the Target Parameter File is as follows:*/
/* ...ISPC dcb_isp,dcb_ih,30,deviceXdcb,1 */
/* The ISP root is given the public name dcb_isp */
/* The Interrupt Handler is named dcb_ih */
/* The device interrupts on vector number 30 (level 6) */
/* deviceXdcb is the name of the public structure variable which */
/* contains information about the specific device. */

void CJ_CCPP dcb_ih(struct dcbinfo *dcbp)
{

local variables, if required
:
Use device control block pointer dcbp to access structure variable
deviceXdcb to determine device addresses.
Clear the source of the interrupt request.
Perform all device service.
:
}

AMX 68000 Target Guide

KADAK

17

3.5 Nonconforming ISPs

The M68000 family of processors provides an interrupt priority ordering mechanism
which permits the use of nonconforming ISPs within an AMX system. Since
nonconforming ISPs bypass the AMX Interrupt Supervisor, they cannot make use of any
AMX services.

Nonconforming ISPs run at the interrupt priority level dictated by the interrupt source. A
nonconforming ISP must NOT set the interrupt priority level to any level numerically
lower than the level of the interrupt which it is servicing. Higher priority interrupts are
only allowed if the corresponding ISPs are also nonconforming ISPs.

A nonconforming ISP must NOT allow an interrupt from ANY higher priority
conforming ISP. Remember that, in this context, the ISP for the device which generates
the AMX clock interrupt is considered to be a conforming ISP.

Upon entry to a nonconforming ISP the processor state matches its state at the time of the
interrupt. The processor is in supervisor mode with interrupts disabled at priorit y level n
(0 to 6) in the status register. No registers are free for use. All registers must be
preserved.

The nonconforming ISP executes on the stack in effect at the time of the interrupt.
Hence, the nonconforming ISP may execute on any task stack including the AMX Kernel
Task's stack. A nonconforming ISP will execute on the AMX Interrupt Stack if the
nonconforming ISP interrupts a conforming ISP.

The nonconforming ISP must service the device to remove the interrupt request and
dismiss the interrupt with an RTE instruction.

18

KADAK

AMX 68000 Target Guide

3.6 Processor Vector Initialization

Whenever an internal or external device interrupt occurs, the M68000 processor
unconditionally vectors to a unique memory address determined by an entry in the
processor Exception Vector Table. The cod e located at that address is cal led an Interrupt
Service Procedure.

Whenever an exception occurs, the M68000 processor also unconditionall y vectors to a
unique memory address determined by an entry in the processor Exception Vector Table.
The code located at that address is called an exception handler.

Your Target Parameter File defines whether the Exception Vector Table is in ROM or
RAM. The Target Parameter File further qualifies whether or not AMX is allowed to
modify the table if it is in RAM.

If the table is declared to be alterable, AMX will allow you to dynamically install
pointers to ISPs and exception handlers into the Exception Vector Table.

If the Exception Vector Table is in RAM and the table is declared to be alterable, AMX
will install pointers to the AMX Exception Supervisor into selected exception vectors in
the Exception Vector Table.

If the Exception Vector Table is unalterable (in ROM or simply constant by design), then
it is your responsibility to initialize the vector table to meet your requirements. The
address of a unique AMX exception handler must be installed in each entry in the
Exception Vector Table for which AMX is to be responsible.

Each AMX exception handler is located at an offset from entry point cj_kdevt in your
Target Configuration Module. Each offset is a multiple of 8 bytes. The AMX exception
mask identifies the specific exceptions which AMX must handle. An exception is
supported if its mask bit (see Figure 3.2-1) is enabled in the AMX exception mask. The
AMX exception handler for the exception identified by mask bit j is located at byte
address cj_kdevt+(i*8) where i is one less than the sum of the enabled bits in the
AMX exception mask, counted from bit 0 to bit j inclusive.

For example, if vectors 2 (bus error) through 8 (privilege violation) inclusive are the only
vectors to be serviced by AMX, the AMX exception mask will have value 0x000001FC.
The AMX bus error exception handler will be found at entry point

cj_kdevt (enable

mask is 0x0004, j is 2, the bit sum is 1 and i is therefore 0). The AMX privilege
violation exception handler will be found at entry point cj_kdevt+(6*8) (enable mask is

0x0100, j is 8, the bit sum is 7 and i is therefore 6).

You must also initialize entries in the Exception Vector Table for each interrupt which
your application can generate. For each interrupting device, you must install the addr ess
of the device's Interrupt Service Procedure (ISP) into the device's entry in the vector
table. For each conforming ISP or clock ISP, the address is the pointer to the ISP root
named in your AMX Target Configuration Module. For prebuilt AMX clock drivers, you
can determine the ISP root name by examining the call to

chclockinit() in the clock driver source module.

cjksivtx() in procedure

AMX 68000 Target Guide

KADAK

rev7 19

This page left blank intentionally.

20

KADAK

AMX 68000 Target Guide

4. Target Configuration Module

4.1 The Target Configuration Proce ss

Every AMX application must include a Target Configuration Module which defines
the manner in which AMX is to be used in your target hardware environment. The
information in this file is derived from parameters which you must provide in your Target
Parameter File.

The Target Parameter File is a text file which is structured according to the
specification presented in Appendix A. You create and edit this file using the AMX
Configuration Builder following the general procedure outlined in Chapter 16 of the
AMX User's Guide. If you have not already done so, you should review that chapter
before proceeding.

Using the Builder

When AMX is installed on your hard disk, the AMX Configuration Manager for
Windows utility program and its related files are stored in directory
AMX installation directory. To start the Configuration Manager, double click on its
filename, CJ532CM.EXE. Alternatively, you can create a Windows shortcut to the
manager's filename and then simply double click the shortcut's icon.

To create a new Target Parameter File, select New Target Parameter File from the File
menu. The Configuration Manager will create a new, as yet unnamed, file using its
default AMX target parameters. When you have finished defining or editing your target
configuration, select Save As... from the File menu. The Configuration Manager will save
your Target Parameter File in the location which you identify using the filename which
you provide.

CFGBLDW in your

A good starting point is to copy one of the Sample Target Parameter Files CJSAMTCF.UP
provided with AMX into file HDWCFG.UP. Choose the file for the evaluation board which
most closely matches your hardware platform. Then edit the file to define the
requirements of your target hardware.

To open an existing Target Parameter File such as

HDWCFG.UP, select Open... from the File

menu and enter the file's name and location or browse to find the file. When you have
finished defining or editing your target configuration, select Save from the File menu.
The Configuration Manager will rename your original Target Parameter File to be

HDWCFG.BAK and create an updated version of the file called HDWCFG.UP.

To direct the Configuration Manager to use its Configuration Generator utilit y to produc e
an updated copy of your Target Configuration Module, say HDWCFG.ASM, select

Generate... from the File menu. If necessary, the path to the template file required by the

generator to create your Target Configuration Module can be defined using the

Templates... command on the File menu.

The assembly language Target Configuration Module must be assembled as described in
the toolset specific chapter of th e AMX Tool Guide for inclusion in your AMX system.
The assembler will generate error messages which exactly pin-point any inconsistencies
in the parameters in your Target Parameter File.

AMX 68000 Target Guide

KADAK

21