VCC
Left Right Audio (Audio)LEFT/RIGHT 4
Expansion RAS Select 3
BLOB
NTSC/PAL Selection
2
BLOB
JP3
JP4
Keyboard Reset
JP2
JP1
BLOB
2
Memory Addr. C0 vs 08
BLOB
7
DESCRIPTION
REF TYPE
PAGE
Mem. Exp. Main-Board
CNX RA-56H
3
Expansion Connector 7
EDGE86P1
Keyboard Connector
CN13 SIL-8
6
Internal Floppy Signal 7
DIL-34
Internal Floppy Power
8
SIL-4
CN11
CN12
Video Output 5
DB23P
Composite Video
5
RCA-J
CN9
CN10
Parallel Printer Port
CN8
CN7
SQ DIN
8
Power Supply Connector
DB25S
6
External Floppy 7
DB23S
RS232 Serial Port
6
DB25P
CN5
CN6
Right Audio Output
CN4
CN3
RCA-J
4
Left Audio Output
RCA-J
4
Mouse/Joystick 1 2
DB9P
Mouse/Joystick 2
2
DB9P
CN1
CN2
DESCRIPTION PAGE
TYPEREF
HY1 asst
5
Video Hybrid
TTL 28.63636 MHz NTSC
X1
OSC
alt
TTL 28.37512 MHz PAL
OSC
2
DRAM 1Mx1, 150 nS
U20-23
U16-19
asst
9
DRAM 1Mx1, 150 nS
asst
3
EIA Line Receiver
U42
U39
NE555
7
Timer
1489
4
BiMOS Op-Amp
U38 1488
4
EIA Line Driver
TL084
alt
U14 LF347
4
BiMOS Op-Amp
ROM 128Kx16, 200 nS
U7-8
U6
8520
6
Amiga VIA, 1 MHz
asst
3
Denise HR
U5 5719
2,4
Gary
8373
alt
Paula
U4
U3
8362
5
Denise
8364
4
Fat Agnus - PAL
8372
alt
Agnus HR
8371
alt
68000 Processor
U2
U1
8370
2
Fat Agnus - NTSC
68000
2
DESCRIPTION
REF CHIP
PAGE
04/27/89
1
PCB Revision 6a/7 Production GRR
03/03/89Add E Clock Termination880283
DATEDESCRIPTIONECO NUMBER
312007
312006
C/A500
09/09/88
GRR
A PAGE FOR SHARON AND VONNIE TO USE
G. Robbins
C/A500 Main Board
C 1
8
1
APPR:
ENGR:
CHKD:
DATEBY:DRAWN
ONUSED ASSYNEXT
OFSHEETSCALE
SIZE
Commodore
REV
04/27/89
"Rock Lobster"
PATH:
/USER/B52_LIB/ROCK_LOBSTER_REV6.X SHEET1
ECO Log
Revision History
ATTEMPT TO FORCE NODE NUMBERS VIA SEQUENCE
Key Components
Jumpers and Stuff
Connectors
Signal Glossary
Schematic A500 R6a/7
A500 Rev 6a/7 PCB
+12V
-12V
+VID
AUDIO EXP
+5X
+12X
Expansion/Tick Option
JP8
JP7
BLOB
6
Light Pen Port Select
BLOB
3/6
Genlock Clock Select 2
BLOB
7MHz Clock Option
7
BLOB
JP5
JP6
TTL vs RS170 Comp Sync 5
BLOBJP11
JP10 BLOB
4
RS232 Audio I/O Cutout
see schematic 312511-01
-
For older Revision 3/5 boards
REV DATEDESCRIPTION MANAGER
APRVL
Upper / Lower Data Strobes (68000) 2,7LDS/UDS
LED Power On LED / Audio Filter Disable 4,6
Keyboard Data (Keyboard)
6Keyboard Reset (Keyboard)KBRESETKBRESET
KBDATA 6
Interrupt Priority Level (68000) 2,4,7IPL[2:0]
KBCLOCK Keyboard Clock (Keyboard) 6
Interrupt Request (Chips)
6,7I/O ResetIORESET
INT[2,3,6] 2,4,6,7
Horizontal Sync (Video)
6,7Index Pulse (Floppy)INDEX
HSYNC 2,5,6
Fire Button 0/1 (Joysticks) 2,5,6FIRE0/1
HLT Processor Halt (68000) 2,7
Expansion Present / RTC Tick
2,7Function Code (68000)FC[2:0]
EXTICK 2,3
Data Terminal Ready (RS232 Port) 6DTR
E Peripheral Enable Clock (68000) 2,6,7
Data Set Ready (RS232 Port) 6DSR
DTACK Data Transfer Acknowledge (68000) 2,3,7
DRAM Address Bus (DRAM)
2,3,4,5DRAM Data Bus (DRAM)DRD[15:0]
DRA[8:0] 2,3
Disk Write Enable (Floppy) 4,7DKWE
DMAL Chip DMA Request Line (Chips) 2,4
Disk Read Data (Floppy)
4,7Disk Write Data (Floppy)DKWD
DKRD 4,7
Processor Data Bus (68000)
6,7Step Direction (Floppy)DIR
D[15:0] 2,3,6,7
Composite Sync (Video) 2,5CSYNC
CTS Clear to Send (RS232 Port) 6
Read-Time Clock Read / Write (RTC)
5Monochrome Composite Video (Video)COMP
CLKRD/WR 2,9
7.15909 MHz Quadrature Clock (Chips) 2,5,7CDAC
CHNG Media Change (Floppy) 6,7
Column Address Strobe (DRAM) 2,3CASL/U
CCK/CCKQ Color Clock / Quadrature (Chips) 2,4,7
Bus Request (68000)
6Device Busy (Parallel Port)BUSY
BR 2,7
Blitter Slowdown (Chips) 2BLISS
BLIT Chip Memory Access (Chips) 2,7
Bus Grant (68000)
2,7Bus Grant Acknowledge (68000)BGACK
BG 2,7
Audio Output (RS232 Jack) 4,6AUDOUT
BEER Bus Error (68000) 2,7
Address Strobe (68000) 2,7AS
AUDIN Audio Input (RS232 Port) 4,6
Processor Address Bus (68000) 2,3,7A[23:1]
ACK Data Acknowledge (Parallel Port) 6
28.63636 MHz Master Clock 228MHZ
7MHZ 7.15909 MHz Processor Clock 2,5
DESCRIPTION (AREA) PAGESSIGNAL
External Data ReadyXRDY 2,5
External Genlock Clock (Video) 2,5XCLK
XCLKEN External Clock Enable (Video) 2,5
Write Enable (DRAM)
6,7Write Protect Sense (Floppy)WPROT
WE 2,3
Valid Peripheral Address (68000) 2,7VPA
VSYNC Vertical Sync (Video) 2,5,6
Transmit Data (RS232 Port) 4,6TXD
VMA Valid Memory Address (68000) 2,6,7
Step In/Out Command (Floppy)
6,7Track Zero Sense (Floppy)TRK0
STEP 6,7
Drive Select (Floppy) 4,6,7SEL[3:0]
SIDE Side Select (Floppy) 6,7
Processor Read/Write (68000)
6Select (Parallel Port)SEL
RW 2,6,7
Processor Reset (68000)
4,6Receive Data (RS232 Port)RXD
RST 2,4,7
ROM Enable (ROM) 2,3ROMEN
RTS Request to Send (RS232 Port) 6
Red / Green / Blue (Video)
6Ring Indicate (RS232 Port)RI
R/G/B 5
General Reset 6,7RESET
RGA[8:1] Register Address Bus (Chips) 2,4,5
Row Address Strobe (DRAM) 2,3RAS0/1
RDY Drive Ready (Floppy) 6,7
RAM Enable (Chips)
2Chip Register Enable (Chips)REGEN
RAMEN 2
Paper Out (Parallel Port) 6POUT
PPD[7:0] Parallel Port Data (Parallel Port) 6
Pot Lines 0 X/Y (Joysticks)
4,5Pot Lines 1 X/Y (Joysticks)POT1X/1Y
POT0X/0Y 4,5
Override System Decoding
5Genlock Pixel Switch (Video)PIXELSW
OVR 2,7
Mouse 1 Quadrature V/H (Joysticks) 5M1V/M1H
OVL Overlay ROM over RAM 2,6
Motor On - Drive 0 (Floppy)
5Mouse 0 Quadrature V/H (Joysticks)M0V/M0H
MTR0 4,6,7
Light Pen Trigger (Joysticks) 2,6LPEN
MTR Motor On (Floppy) 4,6
DESCRIPTION (AREA)SIGNAL PAGES
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