American Dynamics PMC-4U-CACI User Manual

DYNAMIC ENGINEERING

435 Park Dr., Ben Lomond, Calif. 95005

831-336-8891 Fax 831-336-3840

sales@dyneng.com

www.dyneng.com

Est. 1988

User Manual

PMC-4U-CACI

Quad UART - Dual Synchronous

Serial Data Interface

PMC Module

Revision OR

Corresponding Hardware: Revision 01

PMC-4U

Quad UART - Dual Synchronous Serial Data Interface PMC Module

This document contains information of proprietary interest to Dynamic Engineering. It has been supplied in confidence and the recipient, by accepting this material, agrees that the subject matter will not be copied or reproduced, in whole or in part, nor its contents revealed in any manner or to any person except to meet the purpose for which it was delivered.

Dynamic Engineering 435 Park Drive Ben Lomond, CA 95005 831-336-8891 831-336-3840 FAX

Trademarks and registered trademarks are owned by their respective manufactures. Manual Revision OR. Revised July 2, 2001.

Dynamic Engineering has made every effort to ensure

hat this manual is accurate and complete. Still, the company reserves the right to make improvements or changes in the product described in this document at any time and without notice. Furthermore, Dynamic Engineering assumes no liability arising out of the application or use of the device described herein.

The electronic equipment described herein generates, uses, and can radiate radio frequency energy. Operation of this equipment in a residential area is likely to cause radio interference, in which case the user, at his own expense, will be required to take whatever measures may be required to correct the interference.

Dynamic Engineering’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Dynamic Engineering.

This product has been designed to operate with PMC Module carriers and compatible user-provided equipment. Connection of incompatible hardware is likely to cause serious damage.

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Table of Contents

PRODUCT DESCRIPTION 6

THEORY OF OPERATION 9

ADDRESS MAP 10

PROGRAMMING 12

PMC4U_BASE 13 PMC4U_STAT 16 PMC4U_MSK 16 PMC4U_SCC_IVEC 17 PMC4U_DIR_TERM 17 PMC4U_SW_IN 18 PMC4U_SCC_A_CNTL 19 PMC4U_SCC_A_DATA 19 PMC4U_SCC_B_CNTL 19 PMC4U_SCC_B_DATA 19 PMC4U_UART_A 20 PMC4U_UART_B 20 PMC4U_UART_C 20 PMC4U_UART_D 20 PMC4U_IRUPT/PMC4U_IRUPT_CLR 21

Interrupts 22

Loop-back 23

PMC PCI PN1 INTERFACE PIN ASSIGNMENT 24

PMC PCI PN2 INTERFACE PIN ASSIGNMENT 25

PMC-4U FRONT PANEL IO PIN ASSIGNMENT 26

PMC PN4 USER INTERFACE PIN ASSIGNMENT 27

APPLICATIONS GUIDE 28

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Interfacing 28

CONSTRUCTION AND RELIABILITY 29

THERMAL CONSIDERATIONS 29

WARRANTY AND REPAIR 30

SERVICE POLICY 31

OUT OF WARRANTY REPAIRS 31

FOR SERVICE CONTACT: 31

SPECIFICATIONS 32

ORDER INFORMATION 33

SCHEMATICS 33

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List of Figures

FIGURE 1 PMC-4U BLOCK DIAGRAM 6 FIGURE 2 PMC-4U INTERNAL ADDRESS MAP 10 FIGURE 3 PMC-4U UART ADDRESS MAP 11 FIGURE 4 PMC-4U BASE CONTROL REGISTER BIT MAP 13 FIGURE 5 PMC-4U TX CONTROL REGISTER BIT MAP 16 FIGURE 6 PMC-4U INTERRUPT MASK REGISTER BIT MAP 16 FIGURE 7 PMC-4U DIRECTION TERMINATION CONTROL BIT MAP 17 FIGURE 8 PMC-4U SWITCH READ BIT MAP 18 FIGURE 9 PMC-4U INTERRUPT STATUS/CLEAR 21 FIGURE 10 PMC-4U PN1 INTERFACE 24 FIGURE 11 PMC-4U PN2 INTERFACE 25 FIGURE 12 PMC-4U FRONT PANEL INTERFACE 26 FIGURE 13 PMC-4U PN4 INTERFACE 27

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Product Description

PMC-4U-CACI is part of the PMC Module family of modular I/O components by Dynamic Engineering. The PMC-4U is capable of providing multiple serial protocols both synchronous and asynchronous with a wide range of baud rates. The CACI interface uses an RS-423 driver, an RS-422 driver, and an RS-422 receiver for each UART channel. Two enhanced hysteresis MIL STD 188-114A receivers, a MIL STD 188-114A driver, and an open drain active low output driver for one synchronous channel and an RS-422 driver and receiver for the other synchronous channel.

Other variations are possible. Different oscillators can be installed, or other modifications can be made to accommodate your particular requirements. That variation will then be offered as a “standard” special order product. Please see our web page for current products offered and contact Dynamic Engineering with your custom application.

Quad

Osc

DATA

CONTROL

UART

XR16C854

SCC

Osc

Z85X30

+5V

2 channels

switched termination

RS485 RS422

Osc

Dip Switch

Xilinx

XCS40XL

PCI Bus 33/32

1V HYSTERISIS

±12V, ±6V selectable

± 5V

+5V

GND

RS232 RS423 RS188

FIGURE 1 PMC-4U BLOCK DIAGRAM

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An EXAR XR16C854 implements the UART interface. This quad UART device is compatible with the industry standard 16550 UART, but is equipped with 128 byte FIFOs, independent Tx and Rx FIFO counters, automatic hardware/software flow control, and many other enhanced features. An 18.432 MHz oscillator supplies the reference clock for this device allowing baud rates up to 1.152 Mbps.

The synchronous interface uses a Zilog Serial Communication Controller, the Z85C30. This dual channel, multi-protocol device can implement various bit-oriented and byte-oriented synchronous protocols such as HDLC and IBM Bisync and handles asynchronous formats as well.

The PMC-4U also has a wide range of IO drivers and receivers to interface with these two devices. There are 16 differential RS422/485 transceivers that can be configured as either receivers or transmitters, eight single-ended RS188/232/423 drivers operating at selectable voltage levels, and eight single-ended receivers capable of up to +/- 25V input range. There are also two enhanced hysteresis (~1.5V) RS423 receivers for handling noisy input signals and two open drain outputs that sink up to 65 mA. The differential input signals are selectively terminated with switched 150Ω terminations. All IO lines have series 33Ω resistors

for circuit protection.

The UART, SCC, and IO lines all interface through the Xilinx FPGA to allow maximum flexibility of connections. All configuration registers internal to the Xilinx support read and write operations for software convenience. All addresses are long word aligned including the UART and SCC internal registers even though they have only a byte-wide data interface. Please see the XR16C854 and Z85C30 data sheets and user’s manuals for more information on register access and functions.

The PMC-4U conforms to the PMC and CMC draft standards. This guarantees compatibility with multiple PMC Carrier boards. Because the PMC may be mounted on different form factors, while maintaining plug and software compatibility, system prototyping may be done on one PMC Carrier board, with final system implementation on a different one.

PMC-4U uses a 10 mm inter-board spacing for the front panel, standoffs, and PMC connectors. The 10 mm height is the "standard" height and will work in most systems with most carriers. If your carrier has non-standard connectors [height] to mate with the PMC-4U, please let us know. We may be able to do a special build with a different height connector to compensate.

Interrupts are supported by the PMC-4U. Each of the four UARTs and the SCC has a maskable input to the interrupt generation logic in the Xilinx.

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There is also a master interrupt enable that can be set to gate the interrupt onto the PCI bus. The interrupt status is still available in a status register even when the master interrupt enable is off. This facilitates polled operation of interrupt conditions. The individual interrupt conditions are specified in the internal registers of the UART and SCC. Please see the XR16C854 and Z85C30 documentation for more information on interrupt conditions and configuration.

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Theory of Operation

The PMC-4U is designed for transferring data from one point to another with a variety of serial protocols.

The PMC-4U features a Xilinx FPGA. The FPGA contains the general control and status registers as well as the interface to the quad UART, SCC, and IO drivers and receivers. Many additional control and status registers reside in the UART and SCC, which are accessed through the Xilinx interface.

The PMC-4U is a part of the PMC Module family of modular I/O products. It meets the PMC and CMC draft Standards. Contact Dynamic Engineering for a copy of this specification. It is assumed that the reader is at least casually familiar with this document and logic design. In standard configuration, the PMC-4U is a Type 1 mechanical with no components on the back of the board and one slot wide, with 10 mm inter-board height.

The PCI interface to the host CPU is controlled by a logic block within the Xilinx. The PMC-4U design requires one wait state for read or write cycles to addresses other than the SCC and UART which require from three for simple read or write operations to nine for the SCC interrupt acknowledge/vector read cycle. The wait states refer to the number of clocks after the PCI core decode before the “terminate with data” state is reached. Two additional clock periods account for the 1 clock delay to decode the signals from the PCI bus and to convert the terminate with data state into the TRDY signal.

The quad UART and dual Serial Communication Controller can handle multiple asynchronous and synchronous protocols and the IO drivers and receivers support a range of electrical interface standards.

Each of the serial interfaces has its own oscillator and on-board baud rate generator to supply a wide range of clock reference frequencies. The SCC can also operate from external clock sources with separate Rx clock input and Tx clock input/output pins for each channel.

Please refer to the XR16C854 and Z85C30 documentation for more information on the operation and capabilities of these devices.

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Address Map

PMC4U_BASE 0X00 base control read/write PMC4U_STAT 0X04 status read read PMC4U_MSK 0X08 interrupt mask control read/write PMC4U_SCC_IVEC 0X0C SCC interrupt vector read read PMC4U_DIR_TERM 0X10 direction and termination control read/write

PMC4U_SW_IN 0X14 read user switch read

PMC4U_SCC_A_CNTL 0X18 SCC channel A control read/write PMC4U_SCC_A_DATA 0X1C SCC channel A data read/write PMC4U_SCC_B_CNTL 0X20 SCC channel B control read/write PMC4U_SCC_B_DATA 0X24 SCC channel B data read/write PMC4U_UART_A 0X40 UART A base offset read/write PMC4U_UART_B 0X60 UART B base offset read/write PMC4U_UART_C 0X80 UART C base offset read/write PMC4U_UART_D 0XA0 UART D base offset read/write PMC4U_IRUPT 0XE0 interrupt source read read PMC4U_IRUPT_CLR 0XE0 interrupt write clear write

FIGURE 2 PMC-4U INTERNAL ADDRESS MAP

Each UART channel has a number of registers associated with it. These register offsets and their general functions are given in figure 3. For details of the bits and functions of each register consult the documentation for the XR16C854.

The SCC also has a number of internal registers that are accessed in a two-step process. First the register number is written to the control address for the respective channel. Then an additional read or write to the same control address is performed. This causes the data to be read from or written to the desired register. At the end of this process the register pointer is reset so that the next access is again to/from the base control register. For a more complete description of this process, as well as details of registers and their functions, see the user’s manual for the Z85C30.

The address map provided is for the local decoding performed within the PMC-4U. The addresses are all offsets from a base address. The carrier board that the PMC is installed into provides the base address.

The VendorId = 0x10EE. The CardId = 0x0007. Current revision = 0x00

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