AMD PALCE16V8H-10JC-4, PALCE16V8H-10JI-4, PALCE16V8Q-15PC, PALCE16V8Q-20JI, PALCE16V8Q-20JI-4 Datasheet

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Publication# 16493 Rev. D Amendment/0 Issue Date: February 1996

2-36

PALCE16V8 Family

EE CMOS 20-Pin Universal Programmable Array Logic

FINAL

COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25

DISTINCTIVE CHARACTERISTICS

■ Pin and function compatible with all 20-pin

GAL devices

■ Electrically erasable CMOS technology

provides reconfigurable logic and full testability

■ High-speed CMOS technology

— 5-ns propagation delay for “-5” version — 7.5-ns propagation delay for “-7” version

■ Direct plug-in replacement for the PAL16R8

series and most of the PAL10H8 series

■ Outputs programmable as registered or

combinatorial in any combination

■ Peripheral Component Interconnect (PCI)

compliant

■ Programmable output polarity

■ Programmable enable/disable control

■ Preloadable output registers for testability

■ Automatic register reset on power up

■ Cost-effective 20-pin plastic DIP, PLCC, and

SOIC packages

■ Extensive third-party software and programmer

support through FusionPLD partners

■ Fully tested for 100% programming and

functional yields and high reliability

■ 5 ns version utilizes a split leadframe for

improved performance

GENERAL DESCRIPTION

The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells provide a universal device architecture. The PALCE16V8 will directly replace the PAL16R8 and PAL10H8 series devices, with the exception of the PAL16C1.

The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floatinggate cells in the AND logic array that can be erased electrically.

The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an activehigh or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell.

AMD’s FusionPLD program allows PALCE16V8 designs to be implemented using a wide variety of popular industry-standard design tools. By working closely with the FusionPLD partners, AMD certifies that the tools provide accurate, quality support. By ensuring that thirdparty tools are available, costs are lowered because a designer does not have to buy a complete set of new tools for each device. The FusionPLD program also greatly reduces design time since a designer can use a tool that is already installed and familiar.

AMD

2-37PALCE16V8 Family

BLOCK DIAGRAM

Programmable AND Array

32 x 64

MACRO

OE/I

I/O

– I

CLK/I

16493D-1

CONNECTION DIAGRAMS Top View

16493D-2

PLCC/LCC

DIP/SOIC

PIN DESIGNATIONS

CLK = Clock GND = Ground I = Input I/O = Input/Output OE = Output Enable V

= Supply Voltage

Note: Pin 1 is marked for orientation.

CLK/I

9 10

I/O

OE/I

GND

1

20

19

18 17 16 15

14

2

3

4

5 6 7

8

9

10 11 12 13

3

4

5

6

7

I/O

6

I/O

5

I/O

4

I/O

3

I/O

2

OE/I

9

I/O

0

I/O

1

GND

8

CLK/I

0

CC

I/O

7

1

2

16493D-3

AMD

2-38

PALCE16V8H-5/7/10/15/25, Q-10/15/25 (Com’l)

H-10/15/25, Q-20/25 (Ind)

ORDERING INFORMATION Commercial and Industrial Products

PACKAGE TYPE

P = 20-Pin Plastic DIP (PD 020) J = 20-Pin Plastic Leaded Chip

Carrier (PL 020)

S = 20-Pin Plastic Gull-Wing

Small Outline Package (SO 020)

OPERATING CONDITIONS

C = Commercial (0

°C to +75°C)

I = Industrial (–40

°C to +85°C)

Valid Combinations

AMD programmable logic products for commercial and industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:

Valid Combinations

Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

PAL CE 16 V 8 H -5 P C

SPEED

-5 = 5 ns t

-7 = 7.5 ns t

-10 = 10 ns t

-15 = 15 ns t

-20 = 20 ns t

-25 = 25 ns t

FAMILY TYPE

PAL = Programmable Array Logic

POWER

H = Half Power (90 – 125 mA I

)

Q = Quarter Power (55 mA I

)

TECHNOLOGY

CE = CMOS Electrically Erasable

NUMBER OF ARRAY INPUTS

OUTPUT TYPE

V = Versatile

NUMBER OF OUTPUTS

PROGRAMMING DESIGNATOR

Blank = Initial Algorithm /4 = First Revision /5 = Second Revision

(Same Algorithm as /4)

OPTIONAL PROCESSING

Blank = Standard Processing

PALCE16V8H-5 PALCE16V8H-7 PALCE16V8H-10 PALCE16V8Q-10 PALCE16V8H-15 PALCE16V8Q-15 PALCE16V8Q-20 PALCE16V8H-25 PALCE16V8Q-25

PC, JC, SC, PI, JI

PC, JC, PI, JI

PC, JC, SC

PC, JC

Blank,

PC, JC, SC, PI, JI

PC, JC

PC, JC, SC, PI, JI

PI, JI

AMD

2-39PALCE16V8 Family

FUNCTIONAL DESCRIPTION

The PALCE16V8 is a universal PAL device. It has eight independently configurable macrocells (MC

–MC

). Each macrocell can be configured as registered output, combinatorial output, combinatorial I/O or dedicated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Pins 1 and 11 serve either as array inputs or as clock (CLK) and output enable (OE), respectively, for all flip-flops.

Unused input pins should be tied directly to V

or GND. Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state and product terms with both true and complement of any input signal connected assume a logical LOW state.

The programmable functions on the PALCE16V8 are automatically configured from the user’s design

specification. The design specification is processed by development software to verify the design and create a programming file (JEDEC). This file, once downloaded to a programmer, configures the device according to the user’s desired function.

The user is given two design options with the PALCE16V8. First, it can be programmed as a standard PAL device from the PAL16R8 and PAL10H8 series. The PAL programmer manufacturer will supply device codes for the standard PAL device architectures to be used with the PALCE16V8. The programmer will program the PALCE16V8 in the corresponding architecture. This allows the user to use existing standard PAL device JEDEC files without making any changes to them. Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the PALCE16V8 device code. This option allows full utilization of the macrocell.

16493D-4

*In macrocells MC0 and MC

, SG1 is replaced by

SG0

on the feedback multiplexer.

1 1 0 X

1 0

SG1

SL0

1 0 1 1 0 X

1 1 1 0 0 0 0 1

CLK

SL0

Adjacent

Macrocell

From Adjacent Pin

1 1 0 X

1 0

SL1

I/O

PALCE16V8 Macrocell

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2-40 PALCE16V8 Family

Configuration Options

Each macrocell can be configured as one of the following: registered output, combinatorial output, combinatorial I/O, or dedicated input. In the registered output configuration, the output buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled by a product term or always enabled. In the dedicated input configuration, it is always disabled. With the exception of MC

and MC7, a macrocell configured as a dedicated input derives the input signal from an adjacent I/O. MC

derives its input from pin 11 (OE) and

from pin 1 (CLK).

The macrocell configurations are controlled by the configuration control word. It contains 2 global bits (SG0 and SG1) and 16 local bits (SL0

through SL07 and SL1

through SL17). SG0 determines whether registers will be allowed. SG1 determines whether the PALCE16V8 will emulate a PAL16R8 family or a PAL10H8 family device. Within each macrocell, SL0

, in conjunction with SG1, selects the configuration of the macrocell, and SL1

sets the output as either active low or active high

for the individual macrocell. The configuration bits work by acting as control inputs

for the multiplexers in the macrocell. There are four multiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. SG1 and SL0

are the control signals for all four multiplexers. In

and MC7, SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being the adjacent pin for MC

and OE the adjacent pin for MC0.

Registered Output Configuration

The control bit settings are SG0 = 0, SG1 = 1 and SL0x =

0. There is only one registered configuration. All eight product terms are available as inputs to the OR gate. Data polarity is determined by SL1

The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The output buffer is enabled by OE.

Combinatorial Configurations

The PALCE16V8 has three combinatorial output configurations: dedicated output in a non-registered device, I/O in a non-registered device and I/O in a registered device.

Dedicated Output in a Non-Registered Device

The control bit settings are SG0 = 1, SG1 = 0 and SL0x =

0. All eight product terms are available to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the exception of pins 15 and 16. Pins 15 and 16 do not use feedback in this mode. Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin 1 will

use the feedback path of MC

and pin 11 will use the

feedback path of MC

Combinatorial I/O in a Non-Registered Device

The control bit settings are SG0 = 1, SG1 = 1, and SL0x =

1. Only seven product terms are available to the OR gate. The eighth product term is used to enable the output buffer. The signal at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used as an input.

Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as inputs. Pin 1 will use the feedback path of MC

and pin 11 will use the

feedback path of MC

Combinatorial I/O in a Registered Device

The control bit settings are SG0 = 0, SG1 = 1 and SL0

1. Only seven product terms are available to the OR gate. The eighth product term is used as the output enable. The feedback signal is the corresponding I/O signal.

Dedicated Input Configuration

The control bit settings are SG0 = 1, SG1 = 0 and SL0x =

1. The output buffer is disabled. Except for MC

and MC

the feedback signal is an adjacent I/O. For MC0 and MC

the feedback signals are pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2.

Table 1. Macrocell Configuration

SG0 SG1 SL0XCell Configuration Devices Emulated

Device Uses Registers

0 1 0 Registered Output PAL16R8, 16R6,

16R4

0 1 1 Combinatorial I/O PAL16R6, 16R4

Device Uses No Registers

1 0 0 Combinatorial PAL10H8, 12H6,

Output 14H4, 16H2, 10L8,

12L6, 14L4, 16L2

1 0 1 Input PAL12H6, 14H4,

16H2, 12L6, 14L4, 16L2

1 1 1 Combinatorial I/O PAL16L8

Programmable Output Polarity

The polarity of each macrocell can be active-high or active-low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts.

Selection is through a programmable bit SL1

which controls an exclusive-OR gate at the output of the AND/ OR logic. The output is active high if SL1

is 1 and active

low if SL1

is 0.

AMD

2-41PALCE16V8 Family

16493D-5

DQQ

CLK

Registered Active Low

DQQ

CLK

Registered Active High

Combinatorial I/O Active Low Combinatorial I/O Active High

Combinatorial Output Active Low

Combinatorial Output Active High

Adjacent I/O pin

Dedicated Input

Notes:

1. Feedback is not available on pins 15 and 16 in the combinatorial output mode.

2. This configuration is not available on pins 15 and 16.

Note 1 Note 1

Note 2

Figure 2. Macrocell Configurations

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2-42 PALCE16V8 Family

Power-Up Reset

All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE16V8 will depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be HIGH. If combinatorial is selected, the output will be a function of the logic.

The register on the PALCE16V8 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery.

Security Bit

A security bit is provided on the PALCE16V8 as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback and verification of the programmed pattern by a device programmer, securing proprietary designs from competitors. The bit can only be erased in conjunction with the array during an erase cycle.

Electronic Signature Word

An electronic signature word is provided in the PALCE16V8 device. It consists of 64 bits of programmable memory that can contain user-defined data. The signature data is always available to the user independent of the security bit.

Programming and Erasing

The PALCE16V8 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming hardware. No special erase operation is required.

Quality and Testability

The PALCE16V8 offers a very high level of built-in quality. The erasability of the device provides a direct means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming yields and post-programming functional yields in the industry.

Technology

The high-speed PALCE16V8 is fabricated with AMD’s advanced electrically erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clean switching.

PCI Compliance

The PALCE22V10H-7/10 is fully compliant with the

PCI

Local Bus Specification

published by the PCI Special Interest Group. The PALCE22V10H-7/10’s predictable timing ensures compliance with the PCI AC specifications independent of the design.

AMD

2-43PALCE16V8 Family

LOGIC DIAGRAM

16493D-6

034781112151619202324272831

03478111215161920 2427283123

CLK/I

CLK OE

1 1 0 X

1 0

SG1

SL0

1 1 0 X

1 0

SG1

SL0

1 1 0 X

1 0

SG1

SL0

SG1

1 1 0 X

1 0

1 0 1 1

1 1 1 0 0 0 0 1

SL0

0 X

SG1

1 1

0 X

1 0

1 0 1 1

1 1 1 0 0 0 0 1

SL0

0 X

1 1 0 X

1 0

SG1

SL0

SG1

1 1 0 X

1 0

1 0 1 1

1 1 1 0

0 0 0 1

SL0

0 X

SG0

1 1

0 X

1 0

1 1

0 X

1 1 1 0 0 0 0 1

I/O

SL1

SL0

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