AMD MACH211SP-12JI, MACH211SP-12JC, MACH211SP-10VC, MACH211SP-10JI, MACH211SP-10JC Datasheet

...
FINAL
Publication# 20405 Rev: B Amendment/0 Issue Date: February 1996
COM’L: -7.5/10/12/15/20 IND: -10/12/14/18/24
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
JTAG-Compatible, 5-V in-system programming
44 Pins
64 Macrocells
7.5 ns t
PD
Commercial
10 ns t
PD
Industrial
133 MHz f
CNT
34 Bus-Friendly™ Inputs and I/Os
Peripheral Component Interconnect (PCI) compliant (-7/-10)
Programmable power-down mode
32 Outputs
64 Flip-flops; 2 clock choices
4 “PAL26V16” blocks with buried macrocells
Improved routing over the MACH210
IN-SYSTEM PROGRAMMING
In-system programming allows the MACH211SP to be programmed while soldered onto a system board. Pro­gramming the MACH211SP in-system yields numer­ous benefits at all stages of development: prototyping, manufacturing, and in the field. Since insertion into a programmer isn’t needed, multiple handling steps and the resulting bent leads are eliminated. The design can be modified in-system for design changes and debug­ging while prototyping, programming boards in produc­tion, and field upgrades.
The MACH211SP offers advantages not available in other CPLD architectures with in-system programming. MACH devices have extensive routing resources for pin-out retention; design changes resulting in pin-out changes for other CPLDs cancel the advantages of in-system programming. The MACH211SP can be em­ployed in any JTAG (IEEE 1149.1) compliant chain.
GENERAL DESCRIPTION
The MACH211SP is a member of AMD’s EE CMOS Performance Plus MACH
2 device family. This device has approximately six times the logic macrocell capa­bility of the popular PAL22V10 without loss of speed.
The MACH211SP consists of four PAL  blocks inter­connected by a programmable switch matrix. The four PAL blocks are essentially “PAL26V16” structures com­plete with product-term arrays and programmable macrocells, which can be programmed as high speed or low power, and buried macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently.
The MACH211SP has two kinds of macrocell: output and buried. The MACH211SP output macrocell pro­vides registered, latched, or combinatorial outputs with
programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All output macrocells can be con­nected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input.
The MACH211SP has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers or latches for use in synchronizing signals and reducing setup time requirements.
The MACH211SP is an enhanced version of the MACH211, adding the JTAG-compatible in-system pro­gramming feature.
2 MACH211SP-7/10/12/15/20
BLOCK DIAGRAM
20405B-1
Switch Matrix
I/O Cells
Macrocells
I/O
0
–I/O
7
Macrocells
8
8
8
2
CLK
0/I0
CLK1/I
1
52 x 68
AND Logic Array
and
Logic Allocator
26
2
8
2
OE
I/O Cells
Macrocells
I/O
8
–I/O
15
Macrocells
8
8
8
52 x 68
AND Logic Array
and
Logic Allocator
26
8
OE
I/O Cells
Macrocells
I/O
24
–I/O
31
Macrocells
8
8
8
52 x 68
AND Logic Array
and
Logic Allocator
26
8
OE
I/O Cells
Macrocells
I/O
16
–I/O
23
Macrocells
8
8
8
52 x 68
AND Logic Array
and
Logic Allocator
26
8
OE
MACH211SP-7/10/12/15/20 3
CONNECTION DIAGRAM MACH211SP T op View
44-Pin PLCC
PIN DESIGNATIONS
CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V
CC
= Supply V oltage
TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out
1
44
43
42
5
4
3
2
641
40
7 8
9
10
11
12 13
14 15 16
17
23
24
25
26
19
20
21
22
18 27
28
39 38
37
36
35
34 33
32 31 30
29
I/O5 I/O6 I/O7
TDI
CLK0/I0
GND
TCK
I/O8
I/O9 I/O10 I/O11
I/O27 I/O26 I/O25 I/O24 TDO GND CLK1/I1 TMS I/O23 I/O22 I/O21
I/O12
I/O13
I/O14
I/O15
VCC
GND
I/O16
I/O17
I/O18
I/O19
I/O20
I/O4
I/O3
I/O2
I/O1
I/O0
GND
VCC
I/O31
I/O30
I/O29
I/O28
20405B-2
4 MACH211SP-7/10/12/15/20
CONNECTION DIAGRAM MACH211SP T op View
44-Pin TQFP
PIN DESIGNATIONS
CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V
CC
= Supply Voltage
TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out
I/O12
I/O13
I/O14
I/O15
VCC
GND
I/O16
I/O17
I/O18
I/O19
I/O20
I/O4
I/O3
I/O2
I/O1
I/O0
GND
VCC
I/O31
I/O30
I/O29
I/O28
I/O27 I/O26 I/O25 I/O24 TDO GND CLK1/I1 TMS I/O23 I/O22 I/O21
I/O5 I/O6 I/O7
TDI
CLK0/I0
GND
TCK
I/O8
I/O9 I/O10 I/O11
1 2 3 4 5
6 7 8 9 10 11
33 32 31 30 29 28 27 26 25 24 23
4443424140
39
38
373635
34
1213141516
17
18
192021
22
20405B-3
MACH211SP-7/10/12/15/20 (Com’l) 5
ORDERING INFORMATION Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
Valid Combinations
The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combina­tions and to check on newly released combinations.
F AMIL Y TYPE
MACH = Macro Array CMOS High-Speed
MACH 211 SP -7 J C
DEVICE NUMBER
211 = 64 Macrocells, 44 Pins,
Power-Down mode, Bus-Friendly Inputs and I/Os
PRODUCT DESIGNATION
SP = In-system Programmable
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
P ACKA GE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
V = 44-Pin Thin Quad Flat Pack
(PQT044)
SPEED
-7 = 7.5 ns t
PD
-10 = 10 ns t
PD
-12 = 12 ns t
PD
-15 = 15 ns t
PD
-20 = 20 ns t
PD
Valid Combinations
MACH211SP-7
JC, VC
MACH211SP-10 MACH211SP-12 MACH211SP-15 MACH211SP-20
6 MACH211SP-10/12/14/18/24 (Ind)
ORDERING INFORMATION Industrial Products
AMD programmable logic products for industrial applications are av ailab le with se v er al ordering options. The order number (Valid Combination) is formed by a combination of:
Valid Combinations
The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combina­tions and to check on newly released combinations.
DEVICE NUMBER
211 = 64 Macrocells, 44 Pins,
Power-Down mode, Bus-Friendly Inputs and I/Os
PRODUCT DESIGNATION
SP = In-system Programmable
F AMIL Y TYPE
MACH = Macro Array CMOS High-Speed
MACH 211 SP -10 J I
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
I = Industrial (–40
°C to +85°C)
P ACKA GE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
SPEED
-10 = 10 ns t
PD
-12 = 12 ns t
PD
-14 = 14.5 ns t
PD
-18 = 18 ns t
PD
-24 = 24 ns t
PD
Valid Combinations
MACH211SP-10
JI
MACH211SP-12 MACH211SP-14 MACH211SP-18 MACH211SP-24
MACH211SP-7/10/12/15/20 7
FUNCTIONAL DESCRIPTION
The MACH211SP consists of four PAL blocks con­nected by a switch matrix. There are 32 I/O pins feeding the switch matrix. These signals are distributed to the four PAL blocks for efficient design implementation. There are two clock pins that can also be used as ded­icated inputs.
The PAL Blocks
Each P AL b lock in the MA CH211SP (Figure 1) contains a 64-product-term logic array , a logic allocator, 8 output macrocells, 8 buried macrocells, and 8 I/O cells. The switch matrix feeds each PAL block with 26 inputs. This makes the PAL block look effectively like an indepen­dent “PAL26V16” with 8 buried macrocells.
In addition to the logic product terms, two output enable product terms, an asynchronous reset product term, and an asynchronous preset product term are pro­vided. One of the two output enable product terms can be chosen within each I/O cell in the PAL block. All flip-flops within the PAL block are initialized together.
The Switch Matrix
The MACH211SP switch matrix is f ed by the inputs and feedback signals from the PAL blocks. Each PAL block provides 16 internal feedback signals and 8 I/O feed­back signals. The switch matrix distributes these sig­nals back to the PAL blocks in an efficient manner that also provides for high performance. The design soft­ware automatically configures the switch matrix when fitting a design into the device.
The Product-term Array
The MACH211SP product-term array consists of 64 product terms for logic use, and 4 special-purpose product terms. Two of the special-purpose product terms provide programmable output enable; one pro­vides asynchronous reset, and one provides asynchro­nous preset.
The Logic Allocator
The logic allocator in the MACH211SP takes the 64 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven by up to 16 product terms. The design software auto­matically configures the logic allocator when fitting the design into the device.
T ab le 1 illustrates which product term clusters are avail­able to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers.
The Macrocell
The MACH211SP has two types of macrocell: output and buried. The output macrocells can be configured as either registered, latched, or combinatorial, with pro­grammable polarity. The macrocell provides internal
feedback whether configured with or without the flip-flop. The registers can be configured as D-type or T-type, allowing for product-term optimization.
The flip-flops can individually select one of two clock/ gate pins, which are also available as data inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The latch holds its data when the gate input is HIGH, and is transparent when the gate input is LOW. The flip-flops can also be asynchronously ini­tialized with the common asynchronous reset and pre­set product terms.
The buried macrocells are the same as the output macrocells if they are used for generating logic. In that case, the only thing that distinguishes them from the output macrocells is the fact that there is no I/O cell connection, and the signal is only used internally. The buried macrocell can also be configured as an input register or latch.
The I/O Cell
The I/O cell in the MACH211SP consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, al­ways disabled, or controlled by a product term. If prod­uct term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to all I/O cells in a PAL block.
Table 1. Logic Allocation
Macrocell
Available ClustersOutput Buried
M
0
C
0
, C
1
, C
2
M
1
C
0
, C
1
, C
2
, C
3
M
2
C
1
,
C
2
,
C
3
,
C
4
M
3
C
2
,
C
3
,
C
4
,
C
5
M
4
C3, C4, C5, C
6
M
5
C4, C5, C6, C
7
M
6
C5, C6, C7, C
8
M
7
C6, C7, C8, C
9
M
8
C7, C8, C9, C
10
M
9
C8, C9, C10, C
11
M
10
C9, C10, C11, C
12
M
11
C10, C11, C12, C
13
M
12
C11, C12, C13, C
14
M
13
C12, C13, C14, C
15
M
14
C13, C14, C
15
M
15
C14, C
15
8 MACH211SP-7/10/12/15/20
These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus.
Power-Down Mode
The MACH211SP features a progr ammab le low-po w er mode in which individual signal paths can be pro­grammed as low power. These low-power speed paths will be slightly slower than the non-low-power paths. This feature allows speed critical paths to run at maxi­mum frequency while the rest of the paths operate in the low-power mode, resulting in power savings of up to 75%. If all signals in a PAL block are low-pow er , then total power is reduced further.
In-System Programming
Programming is the process where MACH devices are loaded with a pattern defined in a JEDEC file obtained from MACHXL software or third-party software. Pro­gramming is accomplished through four JTAG pins: Test Mode Select (TMS), Test Clock (TCK), Test Data In (TDI), and Test Data Out (TDO). The MACH211SP can be employed in any JTAG (IEEE 1149.1) compli­ant chain. While the MACH211SP is fully JTAG com­patible, it supports the BYPASS instruction, not the EXTEST and SAMPLE/PRELOAD instructions. The MACH211SP can be programmed across the commer­cial temperature range. Programming the MACH de­vice after it has been placed on a circuit board is easily accomplished. Programming is initiated by placing the device into programming mode, using the MACHPRO programming software provided by AMD. The device is bulk erased and the JEDEC file is then loaded. After the data is transferred into the device, the PROGRAM instruction is loaded. Further programming details can be found in application note, “Advanced In-circuit Programming Guidelines.”
On-Board Programming Options
Since the MACHPRO software performs these steps automatically, the following programming options are published for reference.
The configuration file, which is also known as the chain file, defines the MACH de vice JTAG chain. The file con­tains the information concerning which JEDEC file is to be placed into which device, the state which the out­puts should be placed, and whether the security fuses
should be programmed. The configuration file is dis­cussed in detail in the MACHPRO software manual.
The MACH211SP devices tristate the outputs during programming. They hav e one security bit which inhibits program and verify. This allows the user to protect pro­prietary patterns and designs.
Program verification of a MACH device involves read­ing back the programmed pattern and comparing it with the original JEDEC file. The AMD method of program verification performed on the MACH devices permits the verification of one device at a time.
Accidental Programming or Erasure Protection
It is virtually impossible to program or erase a MACH device inadvertently. The following conditions must be met before programming actually takes place:
The device must be in the password-protected program mode
The programming or bulk erase instruction must be in the instruction register
If the above conditions are not met, the programming circuitry cannot be activated.
To ensure that the AMD ten year device data retention guarantee applies, 100 program/erase cycle limit should not be exceeded.
Bus-Friendly Inputs and I/Os
The MACH211SP inputs and I/Os include two inv erters in series which loop back to the input. This double inversion reinforces the state of the input and pulls the voltage away from the input threshold voltage. For an illustration of this configuration, please turn to the Input/Output Equivalent Schematics section.
PCI Compliance
The MACH211SP-7/10 is fully compliant with the
PCI
Local Bus Specification
published by the PCI Special Interest Group. The MACH211SP-7/10’s predictable timing ensures compliance with the PCI AC specifica­tions independent of the design. On the other hand, in CPLD and FPGA architectures without predictable tim­ing, PCI compliance is dependent upon routing and product term distribution.
MACH211SP-7/10/12/15/20 9
0 4 8 12 16 20 24 28 40324336
0 4 8 12 16 20 24 28 40324336
I/O Cell
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Switch Matrix
Output Enable Output Enable
Asynchronous Reset Asynchronous Preset
16
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
Output Macro Cell
Output Macro Cell
Output Macro Cell
Output Macro Cell
Output Macro Cell
Output Macro Cell
Output Macro Cell
Output Macro Cell
8
Buried Macro Cell
Buried Macro Cell
Buried Macro Cell
Buried Macro Cell
Buried Macro Cell
Buried Macro Cell
Buried Macro Cell
Buried Macro Cell
47
51
47
51
CLK
2
0
Logic Allocator
63
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
8
C
9
C
10
C
11
C
12
C
13
C
14
C
15
M
3
M
6
M
5
M
4
M
2
M
1
M
0
M
9
M
8
M
7
M
10
M
11
M
12
M
13
M
14
M
15
20405B-4
Figure 1. MACH211SP PAL Block
10 MACH211SP-7/10 (Com’l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Supply V oltage with
Respect to Ground. . . . . . . . . . . . . . .–0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . .–0.5 V to VCC + 0.5 V
DC Output or
I/O Pin Voltage . . . . . . . . . . . . . .–0.5 V to V
CC
+ 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = 0°C to 70°C). . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . . .0°C to +70°C
Supply V oltage (VCC)
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of I
IL
and I
OZL
(or IIH and I
OZH
).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. V
OUT
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled and reset.
5. This parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
V
OH
Output HIGH Voltage IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL2.4 V
V
OL
Output LOW Voltage IOL = 16 mA, VCC = Min, VIN = VIH or V
IL
0.5 V
V
IH
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1)
2.0 V
V
IL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for all Inputs (Note 1)
0.8 V
I
IH
Input HIGH Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA
I
IL
Input LOW Current VIN = 0 V, V
CC
= Max (Note 2) –10 µA
I
OZH
Off-State Output Leakage Current HIGH
V
OUT
= 5.25 V, V
CC
= Max
V
IN
= V
IH
or VIL (Note 2)
10 µA
I
OZL
Off-State Output Leakage Current LOW
V
OUT
= 0 V, V
CC
= Max
V
IN
= V
IH
or VIL (Note 2)
–10 µA
I
SC
Output Short-Circuit Current V
OUT
= 0.5 V, VCC = Max (Notes 3, 5) –30 –160 mA
I
CC
Supply Current (Static) VCC = 5 V, TA = 25°C, f = 0 MHz (Note 4) 40 mA Supply Current (Active) VCC = 5 V, TA = 25°C, f = 1 MHz (Note 4) 45 mA
MACH211SP-7/10 (Com’l) 11
CAPACITANCE (Note 1)
Parameter
Symbol Parameter Description Test Conditions Typ Unit
C
IN
Input Capacitance V
IN
= 2.0 V
V
CC
= 5.0 V, TA = 25°C
f = 1 MHz
6pF
C
OUT
Output Capacitance V
OUT
= 2.0 V 8 pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol Parameter Description
-7 -10 UnitMin Max Min Max
t
PD
Input, I/O, or Feedback to Combinatorial Output (Note 3) 7.5 10 ns
t
S
Setup Time from Input, I/O, or Feedback to Clock (Note 3)
D-type 5.5 6.5 ns T-type 6.5 7.5 ns
t
H
Register Data Hold Time 0 0 ns
t
CO
Clock to Output (Note 3) 4.5 6 ns
t
WL
Clock Width
LOW 3 5 ns
t
WH
HIGH 3 5 ns
f
MAX
Maximum Frequency (Note 1)
External Feedback 1/(t
S
+ tCO)
D-type 100 80 MHz T-type 91 74 MHz
Internal Feedback (f
CNT
)
D-type 133 100 MHz T-type 125 91 MHz
No Feedback 1/(t
WL
+ tWH) 166.7 100 MHz
t
SL
Setup Time from Input, I/O, or Feedback to Gate 5.5 6.5 ns
t
HL
Latch Data Hold Time 0 0 ns
t
GO
Gate to Output 7 7 ns
t
GWL
Gate Width LOW 3 5 ns
t
PDL
Input, I/O, or Feedback to Output Through Transparent Input or Output Latch
9.5 12 ns
t
SIR
Input Register Setup Time 2 2 ns
t
HIR
Input Register Hold Time 2 2 ns
t
ICO
Input Register Clock to Combinatorial Output 11 13 ns
t
ICS
Input Register Clock to Output Register Setup
D-type 9 10 ns T-type 10 11 ns
t
WICL
Input Register Clock Width
LOW 3 5 ns
t
WICH
HIGH 3 5 ns
f
MAXIR
Maximum Input Register Frequency 166.7 100 MHz
t
SIL
Input Latch Setup Time 2 2 ns
t
HIL
Input Latch Hold Time 2 2 ns
t
IGO
Input Latch Gate to Combinatorial Output 12 14 ns
t
IGOL
Input Latch Gate to Output Through Transparent Output Latch 14 16 ns
t
SLL
Setup Time from Input, I/O , or Feedbac k Through Transparent Input Latch to Output Latch Gate
7.5 8.5 ns
12 MACH211SP-7/10 (Com’l)
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected.
2. See Switching Test Circuit for test conditions.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
t
IGS
Input Latch Gate to Output Latch Setup 10 11 ns
t
WIGL
Input Latch Gate Width LOW 3 5 ns
t
PDLL
Input, I/O, or Feedback to Output Through Transparent Input and Output Latches
12.5 14 ns
t
AR
Asynchronous Reset to Registered or Latched Output 9.5 15 ns
t
ARW
Asynchronous Reset Width (Note 1) 5 10 ns
t
ARR
Asynchronous Reset Recovery Time (Note 1) 5 10 ns
t
AP
Asynchronous Preset to Registered or Latched Output 9.5 15 ns
t
APW
Asynchronous Preset Width (Note 1) 5 10 ns
t
APR
Asynchronous Preset Recovery Time (Note 1) 5 10 ns
t
EA
Input, I/O, or Feedback to Output Enable (Note 1) 9.5 12 ns
t
ER
Input, I/O, or Feedback to Output Disable (Note 1) 9.5 12 ns
t
LP
tPD Increase for Powered-down Macrocell (Note 3) 10 10 ns
t
LPS
tS Increase for Powered-down Macrocell (Note 3) 10 10 ns
t
LPCO
tCO Increase for Powered-down Macrocell (Note 3) 0 0 ns
t
LPEA
tEA Increase for Powered-down Macrocell (Note 3) 10 10 ns
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued)
Parameter
Symbol Parameter Description
-7 -10 UnitMin Max Min Max
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