AMD MACH210AQ-20JC, MACH210AQ-15JC, MACH210AQ-12JC, MACH210A-7VC, MACH210A-7JC Datasheet

FINAL

COM’L: -7/10/12/15/20, Q-12/15/20 IND: -12/14/18/24

MACH210A-7/10/12
MACH210-12/15/20
MACH210AQ-12/15/20

High-Density EE CMOS Programmable Logic

DISTINCTIVE CHARACTERISTICS

44 Pins
64 Macrocells

7.5 ns tPD Commercial
12 ns t

133 MHz f
38 Inputs; 210A Inputs have built-in pull-up

resistors

Industrial

PD

CNT

GENERAL DESCRIPTION

The MACH210 is a member of AMD’s high-performance
EE CMOS MACH 2
approximately six times the logic macrocell capability of
the popular PAL22V10 without loss of speed.

The MACH210 consists of four PAL blocks intercon­nected by a programmable switch matrix. The four PAL
blocks are essentially “PAL22V16” structures complete
with product-term arrays and programmable macro­cells, including additional buried macrocells. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity
between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.

The MACH210 has two kinds of macrocell: output and
buried. The MACH210 output macrocell provides regis-

device family. This device has

Peripheral Component Interconnect (PCI)
compliant

32 Outputs
64 Flip-flops; 2 clock choices
4 “PAL22V16” blocks with buried macrocells
Pin-compatible with MACH110, MACH111,

MACH211, and MACH215

tered, latched, or combinatorial outputs with program­mable polarity. If a registered configuration is chosen,
the register can be configured as D-type or T-type to
help reduce the number of product terms. The register
type decision can be made by the designer or by the
software. All output macrocells can be connected to an
I/O cell. If a buried macrocell is desired, the internal
feedback path from the macrocell can be used, which
frees up the I/O pin for use as an input.

The MACH210 has dedicated buried macrocells which,
in addition to the capabilities of the output macrocell,
also provide input registers or latches for use in
synchronizing signals and reducing setup time require­ments.

Advanced

Micro

Devices

Publication# 14128 Rev. I Amendment/0
Issue Date: May 1995

AMD

BLOCK DIAGRAM

–I/O

I/O

0

7

I/O8–I/O

I0–I

1,

I3–I

15

4

I/O Cells

8

Macrocells

8

8

I/O Cells

8

Macrocells

OE

Macrocells

44 x 68

AND Logic Array

and

Logic Allocator

22 22

Switch Matrix

22 22

44 x 68

AND Logic Array

and

Logic Allocator

OE

8

44 x 68

AND Logic Array

and

Logic Allocator

44 x 68

AND Logic Array

and

Logic Allocator

8

8

Macrocells

OE

OE

8

2

4

2

Macrocells

8

I/O Cells

I/O24–I/O

Macrocells

8

Macrocells

8

Macrocells

8

88

2

I/O Cells

16

–I/O

8

23

CLK0/I

CLK1/I

2,

5

14128I-1

8

31

I/O

MACH210-7/10/12/15/20, Q-12/15/202

CONNECTION DIAGRAM
Top View

AMD

PLCC

I/O
I/O
I/O

GND

CLK0/I

I/O
I/O

I/O

I/O

10

I
I

11

3

I/O4I/O

561324 4443424140

7

5

8

6

9

7

10

0

11

1

12
13

2

14

8

15

9

16
17

18 282726252423222119 20

13

I/O12I/O

2

I/O

14

I/O

1

I/O

15

I/O

0

I/O

CC

V

GND

GND

CC

V

16

I/O

30

31

I/O

I/O

18

I/O17I/O

28

I/O29I/O

39
38
37
36

35
34
33

32
31

30
29

19

20

I/O

I/O

I/O

27

I/O

26

I/O

25

I/O

24

CLK1/I

GND

I

4

I

3

I/O

23

I/O

22

I/O

21

14128I-2

5

Note:
Pin-compatible with MACH110, MACH111, MACH211, and MACH215.

3MACH210-7/10/12/15/20, Q-12/15/20

AMD

CONNECTION DIAGRAM
Top View

I/O4

I/O3

I/O2

TQFP

I/O0

I/O1

GND

V

CC

I/O30

I/O31

I/O28

I/O29

CLK0/I2

Note:
Pin-compatible with MACH111 and MACH211.

PIN DESIGNATIONS

I/O5
I/O6
I/O7

I0
I1

GND

I/O8

I/O9
I/O10
I/O11

4443424140

1
2
3
4
5
6
7
8
9
10
11

1213141516

I/O12

I/O13

I/O14

CC

V

I/O15

39

17

18

GND

I/O16

38

373635

192021

I/O17

I/O18

I/O19

34

33
32
31
30
29
28
27
26
25
24
23

22

I/O20

I/O27
I/O26
I/O25
I/O24
CLK1/I5
GND
I4
I3
I/O23
I/O22
I/O21

14128I-3

CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output

V

= Supply Voltage

CC

MACH210-7/10/12/15/20, Q-12/15/204

AMD

ORDERING INFORMATION
Commercial Products

AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:

MACH -7 J C

FAMILY TYPE

MACH = Macro Array CMOS High-Speed

DEVICE NUMBER

210 = 64 Macrocells, 44 Pins
210A = 64 Macrocells, 44 Pins, Input Pull-Up Resistors
210AQ = 64 Macrocells, 44 Pins, Input Pull-Up Resistors,

SPEED

-7 = 7.5 ns t

-10 = 10 ns t

-12 = 12 ns t

-15 = 15 ns t

-20 = 20 ns t

Quarter Power

PD
PD
PD
PD
PD

Valid Combinations

MACH210A-7
MACH210A-10
MACH210A-12
MACH210-12
MACH210-15
MACH210-20
MACH210AQ-12
MACH210AQ-15
MACH210AQ-20

JC,
VC

JC

210A

OPTIONAL PROCESSING

Blank = Standard Processing

OPERATING CONDITIONS

C = Commercial (0

PACKAGE TYPE

J = 44-Pin Plastic Leaded Chip

Carrier (PL 044)

V = 44-Pin Thin Quad Flat Pack

(PQT044)

Valid Combinations

The Valid Combinations table lists configurations
planned to be supported in volume for this device. Con­sult the local AMD sales office to confirm availability of
specific valid combinations or to check on newly re­leased combinations.

°C to +70°C)

MACH210-7/10/12/15/20, Q-12/15/20 (Com’l)

5

AMD

ORDERING INFORMATION
Industrial Products

AMD programmable logic products for industrial applications are available with several ordering options. The order number (Valid
Combination) is formed by a combination of:

MACH -12 J I

FAMILY TYPE

MACH = Macro Array CMOS High-Speed

DEVICE NUMBER

210 = 64 Macrocells, 44 Pins
210A = 64 Macrocells, 44 Pins, Input Pull-Up Resistors

SPEED

-12 = 12 ns t

-14 = 14.5 ns t

-18 = 18 ns t

-24 = 24 ns t

PD

PD
PD
PD

Valid Combinations

MACH210A-12
MACH210A-14
MACH210-14
MACH210-18
MACH210-24

JI

210A

OPTIONAL PROCESSING

Blank = Standard Processing

OPERATING CONDITIONS

I = Industrial (–40

PACKAGE TYPE

J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)

Valid Combinations

The Valid Combinations table lists configurations
planned to be supported in volume for this device. Con­sult the local AMD sales office to confirm availability of
specific valid combinations or to check on newly re­leased combinations.

°C to +85°C)

6 MACH210-12/14/18/24 (Ind)

AMD

FUNCTIONAL DESCRIPTION

The MACH210 consists of four PAL blocks connected
by a switch matrix. There are 32 I/O pins and 4
dedicated input pins feeding the switch matrix. These
signals are distributed to the four PAL blocks for efficient
design implementation. There are two clock pins that
can also be used as dedicated inputs.

The MACH210A inputs and I/O pins have built-in pull-up
resistors. While it is always a good design practice to tie
unused pins high, the 210A pull-up resistors provide
design security and stability in the event that unused
pins are left disconnected.

The PAL Blocks

Each PAL block in the MACH210 (Figure 1) contains a
64-product-term logic array, a logic allocator, 8 output
macrocells, 8 buried macrocells, and 8 I/O cells. The
switch matrix feeds each PAL block with 22 inputs. This
makes the PAL block look effectively like an independ­ent “PAL22V16” with 8 buried macrocells.

In addition to the logic product terms, two output enable
product terms, an asynchronous reset product term,
and an asynchronous preset product term are provided.
One of the two output enable product terms can be
chosen within each I/O cell in the PAL block. All flip-flops
within the PAL block are initialized together.

The Switch Matrix

The MACH210 switch matrix is fed by the inputs and
feedback signals from the PAL blocks. Each PAL block
provides 16 internal feedback signals and 8 I/O
feedback signals. The switch matrix distributes these
signals back to the PAL blocks in an efficient manner
that also provides for high performance. The design
software automatically configures the switch matrix
when fitting a design into the device.

The Product-term Array

The MACH210 product-term array consists of 64
product terms for logic use, and 4 special-purpose
product terms. Two of the special-purpose product
terms provide programmable output enable; one pro­vides asynchronous reset, and one provides asynchro­nous preset.

The Logic Allocator

The logic allocator in the MACH210 takes the 64 logic
product terms and allocates them to the 16 macrocells
as needed. Each macrocell can be driven by up to 16
product terms. The design software automatically
configures the logic allocator when fitting the design into
the device.

Table 1 illustrates which product term clusters are
available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.

Table 1. Logic Allocation

Macrocell

Output Buried Clusters

M

0

M

1

M

2

M

3

M

4

M

5

M

6

M

7

M

8

M

9

M

10

M

11

M

12

M

13

M

14

M

15

Available

C0, C1, C
C0, C1, C2, C

C1, C2, C3, C
C2, C3, C4, C

C3, C4, C5, C
C4, C5, C6, C

C5, C6, C7, C
C6, C7, C8, C

C7, C8, C9, C

2

3
4

5
6

7
8

9
10

C8, C9, C10, C
C9, C10, C11, C

C10, C11, C12, C
C11, C12, C13, C

C12, C13, C14, C
C13, C14, C

C14, C

15

15

11

12

13
14

15

The Macrocell

The MACH210 has two types of macrocell: output and
buried. The output macrocells can be configured as
either registered, latched, or combinatorial, with pro­grammable polarity. The macrocell provides internal
feedback whether configured with or without the flip­flop. The registers can be configured as D-type or
T-type, allowing for product-term optimization.

The flip-flops can individually select one of two clock/
gate pins, which are also available as data inputs. The
registers are clocked on the LOW-to-HIGH transition of
the clock signal. The latch holds its data when the gate
input is HIGH, and is transparent when the gate input is
LOW. The flip-flops can also be asynchronously initial­ized with the common asynchronous reset and preset
product terms.

The buried macrocells are the same as the output
macrocells if they are used for generating logic. In that
case, the only thing that distinguishes them from the
output macrocells is the fact that there is no I/O cell
connection, and the signal is only used internally. The
buried macrocell can also be configured as an input
register or latch.

7MACH210-7/10/12/15/20, Q-12/15/20

AMD

The I/O Cell

The I/O cell in the MACH210 consists of a three-state
output buffer. The three-state buffer can be configured
in one of three ways: always enabled, always disabled,
or controlled by a product term. If product term control is
chosen, one of two product terms may be used to
provide the control. The two product terms that are
available are common to all I/O cells in a PAL block.

These choices make it possible to use the macrocell as
an output, an input, a bidirectional pin, or a three-state
output for use in driving a bus.

PCI Compliance

The MACH210A-7/10 is fully compliant with the

Local Bus Specification

Interest Group. The MACH210A-7/10’s predictable
timing ensures compliance with the PCI AC specifica­tions independent of the design. On the other hand, in
CPLD and FPGA architectures without predictable
timing, PCI compliance is dependent upon routing and
product term distribution.

published by the PCI Special

PCI

MACH210-7/10/12/15/20, Q-12/15/208

AMD

Switch
Matrix

0 4 8 12 16 20 24 28 40324336

0

63

Output Enable
Output Enable

Asynchronous Reset
Asynchronous Preset

M

M

M

M

C

0

C

M

1

C

2

C

M

3

C

4

C

M

5

C

6

C

M

7

7

C

Logic Allocator

8

C

M

9

8

C

10

C

M

11

C

12

C

M

13

10

C

14

C

M

15

11

M

12

I/O

Output
Macro

0

1

2

3

4

5

6

9

cell

2

Buried
Macro 
cell

2

Output
Macro
cell

2

Buried
Macro 
cell

2

Output
Macro
cell

2

Buried
Macro 
cell

2

Output
Macro
cell

2

Buried
Macro 
cell

2

Output
Macro
cell

2

Buried
Macro 
cell

2

Output
Macro
cell

2

Buried
Macro 
cell

2

Output
Macro
cell

2

Cell

I/O

Cell

I/O

Cell

I/O

Cell

I/O

Cell

I/O

Cell

I/O
Cell

I/O

I/O

I/O

I/O

I/O

I/O

I/O

0 4 8 12 16 20 24 28 40324336

16

8

Figure 1. MACH210 PAL Block

Buried

M

13

M

14

M

15

CLK0

CLK1

Macro 
cell

2

I/O

Output
Macro
cell

2

Buried
Macro 
cell

2

Cell

I/O

14128I-4

9MACH210-7/10/12/15/20, Q-12/15/20

AMD

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature

with Power Applied –55°C to +125°C. . . . . . . . . . . . .

Supply Voltage with

Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .

DC Input Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . .

DC Output or
I/O Pin Voltage –0.5 V to V

CC

+ 0.5 V. . . . . . . . . . . .

OPERATING RANGES

Commercial (C) Devices

Temperature (TA) Operating

in Free Air 0°C to +70°C. . . . . . . . . . . . . . . . . . . . . . .

Supply Voltage (V

Respect to Ground +4.75 V to +5.25 V. . . . . . . . . . . .

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

CC

) with

Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .

Latchup Current
(T

= 0°C to +70°C) 200 mA. . . . . . . . . . . . . . . . . . . .

A

Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability. Pro­gramming conditions may differ.

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

IOZH Off-State Output Leakage V

IOZL Off-State Output Leakage V

I

SC

I

CC

(Note 4)

Notes:

1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

2. I/O pin leakage is the worst case of I

3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
V

= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

OUT

4. This parameter is measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and
capable of being loaded, enabled, and reset.

Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V

= V

IH

or V

IL

V

IN

Output LOW Voltage IOL = 16 mA, VCC = Min 0.5 V

= V

IH

or V

IL

V

IN

Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V

Voltage for all Inputs (Note 1)

Input LOW Voltage Guaranteed Input Logical LOW 0.8 V

Voltage for all Inputs (Note 1)
Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA
Input LOW Leakage Current V

Current HIGH V

Current LOW V
Output Short-Circuit Current V
Supply Current V

and I

IL

(or IIH and I

OZL

= 0 V, V

IN

= 5.25 V, VCC = Max 10 µA

OUT

= V

IN

IH

= 0 V, VCC = Max –100 µA

OUT

= V

IN

IH

= 0.5 V, VCC = Max (Note 3) –30 –160 mA

OUT

= 0 V, Outputs Open (I

IN

= 5.0 V, f = 25 MHz, TA = 25°C

V

CC

OZH

= Max (Note 2) –100 µA

CC

or VIL (Note 2)

or VIL (Note 2)

= 0 mA) 130 mA

OUT

).

10 MACH210A-7 (Com’l)

AMD

CAPACITANCE (Note 1)

Parameter

Symbol Parameter Description Test Conditions Typ Unit

C

C

OUT

IN

Input Capacitance V
Output Capacitance V

= 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF

IN

= 2.0 V f = 1 MHz 8 pF

OUT

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges

Parameter

Symbol Parameter Description Min Max Unit

t

PD

t

S

Input, I/O, or Feedback to Combinatorial Output 7.5 ns
Setup Time from Input, I/O or Feedback to Clock D-Type 5.5 ns

T-Type 6.5 ns

-7

t

H

t

CO

t

WL

t

WH

f

MAX

t

SL

t

HL

t

GO

t

GWL

t

PDL

t

SIR

t

HIR

t

ICO

t

ICS

Register Data Hold Time 0 ns
Clock to Output 5ns
Clock Width LOW 3 ns

HIGH 3 ns

D-Type 100 MHz

Maximum

D-Type 133 MHz

Frequency

External Feedback

Internal Feedback (f

No Feedback

CNT

T-Type 91 MHz

)

T-Type 125 MHz

166.7 MHz
Setup Time from Input, I/O, or Feedback to Gate 5.5 ns
Latch Data Hold Time 0 ns
Gate to Output 6ns
Gate Width LOW 3 ns
Input, I/O, or Feedback to Output Through 9.5 ns

Transparent Input or Output Latch
Input Register Setup Time 2 ns
Input Register Hold Time 2 ns
Input Register Clock to Combinatorial Output 11 ns
Input Register Clock to Output Register Setup D-Type 9 ns

T-Type 10 ns

t

WICL

t

WICH

f

MAXIR

t

SIL

t

HIL

t

IGO

t

IGOL

t

SLL

Input Register Clock Width LOW 3 ns

HIGH 3 ns
Maximum Input Register Frequency 166.7 MHz
Input Latch Setup Time 2 ns
Input Latch Hold Time 2 ns
Input Latch Gate to Combinatorial Output 12 ns
Input Latch Gate to Output Through Transparent Output Latch 14 ns
Setup Time from Input, I/O, or Feedback Through 7.5 ns

Transparent Input Latch to Output Latch Gate

11MACH210A-7 (Com’l)

AMD

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (continued)

Parameter

-7

Symbol Parameter Description Min Max Unit

t

IGS

t

WIGL

t

PDLL

Input Latch Gate to Output Latch Setup 10 ns
Input Latch Gate Width LOW 3 ns
Input, I/O, or Feedback to Output Through Transparent 11.5 ns

Input and Output Latches

t

AR

t

ARW

t

ARR

t

AP

t

APW

t

APR

t

EA

t

ER

Asynchronous Reset to Registered or Latched Output 12 ns
Asynchronous Reset Width 8 ns
Asynchronous Reset Recovery Time 8 ns
Asynchronous Preset to Registered or Latched Output 12 ns
Asynchronous Preset Width 8 ns
Asynchronous Preset Recovery Time 8 ns
Input, I/O, or Feedback to Output Enable 7.5 ns
Input, I/O, or Feedback to Output Disable 7.5 ns

Note:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.

12 MACH210A-7 (Com’l)

AMD

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature

with Power Applied –55°C to +125°C. . . . . . . . . . . . .

Supply Voltage with

Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .

DC Input Voltage –0.5 V to V
DC Output or

I/O Pin Voltage –0.5 V to V

CC

CC

+ 0.5 V. . . . . . . . . . .

+ 0.5 V. . . . . . . . . . . .

OPERATING RANGES

Commercial (C) Devices

Temperature (T

in Free Air 0°C to +70°C. . . . . . . . . . . . . . . . . . . . . . .

Supply Voltage (V

Respect to Ground +4.75 V to +5.25 V. . . . . . . . . . . .

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

) Operating

A

) with

CC

Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .

Latchup Current (T

Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.

= 0°C to +70°C) 200 mA. . . . . .

A

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified

Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

I

OZH

I

OZL

I

SC

I

CC

Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V

V

= VIH or V

IN

IL

Output LOW Voltage IOL = 16 mA, VCC = Min 0.5 V

= VIH or V

V

IN

IL

Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V

Voltage for all Inputs (Note 1)

Input LOW Voltage Guaranteed Input Logical LOW 0.8 V

Voltage for all Inputs (Note 1)

Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA
Input LOW Leakage Current VIN = 0 V, V

Off-State Output Leakage V
Current HIGH V

Off-State Output Leakage V
Current LOW V

Output Short-Circuit Current V
Supply Current (Typical) V

= 5.25 V, VCC = Max 10 µA

OUT

= V

IN

= 0 V, VCC = Max –100 µA

OUT

= V

IN

= 0.5 V, VCC = Max (Note 3) –30 –160 mA

OUT

= 5V, TA = 25°C, f = 25 MHz 135 mA

CC

= Max (Note 2) –100 µA

CC

or VIL (Note 2)

IH

or VIL (Note 2)

IH

(Note 4)

Notes:

1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

2. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

OZH

).

3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being

loaded, enabled, and reset.

MACH210A-10/12 (Com’l)

13

AMD

CAPACITANCE (Note 1)

Parameter
Symbol Parameter Description Test Conditions Typ Unit

C

IN

C

OUT

Input Capacitance V
Output Capacitance V

= 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF

IN

= 2.0 V f = 1 MHz 8 pF

OUT

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)

Parameter

Symbol Parameter Description Min Max Min Max Unit

t

PD

Input, I/O, or Feedback to Combinatorial Output

(Note 3) 10 12 ns

D-Type 6.5 7 ns
T-Type 7.5 8 ns

t
t

t

t

WH

S

t

CO

WL

Setup Time from Input, I/O,
or Feedback to Clock

H

Register Data Hold Time 0 0 ns
Clock to Output (Note 3) 6 8 ns
Clock LOW 5 6 ns

Width HIGH 5 6 ns
D-Type 80 66.7 MHz

f

MAX

t
t

t

t

GWL

t

PDL

SL

HL

GO

Maximum

External Feedback 1/(tS + tCO)

Frequency

D-Type 100 83.3 MHz

(Note 1)

Internal Feedback (f

CNT

No Feedback 1/(t

)

S

+ t

)

H

Setup Time from Input, I/O, or Feedback to Gate 6.5 7 ns
Latch Data Hold Time 0 0 ns
Gate to Output (Note 3) 7 10 ns
Gate Width LOW 5 6 ns
Input, I/O, or Feedback to Output Through

T-Type 74 62.5 MHz

T-Type 91 76.9 MHz

Transparent Input or Output Latch 12 14 ns

t

SIR

t

HIR

t

ICO

t

ICS

Input Register Setup Time 2 2 ns
Input Register Hold Time 2 2 ns
Input Register Clock to Combinatorial Output 13 15 ns
Input Register Clock to Output Register Setup D-Type 10 12 ns

T-Type 11 13 ns

t

WICL

t

WICH

f

MAXIR

t

SIL

t

HIL

t

IGO

t

IGOL

Input Register LOW 5 6 ns
Clock Width HIGH 5 6 ns

Maximum Input Register Frequency 1/(t

WICL

+ t

) 100 83.3 MHz

WICH

Input Latch Setup Time 2 2 ns
Input Latch Hold Time 2 2 ns
Input Latch Gate to Combinatorial Output 14 17 ns
Input Latch Gate to Output Through Transparent

Output Latch 16 19 ns

t

SLL

Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate 8.5 9 ns

t

IGS

Input Latch Gate to Output Latch Setup 11 13 ns

-10 -12

100 83.3 MHz

14

MACH210A-10/12 (Com’l)

AMD

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)

Parameter

Symbol Parameter Description Min Max Min Max Unit

t

WIGL

t

PDLL

t

AR

t

ARW

t

ARR

t

AP

t

APW

t

APR

t

EA

t

ER

Notes:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified

where capacitance may be affected.

2. See Switching Test Circuit, for test conditions.

3. Parameters measured with 16 outputs switching.

Input Latch Gate Width LOW 5 6 ns
Input, I/O, or Feedback to Output Through Transparent

Input and Output Latches 14 16 ns
Asynchronous Reset to Registered or Latched Output 25 16 ns
Asynchronous Reset Width (Note 1) 10 12 ns
Asynchronous Reset Recovery Time (Note 1) 10 8 ns
Asynchronous Preset to Registered or Latched Output 15 16 ns
Asynchronous Preset Width (Note 1) 10 12 ns
Asynchronous Preset Recovery Time (Note 1) 10 8 ns
Input, I/O, or Feedback to Output Enable (Note 3) 10 12 ns
Input, I/O, or Feedback to Output Disable (Note 3) 10 12 ns

-10 -12

MACH210A-10/12 (Com’l)

15

AMD

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature

with Power Applied –55°C to +125°C. . . . . . . . . . . . .

Supply Voltage with

INDUSTRIAL OPERATING RANGES

Temperature (TA) Operating

in Free Air –40°C to +85°C. . . . . . . . . . . . . . . . . . . . .

Supply Voltage (V

Respect to Ground +4.5 V to +5.5 V. . . . . . . . . . . . . .

CC

) with

Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .

DC Input Voltage –0.5 V to V
DC Output or

I/O Pin Voltage –0.5 V to V

CC

CC

+ 0.5 V. . . . . . . . . . .

+ 0.5 V. . . . . . . . . . . .

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .

Latchup Current (T

Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.

= 0°C to +70°C) 200 mA. . . . . .

A

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified

Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

I

OZH

I

OZL

I

SC

I

CC

Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V

V

= VIH or V

IN

IL

Output LOW Voltage IOL = 16 mA, VCC = Min 0.5 V

= VIH or V

V

IN

IL

Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V

Voltage for all Inputs (Note 1)

Input LOW Voltage Guaranteed Input Logical LOW 0.8 V

Voltage for all Inputs (Note 1)

Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA
Input LOW Leakage Current VIN = 0 V, V

Off-State Output Leakage V
Current HIGH V

Off-State Output Leakage V
Current LOW V

Output Short-Circuit Current V
Supply Current (Typical) V

= 5.25 V, VCC = Max 10 µA

OUT

= V

IN

= 0 V, VCC = Max –100 µA

OUT

= V

IN

= 0.5 V, VCC = Max (Note 3) –30 –160 mA

OUT

= 5V, TA = 25°C, f = 25 MHz 135 mA

CC

= Max (Note 2) –100 µA

CC

or VIL (Note 2)

IH

or VIL (Note 2)

IH

(Note 4)

Notes:

1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

2. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

OZH

).

3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being

loaded, enabled, and reset.

16

MACH210A-12/14 (Ind)

AMD

CAPACITANCE (Note 1)

Parameter
Symbol Parameter Description Test Conditions Typ Unit

C

IN

C

OUT

Input Capacitance V
Output Capacitance V

= 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF

IN

= 2.0 V f = 1 MHz 8 pF

OUT

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)

Parameter

Symbol Parameter Description Min Max Min Max Unit

t

PD

Input, I/O, or Feedback to Combinatorial Output

(Note 3) 12 14.5 ns

D-Type 8 8.5 ns
T-Type 9 10 ns

t
t

t

t

WH

S

t

CO

WL

Setup Time from Input, I/O,
or Feedback to Clock

H

Register Data Hold Time 0 0 ns
Clock to Output (Note 3) 7.5 10 ns
Clock LOW 6 7.5 ns

Width HIGH 6 7.5 ns
D-Type 64 53 MHz

f

MAX

t
t

t

t

GWL

t

PDL

SL

HL

GO

Maximum

External Feedback 1/(tS + tCO)

Frequency

D-Type 80 61.5 MHz

(Note 1)

Internal Feedback (f

CNT

No Feedback 1/(t

)

S

+ t

)

H

Setup Time from Input, I/O, or Feedback to Gate 8 8.5 ns
Latch Data Hold Time 0 0 ns
Gate to Output (Note 3) 8.5 12 ns
Gate Width LOW 6 7.5 ns
Input, I/O, or Feedback to Output Through

T-Type 59 50 MHz

T-Type 72.5 57 MHz

Transparent Input or Output Latch 14.5 17 ns

t

SIR

t

HIR

t

ICO

t

ICS

Input Register Setup Time 2.5 2.5 ns
Input Register Hold Time 3 3 ns
Input Register Clock to Combinatorial Output 16 18 ns
Input Register Clock to Output Register Setup D-Type 12 14.5 ns

T-Type 13 16 ns

t

WICL

t

WICH

f

MAXIR

t

SIL

t

HIL

t

IGO

t

IGOL

Input Register LOW 6 7.5 ns
Clock Width HIGH 6 7.5 ns

Maximum Input Register Frequency 1/(t

WICL

+ t

) 80 66.5 MHz

WICH

Input Latch Setup Time 2.5 2.5 ns
Input Latch Hold Time 3 3 ns
Input Latch Gate to Combinatorial Output 17 20.5 ns
Input Latch Gate to Output Through Transparent

Output Latch 19.5 23 ns

t

SLL

Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate 10.5 11 ns

t

IGS

Input Latch Gate to Output Latch Setup 13.5 16 ns

-12 -14

80 66.5 MHz

MACH210A-12/14 (Ind)

17

AMD

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)

Parameter

Symbol Parameter Description Min Max Min Max Unit

t

WIGL

t

PDLL

t

AR

t

ARW

t

ARR

t

AP

t

APW

t

APR

t

EA

t

ER

Notes:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified

where capacitance may be affected.

2. See Switching Test Circuit, for test conditions.

3. Parameters measured with 16 outputs switching.

Input Latch Gate Width LOW 6 7.5 ns
Input, I/O, or Feedback to Output Through Transparent

Input and Output Latches 17 19.5 ns
Asynchronous Reset to Registered or Latched Output 19.5 19.5 ns
Asynchronous Reset Width (Note 1) 12 14.5 ns
Asynchronous Reset Recovery Time (Note 1) 12 10 ns
Asynchronous Preset to Registered or Latched Output 18 19.5 ns
Asynchronous Preset Width (Note 1) 12 14.5 ns
Asynchronous Preset Recovery Time (Note 1) 12 10 ns
Input, I/O, or Feedback to Output Enable (Note 3) 12 14.5 ns
Input, I/O, or Feedback to Output Disable (Note 3) 12 14.5 ns

-12 -14

18

MACH210A-12/14 (Ind)

AMD

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature

with Power Applied –55°C to +125°C. . . . . . . . . . . . .

Supply Voltage with

Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .

DC Input Voltage –0.5 V to V
DC Output or

I/O Pin Voltage –0.5 V to V

CC

CC

+ 0.5 V. . . . . . . . . . .

+ 0.5 V. . . . . . . . . . . .

OPERATING RANGES

Commercial (C) Devices

Temperature (T

in Free Air 0°C to +70°C. . . . . . . . . . . . . . . . . . . . . . .

Supply Voltage (V

Respect to Ground +4.75 V to +5.25 V. . . . . . . . . . . .

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

) Operating

A

) with

CC

Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .

Latchup Current (T

Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.

= 0°C to +70°C) 200 mA. . . . . .

A

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified

Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

I

OZH

I

OZL

I

SC

I

CC

Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V

V

= VIH or V

IN

IL

Output LOW Voltage IOL = 16 mA, VCC = Min 0.5 V

= VIH or V

V

IN

IL

Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V

Voltage for all Inputs (Note 1)

Input LOW Voltage Guaranteed Input Logical LOW 0.8 V

Voltage for all Inputs (Note 1)
Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA
Input LOW Leakage Current VIN = 0 V, V
Off-State Output Leakage V

Current HIGH V
Off-State Output Leakage V

Current LOW V
Output Short-Circuit Current V
Supply Current (Typical) V

= 5.25 V, VCC = Max 10 µA

OUT

= V

IN

= 0 V, VCC = Max –10 µA

OUT

= V

IN

= 0.5 V, VCC = Max (Note 3) –30 –160 mA

OUT

= 5V, TA = 25°C, f = 25 MHz 120 mA

CC

= Max (Note 2) –10 µA

CC

or VIL (Note 2)

IH

or VIL (Note 2)

IH

(Note 4)

Notes:

1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

2. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

OZH

).

3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being

loaded, enabled, and reset.

MACH210-12/15/20 (Com’l)

19

AMD

CAPACITANCE (Note 1)

Parameter
Symbol Parameter Description Test Conditions Typ Unit

C

IN

C

OUT

Input Capacitance V
Output Capacitance V

= 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF

IN

= 2.0 V f = 1 MHz 8 pF

OUT

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)

Parameter

-12

Symbol Parameter Description Min Max Min Max Min Max Unit

t

PD

Input, I/O, or Feedback to Combinatorial Output

(Note 3) 12 15 20 ns

D-type 7 10 13 ns
T-type 8 11 14 ns

t
t

t

t

WH

S

t

CO

WL

Setup Time from Input, I/O,
or Feedback to Clock

H

Register Data Hold Time 0 0 0 ns
Clock to Output (Note 3) 8 10 12 ns
Clock LOW 6 6 8 ns

Width HIGH 6 6 8 ns
D-type 66.7 50 40 MHz

f

MAX

t
t

t

t

GWL

t

PDL

SL

HL

GO

External Feedback 1/(tS + tCO)

Maximum
Frequency

D-type 83.3 66.6 50 MHz

(Note 1)

Internal Feedback (f

CNT

No Feedback 1/(t

)

WL

+ t

WH

)

Setup Time from Input, I/O, or Feedback to Gate 7 10 13 ns
Latch Data Hold Time 0 0 0 ns
Gate to Output (Note 3) 10 11 12 ns
Gate Width LOW 6 6 8 ns
Input, I/O, or Feedback to Output Through

T-type 62.5 47.6 38.5 MHz

T-type 76.9 62.5 47.6 MHz

83.3 83.3 62.5 MHz

Transparent Input or Output Latch 14 17 22 ns

t

SIR

t

HIR

t

ICO

t

ICS

t

WICL

t

WICH

f

MAXIR

t

SIL

t

HIL

t

IGO

t

IGOL

Input Register Setup Time 2 2 2 ns
Input Register Hold Time 2 2.5 3 ns
Input Register Clock to Combinatorial Output 15 18 23 ns
Input Register Clock to Output Register Setup 12 15 20 ns

D-type
T-type

13 16 21 ns

Input Register LOW 6 6 8 ns
Clock Width HIGH 6 6 8 ns

Maximum Input Register Frequency 1/(t

WICL

+ t

) 83.3 83.3 62.5 MHz

WICH

Input Latch Setup Time 2 2 2 ns
Input Latch Hold Time 2 2.5 3 ns
Input Latch Gate to Combinatorial Output 17 20 25 ns
Input Latch Gate to Output Through Transparent

Output Latch 19 22 27 ns

t

SLL

Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate 9 12 15 ns

t

IGS

Input Latch Gate to Output Latch Setup 13 16 21 ns

-15 -20

20

MACH210-12/15/20 (Com’l)

AMD

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)

(continued)

Parameter

Symbol Parameter Description Min Max Min Max Min Max Unit

t

WIGL

t

PDLL

t

AR

t

ARW

t

ARR

t

AP

t

APW

t

APR

t

EA

t

ER

Notes:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified

where capacitance may be affected.

2. See Switching Test Circuit, for test conditions.

3. Parameters measured with 16 outputs switching.

Input Latch Gate Width LOW 6 6 8 ns
Input, I/O, or Feedback to Output Through Transparent

Input and Output Latches 16 19 24 ns
Asynchronous Reset to Registered or Latched Output 16 20 25 ns
Asynchronous Reset Width (Note 1) 12 15 20 ns
Asynchronous Reset Recovery Time (Note 1) 8 10 15 ns
Asynchronous Preset to Registered or Latched Output 16 20 25 ns
Asynchronous Preset Width (Note 1) 12 15 20 ns
Asynchronous Preset Recovery Time (Note 1) 8 10 15 ns
Input, I/O, or Feedback to Output Enable (Note 3) 12 15 20 ns
Input, I/O, or Feedback to Output Disable (Note 3) 12 15 20 ns

-15 -20-12

MACH210-12/15/20 (Com’l)

21

AMD

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature

With Power Applied –55°C to +125°C. . . . . . . . . . . . .

Supply Voltage with

Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .

DC Input Voltage –0.5 V to V

CC

+ 0.5 V. . . . . . . . . . . .

INDUSTRIAL OPERATING RANGES

Ambient Temperature (TA)

Operating in Free Air –40°C to +85°C. . . . . . . . . . . .

Supply Voltage (V

with Respect to Ground +4.5 V to +5.5 V. . . . . . . . . .

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

CC)

DC Output or I/O

CC

Pin Voltage –0.5 V to V

+ 0.5 V. . . . . . . . . . . . . . . .

Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . .

Latchup Current
(T

A = –40°C to +85 °C) 200 mA. . . . . . . . . . . . . . . . . .

Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.

DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise
specified

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V

VIN = VIH or VIL

VOL Output LOW Voltage IOL = 16 mA, VCC = Min 0.5 V

VIN = VIH or VIL

VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V

Voltage for all Inputs (Note 1)

VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V

Voltage for all Inputs (Note 1)

IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA

IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –10 µA

IOZH Off-State Output Leakage VOUT = 5.25 V, VCC = Max 10 µA

Current HIGH VIN = VIH or VIL (Note 2)

IOZL Off-State Output Leakage VOUT = 0 V, VCC = Max –10 µA

Current LOW VIN = VIH or VIL (Note 2)

ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA
ICC

Notes:

1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.

2. I/O pin leakage is the worst case of I

3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.

OUT

= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of
being loaded, enabled, and reset.

Supply Current (Typical) VCC = 5 V, TA = 25°C, f = 25 MHz (Note 4) 120 mA

IL

and I

OZL

(or IIH and I

OZH

).

22

MACH210-14/18/24 (Ind)

AMD

CAPACITANCE (Note 1)

Parameter
Symbol Parameter Description Test Conditions Typ Unit

CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF

COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF

SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)

Parameter

Symbol Parameter Description Min Max Min Max Min Max Unit

tPD Input, I/O, or Feedback to Combinatorial Output 14.5 18 24 ns

(Note 3)

tS

tH Register Data Hold Time 0 0 0 ns
tCO Clock to Output (Note 3) 10 12 14.5 ns
tWL Clock LOW 7.5 7.5 10 ns

tWH Width HIGH 7.5 7.5 10 ns

fMAX D-type 61.5 53 38 MHz

tSL Setup Time from Input, I/O, or Feedback to Gate 8.5 12 16 ns
tHL Latch Data Hold Time 0 0 0 ns

tGO Gate to Output (Note 3) 12 13.5 14.5 ns

tGWL Gate Width LOW 7.5 7.5 10 ns

tPDL Input, I/O, or Feedback to Output Through 17 20.5 26.5 ns

tSIR Input Register Setup Time 2.5 2.5 2.5 ns
tHIR Input Register Hold Time 3 3.5 4 ns

tICO Input Register Clock to Combinatorial Output 18 22 28 ns

tICS Input Register Clock to Output Register Setup 14.5 18 24 ns

tWICL Input Register LOW 7.5 7.5 10 ns
tWICH Clock Width HIGH 7.5 7.5 10 ns

fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) 66.5 66.5 50 MHz

tSIL Input Latch Setup Time 2.5 2.5 2.5 ns
tHIL Input Latch Hold Time 3 3.5 4 ns

tIGO Input Latch Gate to Combinatorial Output 20.5 24 30 ns

tIGOL Input Latch Gate to Output Through Transparent 23 26.5 32.5 ns

tSLL Setup Time from Input, I/O, or Feedback Through 11 14.5 18 ns

tIGS Input Latch Gate to Output Latch Setup 16 19.5 25.5 ns

tWIGL Input Latch Gate Width LOW 7.5 7.5 10 ns
tPDLL Input, I/O, or Feedback to Output Through Transparent 19.5 23 29 ns

Setup Time from Input, I/O,
or Feedback to Clock

D-type 53 40 32 MHz

Maximum
Frequency
(Note 1)

Transparent Input or Output Latch

Output Latch

Transparent Input Latch to Output Latch Gate

Input and Output Latches

External Feedback 1/(tS + tCO)

Internal Feedback (fCNT)
No Feedback 1/(tWL + tWH)

D-type 8.5 12 16 ns
T-type 10 13.5 17 ns

T-type 50 38 30.5 MHz

T-type 57 44 34.5 MHz

D-type
T-type

-14

66.5 66.5 50 MHz

16 19.5 25.5 ns

-18 -24

MACH210-14/18/24 (Ind)

23

AMD

SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)

(continued)

Parameter

Symbol Parameter Description Min Max Min Max Min Max Unit

tAR Asynchronous Reset to Registered or Latched Output 19.5 24 30 ns
tARW Asynchronous Reset Width (Note 1) 14.5 18 24 ns
tARR Asynchronous Reset Recovery Time (Note 1) 10 12 18 ns

tAP Asynchronous Preset to Registered or Latched Output 19.5 24 30 ns
tAPW Asynchronous Preset Width (Note 1) 14.5 18 24 ns

tAPR Asynchronous Preset Recovery Time (Note 1) 10 12 18 ns

tEA Input, I/O, or Feedback to Output Enable (Note 3) 14.5 18 24 ns

tER Input, I/O, or Feedback to Output Disable (Note 3) 14.5 18 24 ns

Notes:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.

2. See Switching Test Circuit, for test conditions.

3. Parameters measured with 16 outputs switching.

-18 -24-14

24

MACH210-14/18/24 (Ind)

AMD

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature

with Power Applied –55°C to +125°C. . . . . . . . . . . . .

Supply Voltage with

Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .

DC Input Voltage –0.5 V to V
DC Output or

I/O Pin Voltage –0.5 V to V

CC

CC

+ 0.5 V. . . . . . . . . . .

+ 0.5 V. . . . . . . . . . . .

OPERATING RANGES

Commercial (C) Devices

Temperature (T

in Free Air 0°C to +70°C. . . . . . . . . . . . . . . . . . . . . . .

Supply Voltage (V

Respect to Ground +4.75 V to +5.25 V. . . . . . . . . . . .

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

) Operating

A

) with

CC

Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .

Latchup Current (T

Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.

= 0°C to +70°C) 200 mA. . . . . .

A

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

V

V

V

V

I

OZH

I

I
I

OH

OL

I

IH

I

IL

OZL

SC

CC

IH

IL

Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V

V

= VIH or V

IN

IL

Output LOW Voltage IOL = 16 mA, VCC = Min 0.5 V

V

= VIH or V

IN

IL

Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V

Voltage for all Inputs (Note 1)

Input LOW Voltage Guaranteed Input Logical LOW 0.8 V

Voltage for all Inputs (Note 1)
Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA
Input LOW Leakage Current VIN = 0 V, V
Off-State Output Leakage V

Current HIGH V
Off-State Output Leakage V

Current LOW V
Output Short-Circuit Current V
Supply Current (Typical) V

= 5.25 V, VCC = Max 10 µA

OUT

= V

IN

= 0 V, VCC = Max –100 µA

OUT

= V

IN

= 0.5 V, VCC = Max (Note 3) –30 –160 mA

OUT

= 5 V, TA = 25°C, f = 25 MHz 45 mA

CC

= Max (Note 2) –100 µA

CC

or VIL (Note 2)

IH

or VIL (Note 2)

IH

(Note 4)

Notes:

1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

2. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

OZH

).

3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
V

= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

OUT

4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.

MACH210AQ-12 (Com’l)

25

AMD

CAPACITANCE (Note 1)

Parameter
Symbol Parameter Description Test Conditions Typ Unit

C

IN

C

OUT

Input Capacitance V
Output Capacitance V

= 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF

IN

= 2.0 V f = 1 MHz 8 pF

OUT

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)

Parameter

Symbol Parameter Description Min Max Unit

t

PD

t

S

t

H

t

CO

t

WL

t

WH

Input, I/O, or Feedback to Combinatorial Output 12 ns

Setup Time from Input, I/O,
or Feedback to Clock

D-type 12 ns

T-type 13 ns
Register Data Hold Time 0 ns
Clock to Output 6ns
Clock LOW 6 ns

Width HIGH 6 ns
D-type 55.6 MHz

f

MAX

t

SL

t

HL

t

GO

t

GWL

t

PDL

Maximum

External Feedback

Frequency

D-type 83.3 MHz

(Note 1)

83.3 MHz

Internal Feedback (f

No Feedback

CNT

)

Setup Time from Input, I/O, or Feedback to Gate 12 ns
Latch Data Hold Time 0 ns
Gate to Output 7ns
Gate Width LOW 6 ns
Input, I/O, or Feedback to Output Through

T-type 52.6 MHz

T-type 76.9 MHz

Transparent Input or Output Latch 14 ns

t

SIR

t

HIR

t

ICO

t

ICS

Input Register Setup Time 2 ns
Input Register Hold Time 2.5 ns
Input Register Clock to Combinatorial Output 17 ns
Input Register Clock to Output Register Setup D-type 15 ns

T-type 16 ns

t

WICL

t

WICH

f

MAXIR

t

SIL

t

HIL

t

IGO

t

IGOL

Input Register LOW 6 ns
Clock Width HIGH 6 ns

Maximum Input Register Frequency 83.3 MHz
Input Latch Setup Time 2 ns
Input Latch Hold Time 2.5 ns
Input Latch Gate to Combinatorial Output 19 ns
Input Latch Gate to Output Through Transparent

Output Latch 20 ns

t

SLL

Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate 13 ns

t

IGS

Input Latch Gate to Output Latch Setup 16 ns

-12

26

MACH210AQ-12 (Com’l)

AMD

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)

(continued)

Parameter

Symbol Parameter Description Min Max Unit

t
t

WIGL

PDLL

Input Latch Gate Width LOW 6 ns
Input, I/O, or Feedback to Output Through Transparent

Input and Output Latches 18 ns
Asynchronous Reset to Registered or Latched Output 24 ns
Asynchronous Reset Width (Note 1) 19 ns
Asynchronous Reset Recovery Time (Note 1) 19 ns
Asynchronous Preset to Registered or Latched Output 24 ns
Asynchronous Preset Width (Note 1) 19 ns
Asynchronous Preset Recovery Time (Note 1) 19 ns
Input, I/O, or Feedback to Output Enable 12 ns
Input, I/O, or Feedback to Output Disable 12 ns

t

t

t
t

t

AR

ARW

ARR

t

AP

APW

APR

t

EA

t

ER

Notes:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.

2. See Switching Test Circuit, for test conditions.

-12

MACH210AQ-12 (Com’l)

27

AMD

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature

with Power Applied –55°C to +125°C. . . . . . . . . . . . .

Supply Voltage with

Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .

DC Input Voltage –0.5 V to V
DC Output or

I/O Pin Voltage –0.5 V to V

CC

CC

+ 0.5 V. . . . . . . . . . .

+ 0.5 V. . . . . . . . . . . .

OPERATING RANGES

Commercial (C) Devices

Temperature (T

in Free Air 0°C to +70°C. . . . . . . . . . . . . . . . . . . . . . .

Supply Voltage (V

Respect to Ground +4.75 V to +5.25 V. . . . . . . . . . . .

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

) Operating

A

) with

CC

Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .

Latchup Current (T

Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.

= 0°C to +70°C) 200 mA. . . . . .

A

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified

Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

I

OZH

I

OZL

I

SC

I

CC

Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V

V

= VIH or V

IN

IL

Output LOW Voltage IOL = 16 mA, VCC = Min 0.5 V

= VIH or V

V

IN

IL

Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V

Voltage for all Inputs (Note 1)

Input LOW Voltage Guaranteed Input Logical LOW 0.8 V

Voltage for all Inputs (Note 1)

Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA
Input LOW Leakage Current VIN = 0 V, V

Off-State Output Leakage V
Current HIGH V

Off-State Output Leakage V
Current LOW V

Output Short-Circuit Current V
Supply Current (Typical) V

= 5.25 V, VCC = Max 10 µA

OUT

= V

IN

= 0 V, VCC = Max –100 µA

OUT

= V

IN

= 0.5 V, VCC = Max (Note 3) –30 –160 mA

OUT

= 5V, TA = 25°C, f = 25 MHz 45 mA

CC

= Max (Note 2) –100 µA

CC

or VIL (Note 2)

IH

or VIL (Note 2)

IH

(Note 4)

Notes:

1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

2. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

OZH

).

3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.

28

MACH210AQ-15/20 (Com’l)

AMD

CAPACITANCE (Note 1)

Parameter
Symbol Parameter Description Test Conditions Typ Unit

C

IN

C

OUT

Input Capacitance V
Output Capacitance V

= 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF

IN

= 2.0 V f = 1 MHz 8 pF

OUT

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)

Parameter

Symbol Parameter Description Min Max Min Max Unit

t

PD

Input, I/O, or Feedback to Combinatorial Output

(Note 3) 15 20 ns

D-type 13 17 ns
T-type 14 18 ns

t
t

t

t

WH

S

t

CO

WL

Setup Time from Input, I/O,
or Feedback to Clock

H

Register Data Hold Time 0 0 ns
Clock to Output (Note 3) 7 8 ns
Clock LOW 6 8 ns

Width HIGH 6 8 ns
D-type 50 40 MHz

f

MAX

Maximum

External Feedback 1/(tS + tCO)

Frequency

D-type 58.8 45.4 MHz

(Note 1)

Internal Feedback (f

CNT

)

T-type 47.6 38.4 MHz

T-type 55.5 43.4 MHz
D-type 76.9 58.8 MHz

t
t

t

t

GWL

t

PDL

SL

HL

GO

T-type 71.4 55.5 MHz

No Feedback 1/(t

Setup Time from Input, I/O, or Feedback to Gate 13 17 ns
Latch Data Hold Time 0 0 ns
Gate to Output (Note 3) 8 8 ns
Gate Width LOW 6 8 ns
Input, I/O, or Feedback to Output Through

S

+ t

)

H

Transparent Input or Output Latch 17 22 ns

t

SIR

t

HIR

t

ICO

t

ICS

Input Register Setup Time 2 2 ns
Input Register Hold Time 2.5 3 ns
Input Register Clock to Combinatorial Output 18 23 ns
Input Register Clock to Output Register Setup 17 22 ns

D-type
T-type

t

WICL

t

WICH

f

MAXIR

t

SIL

t

HIL

t

IGO

t

IGOL

Input Register LOW 6 8 ns
Clock Width HIGH 6 8 ns

Maximum Input Register Frequency 1/(t

WICL

+ t

) 83.3 62.5 MHz

WICH

Input Latch Setup Time 2 2 ns
Input Latch Hold Time 2.5 3 ns
Input Latch Gate to Combinatorial Output 20 25 ns
Input Latch Gate to Output Through Transparent

Output Latch 22 27 ns

t

SLL

Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate 15 19 ns

t

IGS

Input Latch Gate to Output Latch Setup 18 23 ns

-15 -20

18 23 ns

MACH210AQ-15/20 (Com’l)

29

AMD

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)

Parameter

Symbol Parameter Description Min Max Min Max Unit

t

WIGL

t

PDLL

t

AR

t

ARW

t

ARR

t

AP

t

APW

t

APR

t

EA

t

ER

Notes:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.

2. See Switching Test Circuit, for test conditions.

3. Parameters measured with 16 outputs switching.

Input Latch Gate Width LOW 6 8 ns
Input, I/O, or Feedback to Output Through Transparent

Input and Output Latches 19 24 ns
Asynchronous Reset to Registered or Latched Output 25 30 ns
Asynchronous Reset Width (Note 1) 20 25 ns
Asynchronous Reset Recovery Time (Note 1) 20 25 ns
Asynchronous Preset to Registered or Latched Output 25 30 ns
Asynchronous Preset Width (Note 1) 20 25 ns
Asynchronous Preset Recovery Time (Note 1) 20 25 ns
Input, I/O, or Feedback to Output Enable (Note 3) 15 20 ns
Input, I/O, or Feedback to Output Disable (Note 3) 15 20 ns

-15 -20

30

MACH210AQ-15/20 (Com’l)

AMD

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature

With Power Applied –55°C to +125°C. . . . . . . . . . . . .

Supply Voltage with

Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .

DC Input Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .

INDUSTRIAL OPERATING RANGES

Ambient Temperature (TA)

Operating in Free Air –40°C to +85°C. . . . . . . . . . . .

Supply Voltage (V

with Respect to Ground +4.5 V to +5.5 V. . . . . . . . . .

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

CC)

DC Output or I/O
Pin Voltage –0.5 V to V

CC + 0.5 V. . . . . . . . . . . . . . . .

Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . .

Latchup Current
(T

A = –40°C to +85 °C) 200 mA. . . . . . . . . . . . . . . . . .

Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.

DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise
specified

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V

VIN = VIH or VIL

VOL Output LOW Voltage IOL = 16 mA, VCC = Min 0.5 V

VIN = VIH or VIL

VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V

Voltage for all Inputs (Note 1)

VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V

Voltage for all Inputs (Note 1)

IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA

IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –100 µA

IOZH Off-State Output Leakage VOUT = 5.25 V, VCC = Max 10 µA

Current HIGH VIN = VIH or VIL (Note 2)

IOZL Off-State Output Leakage VOUT = 0 V, VCC = Max –100 µA

Current LOW VIN = VIH or VIL (Note 2)
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA
ICC Supply Current (Typical) VCC = 5 V, TA = 25°C, f = 25 MHz (Note 4) 45 mA

Notes:

1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.

IL

and I

OZL

2. I/O pin leakage is the worst case of I

3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.

OUT

= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of
being loaded, enabled, and reset.

(or IIH and I

OZH

).

MACH210AQ-18/24 (Ind)

31

AMD

CAPACITANCE (Note 1)

Parameter
Symbol Parameter Description Test Conditions Typ Unit

CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF

COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF

SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)

Parameter

Symbol Parameter Description Min Max Min Max Unit

tPD Input, I/O, or Feedback to Combinatorial Output 18 24 ns

(Note 3)

tS

tH Register Data Hold Time 0 0 ns
tCO Clock to Output (Note 3) 8.5 10 ns
tWL Clock LOW 7.5 10 ns

tWH Width HIGH 7.5 10 ns

fMAX D-type 47 36 MHz

tSL Setup Time from Input, I/O, or Feedback to Gate 16 20.5 ns
tHL Latch Data Hold Time 0 0 ns

tGO Gate to Output (Note 3) 10 10 ns

tGWL Gate Width LOW 7.5 10 ns

tPDL Input, I/O, or Feedback to Output Through 20.5 26.5 ns

tSIR Input Register Setup Time 2.5 2.5 ns
tHIR Input Register Hold Time 3.5 4 ns

tICO Input Register Clock to Combinatorial Output 22 28 ns

tICS Input Register Clock to Output Register Setup 20.5 26.5 ns

tWICL Input Register LOW 7.5 10 ns
tWICH Clock Width HIGH 7.5 10 ns

fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) 66.5 50 MHz

tSIL Input Latch Setup Time 2.5 2.5 ns
tHIL Input Latch Hold Time 3.5 4 ns

tIGO Input Latch Gate to Combinatorial Output 24 30 ns

tIGOL Input Latch Gate to Output Through Transparent 26.5 32.5 ns

tSLL Setup Time from Input, I/O, or Feedback Through 18 23 ns

tIGS Input Latch Gate to Output Latch Setup 22 28 ns

tWIGL Input Latch Gate Width LOW 7.5 10 ns
tPDLL Input, I/O, or Feedback to Output Through Transparent 23 29 ns

Setup Time from Input, I/O,
or Feedback to Clock

D-type 40 32 MHz

Maximum
Frequency
(Note 1)

T-type 57 47 MHz

Transparent Input or Output Latch

Output Latch

Transparent Input Latch to Output Latch Gate

Input and Output Latches

External Feedback 1/(tS + tCO)

Internal Feedback (fCNT)

No Feedback 1/(tS + tH)

D-type 16 20.5 ns
T-type 17 22 ns

T-type 38 30.5 MHz

T-type 44 34.5 MHz
D-type 61.5 47 MHz

D-type
T-type

-18 -24

22 28 ns

32

MACH210AQ-18/24 (Ind)

AMD

SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)

(continued)

Parameter

Symbol Parameter Description Min Max Min Max Unit

tAR Asynchronous Reset to Registered or Latched Output 30 36 ns
tARW Asynchronous Reset Width (Note 1) 24 30 ns
tARR Asynchronous Reset Recovery Time (Note 1) 24 30 ns

tAP Asynchronous Preset to Registered or Latched Output 30 36 ns
tAPW Asynchronous Preset Width (Note 1) 24 30 ns

tAPR Asynchronous Preset Recovery Time (Note 1) 24 30 ns

tEA Input, I/O, or Feedback to Output Enable (Note 3) 18 24 ns

tER Input, I/O, or Feedback to Output Disable (Note 3) 18 24 ns

Notes:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.

2. See Switching Test Circuit, for test conditions.

3. Parameters measured with 16 outputs switching.

-18 -24

MACH210AQ-18/24 (Ind)

33

AMD

TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS

V

= 5.0 V, TA = 25°C

CC

(mA)

I

OL

80
60

40
20

–0.8 –0.6 –0.4 .2–0.2–1.0

–20

–40

–60

.4 .6 1.0.8

V

(V)

OL

–3 –2 –1

–100
–125

–150

Output, HIGH

–80

Output, LOW

IOH (mA)

25

–25
–50

–75

I

20

(mA)

I

123

45

14128I-5

V

(V)

OH

14128I-6

–2 –1

123

–20
–40

–60
–80

–100

Input

34 MACH210-7/10/12/15/20, Q-12/15/20

45

(V)

V

I

14128I-7

TYPICAL ICC CHARACTERISTICS

VCC = 5 V, TA = 25°C

150

125

100

75

ICC (mA)

AMD

MACH210A

MACH210

MACH210AQ

50

25

0

0 10203040 506070 8090100

Frequency (MHz)

14128I-8

The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of
being loaded, enabled, and reset.

Maximum frequency shown uses internal feedback and a D-type register.

MACH210-7/10/12/15/20, Q-12/15/20

35

AMD

TYPICAL THERMAL CHARACTERISTICS

Measured at 25°C ambient. These parameters are not tested.

Parameter
Symbol Parameter Description TQFP PLCC Unit

θ

jc

Thermal impedance, junction to case 11.3 15 °C/W

Typ

θ

ja

θ

jma

Thermal impedance, junction to ambient 41 40 °C/W
Thermal impedance, junction to 200 lfpm air 35 36 °C/W

ambient with air flow

400 lfpm air 33.7 33 °C/W
600 lfpm air 32.6 31 °C/W
800 lfpm air 32 29 °C/W

Plastic θjc Considerations

The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The

θ

heat-flow paths in plastic-encapsulated devices are complex, making the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the
package. Furthermore,

θ

jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a

constant temperature. Therefore, the measurements can only be used in a similar environment.

jc measurement relative to a specific location on the

36 MACH210-7/10/12/15/20, Q-12/15/20

SWITCHING WAVEFORMS

AMD

Input, I/O,

or Feed-

back

Clock

Registered

Output

Input, I/O, or

Feedback

Combinatorial

Output

t

S

V

Registered Output

V

T

t

PD

V

T

14128I-9

Combinatorial Output

T

Input, I/O, or

Feedback

Gate

Latched

Out

t

PDL

V

T

t

H

T

t

CO

V

14128I-10

V

T

t

t

HL

SL

V

T

t

GO

V

T

14128I-11

Latched Output (MACH 2, 3, and 4)

t

WH

Clock

Clock Width

Registered

Input

t

SIR

Input

Register

Clock

Combinatorial

Output

Registered Input (MACH 2 and 4)

Notes:

= 1.5 V.

1. V

T

2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2 ns–4 ns typical.

t

WL

V

T

t

ICO

14128I-12

Gate

t

GWS

V

T

14128I-13

Gate Width (MACH 2, 3, and 4)

V

t

T

HIR

Registered

Input

V

T

Input

Register

V

T

Clock

t

V

T

Output

Register

14128I-14 14128I-15

Clock

ICS

V

T

Input Register to Output Register Setup

(MACH 2 and 4)

37MACH210-7/10/12/15/20, Q-12/15/20

AMD

SWITCHING WAVEFORMS

Latched

Combinatorial

In

Latched

Gate

Output

V

In

t

SIL

T

t

HIL

V

T

t

IGO

V

T

14128I-16

Latched Input (MACH 2 and 4)

t

PDLL

V

T

Latched

Out

t

Input

IGOL

Latch Gate

t

IGS

Output

Latch Gate

Notes:

1. VT = 1.5 V.

2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2 ns–4 ns typical.

Latched Input and Output

(MACH 2, 3, and 4)

V

T

t

SLL

V

T

14128I-17

MACH210-7/10/12/15/20, Q-12/15/2038

SWITCHING WAVEFORMS

t

WICH

Clock

Input Register Clock Width

(MACH 2 and 4)

t

WICL

V

T

14128I-18

Input

Latch

Gate

t

WIGL

Input Latch Gate Width

(MACH 2 and 4)

AMD

V

T

14128I-19

Input, I/O, or

Feedback

Registered

Output

Clock

t

ARW

t

AR

V

T

Asynchronous Reset

Input, I/O, or

Feedback

Outputs

V

T

t

ARR

V

T

14128I-20

t

ER

Input, I/O,

or Feedback

Registered

Output

Clock

V

- 0.5V

OH

+ 0.5V

V

OL

t

APW

V

T

t

AP

V

T

t

APR

V

T

14128I-21

Asynchronous Preset

V

T

t

EA

V

T

Notes:

= 1.5 V.

1. V

T

2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2 ns–4 ns typical.

14128I-22

Output Disable/Enable

39MACH210-7/10/12/15/20, Q-12/15/20

AMD

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

SWITCHING TEST CIRCUIT

Must be
Steady

May
Change
from H to L

May
Change
from L to H

Don’t Care,
Any Change
Permitted

Does Not
Apply

5 V

Will be
Steady

Will be
Changing
from H to L

Will be
Changing
from L to H

Changing,
State
Unknown

Center
Line is High­Impedance
“Off” State

KS000010-PAL

S

1

R

1

Specification S

, t

t

PD

CO

t

EA

Output

R

2

Commercial

1

C

L

R

1

Closed 1.5 V
Z → H: Open 35 pF 1.5 V

C

L

Test Point

R

2

14128I-23

Measured

Output Value

Z → L: Closed 300 Ω 390 Ω

t

ER

H →Z: Open 5 pF H → Z: VOH – 0.5 V
L →Z: Closed L →Z: V

*Switching several outputs simultaneously should be avoided for accurate measurement.

+ 0.5 V

OL

MACH210-7/10/12/15/20, Q-12/15/2040

f

PARAMETERS

MAX

The parameter f

is the maximum clock rate at which

MAX

the device is guaranteed to operate. Because the flexi­bility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, f

is specified for

MAX

three types of synchronous designs.
The first type of design is a state machine with feedback

signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the in­put setup time for the external signals (t
ciprocal, f

, is the maximum frequency with external

MAX

+ tCO). The re-

S

feedback or in conjunction with an equivalent speed de­vice. This f

is designated “f

MAX

external.”

MAX

The second type of design is a single-chip state ma­chine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop out­puts. Under these conditions, the period is limited by the
internal delay from the flip-flop outputs through the inter­nal feedback and logic to the flip-flop inputs. This f
designated “f

internal”. A simple internal counter is a

MAX

MAX

is

good example of this type of design; therefore, this pa­rameter is sometimes called “f

CNT.

”

AMD

The third type of design is a simple data path applica­tion. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (t
a lower limit for the period of each f
mum clock period (t

+ tWL). Usually, this minimum

WH

clock period determines the period for the third f
ignated “f

no feedback.”

MAX

For devices with input registers, one additional f
rameter is specified: f

. Because this involves no

MAXIR

feedback, it is calculated the same way as f

+ tH). However,

S

type is the mini-

MAX

MAX

no feed-

MAX

, des-

MAX

pa-

back. The minimum period will be limited either by the

+ t

sum of the setup and hold times (t
the clock widths (t

WICL

+ t

WICH

SIR

). The clock widths are nor­mally the limiting parameters, so that f
as 1/(t

WICL

+ t

). Note that if both input and output reg-

WICH

) or the sum of

HIR

is specified

MAXIR

isters are use in the same path, the overall frequency will
be limited by t

All frequencies except f
other measured AC parameters. f

ICS

.

internal are calculated from

MAX

internal is meas-

MAX

ured directly.

CLK

(SECOND

CHIP)

LOGIC REGISTER

tt

SCO

f

External; 1/(tS + tCO)

MAX

t

S

CLK

LOGIC REGISTER

CLK

LOGIC REGISTER

f

Internal (f

MAX

CNT

)

CLK

REGISTER

LOGIC

t

S

f

No Feedback; 1/(tS + tH) or 1/(tWH + tWL)

MAX

t

SIR

f

MAXIR

t

HIR

; 1/(t

SIR

+ t

HIR

) or 1/(t

WICL

+ t

WICH

14128I-24

)

41MACH210-7/10/12/15/20, Q-12/15/20

AMD

ENDURANCE CHARACTERISTICS

The MACH families are manufactured using AMD’s
advanced Electrically Erasable process. This technol­ogy uses an EE cell to replace the fuse link used in

bipolar parts. As a result, the device can be erased and
reprogrammed, a feature which allows 100% testing at
the factory.

Endurance Characteristics

Parameter

Symbol Parameter Description Min Units Test Conditions

10 Years Max Storage

Temperature

t

DR

N Max Reprogramming Cycles 100 Cycles Normal Programming

Min Pattern Data Retention Time

20 Years Max Operating

Temperature

Conditions

MACH210-7/10/12/15/20, Q-12/15/2042

INPUT/OUTPUT EQUIVALENT SCHEMATICS

1 kΩ

ESD

Protection

Input

AMD

V

CC

100 kΩ

V

CC

V

CC

Preload

Circuitry

100 kΩ

Feedback

Input

I/O

V

CC

1 kΩ

14128I-25

43MACH210-7/10/12/15/20, Q-12/15/20

AMD

POWER-UP RESET

The MACH devices have been designed with the capa­bility to reset during system power-up. Following power­up, all flip-flops will be reset to LOW. The output state

wide range of ways V
conditions are required to insure a valid power-up reset.
These conditions are:

will depend on the logic polarity. This feature provides
extra flexibility to the designer and is especially valuable
in simplifying state machine initialization. A timing dia­gram and parameter table are shown below. Due to the
synchronous operation of the power-up reset and the

Parameter
Symbol Parameter Descriptions Max Unit

1. The V

2. Following reset, the clock input must not be driven

from LOW to HIGH until all applicable input and
feedback setup times are met.

rise must be monotonic.

CC

can rise to its steady state, two

CC

t

PR

t

S

t

WL

Registered

Power

Output

Clock

Power-Up Reset Time 10 µs
Input or Feedback Setup Time
Clock Width LOW

4 V

t

PR

t

S

t

WL

See
Switching
Characteristics

V

CC

14128I-26

Power-Up Reset Waveform

MACH210-7/10/12/15/20, Q-12/15/2044

USING PRELOAD AND OBSERVABILITY

In order to be testable, a circuit must be both controllable
and observable. To achieve this, the MACH devices
incorporate register preload and observability.

In preload mode, each flip-flop in the MACH device can
be loaded from the I/O pins, in order to perform
functional testing of complex state machines. Register
preload makes it possible to run a series of tests from a
known starting state, or to load illegal states and test for
proper recovery. This ability to control the MACH
device’s internal state can shorten test sequences,
since it is easier to reach the state of interest.

The observability function makes it possible to see the
internal state of the buried registers during test by
overriding each register’s output enable and activating
the output buffer. The values stored in output and buried
registers can then be observed on the I/O pins. Without
this feature, a thorough functional test would be
impossible for any designs with buried registers.

While the implementation of the testability features is
fairly straightforward, care must be taken in certain
instances to insure valid testing.

Preloaded

HIGH

DQQ

1

AR

Preloaded

HIGH

Q

D

2

Q

AR

AMD

One case involves asynchronous reset and preset. If the
MACH registers drive asynchronous reset or preset
lines and are preloaded in such a way that reset or
preset are asserted, the reset or preset may remove the
preloaded data. This is illustrated in Figure 2. Care
should be taken when planning functional tests, so that
states that will cause unexpected resets and presets are
not preloaded.

Another case to be aware of arises in testing combinato­rial logic. When an output is configured as combinato­rial, the observability feature forces the output into
registered mode. When this happens, all product terms
are forced to zero, which eliminates all combinatorial
data. For a straight combinatorial output, the correct
value will be restored after the preload or observe
function, and there will be no problem. If the function
implements a combinatorial latch, however, it relies on
feedback to hold the correct value, as shown in Figure 3.
As this value may change during the preload or observe
operation, you cannot count on the data being correct
after the operation. To insure valid testing in these
cases, outputs that are combinatorial latches should not
be tested immediately following a preload or observe
sequence, but should first be restored to a known state.

Preload

Mode

Q

1

AR

Q

2

Set

On

Off

Figure 2. Preload/Reset Conflict

14128I-27

All MACH 2 devices support both preload and
observability.

Contact individual programming vendors in order to
verify programmer support.

Reset

Figure 3. Combinatorial Latch

14128I-28

45MACH210-7/10/12/15/20, Q-12/15/20

AMD

DEVELOPMENT SYSTEMS (subject to change)

For more information on the products listed below, please consult the AMD FusionPLD Catalog.

MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS

Advanced Micro Devices, Inc.
P.O. Box 3453, MS 1028
Sunnyvale, CA 94088-3543
[phone] or [phone]

Advanced Micro Devices, Inc.
P.O. Box 3453, MS 1028
Sunnyvale, CA 94088-3543
[phone] or [phone]

Advanced Micro Devices, Inc.
P.O. Box 3453, MS 1028
Sunnyvale, CA 94088-3543
[phone] or [phone]

Advanced Micro Devices, Inc.
P.O. Box 3453, MS 1028
Sunnyvale, CA 94088-3543
[phone] or [phone]

Cadence Design Systems
555 River Oaks Pkwy
San Jose, CA 95134
[phone]

Capilano Computing
960 Quayside Dr., Suite 406
New Westminster, B.C.
Canada V3M 6G2
[phone] or [phone]

MACHXL Software

Ver. 2.0

Design Center/AMD

Software

AMD-ABEL Software

Data I/O MACH Fitters

PROdeveloper/AMD

Software

PROsynthesis/AMD Software

TM

ComposerPIC

Designer

(Requires MACH Fitter)

Verilog, LeapFrog, RapidSim Simulators

(Models also available from Logic Modeling)

Ver. 3.3

MacABEL

TM

Software

(Requires SmartPart MACH Fitter)

CINA, Inc.
P.O. Box 4872
Mountain View, CA 94040
[phone]

Data I/O Corporation
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
[phone] or [phone]

iNt GmbH
Busenstrasse 6
D-8033 Martinsried, Munich, Germany
(89) 857-6667

ISDATA GmbH
Daimlerstr. 51
D7500 Karlsruhe 21 Germany
Germany: 0721/75 10 87
U.S.: [phone]

Logic Modeling
19500 NW Gibbs Dr.
P.O. Box 310
Beaverton, OR 97075
[phone]

Logical Devices, Inc.
692 S. Military Trail
Deerfield Beach, FL 33442
[phone] or [phone]

SmartCAT Circuit Analyzer

TM

-5 Software

ABEL

(Requires MACH Fitter)

TM

Synario

Software

PLDSim 90

LOG/iCTM Software

(Requires MACH Fitter)

SmartModelLibrary

CUPLTM Software

MACH210-7/10/12/15/20, Q-12/15/2046

DEVELOPMENT SYSTEMS (subject to change) (continued)

MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS

Mentor Graphics Corp.
8005 S.W. Boeckman Rd.
Wilsonville, OR 97070-7777
[phone] or [phone]

PLDSynthesis

(Requires MACH Fitter)

QuickSim Simulator

(Models also available from Logic Modeling)

TM

AMD

MicroSim Corp.
20 Fairbanks
Irvine, CA 92718
[phone]

MINC Incorporated
6755 Earl Drive, Suite 200
Colorado Springs, CO 80918
(800) 755-FPGA or [phone]

OrCAD
3175 N.W. Aloclek Dr.
Hillsboro, OR 97124
[phone]

SUSIE–CAD
10000 Nevada Highway, Suite 201
Boulder City, NV 89005
[phone]

Teradyne EDA
321 Harrison Ave.
Boston, MA 02118
[phone] or [phone]

Viewlogic Systems, Inc.
293 Boston Post Road West
Marlboro, MA 01752
[phone] or [phone]

Design Center Software

(Requires MACH Fitter)

PLDesignerTM-XL Software

(Requires MACH Fitter)

Programmable Logic Design Tools 386+

Schematic Design Tool 386+

Digital Simulation Tools

TM

SUSIE

MultiSIM Interactive Simulator

ViewPLD or PROPLD

(Requires PROSim Simulator MACH Fitter)

ViewSim Simulator

(Models for ViewSim also available

from Logic Modeling)

Simulator

LASAR

MANUFACTURER TEST GENERATION SYSTEM

Acugen Software, Inc.
427-3 Amherst St., Suite 391
Nashua, NH 03063
[phone]

iNt GmbH
Busenstrasse 6
D-8033 Martinsried, Munich, Germany
(87) 857-6667

Advanced Micro Devices is not responsible for any information relating to the products of third parties. The inclusion of such information is not a representation nor
an endorsement by AMD of these products.

ATGENTM Test Generation Software

PLDCheck 90

47MACH210-7/10/12/15/20, Q-12/15/20

AMD

APPROVED PROGRAMMERS (subject to change)

For more information on the products listed below, please consult the AMD FusionPLD Catalog.

MANUFACTURER PROGRAMMER CONFIGURATION

Advin Systems, Inc.
1050-L East Duane Ave.
Sunnyvale, CA 94086
[phone]

BP Microsystems
100 N. Post Oak Rd.
Houston, TX 77055-7237
[phone] or [phone]

Data I/O Corporation
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
[phone] or [phone]

Logical Devices Inc./Digelec
692 S. Military Trail
Deerfield Beach, FL 33442
[phone] or [phone]

SMS North America, Inc.
16522 NE 135th Place
Redmond, WA 98052
[phone]
or
SMS
lm Grund 15
D-7988 Vangen Im Allgau, Germany
07522-5018

UniSite

TM

Pilot U84

BP1200

Model 3900

ALLPROTM–88

Sprint/Expert

AutoSite

Stag Microsystems Inc.
1600 Wyatt Dr. Suite 3
Santa Clara, CA 95054
[phone]
or
Stag House
Martinfield, Welwyn Garden City
Herfordshire UK AL7 1JT
707-332148

System General
510 S. Park Victoria Dr.
Milpitas, CA 95035
[phone]
or
3F, No. 1, Alley 8, Lane 45
Bao Shing Rd., Shin Diau
Taipei, Taiwan
2-917-3005

Stag Quazar

Turpro-1

APPROVED ON-BOARD PROGRAMMERS

MANUFACTURER PROGRAMMER CONFIGURATION

Corelis, Inc.
12607 Hidden Creek Way, Suite H
Cerritos, California 70703
[phone]

Advanced Micro Devices
P.O. Box 3453, MS-1028
Sunnyvale, CA 94088-3453
[phone]

JTAG PROG

MACHpro

MACH210-7/10/12/15/20, Q-12/15/2048

PROGRAMMER SOCKET ADAPTERS (subject to change)

MANUFACTURER PART NUMBER

EDI Corporation
P.O. Box 366
Patterson, CA 95363
[phone]

Emulation Technology
2344 Walsh Ave., Bldg. F
Santa Clara, CA 95051
[phone]

Logical Systems Corp.
P.O. Box 6184
Syracuse, NY 13217-6184
[phone]

Procon Technologies, Inc.
1333 Lawrence Expwy, Suite 207
Santa Clara, CA 95051
[phone]

Contact Manufacturer

Contact Manufacturer

Contact Manufacturer

Contact Manufacturer

AMD

49MACH210-7/10/12/15/20, Q-12/15/20

AMD

PHYSICAL DIMENSIONS*
PL 044

44-Pin Plastic Leaded Chip Carrier (measured in inches)

.685
.695

.650
.656

.042
.056

.062
.083

.685
.695

.650
.656

.026
.032

Pin 1 I.D.

TOP VIEW

.050 REF

.009
.015

.090
.120

.165
.180

SIDE VIEW

.590

.500

.630

REF

.013
.021

SEATING PLANE

16-038-SQ
PL 044
DA78
6-28-94 ae

MACH210-7/10/12/15/20, Q-12/15/2050

PHYSICAL DIMENSIONS*
PQT044

44-Pin Thin Quad Flat Pack (measured in millimeters)

44

1

9.80

10.20

11.80

12.20

AMD

11.80

12.20

9.80

10.20

11° – 13°

0.95

1.05

1.00 REF.

0.30

0.45

0.80 BSC

1.20 MAX

11° – 13°

16-038-PQT-2_AH
PQT 44
5-4-95 ae


*For reference only. BSC is an ANSI standard for Basic Space Centering.

Trademarks

Copyright  1995 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, MACH, and PAL are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

51MACH210-7/10/12/15/20, Q-12/15/20