AMD MACH111-18JI, MACH111-7JI, MACH111-5JC, MACH111-10JC, MACH111-12VC Datasheet

FINAL

MACH

®

111-5/7/10/12/15

COM’L: -5/7/10/12/15 IND: -7/10/12/14/18

High-Performance EE CMOS Programmable Logic

DISTINCTIVE CHARACTERISTICS

44 Pins in PLCC and TQFP

◆

32 Macrocells

◆

5 ns t

◆

182 MHz f

◆

32 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs

◆

32 Flip-flops; 4 clock choices

◆

2 “PALCE26V16” blocks

◆

SpeedLocking™ for guaranteed fixed timing

◆

Bus-Friendly™ Inputs and I/Os

◆

Peripheral Component Interconnect (PCI) compliant (-5/-7/-10/-12)

◆

Programmable power-down mode

◆

Safe for mixed supply voltage system designs

◆

Pin-compatible with the MACH211

◆

Commercial, 7.5 ns t

PD

CNT

Industrial

PD

GENERAL DESCRIPTION

The MACH111 is a member of Vantis’ high-performance EE CMOS MACH 1 & 2 families. This
device has approximately three times the logic macrocell capability of the popular P ALCE22V10
without loss of speed.

The MACH111 consists of two PAL
The two PAL blocks are essentially “PALCE26V16” structures complete with product-term arrays
and programmable macrocells, which can be programmed as high speed or low power. The
switch matrix connects the PAL blocks to each other and to all input pins, providing a high
degree of connectivity between the fully connected P AL blocks. This allows designs to be placed
and routed efficiently.

The MACH111 macrocell provides either registered or combinatorial outputs with programmable
polarity. If a registered configuration is chosen, the register can be configured as D-type or T­type to help reduce the number of product terms. The register type decision can be made by
the designer or by the software. All macrocells can be connected to an I/O cell. If a buried
macrocell is desired, the internal feedback path from the macrocell can be used, which frees up
the I/O pin for use as an input.

Vantis offers software design support for MACH devices through its own development system
and device fitters integrated into third-party CAE tools. Platform support extends across PCs,
Sun and HP workstations under advanced operating systems such as Windows 3.1, Windows 95
and NT, SunOS and Solaris, and HPUX.

®

blocks interconnected by a programmable switch matrix.

Publication# 20420 Rev: B
Amendment/+1 Issue Date: June 1998

MACHXL

®

software is a complete development system for the PC, supporting Vantis' MACH
devices. It supports design entry with Boolean and behavioral syntax, state machine syntax and
truth tables. Functional simulation and static timing analysis are also included in this easy-to­use system. This development system includes high-performance device fitters for all MACH
devices.

The same fitter technology included in MACHXL software is seamlessly incorporated into third-party
tools from leading CAE vendors such as Synario, Viewlogic, Mentor Graphics, Cadence and MINC.
Interface kits and MACHXL configurations are also available to support design entry and verification
with other leading vendors such as Synopsys, Exemplar, OrCAD, Synplicity and Model T echnology.
These MACHXL configurations and interfaces accept EDIF 2.0.0 netlists, generate JEDEC files for
MACH devices, and create industry-standard SDF , VIT AL-compliant VHDL and V erilog output files for
design simulation.

®

Vantis offers in-system programming support for MACH devices through its MACHPRO
software enabling MACH device programmability through JT AG compliant ports and easy-to-use
PC interface. Additionally, MACHPRO generated vectors work seamlessly with HP3070, GenRad
and Teradyne testers to program MACH devices or test them for connectivity.

All MACH devices are supported by industry standard programmers available from a number of
vendors. These programmer vendors include Advin Systems, BP Microsystems, Data I/O
Corporation, Hi-Lo Systems, SMS GmbH, Stag House, and System General.

2 MACH111-5/7/10/12/15

BLOCK DIAGRAM

Block A

I/O0 – I/O

I0-I1/CLK

15

I3-I4/CLK

0
2

4

OE

AND Logic Array

Logic Allocator

AND Logic Array

Logic Allocator

OE

16

I/O Cells

16

Macrocells

52 x 70

and

26

Switch Matrix

26

52 x 70

and

16

16

4

2

2

4

4

Macrocells

16

I/O Cells

16

I/O16 – I/O

Block B

16

16

31

4

2

CLK3/I
CLK1/I

5
2

20420B-1

MACH111-5/7/10/12/15 3

CONNECTION DIAGRAM

Top View

I/O4

I/O3

I/O2

I/O1

44-Pin PLCC

I/O0

GND

VCC

I/O31

I/O30

I/O29

I/O28

5

641

I/O5
I/O6
I/O7

CLK0/I1

Block A

Note:

Pin-compatible with the MACH211SP and MACH211.

GND

CLK1/I2

I/O8

I/O9
I/O10
I/O11

7
8

9

10

I0

11
12

13
14

15

16

17

19

18 27

I/O12

I/O13

PIN DESIGNATIONS

4

20

3

21

I/O14

2

22

I/O15

VCC

1

23

44

24

GND

43

25

I/O16

42

26

I/O17

I/O18

40

28

I/O19

39
38

37

36

35

34
33

32
31
30

29

I/O20

I/O27
I/O26
I/O25
I/O24
CLK3/I5
GND
CLK2/I4
I3
I/O23
I/O22
I/O21

Block B

20420B-2

CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
V

= Supply Voltage

CC

4 MACH111-5/7/10/12/15

CONNECTION DIAGRAM

Top View

I/O4

44-Pin TQFP

I/O3

I/O2

I/O1

I/O0

GND

VCC

I/O31

I/O30

I/O29

I/O28

I/O5
I/O6
I/O7

I0

CLK0/I1

GND

Block A

Note:

Pin-compatible with the MACH211SP.

CLK1/I2

I/O8

I/O9
I/O10
I/O11

PIN DESIGNATIONS

4443424140

1
2
3
4
5

6
7
8
9
10

11

1213141516

I/O12

I/O13

I/O14

VCC

I/O15

39

17

GND

38

373635

18

192021

I/O16

I/O17

I/O18

I/O19

34

33
32
31
30
29
28
27
26
25
24
23

22

I/O20

I/O27
I/O26
I/O25
I/O24
CLK3/I5
GND
CLK2/I4
I3
I/O23
I/O22
I/O21

Block B

20420B-3

CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
V

= Supply Voltage

CC

MACH111-5/7/10/12/15 5

ORDERING INFORMATION

Commercial Products

Vantis programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:

MACH 111 -5 J C

FAMILY TYPE

MACH = Macro Array CMOS High-Speed

DEVICE NUMBER

111 = 32 Macrocells, 44 Pins,

Power-Down option,
Bus-Friendly Inputs

SPEED

-5 = 5 ns t

-7 = 7.5 ns t

-10 = 10 ns t

-12 = 12 ns t

-15 = 15 ns t

PD

PD
PD
PD
PD

Valid Combinations

MACH111-5
MACH111-7
MACH111-10
MACH111-12
MACH111-15

JC, VC

OPERATING CONDITIONS

C = Commercial (0°C to +70°C)

PACKAGE TYPE

J = 44-Pin Plastic Leaded Chip

Carrier (PL 044)

V = 44-Pin Thin Quad Flat Pack

(PQT044)

Valid Combinations

The Valid Combinations table lists configurations planned to
be supported in volume for this device. Consult the local
Vantis sales office to confirm availability of specific valid
combinations and to check on newly released combinations.

6 MACH111-5/7/10/12/15 (Com’l)

ORDERING INFORMATION

Industrial Products

Vantis programmable logic products for industrial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:

MACH 111 -7 J I

FAMILY TYPE

MACH = Macro Array CMOS High-Speed

DEVICE NUMBER

111 = 32 Macrocells, 44 Pins,

Power-Down option,
Bus-Friendly Inputs

SPEED

-7 = 7.5 ns t

-10 = 10 ns t

-12 = 12 ns t

-14 = 14 ns t

-18 = 18 ns t

PD

PD
PD
PD
PD

Valid Combinations

MACH111-7
MACH111-10
MACH111-12
MACH111-14
MACH111-18

OPERATING CONDITIONS

I = Industrial (–40

PACKAGE TYPE

J = 44-Pin Plastic Leaded Chip

Carrier (PL 044)

Valid Combinations

The Valid Combinations table lists configurations planned to
be supported in volume for this device. Consult the local
Vantis sales office to confirm availability of specific valid
combinations and to check on newly released combinations.

JI

°C to +85°C)

MACH111-7/10/12/14/18 (Ind) 7

FUNCTIONAL DESCRIPTION

The MACH111 consists of two PAL blocks connected by a switch matrix. There are 32 I/O pins
and 2 dedicated input pins feeding the switch matrix. These signals are distributed to the two
PAL blocks for efficient design implementation. There are four clock pins that can also be used
as dedicated inputs.

The PAL Blocks

Each PAL block in the MACH111 (Figure 1) contains a 64-product-term logic array, a logic
allocator, 16 macrocells, and 16 I/O cells. The switch matrix feeds each PAL block with 26 inputs.
This makes the PAL block look effectively like an independent “PALCE26V16.”

There are four additional output enable product terms in each P AL block. For purposes of output
enable, the 16 I/O cells are divided into 2 banks of 8 macrocells. Each bank is allocated two of
the output enable product terms.

An asynchronous reset product term and an asynchronous preset product term are provided for
flip-flop initialization. All flip-flops within the PAL block are initialized together.

The Switch Matrix

The MACH111 switch matrix is fed by the inputs and feedback signals from the P AL blocks. Each
P AL block provides 16 internal feedback signals and 16 I/O feedback signals. The switch matrix
distributes these signals back to the P AL blocks in an efficient manner that also provides for high
performance. The design software automatically configures the switch matrix when fitting a
design into the device.

The Product-term Array

The MACH111 product-term array consists of 64 product terms for logic use, and 6
special-purpose product terms. Four of the special-purpose product terms provide
programmable output enable; one provides asynchronous reset, and one provides asynchronous
preset. Two of the output enable product terms are used for the first eight I/O cells; the other
two control the last eight macrocells.

The Logic Allocator

The logic allocator in the MACH111 takes the 64 logic product terms and allocates them to the
16 macrocells as needed. Each macrocell can be driven by up to 12 product terms. The design
software automatically configures the logic allocator when fitting the design into the device.

Table 1 illustrates which product term clusters are available to each macrocell within a PAL
block. Refer to Figure 1 for cluster and macrocell numbers.

Table 1. Logic Allocation

Output Macrocell Available Clusters Output Macrocell Available Clusters

M

0

M

1

M

2

M

3

M

4

M

5

M

6

M

7

C

, C

0

C

, C

, C

0

1

C1, C2, C
C2, C3, C
C3, C4, C
C4, C5, C
C5, C6, C

C6, C

1

2
3
4
5
6
7

7

M

8

M

9

M

10

M

11

M

12

M

13

M

14

M

15

C

, C

8

9

, C9, C

C

8

C9, C10, C
C10, C11, C
C11, C12, C
C12, C13, C
C13, C14, C

C14, C

15

10

11

12
13
14
15

8 MACH111-5/7/10/12/15

The Macrocell

The MACH111 macrocells can be configured as either registered or combinatorial, with
programmable polarity. The macrocell provides internal feedback whether configured as
registered or combinatorial. The flip-flops can be configured as D-type or T-type, allowing for
product-term optimization.

The flip-flops can individually select one of four clock pins, which are also available as data inputs.
The registers are clocked on the LOW-to-HIGH transition of the clock signal. The flip-flops can also
be asynchronously initialized with the common asynchronous reset and preset product terms.

The I/O Cell

The I/O cell in the MACH111 consists of a three-state output buffer. The three-state buffer can
be configured in one of three ways: always enabled, always disabled, or controlled by a product
term. If product term control is chosen, one of two product terms may be used to provide the
control. The two product terms that are available are common to eight I/O cells. Within each
PAL block, two product terms are available for selection by the first eight three-state outputs;
two other product terms are available for selection by the last eight three-state outputs.

SpeedLocking for Guaranteed Fixed Timing

The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in
both raw speed, but even more importantly, guaranteed fixed speed. Using the design of the
central switch matrix, the MACH111 product offers the SpeedLocking feature, which allows a
stable fixed pin-to-pin delay, independent of logic paths, routing resources and design refits for
up to 12 product terms per output. Other non-Vantis CPLDs incur serious timing delays as
product terms expand beyond their typical 4 or 5 product-term limits. Speed and SpeedLocking
combine for continuous, high performance required in today's demanding designs.

Bus-Friendly Inputs and I/Os

The MACH111 inputs and I/Os include two inverters in series which loop back to the input. This
double inversion reinforces the state of the input and pulls the voltage away from the input
threshold voltage. Unlike a pull-up, this configuration cannot cause contention on a bus. For an
illustration of this configuration, please turn to the Input/Output Equivalent Schematics section.

PCI Compliant

The MACH111-5/7/10/12 is fully compliant with the PCI Local Bus Specification published by
the PCI Special Interest Group. The MACH111-5/7/10/12’s predictable timing ensures
compliance with the PCI AC specifications independent of the design.

Power-Down Mode

The MACH111 features a programmable low-power mode in which individual signal paths can be
programmed as low power. These low-power speed paths will be slightly slower than the
non-low-power paths. This feature allows speed critical paths to run at maximum frequency while
the rest of the paths operate in the low-power mode, resulting in power savings of up to 50%.

Safe for Mixed Supply Voltage System Designs

The MACH111 is safe for mixed supply voltage system designs. The 5-V device will not overdrive

3.3-V devices above the output voltage of 3.3 V , while it accepts inputs from other 3.3-V devices.
Thus, the MACH111 provides easy-to-use mixed-voltage design compatibility.

MACH111-5/7/10/12/15 9

0 4 8 12 16 20 24 28 40324336

47

51

Output Enable
Output Enable

Asynchronous Reset
Asynchronous Preset

Switch
Matrix

0

63

0 4 8 12 16 20 24 28 40324336

16

16

47

51

Figure 1. MACH111 PAL Block

M

M

M

M

C

0

M

C

1

C

2

M

C

3

C

4

M

C

5

C

6

M

C

7

C

Logic Allocator

8

M

8

C

9

C

10

M

C

11

C

12

M

C

10

13

C

14

C

M

15

11

M

12

M

13

M

14

M

15

Output Enable

Output Enable

I/O

Output

0

1

2

3

4

5

6

7

9

CLK

2

Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

20420B-4

10 MACH111-5/7/10/12/15

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature. . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –55°C to +125°C

Device Junction Temperature . . . . . . . . . . . . . +150°C

Supply Voltage with

Respect to Ground . . . . . . . . . . . . . . –0.5 V to +7.0 V

DC Input Voltage . . . . . . . . . . . .–0.5 V to VCC + 0.5 V

Commercial (C) Devices

Ambient Temperature (TA)

Operating in Free Air. . . . . . . . . . . . . . . 0°C to +70°C

Supply Voltage (VCC)

with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

DC Output or

I/O Pin Voltage. . . . . . . . . . . . . –0.5 V to V

+ 0.5 V

CC

Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V

Latchup Current (TA = 0°C to 70°C) . . . . . . . . . 200 mA

Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.

DC CHARACTERISTICS over COMMERCIAL operating ranges

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

V
V

V

V

I

I

OZH

I

OZL

I

I

I

OH

OL

IH

IL

SC

CC

Output HIGH Voltage IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL2.4 V
Output LOW Voltage IOL = 16 mA, VCC = Min, VIN = VIH or V

Input HIGH Voltage

IH

Input LOW Voltage

IL

Guaranteed Input Logical HIGH Voltage
for all Inputs (Note 1)

Guaranteed Input Logical LOW V oltage for
all Inputs (Note 1)

IL

2.0 V

Input HIGH Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA
Input LOW Current VIN = 0 V, V
Off-State Output Leakage Current

HIGH
Off-State Output Leakage Current

LOW
Output Short-Circuit Current V

V

= 5.25 V, V

OUT

V

= V

IN

V

= 0 V, V

OUT

V

= V

IN

= 0.5 V, VCC = Max (Note 3) –30 –160 mA

OUT

= Max (Note 2) –10 µA

CC

= Max

CC

or VIL (Note 2)

IH

= Max

CC

or VIL (Note 2)

IH

Supply Current (Static) VCC = 5 V, TA = 25°C, f = 0 MHz (Note 4) 40 mA
Supply Current (Active) VCC = 5 V, TA = 25°C, f = 1 MHz (Note 4) 45 mA

0.5 V

0.8 V

10 µA

–10 µA

Notes:

1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.

2. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

OZH

).

3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

4. Measured with a 16-bit up/down counter program in low-power mode. This pattern is programmed in each PAL block and is

capable of being enabled and reset.

MACH111-5/7/10/12/15 (Com’l) 11

CAPACITANCE (Note 1)

Parameter

Symbol Parameter Description Test Conditions Typ Unit

C

IN

C

OUT

Input Capacitance V
Output Capacitance V

= VCC –0.5 V

IN

= 2.0 V 8 pF

OUT

= 5.0 V, TA = 25°C

V

CC

f = 1 MHz

6pF

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)

Paramete
r Symbol Parameter Description

t

t
t

t

WH

f

MAX

t

t

ARW

t

ARR

t

t

APW

t

APR

t
t

t

t

LPS

t

LPCO

t

LPEA

Input, I/O, or Feedback to Combinatorial

PD

Output
Setup Time from Input, I/O, or

t

S

Feedback to Clock
Register Data Hold Time 0 0 0 0 0 ns

t

H

Clock to Output 3.5 5 6 8 10 ns

CO
WL

Clock Width

External

Feedback
Maximum
Frequency
(Note 1)

Internal Feedback

(f

CNT

No

Feedback
Asynchronous Reset to Registered Output 7.5 9.5 11 16 20 ns

AR

1/(t

+ tCO)

S

)

+ tWH) 200 166.7 100 83.3 83.3 MHz

1/(t

WL

Asynchronous Reset Width (Note 1) 4.5 5 7.5 12 15 ns
Asynchronous Reset Recovery Time 4.5 5 7.5 8 10 ns
Asynchronous Preset to Registered Output 7.5 9.5 11 16 20 ns

AP

Asynchronous Preset Width (Note 1) 4.5 5 7.5 12 15 ns
Asynchronous Preset Recovery Time

(Note 1)
Input, I/O, or Feedback to Output Enable 7.5 9.5 10 12 15 ns

EA

Input, I/O, or Feedback to Output Disable 7.5 9.5 10 12 15 ns

ER

tPD Increase for Powered-down Macrocell

LP

(Note 3)
tS Increase for Powered-down Macrocell

(Note 3)
tCO Increase for Powered-down Macrocell

(Note 3)
tEA Increase for Powered-down Macrocell

(Note 3)

-5 -7 -10 -12 -15
UnitMin Max Min Max Min Max Min Max Min Max

5 7.5 10 12 15 ns

D-type 3.5 5.5 6.5 7 10 ns
T-type 4 6.5 7.5 8 11 ns

LOW 2.5 3 5 6 6 ns
HIGH 2.5 3 5 6 6 ns
D-type 143 95 80 66.7 50 MHz
T-type 133 87 74 62.5 47.6 MHz
D-type 182 133 100 76.9 66.6 MHz
T-type 167 125 91 71.4 55.5 MHz

4.5 5 7.5 8 10 ns

10 10 10 10 10 ns

77777ns

33333ns

10 10 10 10 10 ns

Notes:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
frequency may be affected.

2. See Switching Test Circuit for test conditions.

3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.

12 MACH111-5/7/10/12/15 (Com’l)

ABSOLUTE MAXIMUM RATINGS

Storage Temperature. . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –55°C to +125°C

Device Junction Temperature . . . . . . . . . . . . . +150°C

Supply Voltage

with Respect to Ground . . . . . . . . . . –0.5 V to +7.0 V

DC Input Voltage . . . . . . . . . . . .–0.5 V to VCC + 0.5 V

OPERATING RANGES

Industrial (I) Devices

Temperature (TA)

Operating in Free Air. . . . . . . . . . . . . .–40°C to +85°C

Supply Voltage (VCC)

with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

DC Output

or I/O Pin Voltage. . . . . . . . . . . –0.5 V to V

+ 0.5 V

CC

Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V

Latchup Current (TA = –40°C to +85°C) . . . . . .200 mA

Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.

DC CHARACTERISTICS over INDUSTRIAL operating ranges

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

V
V

V

V

I

I

OZH

I

OZL

I

I

OH

IH

I

SC

CC

OL

IL

Output HIGH Voltage IOH = –3.2 mA, VCC = Min, VIN = VIH or V
Output LOW Voltage IOL = 16 mA, VCC = Min, VIN = VIH or V

Input HIGH Voltage

IH

Input LOW Voltage

IL

Guaranteed Input Logical HIGH Voltage for all
Inputs (Note 1)

Guaranteed Input Logical LOW Voltage for all
Inputs (Note 1)

IL

IL

Input HIGH Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA
Input LOW Current VIN = 0 V, V
Off-State Output Leakage

Current HIGH
Off-State Output Leakage

Current LOW
Output Short-Circuit

Current

V

= 5.25 V, V

OUT

V

= V

IN

V

= 0 V, V

OUT

V

= V

IN

V

= 0.5 V, VCC = Max (Note 3) –30 –160 mA

OUT

= Max (Note 2) –10 µA

CC

= Max

CC

or VIL (Note 2)

IH

= Max

CC

or VIL (Note 2)

IH

Supply Current (Static) VCC = 5 V, TA = 25°C, f = 0 MHz (Note 4) 40 mA
Supply Current (Active) V

= 5 V, TA = 25°C, f = 1 MHz (Note 4) 45 mA

CC

Notes:

1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.

2. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

OZH

).

3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.

= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

4. Measured with a 16-bit up/down counter program in low-power mode. This pattern is programmed in each PAL block and is
capable of being enabled and reset.

2.4 V

0.5 V

2.0 V

0.8 V

10 µA

–10 µA

MACH111-7/10/12/14/18 (Ind) 13

CAPACITANCE (Note 1)

Parameter

Symbol Parameter Description Test Conditions Typ Unit

C

IN

C

OUT

Input Capacitance V
Output Capacitance V

= VCC –0.5 V

IN

= 2.0 V 8 pF

OUT

= 5.0 V, TA = 25°C

V

CC

f = 1 MHz

6pF

SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)

Parameter

Symbol Parameter Description

t

PD

t

t

t

CO

t

WL

t

WH

f

MAX

t

AR

t

ARW

t

ARR

t

AP

t

APW

t

APR

t

EA

t

ER

t

t

LPS

t

LPCO

t

LPEA

Input, I/O, or Feedback to Combinatorial
Output

Setup Time from Input, I/O, or

S

Feedback to Clock
Register Data Hold Time 0 0 0 0 0 ns

H

Clock to Output 5 6 8 10 12 ns

Clock Width

Maximum
Frequency
(Note 1)

External
Feedback

Internal Feedback
(f

CNT

No
Feedback

1/(t

+ tCO)

S

)

1/(t

WL

Asynchronous Reset to Registered Output 9.5 11 16 19.5 24 ns
Asynchronous Reset Width (Note 1) 5 7.5 12 14.5 18 ns
Asynchronous Reset Recovery Time 5 7.5 8 10 12 ns
Asynchronous Preset to Registered Output 9.5 11 16 19.5 24 ns
Asynchronous Preset Width (Note 1) 5 7.5 12 14.5 18 ns
Asynchronous Preset Recovery Time 5 7.5 8 10 12 ns
Input, I/O, or Feedback to Output Enable

(Note 1)
Input, I/O, or Feedback to Output Disable

(Note 1)
tPD Increase for Powered-down Macrocell

LP

(Note 3)
tS Increase for Powered-down Macrocell

(Note 3)
tCO Increase for Powered-down Macrocell

(Note 3)
tEA Increase for Powered-down Macrocell

(Note 3)

-7 -10 -12 -14 -18
UnitMin Max Min Max Min Max Min Max Min Max

7.5 10 12 14 18 ns

D-type 5.5 6.5 7 8.5 12 ns
T-type 6.5 7.5 8 10 13.5 ns

LOW 3 5 6 6 7.5 ns
HIGH 3 5 6 6 7.5 ns
D-type 95 80 66.7 54 40 MHz
T-type 87 74 62.5 50 38 MHz
D-type 133 100 76.9 61.5 53 MHz
T-type 125 91 71.4 57 44 MHz

+ tWH) 166.7 100 83.3 83.3 61.5 MHz

9.5 10 12 14.5 18 ns

9.5 10 12 14.5 18 ns

10 10 10 10 10 ns

77777ns

33333ns

10 10 10 10 10 ns

Notes:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
frequency may be affected.

2. See Switching Test Circuit for test conditions.

3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.

14 MACH111-7/10/12/14/18 (Ind)

TYPICAL CURRENT vs. VOLTAGE (I-V) CHARACTERISTICS

VCC = 5.0 V, TA = 25°C

I

(mA)

OL

80
60

40
20

-0.8 -0.6 -0.4 .2-0.2-1.0 .4 .6 1.0.8

-3 -2 -1

-20

-40

-60

-80

Output, LOW

IOH (mA)

25

123

-25

45

V

(V)

OL

20420B-5

(V)

V

OH

-100

-125

-150

Output, HIGH

-2 -1

-100

-50

-75

20

-20

-40

-60

-80

I

(mA)

I

Input

123

45

20420B-6

(V)

V

I

20420B-7

MACH111-5/7/10/12/15 15

TYPICAL ICC CHARACTERISTICS

VCC = 5 V, TA = 25°C

150

125

100

75

(mA)

CC

I

50

High Speed

Low Power

25

0

0 102030405060708090

Frequency (MHz)

The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.

Maximum frequency shown uses internal feedback and a D-type register.

100 110 120 130 140

150

20420B-6

16 MACH111-5/7/10/12/15

TYPICAL THERMAL CHARACTERISTICS

Measured at 25°C ambient. These parameters are not tested.

Parameter

Symbol Parameter Description

θ

jc

θ

ja

Thermal impedance, junction to case 11 15 °C/W
Thermal impedance, junction to ambient 40 24 °C/W

Typ

UnitTQFP PLCC

200 lfpm air 35 18 °C/W

θ

jma

Thermal impedance, junction to ambient with air flow

400 lfpm air 33 17 °C/W
600 lfpm air 32 16 °C/W
800 lfpm air 31 15 °C/W

Plastic θjc Considerations

The data listed for plastic
heat-flow paths in plastic-encapsulated devices are complex, making the

θ

are for reference only and are not recommended for use in calculating junction temperatures. The

jc

θ

measurement relative to a specific location on the

jc

package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the
package. Furthermore,

θ

tests on packages are performed in a constant-temperature bath, keeping the package surface at a

jc

constant temperature. Therefore, the measurements can only be used in a similar environment. The thermal measurements are
taken with components on a six-layer printed circuit board.

SWITCHING WAVEFORMS

Input, I/O, or

Feedback

Combinatorial

Output

Combinatorial Output

V

T

t

PD

V

T

20420B-7

Input, I/O, or

Feedback

t

S

Clock

Registered

Output

Registered Output Clock Width

Notes:

1. VT = 1.5 V.

2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2 ns–4 ns typical.

V

T

t

H

V

T

t

CO

V

T

20420B-8 20420B-9

Clock

t

WH

t

WL

MACH111-5/7/10/12/15 17

SWITCHING WAVEFORMS

Input, I/O, or

Feedback

t

ARW

V

T

t

AR

Registered

Output

Clock

Input, I/O,

or Feedback

Registered

Output

Clock

Asynchronous Reset

t

APW

t

AP

Asynchronous Preset

V

T

t

ARR

V

T

20420B-10

V

T

V

T

t

APR

V

T

20420B-11

Input, I/O, or

Feedback

t

ER

V

– 0.5 V

Outputs

V

OH

OL

+ 0.5 V

Output Disable/Enable

Notes:

1. VT = 1.5 V.

2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2 ns–4 ns typical.

18 MACH111-5/7/10/12/15

V

T

t

EA

20420B-12

V

T

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

SWITCHING TEST CIRCUIT*

5 V

Must be
Steady

May
Change
from H to L

May
Change
from L to H

Don’t Care,
Any Change
Permitted

Does Not
Apply

Will be
Steady

Will be
Changing
from H to L

Will be
Changing
from L to H

Changing,
State
Unknown

Center
Line is High­Impedance
“Off” State

KS000010-PAL

S

1

R

1

Output

R

2

C

L

Test Point

Commercial

Specification S

tPD, t

t

t

CO

EA

ER

Closed
Z → H: Open

Z → L: Closed
H → Z: Open

L → Z: Closed

1

C

L

35 pF

5 pF

1

R

300 Ω 390 Ω

* Switching several outputs simultaneously should be avoided for accurate measurement.

20420B-13

2

Measured Output ValueR

1.5 V

H → Z: V

L → Z: V

– 0.5 V

OH

+ 0.5 V

OL

MACH111-5/7/10/12/15 19

f

PARAMETERS

MAX

The parameter f

is the maximum clock rate at which the device is guaranteed to operate.

MAX

Because the flexibility inherent in programmable logic devices offers a choice of clocked
flip-flop designs, f

is specified for three types of synchronous designs.

MAX

The first type of design is a state machine with feedback signals sent off-chip. This external
feedback could go back to the device inputs, or to a second device in a multi-chip state machine.
The slowest path defining the period is the sum of the clock-to-output time and the input setup
time for the external signals (t

+ tCO). The reciprocal, f

S

external feedback or in conjunction with an equivalent speed device. This f

external.”

“f

MAX

, is the maximum frequency with

MAX

is designated

MAX

The second type of design is a single-chip state machine with internal feedback only. In this
case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these
conditions, the period is limited by the internal delay from the flip-flop outputs through the
internal feedback and logic to the flip-flop inputs. This f

is designated “f

MAX

internal”. A

MAX

simple internal counter is a good example of this type of design; therefore, this parameter is
sometimes called “f

CNT.

”

The third type of design is a simple data path application. In this case, input data is presented to the
flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited
by the sum of the data setup time and the data hold time (t
of each f
determines the period for the third f

type is the minimum clock period (tWH + tWL). Usually, this minimum clock period

MAX

, designated “f

MAX

internal are calculated from other measured AC parameters. f

+ tH). However, a lower limit for the period

S

no feedback.” All frequencies except f

MAX

internal is measured directly.

MAX

MAX

LOGIC

t

S

f

External 1/(ts + tCO)

MAX

CLK

REGISTER

t

CO

No Feedback; 1/(ts + tH) or 1/(t

f

MAX

LOGIC

t

S

(SECOND

CHIP)

t

S f

CLK

REGISTER

WH + tWL

LOGIC

MAX

)

Internal (f

CLK

REGISTER

)

CNT

20420B-14

20 MACH111-5/7/10/12/15

ENDURANCE CHARACTERISTICS

The MACH families are manufactured using Vantis’ advanced Electrically Erasable process. This
technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device
can be erased and reprogrammed, a feature which allows 100% testing at the factory.

Endurance Characteristics

Parameter

Symbol Parameter Description Units Test Conditions

t

DR

Min Pattern Data Retention Time

N Max Reprogramming Cycles 100 Cycles Normal Programming Conditions

10 Years Max Storage Temperature
20 Years Max Operating Temperature

INPUT/OUTPUT EQUIVALENT SCHEMATICS

V

CC

100 kΩ

V

1 kΩ

ESD

Protection

CC

V

CC

Preload

Circuitry

Input

100 kΩ

Feedback

Input

I/O

V

CC

1 kΩ

20420B-15

MACH111-5/7/10/12/15 21

POWER-UP RESET

The MACH devices have been designed with the capability to reset during system power-up.
Following power-up, all flip-flops will be reset to LOW . The output state will depend on the logic
polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying
state machine initialization. A timing diagram and parameter table are shown below. Due to the
synchronous operation of the power-up reset and the wide range of ways V
state, two conditions are required to insure a valid power-up reset. These conditions are:

1. The VCC rise must be monotonic.

2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.

Parameter Symbol Parameter Descriptions Max Unit

t

PR

t

S

t

WL

Power

Power-Up Reset Time 10 µs
Input or Feedback Setup Time
Clock Width LOW

4 V

t

PR

See Switching Characteristics

can rise to its steady

CC

V

CC

Registered

Output

Clock

t

WL

Power-Up Reset Waveform

t

S

20420B-16

22 MACH111-5/7/10/12/15

DEVELOPMENT SYSTEMS (subject to change)

For more information on the products listed below, please consult the local Vantis sales office.

MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS

Vantis Corporation
P.O. Box 3755
920 DeGuigne Drive
Sunnyvale, CA 94088
[phone] or 1(888) 826-8472 (VANTIS2)
http://www.vantis.com

Aldec, Inc.
3 Sunset Way, Suite F
Henderson, NV 89014
[phone] or [phone]

Cadence Design Systems
555 River Oaks Pkwy
San Jose, CA 95134
[phone] or [phone]

Exemplar Logic, Inc.
815 Atlantic Avenue, Suite 105
Alameda, CA 94501
[phone]

Logic Modeling
19500 NW Gibbs Dr.
P.O. Box 310
Beaverton, OR 97075
[phone]

Mentor Graphics Corp.
8005 S.W. Boeckman Rd.
Wilsonville, OR 97070-7777
[phone] or [phone]

MicroSim Corp.
20 Fairbanks
Irvine, CA 92718
[phone]

MINC Inc.
6755 Earl Drive, Suite 200
Colorado Springs, CO 80918
(800) 755-FPGA or [phone]

Model Technology
8905 S.W. Nimbus Avenue, Suite 150
Beaverton, OR 97008
[phone]

OrCAD, Inc.
9300 S.W. Nimbus Avenue
Beaverton, OR 97008
[phone] or [phone]

®

Synario
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
[phone] or [phone]

Design Automation

Design Architect, PLDSynthesis™ II

Autologic II Synthesizer, QuickSim Simulator, QuickHDL Simulator

MACHXL Software

Vantis-ABEL Software

Vantis-Synario Software

ACTIVE-CAD

PIC Designer

Concept/Composer

Synergy

Leapfrog/Verilog-XL

Leonardo™

Galileo™

SmartModel

MicroSim Design Lab

PLogic, PLSyn

PLDesigner-XL™ Software

V-System/VHDL

OrCAD Express

Synario™ Software

®

ABEL™

Library

MACH111-5/7/10/12/15 23

MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS

Synopsys
700 E. Middlefield Rd.
Mountain View, CA 94040
[phone] or [phone]

Synplicity, Inc.
624 East Evelyn Ave.
Sunnyvale, CA 94086
[phone]

Teradyne EDA
321 Harrison Ave.
Boston, MA 02118
[phone] or [phone]

VeriBest, Inc.
6101 Lookout Road, Suite A
Boulder, CO 80301
[phone]

Viewlogic Systems, Inc.
293 Boston Post Road West
Marlboro, MA 01752
[phone] or [phone]

MANUFACTURER TEST GENERATION SYSTEM

Acugen Software, Inc.
427-3 Amherst St., Suite 391
Nashua, NH 03063
[phone]

iNt GmbH
Busenstrasse 6
D-8033 Martinsried, Munich, Germany
(87) 857-6667

Vantis is not responsible for any information relating to the products of third parties. The inclusion of such information is not a
representation nor an endorsement by Vantis of these products.

Speedwave Simulator, ViewSim Simulator, VCS Simulator

FPGA or Design Compiler

(Requires MINC PLDesigner-XL™)

VSS Simulator

Synplify

MultiSIM Interactive Simulator

LASAR

VeriBest PLD

Viewdraw, ViewPLD, Viewsynthesis

ATGEN™ Test Generation Software

PLDCheck 90

24 MACH111-5/7/10/12/15

APPROVED PROGRAMMERS (SUBJECT TO CHANGE)

For more information on the products listed below, please consult the local Vantis sales office.

MANUFACTURER PROGRAMMER CONFIGURATION

Advin Systems, Inc.
1050-L East Duane Ave.
Sunnyvale, CA 940 86
[phone] or [phone]
BBS [phone]
Fax [phone]

BP Microsystems
1000 N. Post Oak Rd., Suite 225
Houston, TX 77055-7237
[phone] or [phone]
BBS [phone]
Fax [phone]

Data I/O Corporation
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
[phone] or [phone]
BBS [phone]
Fax [phone]

Hi-Lo Systems
4F, No. 2, Sec. 5, Ming Shoh E. Road
Taipei, Taiwan
(886) 2-764-0215
Fax [phone]
or
Tribal Microsystems / Hi-Lo Systems
44388 South Grimmer Blvd.
Fremont, CA 94538
[phone]
BBS [phone]
Fax [phone]

SMS GmbH
Im Grund 15
88239 Wangen
Germany
(49) 7522-97280
Fax [phone]
or
SMS USA
544 Weddell Dr. Suite 12
Sunnyvale, CA 94089
[phone]

Stag House
Silver Court Watchmead, Welwyn Garden City
Herfordshire UK AL7 1LT
44-1-707-332148
Fax [phone]

UniSite™ Model 2900 Model 3900 AutoSite

Pilot-U40 Pilot-U84 MVP

BP1200 BP1400 BP2100 BP2200

ALL-07 FLEX-700

Sprint Expert Sprint Optima Multisite

Stag Quazar

MACH111-5/7/10/12/15 25

MANUFACTURER PROGRAMMER CONFIGURATION

System General
1603A South Main Street
Milpitas, CA 95035
[phone]
BBS [phone]
Fax [phone]
or
3F, No. 1, Alley 8, Lane 45
Bao Shing Road, Shin Diau
Taipei, Taiwan
(886) 2-917-3005
Fax [phone]

APPROVED ADAPTER MANUFACTURERS

MANUFACTURER PROGRAMMER CONFIGURATION

California Integration Coordinators, Inc.
656 Main Street
Placerville, CA 95667
[phone]
Fax [phone]

Emulation Technology, Inc.
2344 Walsh Ave., Bldg. F
Santa Clara, CA 95051
[phone]
Fax [phone]

Turpro-1 Turpro-1/FX Turpro-1/TX

MACH/PAL Programming Adapters

Adapt-A-Socket

Programming Adapters

®

APPROVED ON-BOARD ISP PROGRAMMING TOOLS

MANUFACTURER PROGRAMMER CONFIGURATION

Corelis, Inc.
12607 Hidden Creek Way, Suite H
Cerritos, California 70703
[phone]

Vantis Corporation
P.O. Box 3755
920 DeGuigne Drive
Sunnyvale, CA 94088
[phone] or 1(888) 826-8472 (VANTIS2)
http://www.vantis.com

JTAGPROG™

MACHPRO

®

26 MACH111-5/7/10/12/15

PHYSICAL DIMENSIONS

PL 044
44-Pin Plastic Leaded Chip Carrier (measured in inches)

.685
.695

.650
.656

.042
.056

.062
.083

.685
.695

.650
.656

.026
.032

Pin 1 I.D.

TOP VIEW

.050 REF

.009
.015

.090
.120

.165
.180

SIDE VIEW

.590

.500

.630

REF

.013
.021

SEATING PLANE

16-038-SQ
PL 044
DA78
6-28-94 ae

MACH111-5/7/10/12/15 27

PHYSICAL DIMENSIONS

PQT044
44-Pin Thin Quad Flat Pack (measured in millimeters)

44

1

9.80

10.20

11.80

12.20

11.80

12.20

9.80

10.20

11° – 13°

0.95

1.05

0.30

1.00 REF.

Trademarks

Copyright  1998 Vantis Corporation. All rights reserved.
AMD is a registered trademark of Advanced Micro Devices, Inc.
Vantis, the Vantis logo and combinations thereof, SpeedLocking and Bus-Friendly are trademarks, and MACH, MACHXL, MACHPRO and PAL are

registered trademarks of Vantis Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

0.45

0.80 BSC

1.20 MAX

11° – 13°

16-038-PQT-2
PQT 44
7-11-95 ae

28 MACH111-5/7/10/12/15