AMD MACH110-24JI, MACH110-20JC, MACH110-18JI, MACH110-15JC, MACH110-14JI Datasheet

Publication# 14127 Rev. I Amendment/0
Issue Date: May 1995

Advanced

Micro

Devices

MACH110-12/15/20

High-Density EE CMOS Programmable Logic

FINAL

COM’L: -12/15/20 IND: -14/18/24

DISTINCTIVE CHARACTERISTICS

■ 44 Pins

■ 32 Macrocells

■ 12 ns t

PD

Commercial

14 ns t

PD

Industrial

■ 77 MHz f

CNT

■ 38 Inputs

■ 32 Outputs

■ 32 Flip-flops; 2 clock choices

■ 2 “PAL22V16” Blocks

■ Pin-compatible with MACH111, MACH210,

MACH211, MACH215

GENERAL DESCRIPTION

The MACH110 is a member of AMD’s high-performance
EE CMOS MACH 1 family. This device has approxi­mately three times the logic macrocell capability of the
popular PAL22V10 without loss of speed.

The MACH110 consists of two PAL blocks intercon­nected by a programmable switch matrix. The two PAL
blocks are essentially “PAL22V16” structures complete
with product-term arrays and programmable macro­cells. The switch matrix connects the PAL blocks to
each other and to all input pins, providing a high degree
of connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.

The MACH110 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type or T-type to help reduce the
number of product terms. The register type decision can
be made by the designer or by the software. All
macrocells can be connected to an I/O cell. If a buried
macrocell is desired, the internal feedback path from the
macrocell can be used, which frees up the I/O pin for use
as an input.

AMD

2 MACH110-12/15/20

BLOCK DIAGRAM

44 x 70

AND Logic Array

and

Logic Allocator

44 x 70

AND Logic Array

and

Logic Allocator

I/O0 – I/O

15

I0 – I

1,

I3 – I

4

I/O

Cells

Macrocells

Switch Matrix

Macrocells

I/O

Cells

I/O

16

– I/O

31

CLK1/I

5,

CLK0/I

2

14127I-1

16

16

16

16

22

22

16

16

16

16

2

4

2

2

2

OE

OE

AMD

3MACH110-12/15/20

CONNECTION DIAGRAM
Top View

PLCC

14127I-2

I/O

5

I/O

6

I/O

7

I

0

I

1

CLK0/I

2

I/O

8

I/O

9

GND

I/O

10

I/O

11

I/O4I/O

3

I/O

2

I/O

1

I/O

0

GND

V

CC

I/O

31

I/O

30

I/O29I/O

28

I/O

27

I/O

26

I/O

25

I

3

I

4

I/O

24

CLK1/I

5

GND

I/O

23

I/O

22

I/O

21

I/O12I/O

13

I/O

14

V

CC

GND

I/O

16

I/O

15

I/O17I/O

18

I/O

19

I/O

20

7
8
9

10
11
12
13

15
16

14

17

561324 4443424140

29

30

31

32

33

34

35

36

37

38

39

18 282726252423222119 20

PIN DESIGNATIONS

CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output

V

CC

= Supply Voltage

Note:
Pin-compatible with MACH111, MACH210, MACH211, and MACH215.

AMD

MACH110-12/15/20 (Com’l)4

ORDERING INFORMATION
Commercial Products

Valid Combinations

The Valid Combinations table lists configurations
planned to be supported in volume for this device.
Consult the local AMD sales office to confirm availability
of specific valid combinations and to check on newly
released combinations.

AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:

OPERATING CONDITIONS

C = Commercial (0

°C to +70°C)

FAMILY TYPE

MACH = Macro Array CMOS High-Speed

SPEED

-12 = 12 ns t

PD

-15 = 15 ns t

PD

-20 = 20 ns t

PD

MACH110-12
MACH110-15
MACH110-20

MACH -12 J C

Valid Combinations

OPTIONAL PROCESSING

Blank = Standard Processing

110

DEVICE NUMBER

110 = 32 Macrocells, 44 Pins

PACKAGE TYPE

J = 44-Pin Plastic Leaded

Chip Carrier (PL 044)

JC

AMD

5MACH110-14/18/25 (Ind)

ORDERING INFORMATION
Industrial Products

Valid Combinations

The Valid Combinations table lists configurations
planned to be supported in volume for this device.
Consult the local AMD sales office to confirm availability
of specific valid combinations and to check on newly
released combinations.

AMD programmable logic products for Industrial applications are available with several ordering options. The order number (Valid
Combination) is formed by a combination of:

OPERATING CONDITIONS

I = Industrial (–40°C to +85°C)

FAMILY TYPE

MACH = Macro Array CMOS High-Speed

SPEED

-14 = 14 ns t

PD

-18 = 18 ns t

PD

-24 = 24 ns t

PD

MACH110-14
MACH110-18 JI
MACH110-24

MACH -14 I

Valid Combinations

OPTIONAL PROCESSING

Blank = Standard Processing

110

DEVICE NUMBER

110 = 32 Macrocells, 44 Pins

J

PACKAGE TYPE

J = 44-Pin Plastic Leaded Chip

Carrier (PL 044)

AMD

6 MACH110-12/15/20

FUNCTIONAL DESCRIPTION

The MACH110 consists of two PAL blocks connected by
a switch matrix. There are 32 I/O pins and 6 dedicated
input pins feeding the switch matrix. These signals are
distributed to the two PAL blocks for efficient design
implementation. There are two clock pins that can also
be used as dedicated inputs.

The PAL Blocks

Each PAL block in the MACH110 (Figure 1) contains a
64-product-term logic array, a logic allocator, 16 macro­cells and 16 I/O cells. The switch matrix feeds each PAL
block with 22 inputs. This makes the PAL block look
effectively like an independent “PAL22V16”.

There are four additional output enable product terms in
each PAL block. For purposes of output enable, the 16
I/O cells are divided into 2 banks of 8 macrocells. Each
bank is allocated two of the output enable product terms.

An asynchronous reset product term and an asynchro­nous preset product term are provided for flip-flop
initialization. All flip-flops within the PAL block are
initialized together.

The Switch Matrix

The MACH110 switch matrix is fed by the inputs and
feedback signals from the PAL blocks. Each PAL block
provides 16 internal feedback signals and 16 I/O
feedback signals. The switch matrix distributes these
signals back to the PAL blocks in an efficient manner
that also provides for high performance. The design
software automatically configures the switch matrix
when fitting a design into the device.

The Product-Term Array

The MACH110 product-term array consists of 64
product terms for logic use, and 6 special-purpose
product terms. Four of the special-purpose product
terms provide programmable output enable, one
provides asynchronous reset, and one provides a
synchronous preset. Two of the output enable product
terms are used for the first eight I/O cells; the other two
control the last eight macrocells.

The Logic Allocator

The logic allocator in the MACH110 takes the 64 logic
product terms and allocates them to the 16 macrocells
as needed. Each macrocell can be driven by up to
12 product terms. The design software automatically
configures the logic allocator when fitting the design into
the device.

Table 1 illustrates which product term clusters are
available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.

Table 1. Logic Allocation

Available

Output Macrocell Clusters

M

0

C0, C

1

M

1

C0, C1, C

2

M

2

C1, C2, C

3

M

3

C2, C3, C

4

M

4

C3, C4, C

5

M

5

C4, C5, C

6

M

6

C5, C6, C

7

M

7

C6, C

7

M

8

C8, C

9

M

9

C8, C9, C

10

M

10

C9, C10, C

11

M

11

C10, C11, C

12

M

12

C11, C12, C

13

M

13

C12, C13, C

14

M

14

C13, C14, C

15

M

15

C14, C

15

The Macrocell

The MACH110 macrocells can be configured as either
registered or combinatorial, with programmable polar­ity. The macrocell provides internal feedback whether
configured as registered or combinatorial. The flip-flops
can be configured as D-type or T-type, allowing for
product-term optimization.

The flip-flops can individually select one of two clock
pins, which are also available as data inputs. The regis­ters are clocked on the LOW-to-HIGH transition of the
clock signal. The flip-flops can also be asynchronously
initialized with the common asynchronous reset and
preset product terms.

The I/O Cell

The I/O cell in the MACH110 consists of a three-state
output buffer. The three-state buffer can be configured
in one of three ways: always enabled, always disabled,
or controlled by a product term. If product term control is
chosen, one of two product terms may be used to
provide the control. The two product terms that are
available are common to eight I/O cells. Within each
PAL block, two product terms are available for selection
by the first eight three-state outputs; two other product
terms are available for selection by the last eight
three-state outputs.

These choices make it possible to use the macrocell as
an output, an input, a bidirectional pin, or a three-state
output for use in driving a bus.

AMD

7MACH110-12/15/20

14127I-3

0 4 8 12 16 20 24 28 40324336

0 4 8 12 16 20 24 28 40324336

I/O
Cell

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Switch
Matrix

Output Enable
Output Enable

Asynchronous Reset
Asynchronous Preset

Output Enable

Output Enable

CLK

16

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

I/O
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

16

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

Output
Macro
Cell

4

0

Logic Allocator

63

C

0

C

1

C

2

C

3

C

4

C

5

C

6

C

7

C

8

C

9

C

10

C

11

C

12

C

13

C

14

C

15

M

3

M

6

M

5

M

4

M

2

M

1

M

0

M

9

M

8

M

7

M

10

M

11

M

12

M

13

M

14

M

15

Figure 1. MACH110 PAL Block

AMD

MACH110-12/15/20 (Com’l)8

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature

With Power Applied –55°C to +125°C. . . . . . . . . . . . .

Supply Voltage with

Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .

DC Input Voltage –0.5 V to V

CC

+ 0.5 V. . . . . . . . . . . .

DC Output or I/O
Pin Voltage –0.5 V to V

CC

+ 0.5 V. . . . . . . . . . . . . . . .

Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . .

Latchup Current
(T

A

= 0°C to 70°C) 200 mA. . . . . . . . . . . . . . . . . . . . .

Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability. Pro­gramming conditions may differ.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

A

)

Operating in Free Air 0°C to +70°C. . . . . . . . . . . .

Supply Voltage (V

CC

)

with Respect to Ground +4.75 V to +5.25 V. . . . .

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

V

OH

Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V

V

IN

= V

IH

or V

IL

V

OL

Output LOW Voltage IOL = 16 mA, VCC = Min 0.5 V

V

IN

= V

IH

or V

IL

V

IH

Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V

Voltage for all Inputs (Note 1)

V

IL

Input LOW Voltage Guaranteed Input Logical LOW 0.8 V

Voltage for all Inputs (Note 1)

I

IH

Input HIGH Current VIN = 5.25 V, V

CC

= Max (Note 2) 10 µA

I

IL

Input LOW Current VIN = 0 V, V

CC

= Max (Note 2) –10 µA

I

OZH

Off-State Output Leakage V

OUT

= 5.25 V, V

CC

= Max 10 µA

Current HIGH V

IN

= V

IH

or VIL (Note 2)

I

OZL

Off-State Output Leakage V

OUT

= 0 V, V

CC

= Max –10 µA

Current LOW V

IN

= V

IH

or VIL (Note 2)

I

SC

Output Short-Circuit Current V

OUT

= 0.5 V, V

CC

= Max (Note 3) –30 –160 mA

I

CC

Supply Current (Typical) V

CC

= 5 V, T

A

=25°C, 95 mA

f = 25 MHz (Note 4)

Notes:

1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.

2. I/O pin leakage is the worst case of I

IL

and I

OZL

(or IIH and I

OZH

).

3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
V

OUT

= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

4. Measured with a 16-bit up/down counter program. This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.

AMD

9MACH110-12/15/20 (Com’l)

CAPACITANCE (Note 1)

Parameter
Symbol Parameter Description Test Conditions Typ Unit

C

IN

Input Capacitance V

IN

= 2.0 V VCC = 5.0 V, TA = 25°C6 pF

C

OUT

Output Capacitance V

OUT

= 2.0 V f = 1 MHz 8 pF

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)

Parameter
Symbol Parameter Description Min Max Min Max Min Max Unit

t

PD

Input, I/O, or Feedback to Combinatorial 12 15 20 ns
Output (Note 3)

71013ns
81114ns

t

H

Hold Time 0 0 0 ns

t

CO

Clock to Output (Note 3) 8 10 12 ns

t

WL

668ns

t

WH

668ns

66.7 50 40 MHz

62.5 47.6 38.5 MHz

f

MAX

76.9 66.6 47.6 MHz

71.4 55.5 43.5 MHz

No Feedback 1/(t

WL

+ tWH) 83.3 83.3 62.5 MHz

t

AR

Asynchronous Reset to Registered Output 16 20 25 ns

t

ARW

Asynchronous Reset Width (Note 1) 12 15 20 ns

t

ARR

Asynchronous Reset Recovery Time (Note 1) 8 10 15 ns

t

AP

Asynchronous Preset to Registered Output 16 20 25 ns

t

APW

Asynchronous Preset Width (Note 1) 12 15 20 ns

t

APR

Asynchronous Preset Recovery Time (Note 1) 8 10 15 ns

t

EA

Input, I/O, or Feedback to Output Enable (Note 3) 12 15 20 ns

t

ER

Input, I/O, or Feedback to Output Disable (Note 3) 12 15 20 ns

Notes:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.

2. See Switching Test Circuit, for test conditions.

3. Parameters measured with 16 outputs switching.

Setup Time from Input, I/O, or Feedback
to Clock

-12 -20

Clock Width

D-type
T-type

D-type
T-type

LOW
HIGH

D-type
T-type

Maximum
Frequency
(Note 1)

External Feedback 1/(t

S

+ tCO)

Internal Feedback (f

CNT

)

t

S

-15

AMD

MACH110-14/18/20 (Ind)10

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature

With Power Applied –55°C to +125°C. . . . . . . . . . . . .

Supply Voltage with

Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .

DC Input Voltage –0.5 V to V

CC

+ 0.5 V. . . . . . . . . . . .

DC Output or I/O
Pin Voltage –0.5 V to V

CC

+ 0.5 V. . . . . . . . . . . . . . . .

Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . .

Latchup Current
(T

A = –40°C to +85°C) 200 mA. . . . . . . . . . . . . . . . . .

Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.

INDUSTRIAL OPERATING RANGES

Ambient Temperature (TA)

Operating in Free Air –40°C to +85°C. . . . . . . . . . . .

Supply Voltage (V

CC)

with Respect to Ground +4.5 V to +5.5 V. . . . . . . . . .

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V

VIN = VIH or VIL

VOL Output LOW Voltage IOL = 16 mA, VCC = Min 0.5 V

VIN = VIH or VIL

VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V

Voltage for all Inputs (Note 1)

VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V

Voltage for all Inputs (Note 1)

IIH Input HIGH Current VIN = 5.25 V, VCC

= Max (Note 2) 10 µA

IIL Input LOW Current VIN = 0 V, VCC

= Max (Note 2) –10 µA

IOZH Off-State Output Leakage VOUT

= 5.25 V, VCC = Max 10 µA

Current HIGH VIN = VIH or VIL (Note 2)

IOZL Off-State Output Leakage VOUT = 0 V, VCC

= Max –10 µA

Current LOW VIN = VIH or VIL (Note 2)

ISC Output Short-Circuit Current VOUT = 0.5 V, VCC

= Max (Note 3) –30 –160 mA

Supply Current (Typical) VCC = 5 V, TA = 25°C, f = 25 MHz (Note 4) 95 mA

Notes:

1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.

2. I/O pin leakage is the worst case of I

IL

and I

OZL

(or IIH and I

OZH

).

3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
V

OUT

= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of
being loaded, enabled, and reset.

ICC

AMD

11MACH110-14/18/20 (Ind)

CAPACITANCE (Note 1)

Parameter
Symbol Parameter Description Test Conditions Typ Unit

CIN Input Capacitance VIN

= 2.0 V VCC = 5.0 V, TA = 25°C6pF

COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF

SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)

Parameter
Symbol Parameter Description Min Max Min Max Min Max Unit

t

PD Input, I/O, or Feedback to Combinatorial 14.5 18 24 ns

Output (Note 3)

8.5 12 16 ns
10 13.5 17 ns

t

H Hold Time 0 0 0 ns

tCO Clock to Output (Note 3) 10 12 14.5 ns
t

WL 7.5 7.5 10 ns

t

WH 7.5 7.5 10 ns

53.5 40 32 MHz
50 38 30 MHz

f

MAX 61.5 53 38 MHz

57 44 34.5 MHz

No Feedback 1/(t

WL + tWH) 66.5 66.5 50 MHz

t

AR Asynchronous Reset to Registered Output 19.5 24 30 ns

t

ARW Asynchronous Reset Width (Note 1) 14.5 18 24 ns

t

ARR Asynchronous Reset Recovery Time (Note 1) 10 12 18 ns

t

AP Asynchronous Preset to Registered Output 19.5 24 30 ns

t

APW Asynchronous Preset Width (Note 1) 14.5 18 24 ns

t

APR Asynchronous Preset Recovery Time (Note 1) 10 12 18 ns

t

EA Input, I/O, or Feedback to Output Enable (Note 3) 14.5 18 24 ns

tER Input, I/O, or Feedback to Output Disable (Note 3) 14.5 18 24 ns

Notes:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.

2. See Switching Test Circuit, for test conditions.

3. Parameters measured with 16 outputs switching.

Setup Time from Input, I/O, or Feedback
to Clock

-14 -24

Clock Width

D-type
T-type

D-type
T-type

LOW
HIGH

D-type
T-type

Maximum
Frequency
(Note 1)

External Feedback 1/(t

S

+ tCO)

Internal Feedback (f

CNT)

t

S

-18

AMD

12 MACH110-12/15/20

TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS

V

CC

= 5.0 V, TA = 25°C

Input

20

–40

–60
–80

–2 –1

123

Output, HIGH

I

I

(mA)

V

I

(V)

–20

I

OH

(mA)

V

OH

(V)

25

–50

–75

–100

–3 –2 –1

123

–25

–125

–150

45

45

–100

–0.8 –0.6 –0.4 .2–0.2–1.0

14127I-4

Output, LOW

.4 .6 1.0.8

60

40
20

–20

–40

80

–60

–80

I

OL

(mA)

V

OL

(V)

14127I-5

14127I-6

AMD

13MACH110-12/15/20

TYPICAL ICC CHARACTERISTICS
V

CC

= 5 V, TA = 25°C

14127I-7

MACH110

150

125

100

75

50

25

0

0 102030405060708090

ICC (mA)

Frequency (MHz)

The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of
being loaded, enabled, and reset.

Maximum frequency shown uses internal feedback and a D-type register.

AMD

14 MACH110-12/15/20

TYPICAL THERMAL CHARACTERISTICS

Measured at 25°C ambient. These parameters are not tested.

Parameter
Symbol Parameter Description PLCC Unit

θ

jc

Thermal impedance, junction to case 14 °C/W

θ

ja

Thermal impedance, junction to ambient 39 °C/W

θ

jma

Thermal impedance, junction to 200 lfpm air 33 °C/W

400 lfpm air 30 °C/W
600 lfpm air 27 °C/W
800 lfpm air 25 °C/W

Plastic θjc Considerations

The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the

θ

jc measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the
package. Furthermore,

θ

jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a

constant temperature. Therefore, the measurements can only be used in a similar environment.

Typ

ambient with air flow

AMD

15MACH110-12/15/20

SWITCHING WAVEFORMS

Notes:

1. V

T

= 1.5 V.

2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2 ns–4 ns typical.

t

PD

Input, I/O, or

Feedback

Combinatorial

Output

V

T

V

T

Combinatorial Output

V

T

Input, I/O,

or Feed-

back

Registered

Output

Registered Output

t

S

t

CO

V

T

t

H

V

T

Clock

t

WH

Clock

Clock Width

t

WL

V

T

Combinatorial

Output

Registered Input (MACH 2 and 4)

t

SIR

t

ICO

V

T

t

HIR

V

T

Input

Register

Clock

Registered

Input

Latched Output (MACH 2, 3, and 4)

Gate

Gate Width (MACH 2, 3, and 4)

t

GWS

V

T

V

T

V

T

V

T

t

ICS

Input Register to Output Register Setup

(MACH 2 and 4)

Output

Register

Clock

Input

Register

Clock

Registered

Input

t

PDL

Input, I/O, or

Feedback

Latched

Out

Gate

V

T

t

HL

t

SL

t

GO

V

T

V

T

14127I-8

14127I-9

14127I-10

14127I-11

14127I-12

14127I-13 14127I-14

AMD

16 MACH110-12/15/20

SWITCHING WAVEFORMS

Notes:

1. VT = 1.5 V.

2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2 ns–4 ns typical.

Latched Input (MACH 2 and 4)

Latched Input and Output

(MACH 2, 3, and 4)

Latched

In

Output

Latch Gate

Latched

Out

t

SLL

Combinatorial

Output

Gate

t

HIL

t

SIL

t

IGO

Latched

In

t

PDLL

t

IGOL

t

IGS

Input

Latch Gate

V

T

V

T

V

T

V

T

V

T

V

T

14127I-15

14127I-16

AMD

17MACH110-12/15/20

SWITCHING WAVEFORMS

t

WICH

Clock

Input Register Clock Width

(MACH 2 and 4)

V

T

t

WICL

V

T

V

T

t

ARW

V

T

t

AR

Asynchronous Reset

Input, I/O, or

Feedback

Registered

Output

Clock

t

ARR

Asynchronous Preset

Registered

Output

Clock

V

T

V

T

Outputs

Output Disable/Enable

t

ER

t

EA

V

OH

- 0.5V

V

OL

+ 0.5V

Notes:

1. V

T

= 1.5 V.

2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2 ns–4 ns typical.

Input, I/O,

or Feedback

V

T

V

T

Input, I/O, or

Feedback

t

APW

V

T

t

AP

t

APR

Input

Latch

Gate

Input Latch Gate Width

(MACH 2 and 4)

t

WIGL

V

T

14127I-17

14127I-18

14127I-19

14127I-20

14127I-21

AMD

18 MACH110-12/15/20

KEY TO SWITCHING WAVEFORMS

KS000010-PAL

Must be
Steady

May
Change
from H to L

May
Change
from L to H

Does Not
Apply

Don’t Care,
Any Change
Permitted

Will be
Steady

Will be
Changing
from H to L

Will be
Changing
from L to H

Changing,
State
Unknown

Center
Line is High­Impedance
“Off” State

WAVEFORM INPUTS OUTPUTS

SWITCHING TEST CIRCUIT

Measured

Specification S

1

C

L

R

1

R

2

Output Value

t

PD

, t

CO

Closed 1.5 V

t

EA

Z → H: Open 35 pF 1.5 V
Z → L: Closed 300 Ω 390 Ω

t

ER

H →Z: Open 5 pF H →Z: VOH – 0.5 V
L →Z: Closed L →Z: V

OL

+ 0.5 V

Commercial

14127I-22

C

L

Output

R

1

R

2

S

1

Test Point

5 V

*Switching several outputs simultaneously should be avoided for accurate measurement.

AMD

19MACH110-12/15/20

f

MAX

PARAMETERS

The parameter f

MAX

is the maximum clock rate at which
the device is guaranteed to operate. Because the flexi­bility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, f

MAX

is specified for

three types of synchronous designs.
The first type of design is a state machine with feedback

signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the in­put setup time for the external signals (t

S

+ tCO). The re-

ciprocal, f

MAX

, is the maximum frequency with external
feedback or in conjunction with an equivalent speed de­vice. This f

MAX

is designated “f

MAX

external.”

The second type of design is a single-chip state ma­chine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop out­puts. Under these conditions, the period is limited by the
internal delay from the flip-flop outputs through the inter­nal feedback and logic to the flip-flop inputs. This f

MAX

is

designated “f

MAX

internal”. A simple internal counter is a

good example of this type of design; therefore, this pa­rameter is sometimes called “f

CNT.

”

The third type of design is a simple data path applica­tion. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (t

S

+ tH). However,

a lower limit for the period of each f

MAX

type is the mini-

mum clock period (t

WH

+ tWL). Usually, this minimum

clock period determines the period for the third f

MAX

, des-

ignated “f

MAX

no feedback.”

For devices with input registers, one additional f

MAX

pa-

rameter is specified: f

MAXIR

. Because this involves no

feedback, it is calculated the same way as f

MAX

no feed­back. The minimum period will be limited either by the
sum of the setup and hold times (t

SIR

+ t

HIR

) or the sum of

the clock widths (t

WICL

+ t

WICH

). The clock widths are nor-

mally the limiting parameters, so that f

MAXIR

is specified

as 1/(t

WICL

+ t

WICH

). Note that if both input and output reg­isters are use in the same path, the overall frequency will
be limited by t

ICS

.
All frequencies except f

MAX

internal are calculated from

other measured AC parameters. f

MAX

internal is meas-

ured directly.

t

HIR

t

SIR

LOGIC REGISTER

tt

CLK

(SECOND

CHIP)

SCO

t

S

f

MAX

External; 1/(tS + tCO)

LOGIC REGISTER

CLK

f

MAX

Internal (f

CNT

)

LOGIC REGISTER

t

CLK

S

f

MAX

No Feedback; 1/(tS + tH) or 1/(tWH + tWL)

14127I-23

LOGIC

REGISTER

CLK

f

MAXIR

; 1/(t

SIR

+ t

HIR

) or 1/(t

WICL

+ t

WICH

)

AMD

20 MACH110-12/15/20

ENDURANCE CHARACTERISTICS

The MACH families are manufactured using AMD’s
advanced Electrically Erasable process. This technol­ogy uses an EE cell to replace the fuse link used in

bipolar parts. As a result, the device can be erased and
reprogrammed, a feature which allows 100% testing at
the factory.

Endurance Characteristics

Parameter

Symbol Parameter Description Min Units Test Conditions

10 Years Max Storage

Temperature

20 Years Max Operating

Temperature

N Max Reprogramming Cycles 100 Cycles Normal Programming

Conditions

t

DR

Min Pattern Data Retention Time

AMD

21MACH110-12/15/20

INPUT/OUTPUT EQUIVALENT SCHEMATICS

Input

I/O

Preload

Circuitry

ESD

Protection

Feedback

Input

V

CC

V

CC

1 kΩ

100 kΩ

V

CC

V

CC

100 kΩ

1 kΩ

14127I-24

AMD

22 MACH110-12/15/20

POWER-UP RESET

The MACH devices have been designed with the capa­bility to reset during system power-up. Following power­up, all flip-flops will be reset to LOW. The output state
will depend on the logic polarity. This feature provides
extra flexibility to the designer and is especially valuable
in simplifying state machine initialization. A timing dia­gram and parameter table are shown below. Due to the
synchronous operation of the power-up reset and the

wide range of ways V

CC

can rise to its steady state, two
conditions are required to insure a valid power-up reset.
These conditions are:

1. The V

CC

rise must be monotonic.

2. Following reset, the clock input must not be driven

from LOW to HIGH until all applicable input and
feedback setup times are met.

Parameter
Symbol Parameter Descriptions Max Unit

t

PR

Power-Up Reset Time 10 µs

t

S

Input or Feedback Setup Time

t

WL

Clock Width LOW

See
Switching
Characteristics

t

PR

t

WL

t

S

4 V

V

CC

Power

Registered

Output

Clock

14127I-25

Power-Up Reset Waveform

AMD

23MACH110-12/15/20

USING PRELOAD AND OBSERVABILITY

In order to be testable, a circuit must be both controllable
and observable. To achieve this, the MACH devices
incorporate register preload and observability.

In preload mode, each flip-flop in the MACH device can
be loaded from the I/O pins, in order to perform
functional testing of complex state machines. Register
preload makes it possible to run a series of tests from a
known starting state, or to load illegal states and test for
proper recovery. This ability to control the MACH
device’s internal state can shorten test sequences,
since it is easier to reach the state of interest.

The observability function makes it possible to see the
internal state of the buried registers during test by
overriding each register’s output enable and activating
the output buffer. The values stored in output and buried
registers can then be observed on the I/O pins. Without
this feature, a thorough functional test would be
impossible for any designs with buried registers.

While the implementation of the testability features is
fairly straightforward, care must be taken in certain
instances to insure valid testing.

One case involves asynchronous reset and preset. If the
MACH registers drive asynchronous reset or preset
lines and are preloaded in such a way that reset or
preset are asserted, the reset or preset may remove the
preloaded data. This is illustrated in Figure 2. Care
should be taken when planning functional tests, so that
states that will cause unexpected resets and presets are
not preloaded.

Another case to be aware of arises in testing combinato­rial logic. When an output is configured as combinato­rial, the observability feature forces the output into
registered mode. When this happens, all product terms
are forced to zero, which eliminates all combinatorial
data. For a straight combinatorial output, the correct
value will be restored after the preload or observe
function, and there will be no problem. If the function
implements a combinatorial latch, however, it relies on
feedback to hold the correct value, as shown in Figure 3.
As this value may change during the preload or observe
operation, you cannot count on the data being correct
after the operation. To insure valid testing in these
cases, outputs that are combinatorial latches should not
be tested immediately following a preload or observe
sequence, but should first be restored to a known state.

All MACH 2 devices support both preload and
observability.

Contact individual programming vendors in order to
verify programmer support.

AR

Figure 2. Preload/Reset Conflict

Q

1

On

Off

Preload

Mode

Q

2

AR

Preloaded

HIGH

DQQ

1

D

Q

AR

Preloaded

HIGH

Q

2

14127I-26

Figure 3. Combinatorial Latch

Set

Reset

14127I-27

AMD

24 MACH110-12/15/20

DEVELOPMENT SYSTEMS (subject to change)

For more information on the products listed below, please consult the AMD FusionPLD Catalog.

MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS

Advanced Micro Devices, Inc.
P.O. Box 3453, MS 1028
Sunnyvale, CA 94088-3543
[phone] or [phone]

Advanced Micro Devices, Inc.
P.O. Box 3453, MS 1028
Sunnyvale, CA 94088-3543
[phone] or [phone]

Advanced Micro Devices, Inc.
P.O. Box 3453, MS 1028
Sunnyvale, CA 94088-3543
[phone] or [phone]

Advanced Micro Devices, Inc.
P.O. Box 3453, MS 1028
Sunnyvale, CA 94088-3543
[phone] or [phone]

Cadence Design Systems
555 River Oaks Pkwy
San Jose, CA 95134
[phone]

Capilano Computing
960 Quayside Dr., Suite 406
New Westminster, B.C.
Canada V3M 6G2
[phone] or [phone]

CINA, Inc.
P.O. Box 4872
Mountain View, CA 94040
[phone]

Data I/O Corporation
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
[phone] or [phone]

iNt GmbH
Busenstrasse 6
D-8033 Martinsried, Munich, Germany
(89) 857-6667

ISDATA GmbH
Daimlerstr. 51
D7500 Karlsruhe 21 Germany
Germany: 0721/75 10 87
U.S.: [phone]

Logic Modeling
19500 NW Gibbs Dr.
P.O. Box 310
Beaverton, OR 97075
[phone]

Logical Devices, Inc.
692 S. Military Trail
Deerfield Beach, FL 33442
[phone] or [phone]

MACHXL Software

Ver. 2.0

ComposerPIC

TM

Designer

(Requires MACH Fitter)

Verilog, LeapFrog, RapidSim Simulators

(Models also available from Logic Modeling)

Ver. 3.3

LOG/iCTM Software

(Requires MACH Fitter)

ABEL

TM

-5 Software

(Requires MACH Fitter)

Synario

TM

Software

MacABEL

TM

Software

(Requires SmartPart MACH Fitter)

AMD-ABEL Software

Data I/O MACH Fitters

PROdeveloper/AMD

Software

PROsynthesis/AMD Software

Design Center/AMD

Software

SmartModelLibrary

SmartCAT Circuit Analyzer

PLDSim 90

CUPLTM Software

AMD

25MACH110-12/15/20

MANUFACTURER TEST GENERATION SYSTEM

Acugen Software, Inc.
427-3 Amherst St., Suite 391
Nashua, NH 03063
[phone]

iNt GmbH
Busenstrasse 6
D-8033 Martinsried, Munich, Germany
(87) 857-6667

DEVELOPMENT SYSTEMS (subject to change) (continued)

Advanced Micro Devices is not responsible for any information relating to the products of third parties. The inclusion of such information is not a representation nor
an endorsement by AMD of these products.

ATGENTM Test Generation Software

MultiSIM Interactive Simulator

LASAR

PLDCheck 90

MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS

Mentor Graphics Corp.
8005 S.W. Boeckman Rd.
Wilsonville, OR 97070-7777
[phone] or [phone]

MicroSim Corp.
20 Fairbanks
Irvine, CA 92718
[phone]

MINC Incorporated
6755 Earl Drive, Suite 200
Colorado Springs, CO 80918
(800) 755-FPGA or [phone]

OrCAD
3175 N.W. Aloclek Dr.
Hillsboro, OR 97124
[phone]

SUSIE–CAD
10000 Nevada Highway, Suite 201
Boulder City, NV 89005
[phone]

Teradyne EDA
321 Harrison Ave.
Boston, MA 02118
[phone] or [phone]

Viewlogic Systems, Inc.
293 Boston Post Road West
Marlboro, MA 01752
[phone] or [phone]

Programmable Logic Design Tools 386+

Schematic Design Tool 386+

Digital Simulation Tools

ViewPLD or PROPLD

(Requires PROSim Simulator MACH Fitter)

ViewSim Simulator

(Models for ViewSim also available

from Logic Modeling)

PLDesignerTM-XL Software

(Requires MACH Fitter)

PLDSynthesis

TM

(Requires MACH Fitter)

QuickSim Simulator

(Models also available from Logic Modeling)

Design Center Software

(Requires MACH Fitter)

SUSIE

TM

Simulator

AMD

26 MACH110-12/15/20

APPROVED PROGRAMMERS (subject to change)

For more information on the products listed below, please consult the AMD FusionPLD Catalog.

MANUFACTURER PROGRAMMER CONFIGURATION

Advin Systems, Inc.
1050-L East Duane Ave.
Sunnyvale, CA 94086
[phone]

BP Microsystems
100 N. Post Oak Rd.
Houston, TX 77055-7237
[phone] or [phone]

Data I/O Corporation
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
[phone] or [phone]

Logical Devices Inc./Digelec
692 S. Military Trail
Deerfield Beach, FL 33442
[phone] or [phone]

SMS North America, Inc.
16522 NE 135th Place
Redmond, WA 98052
[phone]
or
SMS
lm Grund 15
D-7988 Vangen Im Allgau, Germany
07522-5018

Stag Microsystems Inc.
1600 Wyatt Dr. Suite 3
Santa Clara, CA 95054
[phone]
or
Stag House
Martinfield, Welwyn Garden City
Herfordshire UK AL7 1JT
707-332148

System General
510 S. Park Victoria Dr.
Milpitas, CA 95035
[phone]
or
3F, No. 1, Alley 8, Lane 45
Bao Shing Rd., Shin Diau
Taipei, Taiwan
2-917-3005

BP1200

Pilot U84

Model 3900

Turpro-1

UniSite

TM

AutoSite

Stag Quazar

Sprint/Expert

ALLPROTM–88

MANUFACTURER PROGRAMMER CONFIGURATION

Corelis, Inc.
12607 Hidden Creek Way, Suite H
Cerritos, California 70703
[phone]

Advanced Micro Devices
P.O. Box 3453, MS-1028
Sunnyvale, CA 94088-3453
[phone]

MACHpro

JTAG PROG

APPROVED ON-BOARD PROGRAMMERS

AMD

27MACH110-12/15/20

PROGRAMMER SOCKET ADAPTERS (subject to change)

MANUFACTURER PART NUMBER

EDI Corporation
P.O. Box 366
Patterson, CA 95363
[phone]

Emulation Technology
2344 Walsh Ave., Bldg. F
Santa Clara, CA 95051
[phone]

Logical Systems Corp.
P.O. Box 6184
Syracuse, NY 13217-6184
[phone]

Procon Technologies, Inc.
1333 Lawrence Expwy, Suite 207
Santa Clara, CA 95051
[phone]

Contact Manufacturer

Contact Manufacturer

Contact Manufacturer

Contact Manufacturer

AMD

28 MACH110-12/15/20

PHYSICAL DIMENSIONS*
PL 044

44-Pin Plastic Leaded Chip Carrier (measured in inches)

TOP VIEW

SEATING PLANE

.685
.695

.650
.656

Pin 1 I.D.
.685
.695

.650
.656

.026
.032

.050 REF

.042
.056

.062
.083

.013
.021

.590
.630

.500
REF

.009
.015

.165
.180

.090
.120

16-038-SQ
PL 044
DA78
6-28-94 ae

SIDE VIEW

*For reference only. BSC is an ANSI standard for Basic Space Centering.

Trademarks

Copyright  1995 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, MACH, and PAL are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.