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FINAL
Am79C98
Twisted-Pair Ethernet Transceiver (TPEX)
DISTINCTIVE CHARACTERISTICS
CMOS device provides compliant operation and
low operating current from a single +5 V supply
Power Down mode provides reduced power
consumption for battery-powered applications.
Reset capability allows use in remote MAU
applications.
Pin-selectable twisted-pair receive polarity
detection and automatic inversion of the receive
signal. Polarity indication output pin can
directly drive an LED.
Pin-selectable twisted-pair Link Integrity Test
capability conforming to the IEEE 802.3
standard for 10BASE-T. Link status pin can
directly drive an LED.
Internal twisted-pair transmitter digital
predistortion circuit reduces medium-induced
jitter and ensures compliance with the
10BASE-T transmit and receive waveform
requirements
Pin-selectable SQE Test (heartbeat) enable
Transmit and receive status indications are
available on separate, dedicated pins
AUI loopback, Jabber Control, and SQE Test
functions comply with the 10BASE-T standard
IEEE Std 802.3i-1990
GENERAL DESCRIPTION
The Am79C98 Twisted-Pair Ethernet Transceiver
(TPEX) is an integrated circuit that implements the
medium attachment unit (MAU) functions for the
twisted-pair medium, as specified by the IEEE 802.3
standard (Type 10BASE-T). This device provides the
necessary electrical and functional interface between
the IEEE 802.3 standard attachment unit interface
(AUI) and the twisted-pair cable.
A network based on the 10BASE-T standard can use
unshielded twisted-pair cables, providing an economical solution to networking by allowing the use of existing telephone wiring. The Am79C98 provides a minimal
component count and cost-effective solution to the
design and implementation of 10BASE-T standard
networks.
TPEX provides twisted-pair driver and receiver circuits,
including on-board transmit digital predistortion, receiver squelch, and an AUI port with pin-selectable
SQE Test enable. The device also provides a number of
additional features, including pin-selectable TwistedPair Receive Polarity Detection and Automatic Polarity
Reversal, Link Status indication, Link Test disable function, and transmit and receive status. The Twisted-Pair
Polarity and Link Status pins can be used to drive LEDs
directly.
The Am79C98 is fabricated in CMOS technology and
requires a single +5 V supply. The device is available in
24-pin SKINNYDIP
plastic leaded chip carrier (PLCC) packaging.
®
plastic dual in-line and 28-pin
Publication# 14395 Rev: DAmendment/0
Issue Date: May 1994
1
BLOCK DIAGRAM
Twisted-Pair
Interface
TXD–
TXD+
Line Driver
TXP–
TXP+
and
Predistortion
Jabber
Control
LNKST
Link T est
and
Collision
RXD–
RCV
Loopback
RXD+
and
Line Receiver
and
Polarity Detect
Smart Squelch
Auto Reversal
RXPOL
Voltage
Oscillator
Controlled
and
CI+
Line Driver
CI–
DI+
SQE TEST
Line Receiver
DO+
Squelch Circuit
DO–
XMT
2 Am79C98
Line Driver
DI–
REXT
TEST
PRDN/RST
(AUI)
Attachment
Unit Interface
14395D-1
AMD
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TM
TM
)
(ILACCTM)
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(HIMIBTM)
Plug n’ Play support)
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Am79C940 Media Access Controller for Ethernet (MACE
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Am79C965 PCnet-32 Single-Chip Ethernet Controller (for 386DX, 486 and VL buses)
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(IMR+TM)
Am79C987 Hardware Implemented Management Information Base
CONNECTION DIAGRAM
Top View
DIP
CI+
CI–
DI+
DI–
DV
SS
XMT
LNKST
AV
SS
DO+
DO–
PRDN/RST
REXT
Note:
Pin 1 is marked for orientation
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
TXD+
TXD–
TXP+
TXP–
DV
DD
TEST
SQE^TEST
AV
DD
RXD+
RXD–
RXPOL
RCV
14395D-2
DV
SS
DV
SS
XMT
LNKST
AV
SS
AV
SS
DO+
5
6
7
8
9
10
11
DI–
DO–
DI+
PLCC
CI–
CI+
1324
15131412 161718
RCV
REXT
PRDN/RST
TXD–
TXD+
282726
RXD–
RXPOL
TXP+
25
24
23
22
21
20
19
RXD+
TXP–
DV
DD
DV
DD
TEST
SQE^TEST
AV
DD
AV
DD
14395D-3
3Am79C98
AMD
LOGIC SYMBOL
DV
DD AVDD
TXD+
TXP+
TXD–
TXP–
RXD+
RXD–
LNKST
RXPOL
XMT
RCV
Twisted Pair
Interface
14395D-4
Attachment
Unit Interface
(AUI)
DO+
DO–
DI+
DI–
CI+
CI–
SQE TEST
TEST
REXT
PRDN/RST
DV
Am79C98
SS AVSS
4 Am79C98
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed
by a combination of the elements below.
AM79C98
DEVICE NUMBER/DESCRIPTION
Am79C98
Twisted-Pair Ethernet Transceiver (TPEX)
Valid Combinations
AM79C98 PC, JC
OPTIONAL PROCESSING
Blank = Standard Processing
TECHNOLOGY
C = CMOS Electrically Erasable
PACKAGE TYPE
P=24-Pin Plastic DIP (PD 3024)
J=28-Pin Plastic Leaded Chip Carrier (PL 028)
SPEED
Not Applicable
Valid Combinations
Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am79C98 5
PIN DESCRIPTION
AV
DD
Analog Power
This pin supplies +5 V to analog portions of the TPEX
circuitry.
AV
SS
Analog Ground
This pin is the ground reference for analog portions of
the TPEX circuitry.
CI+, CI–
Control In
Output
AUI port differential driver.
DI+, DI–
Data In
Output
AUI port differential driver.
DO+, DO–
Data Out
Input
AUI port differential receiver.
DV
DD
Digital Power
This pin supplies +5 V to digital portions of the TPEX
circuitry.
DV
SS
Digital Ground
This pin is the ground reference for digital portions of
TPEX circuitry.
LNKST
Link Status
Open Drain, Input/Output
When this pin is tied LOW, the internal Link Test
Receive function is disabled and the Transmit and Receive functions will remain active irrespective of arriving idle Link Test pulses and data. TPEX continues to
generate idle Link Test pulses irrespective of the status
of this pin.
As an output, this pin is driven LOW if the link is identified as functional. However, if the link is determined to
be nonfunctional, due to missing idle Link Test pulses
or data packets, then this pin is not driven. In the LOW
output state, the pin is capable of sinking a maximum
of 16 mA and can be used to drive an LED.
This pin is internally pulled HIGH when inactive.
PRDN/RST
Power Down/Reset
Input, Active LOW
Driving this input LOW resets the internal logic of TPEX
and places the device in a special Power Down mode.
In the Power Down/Reset mode, all output drivers are
placed in their inactive state.
RCV
Receive
Output
This pin is driven HIGH while TPEX is receiving data on
the RXD pins and is transferring the received signal
onto the AUI DI pair. The RCV and XMT pins are simultaneously driven HIGH during collision.
REXT
External Resistor
Input
An external precision resistor is connected between
this pin and AV
ence for the internal voltage-controlled oscillator
(VCO).
in order to provide a voltage refer-
DD
RXD+, RXD–
Receive Data
Input
10BASE-T port differential receivers.
RXPOL
Receive Polarity
Open Drain, Input/Output
The twisted-pair receiver is capable of detecting a receive signal with reversed polarity (wiring error). The
RXPOL pin is normally in the LOW state, indicating correct polarity of the received signal. If the receiver detects reversed polarity, then this pin is not driven (goes
HIGH) and the polarity of subsequent packets is inverted. In the LOW output state, this pin can sink up to
a maximum of 16 mA and is therefore capable of driving an LED.
This feature can be disabled by strapping this pin LOW.
In this case, the Receive Polarity correction circuit is
disabled and the internal receive signal remains noninverted, irrespective of the received signal.
This pin is internally pulled HIGH when inactive.
SQE
TEST
Signal Quality Test (Heartbeat) Enable
Input, Active LOW
The SQE Test function is enabled by tying this input
LOW.
This input is internally pulled HIGH when inactive.
6 Am79C98
TEST
Test
Input, Active HIGH
This pin should be tied HIGH for normal operation. If
this pin is driven LOW, TPEX will enter Loopback Test
mode. The type of loopback is determined by the state
of the SQE
(Station MAU), TPEX transfers data independently
from DO to the TXD/TXP circuit and from RXD to the DI
circuit. If the SQE TEST is in the HIGH state (Repeater
MAU), then data on the RXD circuit is transmitted back
onto the TXD/TXP circuit and data on the DO circuit is
transmitted onto the DI pair.
TEST pin. If this pin is in the LOW state
TXD+, TXD–
Transmit Data
Output
10BASE-T port differential drivers.
TXP+, TXP–
Transmit Predistortion
Output
Transmit waveform predistortion control.
XMT
Transmit
Output
This pin is driven HIGH while TPEX is receiving data on
the AUI DO pair and is transmitting data on the TXD/
TXP pins. The XMT and RCV pins are simultaneously
driven HIGH during collision.
Am79C98 7
FUNCTIONAL DESCRIPTION
The Twisted-Pair Ethernet Transceiver (TPEX) complies with the requirements specified by the IEEE 802.3
standard for the attachment unit interface (AUI) and the
standard for 10BASE-T medium attachment unit
(MAU). TPEX also implements a number of features in
addition to the IEEE 802.3 standard. An outline of functions implemented by the Am79C98 is given below.
Attachment Unit Interface
(DO+/–, DI+/–, CI+/–)
The AUI electrical and functional characteristics comply with those specified by the IEEE 802.3, Sections 7
and 14 (drafted). The AUI pins can be wired directly to
the isolation transformer, for a remote MAU application,
or to another device (e.g., Am7992 serial interface
adapter). The end-of-packet SQE Test function (heartbeat) can be disabled to allow the device to be employed in a repeater application.
Twisted-Pair Transmit Function
Data transmission to the 10BASE-T medium occurs
when valid AUI signals appear on the DO+/–differential
pair. This data stream is routed to the differential driver
circuitry in the TXD+/– pins. The driver circuitry provides necessary electrical driving capability and predistortion control for transmitting signals over
maximum-length twisted-pair cable, as specified by the
IEEE 802.3 10BASE-T standard. The transmit function
meets the propagation delays and jitter specified by the
standard. During transmission, the XMT pin is driven
HIGH and can be used for status information.
Twisted-Pair Receive Function
The receiver complies with the receiver specifications
of the IEEE 802.3 10BASE-T standard, including noise
immunity and received signal rejection criteria (“Smart
Squelch”). Signals meeting these criteria appearing at
the RXD+/– differential input pair are routed to the DI+/–
outputs. The receiver function meets the propagation
delays and jitter requirements specified by the standard. Receiver squelch level drops to approximately
half its threshold value after unsquelch to allow reception of minimum amplitude signals and to offset carrier
fade in the event of worst-case signal attenuation and
crosstalk noise conditions. During receive, the RCV pin
is driven HIGH and can be used for status information.
Link Test Function
The Link Test function is implemented as specified by
the IEEE 802.3 10BASE-T standard. During periods of
transmit pair inactivity, Link Test pulses will be periodically sent over the twisted-pair medium to allow constant monitoring of medium integrity. When the Link
Test function is enabled, the absence of Link Test
pulses on the RXD+/– pair will cause the TPEX to go
into a Link Fail state. In Link Fail state, data transmission,
data reception, and the collision detection functions are
disabled, and remain disabled until valid data or >2
consecutive Link Test pulses appear on the RXD+/–
pair. During Link Fail, the LNKST pin is internally pulled
HIGH. When the link is identified as functional, the
LNKST pin is driven LOW and is capable of directly
driving a “link OK” LED. In order to interoperate with
systems that do not implement Link Test, this function
can be disabled by grounding the LNKST pin. When
disabled, the driver and receiver functions remain enabled irrespective of the presence or absence of data
or Link Test pulses on the RXD+/– pair. The transmitter
continues to generate Link Test pulses in the absence
of transmit data even if the Link Test function is
disabled.
Polarity Detection and Reversal
The TPEX receive function includes the ability to invert
the polarity of the signals appearing at the RXD ± pair if
the polarity of the received signal is reversed (such as
in the case of a wiring error). This feature allows data
packets received from a reverse-wired RXD ± input pair
to be corrected in the TPEX prior to transfer to the DTE
via the AUI interface (DI ± ). The polarity detection function is activated following reset or Link Fail, and will reverse the receive polarity based on both the polarity of
any previous Link Test pulses and the polarity of subsequent packets with a valid end transmit delimiter (ETD).
When in the Link Fail state, TPEX will recognize Link
Test pulses of either positive or negative polarity. Exit
from the Link Fail state is caused by the reception of
five to six consecutive Link Test pulses of identical polarity. On entry to the Link Pass state, the polarity of the
last five Link Test pulses is used to determine the initial
receive polarity configuration and the receiver is reconfigured to subsequently recognize only Link Test pulses
of the previously established polarity. This link pulse
algorithm is employed only until ETD polarity determination is made, as described later in this section.
Positive Link Test pulses are defined as received signals with a positive amplitude greater than 520 mV and
a pulse width of 60 ns to 200 ns. This positive excursion
may be followed by a negative excursion. This definition
is consistent with the expected received signal at a correctly wired receiver when a Link Test pulse that fits the
template of Figure 14-12 in the 10BASE-T standard is
generated at a transmitter and passed through 100 m
of twisted-pair cable.
Negative Link Test pulses are defined as received signals with a negative amplitude greater than 520 mV
and a pulse width of 60 ns to 200 ns. This negative excursion may be followed by a positive excursion. This
definition is consistent with the expected received signal
at a reverse wired receiver when a Link Test pulse that
fits the template of Figure 14-12 in the 10BASE-T
8 Am79C98
standard is generated at a transmitter and passed
through 100 m of twisted-pair cable.
The polarity detection/correction algorithm will remain
“armed” until two consecutive packets with valid ETD of
identical polarity are detected. When “armed,” the receiver is capable of changing the initial or previous
polarity configuration based on the most recent ETD
polarity.
On receipt of the first packet with valid ETD following
reset or Link Fail, TPEX will utilize the inferred polarity
information to configure its RXD ± input, regardless of
its previous state. On receipt of a second packet with a
valid ETD with correct polarity, the detection/correction
algorithm will “lock in” the initial polarity. If the second
(or subsequent) packet is not detected as confirming
the previous polarity decision, the most recently detected ETD polarity will be used as the new default.
Note that packets with invalid ETD have no effect on
updating the previous polarity decision. Once two consecutive packets with valid ETD have been received,
TPEX will disable the detection/correction algorithm
until either a Link Fail condition occurs or PRDN/RST
asserted.
During polarity reversal, the RXPOL pin is internally
pulled HIGH. During normal polarity conditions, the
RXPOL pin is driven LOW and is capable of directly
driving a “Polarity OK” LED using an integrated 16 mA
driver. If desired, the polarity reversal function can be
disabled by grounding the RXPOL pin.
is
Twisted-Pair Interface Status
Two outputs (XMT and RCV) indicate whether TPEX is
transmitting (AUI to twisted-pair) or receiving (twistedpair to AUI). Both signals are asserted during a collision. In Link Fail mode, RCV is disabled. In Jabber
Detect mode, XMT is disabled. Both signals are active
HIGH.
Collision Detect Function
Simultaneous carrier sense (presence of valid data signals) by both the AUI DO+/– pair and the RXD+/– pair
constitutes a collision, thereby causing a 10 MHz signal
to be asserted on the CI+/– output pair. The CI+/– output
meets the drive requirements for the AUI. This 10 MHz
signal will remain on the CI+/– pair until one of the two
colliding states changes from active to idle. The CI+/–
output pair stays HIGH for two bit times at the end of a
collision, decreasing to the idle level within eighty bit
times after the last LOW-to-HIGH transition. Both the
XMT and RCV pins are driven HIGH during collision.
Signal Quality Error (SQE) Test (Heartbeat)
Function
When the SQE
routinely exercise the collision detection circuitry by
generating an SQE message at the end of every trans-
TEST pin is driven LOW, TPEX will
mission. This signal is a self-test indication to the DTE
that the MAU collision circuitry is functional. An SQE
message consists of a 10 MHz signal on the CI+/–
pair with a duration of 8 bit times (800 ns). When enabled, an SQE Test will occur at the end of every transmission, starting eight bit times (800 ns) after the last
transition of the transmitted signal. For repeater applications, the SQE Test function can be disabled by tying
the SQE
TEST pin HIGH or by leaving it disconnected.
Jabber Function
The Jabber function inhibits the twisted-pair transmit
function of TPEX if the DO+/– circuit is active longer
than the time permitted to transmit the maximumlength 802.3/Ethernet data packet (50 ms nominal).
This prevents any one node from disrupting the network due to a “stuck on” or faulty transmitter. If this
maximum transmit time is exceeded, TPEX transmitter
circuitry is disabled and a 10 MHz signal is driven onto
the CI+/– pair. Once the transmit data stream is removed from the DO+/– pair of inputs, an “unjab” time of
250 ms to 750 ms will elapse before TPEX removes the
10 MHz signal from the CI+/– pair and re-enables the
transmit path.
Power Down
In addition to on-board power-on-reset circuitry, the
PRDN/RST
PRDN/RST must be driven LOW for a minimum of two
microseconds for reset to occur. The PRDN/RST pin
can also be used to put the TPEX into an inactive state,
causing the device to consume less power. This feature
is useful in battery-powered or low-duty-cycle systems.
Driving PRDN/RST LOW resets the internal logic of
TPEX and places the device into idle mode. In this
mode, the twisted-pair driver pins (TXD+/–,TXP+/–)
are driven LOW, the AUI pins (CI+/–, DI+/–) are driven
HIGH, the LNKST and RXPOL pins are in the inactive
state, and XMT and RCV are LOW. TPEX will remain in
idle as long as PRDN/RST is asserted. Following the
rising edge of the signal on PRDN/RST, TPEX will remain in the reset state for 10 µ s.
pin is used as the master reset for TPEX.
Test Modes
TPEX implements two types of loopback test modes
suitable for Station (DTE) or Repeater applications.
The Test mode is entered by driving the TEST pin
HIGH. The two types of test modes available are:
1. Station (DTE): SQE
pair is transmitted onto the TXD+/– and TXP+/–
pairs and data on the RXD+/– input pair is transmitted onto the DI+/– output pair. The jabber function
and collision detection functions are disabled.
2. Repeater: SQE TEST pin HIGH. Data on DO+/–
pair is looped back onto the DI+/– pair and data on
the RXD+/– pair is retransmitted on the twisted-pair
drivers (TXD+/– and TXP+/– pairs).
TEST pin LOW. Data on DO+/–
Am79C98 9
In both modes, the jabber circuitry, collision detection,
and collision oscillator functions are disabled and the
AUI and RXD+/– squelch circuits are active.
TPEX External Components
Figure 1 shows a typical twisted-pair port external
components schematic. The resistors used should
have a ± 1% tolerance to ensure interoperability with
10BASE-T-compliant networks. Filters and pulse transformers are necessary devices that have a major influence on the performance and compliance of a TPEX-
57.6
324.0
768.0
57.6
324.0
100 Ω
Am79C100
TPEX
TXD+
TXP+
TXD–
TXP–
RXD+
RXD–
based MAU. Specifically, the transmitted waveforms
are heavily influenced by filter characteristics and the
twisted-pair receivers employ several criteria to continuously monitor the incoming signal’s amplitude and
timing characteristics to determine when and if to assert the internal carrier sense. For these reasons, it is
crucial that the values and tolerances of the external
components be as specified. Several manufacturers
produce a module that combines the functions of the
transmit and receive filters and the pulse transformers
into one package.
1:1
1:1
TD+
TD–
Twisted-Pair
Cable
RD+
RD–
14395D-5
XMIT
Filter
RECV
Filter
Module
Note:
The filter/transformer module shown is available from the following manufacturers: Belfuse , TDK, Pulse Engineering, PCA, Valor
Electronics, and Nano Pulse.
Figure 1. Typical Twisted-Pair Port External Components
10 Am79C98
AMD
1
2
3
6
0.1 µF
Filter and
ANLG GND
0.1µF
RJ45
Connector
Module
Transformer
ANLG GND
57.6 Ω
324.0 Ω
TXD+
AVSS
AVDD
DO+
TD+
XMT
57.6 Ω
TXP+
DO-
TD–
Filter
768.0 Ω
TXD-
DI+
Note 1Note 2
324.0 Ω
TXP-
DI-
RD+
RCV
100 Ω
RXD+
CI+
RD–
Filter
RXD-
CI-
Am79C98
SQE^TEST
DGTL +5 V
LINK OK
LNKST
RCV
XMT
RX POL OK
RCV
XMT
RXPOL
REXT
TEST
330 Ω
100 K
47 pF 47 pF
DVSSDVDD
PWDN/RST
COL
DGTL GND
74HC132
0.01µF
Optional
0.1µF
14395D-7
DGTL GND
4.7µF
ANLG +5 V
0.01µF
Optional
40.2 Ω 40.2 Ω
Pulse
Transformer
AUI
Connector
Note 3
Enable Heartbeat
DGTL GND
Optional
24.3 kΩ 1%
ANLG +5 V
DGTL +5 V
Notes:
1. Compatible filter modules, with a brief description of package type
Figure 3. Typical TPEX System Application
and features are included in Table 1 of this section.
2. The resistor values are recommended for general purpose use, and should
allow compliance to the 10BASE-T specification for template fit and jitter
performance. However, the overall performance of the transmitter is also
affected by the transmit filter configuration.
3. Compatible AUI transformer modules, with a brief description of package type
and features are included in Table 2 of this section.
12 Am79C98
AMD
Table 1. TPEX Compatible Media Interface Modules
Manufacturer Part # Package Description
Bel Fuse A556-2006-DE 16-pin 0.3” DIL Transmit and receive filters and transformers
Bel Fuse 0556-2006-00 14-pin SIP Transmit and receive filters and transformers
Bel Fuse 0556-2006-01 14-pin SIP Transmit and receive filters, transformers and
Valor Electronics PT3877 16-pin 0.3” DIL Transmit and receive filters and transformers
Valor Electronics PT3983 8-pin 0.3” DIL Transmit and receive common mode chokes
Valor Electronics FL1012 16-pin 0.3” DIL Transmit and receive filters and transformers,
Nano pulse NP6612 16-pin 0.3” DIL Transmit and receive filters, transformers and
Nano pulse NP6581 8-pin 0.3” DIL Transmit and receive common mode chokes
Nano pulse NP6696 24-pin 0.6” DIL Transmit and receive filters, transformers and
TDK TLA 470 14-pin SIP Transmit and receive filters and transformers
TDK HIM3000 24-pin 0.6” DIL Transmit and receive filters, transformers and
Pulse Engineering PE65421 16-pin 0.3” DIL Transmit and receive filters and transformers
Pulse Engineering SUPRA 1.1 16-pin 0.5” DIL Transmit and receive filters and transformers,
Bel Fuse 0556-6392-00 16-pin 0.5” DIL Transmit and receive filters, transformers, and
common mode chokes
transmit common mode choke
common mode chokes
common mode chokes
common mode chokes
transmit common mode choke
common mode chokes
Table 2. Am79C98 TPEX Compatible AUI Transformers
Manufacturer Part # Package Description
Bel Fuse A553-0506-AB 16-pin 0.3” DIL 50 µH
Valor Electronics LT6031 16-pin 0.3” DIL 50 µH
TDK TLA 100-3E 16-pin 0.3” DIL 100 µH
Pulse Engineering PE64106 16-pin 0.3” DIL 50 µH
13Am79C98
AMD
ABSOLUTE MAXIMUM RATINGS
Storage Temperature: -65°C to +150°C. . . . . . . . . . .
Ambient Temperature Under Bias: 0°C to +70°C. . . .
Supply Voltage to AV
(AVDD, DVDD): –0.3 V to +6 V. . . . . . . . . . . . . . . . . . .
or DV
SS
SS
OPERATING RANGES
Commercial (C) Devices
Temperature (T
Supply Voltages (AV
Operating ranges define those limits between which the func-
): 0°C to +70°C. . . . . . . . . . . . . . . .
A
, DVDD): +5 V ± 5%. . . . . . . . .
DD
tionality of the device is guaranteed.
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
DC CHARACTERISTICS over COMMERCIAL operating range unless otherwise specified
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
Digital Input Voltage
V
IL
V
IH
Digital Output Voltage
V
OL
V
OH
Digital Input Leakage Current
I
ILL
I
ILD
AUI
I
IAXD
V
AICM
V
AIDV
V
ASQ
V
ATH
V
AOD
V
AODI
V
OFF DI+/- & CI+/- RL = 78 Ω -40 +40 mV
AOD
I
OFF DI+/- & CI+/- RL = 78 Ω -1 1 mA
AOD
V
AOCM
Input LOW Voltage DVSS-0.5 0.8 V
Input HIGH Voltage 2.0 0.5+DV
Output LOW Voltage I
= 16 mA (Open drain) 0.4 V
OL1
= 4.0 mA
I
OL2
DD
V
Output HIGH Voltage IOH = -0.4 mA 2.4 V
Input Leakage Current 0 < VIN < DVDD + 0.5 V 10 µA
Input Leakage Current 0 < VIN < DVDD + 0.5 V 500 µA
(Open drain pins,
output inactive)
Input Current at DO+, DO- -1 < Vin < AVDD + 0.5 V -500 500 µA
DO+/- Open Circuit Input IIN = 0 V AVDD - 3.0 AVDD - 1.0 V
Common Mode Voltage (Bias)
Differential Mode Input AV
= 5 V -2.5 +2.5 V
DD
Voltage Range (DO+/-)
DO+/- Squelch Threshold 160 -275 mV
DO+ Switching Threshold (Note 1) -35 +35 mV
Differential Output Voltage RL = 78 Ω 620 1100 mV
|(DI+) - (DI-)| OR |(CI+) - (CI-)|
DI+/- & CI+/- RL = 78 Ω -25 +25 mV
Differential Output (Note 1)
Voltage Imbalance
Differential Idle Output Voltage
Differential Idle Output Current (Note 1)
DI+/- & CI+/- Common RL = 78 Ω 2.5 AV
DD
V
Mode Output Voltage
14 Am79C98
AMD
DC CHARACTERISTICS (continued)
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
Twisted Pair Interface
I
IRXD
R
RXD
V
TIVB
V
TIDV
V
TSQ+
V
TSQ–
V
THS+
V
THS–
V
RXDTH
V
TXH
V
TXL
V
TXI
V
TXOFF
R
TX
I
IREXT
Power Supply Current
I
DD
I
DDPRDN
Input Current at RXD+/– AV
< VIN < AV
SS
DD
–500 500 µA
RXD+/– Differential Input (Note 1) 10 KΩ
Resistance
RXD+, RXD– Open Circuit Input IIN = 0 mA AVDD - 3.0 AVDD - 1.5 V
Voltage (Bias)
Differential Mode Input AVDD = +5 V –3.1 3.1 V
Voltage Range (RXD+/–)
RXD Positive Sinusoid 5 MHz < f< 10 MHz 300 520 mV
Squelch Threshold (Peak)
RXD Negative Sinusoid 5 MHz < f< 10 MHz –520 –300 mV
Squelch Threshold (Peak)
RXD Post-Squelch Positive Sinusoid 5 MHz < f< 10 MHz 150 293 mV
Threshold (Peak)
RXD Post-Squelch Negative Sinusoid 5 MHz < f< 10 MHz –293 –150 mV
Threshold (Peak)
RXD Switching Threshold (Note 1) –60 60 mV
TXD+/– and TXP+/– (Note 2) DVDD - 0.6 DV
Output HIGH Voltage DV
TXD+/– and TXP+/– (Note 2) DV
Output LOW Voltage DV
= 0 V
SS
= +5 V
DD
SS DVSS
DD
+ 0.6 V
V
TXD+/– and TXP+/– –40 +40 mV
Differential Output
Voltage Imbalance
TXD+/– and TXP+/– DVDD = +5 V –40 +40 mV
Differential Idle Output Voltage
TXD+/– and TXP+/– (Note 1) 40 Ω
Differential Driver
Output Impedance
Input Current at REXT Pin R
= 24.3K Ω ± 1% 120 µA
EXT
= +5 V
AV
DD
Power Supply Current PRDN/RST = HIGH 115 mA
(Transmitting 10 MHz Data)
(Typical TP load)
Power Supply Current PRDN/RST = HIGH 90 mA
(Transmitting 10 MHz Data)
(No TP load)
Power Supply Current PRDN/RST = LOW 4 mA
in Power Down Mode
15Am79C98
AMD
SWITCHING CHARACTERISTICS over COMMERCIAL
Parameter
Symbol Parameter Description Min Max Unit
Transmit Timing
t
PWODO
t
PWKDO
t
TON
t
TSD
t
DODION
t
DODISD
t
TETD
t
TR
t
TF
(90% to 10%)
t
TM
t
THD
t
TLD
t
THDP
t
TLDP
t
XMTON
t
XMTOFF
t
PERLP
t
PWLP
t
PWPLP
t
JA
t
JR
t
JREC
DO Pulse Width |VIN| > |V
|1535ns
ASQ
Accept/Reject Threshold (Note 3)
DO Pulse Width |VIN| > |V
| 105 200 ns
ASQ
Maintain/Turn-Off Threshold (Note 4)
Transmit Start Up Delay 300 ns
Transmit Static Propagation 120 ns
Delay (DO to TXD)
DO to DI Startup Delay 300 ns
DO to DI Static Propagation 100 ns
Delay
Transmit End of Transmission 250 450 ns
Transmitter Rise Time 10 ns
(10% to 90%)
Transmitter Fall Time 10 ns
Transmitter Rise and Fall 4 ns
Time Mismatch
DO L–>H to TXD+ L–>H Steady State t
– 1.0 t
TSD
+ 1.0 ns
TSD
and TXD- H->L Delay (Note 1)
DO H–>L to TXD+ H–>L Steady State t
– 1.0 t
TSD
+ 1.0 ns
TSD
and TXD– L–>H Delay (Note 1)
DO L–>H to TXP+ H–>L Steady State t
+ 40 t
TSD
+ 60 ns
TSD
and TXP- L->H Delay (Note 1)
DO H–>L to TXP+ L–>H Steady State t
+ 40 t
TSD
+ 60 ns
TSD
and TXP– H->L Delay (Note 1)
XMT Asserted Delay 100 ns
XMT De-asserted Delay 300 ns
Idle Signal Period 8 24 ms
Idle Link Test Pulse Width (Note 1) 75 120 ns
Predistortion Idle Link Test (Note 1) 40 60 ns
Pulse Width
Transmit Jabber 20 150 ms
Activation Time
Transmit Jabber 250 750 ms
Reset Time
Transmit Jabber 1.0 – µs
Recovery Time (Minimum time
gap between transmitted
packets to prevent jabber
activation)
16 Am79C98
AMD
SWITCHING CHARACTERISTICS (continued)
Parameter
Symbol Parameter Description Min Max Unit
Receive Timing
t
PWKRD
t
RON
t
RVB
t
RSD
Delay (RXD to DI)
t
RETD
t
RHD
t
RLD
t
RR
t
RF
Time (10% to 90%)
t
RM
t
RCVON
t
RCVOFF
Collision Detection and SQE Test
t
CON
t
COFF
t
PER
t
CPW
t
SQED
t
SQEL
Notes:
1. Parameter not tested.
2. Uses switching test load.
3. DO pulses narrower than t
4. DO pulses narrower than t
internal DO carrier sense off.
5. RXD pulses narrower than t
internal RXD carrier sense off.
RXD Pulse Width |VIN| >|V
| 136 200 ns
THS
Maintain/Turn-Off Threshold (Note 5)
Receiver Start Up Delay 5 MHz Sinusoid 200 400 ns
(RXD to DI+/–)
First Validly Timed Bit t
+100 ns
RON
on DI+/– (RXD to DI)
Receiver Static Propagation 70 ns
DI End of Transmission 200 ns
RXD L–>H to DI+ L–>H (Note 1) t
– 2.5 t
RSD
+ 2.5 ns
RSD
and DI– H–>L Delay
RXD H–>L to DI+ H–>L (Note 1) t
– 2.5 t
RSD
+ 2.5 ns
RSD
and DI- L->H Delay
DI+, DI–, CI+, CI– Rise 5.0 ns
Time (10% to 90%)
DI+, DI–, CI+, CI– Fall 5.0 ns
DI+/– & CI+/– Rise and Fall 2.0 ns
Time Mismatch (|t
RCV Asserted Delay t
RCV De-asserted Delay t
RR
– tRF|)
– 50 t
RON
+ 100 ns
RON
+ 250 ns
RSD
Collision Turn-On 500 ns
Delay (CI+/–)
Collision Turn-Off 500 ns
Delay (CI+/–)
Collision Period (CI+/–) 87 117 ns
Collision Output Pulse Width 40 60 ns
(CI+/-)
SQE Test Delay Time 600 1600 ns
SQE Test Length 500 1500 ns
(min) will be rejected; pulses wider than t
PWODO
(min) will maintain internal DO carrier sense on; pulses wider than t
PWKDO
(min) will maintain internal RXD carrier sense on; pulses wider than t
PWKRD
(max) will turn internal DO carrier sense on.
PWODO
(max) will turn
PWKDO
PWKRD
(max) will turn
17Am79C98
AMD
SWITCHING WAVEFORMS
t
PWPLP
TXD+
TXP+
t
PWPLP
TXD–
TXP–
t
PWLP tPERLP
14395D-9
SWITCHING TEST CIRCUITS
TXD+
TXD–
Includes test
jig capacitance
TXP+
TXP–
Includes test
jig capacitance
TP Idle Link Test Pulse
DV
DD
294 Ω
DV
294 Ω
SS
100 pF
TXD Switching Test Circuit
DV
DD
715 Ω
100 pF
715 Ω
Test Point
14395D-10
Test Point
DV
SS
14395D-11
TXP Switching Test Circuit
19Am79C98
AMD
RECEIVE TEST CIRCUIT
DV
DD
DO + / –
RXD + / –
CI +
CI –
t
CON
DI+
DI–
CI+
CI–
52.3 Ω
Test Point
DV
154 Ω
SS
100 pF
AUI DI, CI Switching Test Circuit
t
COFF
14395D-13
DO + / –
CI +
CI –
t
CPW tPER
Collision Timing
t
SQED
t
SQEL
SQE Test Timing (SQE^Test Pin Connected to VSS)
14395D-14
14395D-15
21Am79C98
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am186, Am386, Am486, Am29000,
PCnet-
FAST
, PCnet-
FAST
Micro Devices, Inc.
Microsoft is a registered trademark of Microsoft Corporation.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
+, PCnet-Mobile, QFEX, QFEXr, QuASI
b
IMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet,
,
QuEST , QuIET, TAXIchip , TPEX, and TPEX Plus are trademarks of Advanced
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