AMD Advanced Micro Devices AM79C98JC Datasheet

■

FINAL

Am79C98

Twisted-Pair Ethernet Transceiver (TPEX)

DISTINCTIVE CHARACTERISTICS

CMOS device provides compliant operation and low operating current from a single +5 V supply

Power Down mode provides reduced power consumption for battery-powered applications. Reset capability allows use in remote MAU applications.

Pin-selectable twisted-pair receive polarity detection and automatic inversion of the receive signal. Polarity indication output pin can directly drive an LED.

Pin-selectable twisted-pair Link Integrity Test capability conforming to the IEEE 802.3 standard for 10BASE-T. Link status pin can directly drive an LED.

Internal twisted-pair transmitter digital predistortion circuit reduces medium-induced jitter and ensures compliance with the 10BASE-T transmit and receive waveform requirements

Pin-selectable SQE Test (heartbeat) enable Transmit and receive status indications are

available on separate, dedicated pins AUI loopback, Jabber Control, and SQE Test

functions comply with the 10BASE-T standard IEEE Std 802.3i-1990

GENERAL DESCRIPTION

The Am79C98 Twisted-Pair Ethernet Transceiver (TPEX) is an integrated circuit that implements the medium attachment unit (MAU) functions for the twisted-pair medium, as speciﬁed by the IEEE 802.3 standard (Type 10BASE-T). This device provides the necessary electrical and functional interface between the IEEE 802.3 standard attachment unit interface (AUI) and the twisted-pair cable.

A network based on the 10BASE-T standard can use unshielded twisted-pair cables, providing an economical solution to networking by allowing the use of existing telephone wiring. The Am79C98 provides a minimal component count and cost-effective solution to the design and implementation of 10BASE-T standard networks.

TPEX provides twisted-pair driver and receiver circuits, including on-board transmit digital predistortion, receiver squelch, and an AUI port with pin-selectable SQE Test enable. The device also provides a number of additional features, including pin-selectable TwistedPair Receive Polarity Detection and Automatic Polarity Reversal, Link Status indication, Link Test disable function, and transmit and receive status. The Twisted-Pair Polarity and Link Status pins can be used to drive LEDs directly.

The Am79C98 is fabricated in CMOS technology and requires a single +5 V supply. The device is available in 24-pin SKINNYDIP plastic leaded chip carrier (PLCC) packaging.

plastic dual in-line and 28-pin

Publication# 14395 Rev: DAmendment/0 Issue Date: May 1994

BLOCK DIAGRAM

Twisted-Pair

Interface

TXD–

TXD+

Line Driver

TXP–

TXP+

and

Predistortion

Jabber

Control

LNKST

Link T est

and

Collision

RXD–

RCV

Loopback

RXD+

and

Line Receiver

and

Polarity Detect

Smart Squelch

Auto Reversal

RXPOL

Voltage

Oscillator

Controlled

and

CI+

Line Driver

CI–

DI+

SQE TEST

Line Receiver

DO+

Squelch Circuit

DO–

XMT

2 Am79C98

Line Driver

DI–

REXT

TEST

PRDN/RST

(AUI)

Attachment

Unit Interface

14395D-1

AMD

RELATED AMD PRODUCTS

Part No. Description

Am7996 IEEE-802.3/Ethernet/Cheapernet Tap Transceiver Am79C100 Twisted-Pair Ethernet Transceiver Plus (TPEX+) Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)

)

(ILACCTM)



(HIMIBTM)

Plug n’ Play support)

Am79C900 Integrated Local Area Communications Controller Am79C940 Media Access Controller for Ethernet (MACE Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus) Am79C961 PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft Am79C965 PCnet-32 Single-Chip Ethernet Controller (for 386DX, 486 and VL buses) Am79C970 PCnet-PCI Single-Chip Ethernet Controller (for PCI bus) Am79C974 PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems Am79C981 Integrated Multiport Repeater Plus

(IMR+TM)

Am79C987 Hardware Implemented Management Information Base

CONNECTION DIAGRAM Top View

DIP

CI+ CI– DI+ DI–

XMT

LNKST

DO+ DO–

PRDN/RST

REXT

Note:

Pin 1 is marked for orientation

1 2 3 4 5 6 7 8

9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

TXD+ TXD– TXP+ TXP– DV

TEST

SQE^TEST

RXD+ RXD–

RXPOL RCV

14395D-2

XMT

LNKST

DO+

5 6 7 8 9

10 11

DI–

DO–

DI+

PLCC

CI–

CI+

1324

15131412 161718

RCV

REXT

PRDN/RST

TXD–

TXD+

282726

RXD–

RXPOL

TXP+

25 24 23 22 21

20 19

RXD+

TXP– DV

TEST

SQE^TEST

14395D-3

3Am79C98

AMD

LOGIC SYMBOL

DD AVDD

TXD+ TXP+

TXD– TXP–

RXD+ RXD–

LNKST RXPOL

XMT RCV

Twisted Pair

Interface

14395D-4

Attachment

Unit Interface

(AUI)

DO+ DO–

DI+ DI–

CI+ CI–

SQE TEST

TEST REXT

PRDN/RST

Am79C98

SS AVSS

4 Am79C98

ORDERING INFORMATION Standard Products

AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below.

AM79C98

DEVICE NUMBER/DESCRIPTION

Am79C98 Twisted-Pair Ethernet Transceiver (TPEX)

Valid Combinations

AM79C98 PC, JC

OPTIONAL PROCESSING

Blank = Standard Processing

TECHNOLOGY

C = CMOS Electrically Erasable

PACKAGE TYPE

P=24-Pin Plastic DIP (PD 3024) J=28-Pin Plastic Leaded Chip Carrier (PL 028)

SPEED

Not Applicable

Valid Combinations

Valid combinations list conﬁgurations planned to be supported in volume for this device. Consult the local AMD sales ofﬁce to conﬁrm availability of speciﬁc valid combinations and to check on newly released combinations.

Am79C98 5

PIN DESCRIPTION AV

Analog Power

This pin supplies +5 V to analog portions of the TPEX circuitry.

Analog Ground

This pin is the ground reference for analog portions of the TPEX circuitry.

CI+, CI–

Control In Output

AUI port differential driver.

DI+, DI–

Data In Output

AUI port differential driver.

DO+, DO–

Data Out Input

AUI port differential receiver.

Digital Power

This pin supplies +5 V to digital portions of the TPEX circuitry.

Digital Ground

This pin is the ground reference for digital portions of TPEX circuitry.

LNKST

Link Status Open Drain, Input/Output

When this pin is tied LOW, the internal Link Test Receive function is disabled and the Transmit and Receive functions will remain active irrespective of arriving idle Link Test pulses and data. TPEX continues to generate idle Link Test pulses irrespective of the status of this pin.

As an output, this pin is driven LOW if the link is identified as functional. However, if the link is determined to be nonfunctional, due to missing idle Link Test pulses or data packets, then this pin is not driven. In the LOW output state, the pin is capable of sinking a maximum of 16 mA and can be used to drive an LED.

This pin is internally pulled HIGH when inactive.

PRDN/RST

Power Down/Reset Input, Active LOW

Driving this input LOW resets the internal logic of TPEX and places the device in a special Power Down mode. In the Power Down/Reset mode, all output drivers are placed in their inactive state.

RCV

Receive Output

This pin is driven HIGH while TPEX is receiving data on the RXD pins and is transferring the received signal onto the AUI DI pair. The RCV and XMT pins are simultaneously driven HIGH during collision.

REXT

External Resistor Input

An external precision resistor is connected between this pin and AV ence for the internal voltage-controlled oscillator (VCO).

in order to provide a voltage refer-

RXD+, RXD–

Receive Data Input

10BASE-T port differential receivers.

RXPOL

Receive Polarity Open Drain, Input/Output

The twisted-pair receiver is capable of detecting a receive signal with reversed polarity (wiring error). The RXPOL pin is normally in the LOW state, indicating correct polarity of the received signal. If the receiver detects reversed polarity, then this pin is not driven (goes HIGH) and the polarity of subsequent packets is inverted. In the LOW output state, this pin can sink up to a maximum of 16 mA and is therefore capable of driving an LED.

This feature can be disabled by strapping this pin LOW. In this case, the Receive Polarity correction circuit is disabled and the internal receive signal remains noninverted, irrespective of the received signal.

This pin is internally pulled HIGH when inactive.

SQE

TEST

Signal Quality Test (Heartbeat) Enable Input, Active LOW

The SQE Test function is enabled by tying this input LOW.

This input is internally pulled HIGH when inactive.

6 Am79C98

TEST

Test Input, Active HIGH

This pin should be tied HIGH for normal operation. If this pin is driven LOW, TPEX will enter Loopback Test mode. The type of loopback is determined by the state of the SQE (Station MAU), TPEX transfers data independently from DO to the TXD/TXP circuit and from RXD to the DI circuit. If the SQE TEST is in the HIGH state (Repeater MAU), then data on the RXD circuit is transmitted back onto the TXD/TXP circuit and data on the DO circuit is transmitted onto the DI pair.

TEST pin. If this pin is in the LOW state

TXD+, TXD–

Transmit Data Output

10BASE-T port differential drivers.

TXP+, TXP–

Transmit Predistortion Output

Transmit waveform predistortion control.

XMT

Transmit Output

This pin is driven HIGH while TPEX is receiving data on the AUI DO pair and is transmitting data on the TXD/ TXP pins. The XMT and RCV pins are simultaneously driven HIGH during collision.

Am79C98 7

+ 15 hidden pages