AMD Advanced Micro Devices AM79C988AJCT Datasheet
PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 19880 Rev: B Amendment/+2
Issue Date: November 1997
Am79C988A
Quad Integrated Ethernet Transceiver (QuIET™)
DISTINCTIVE CHARACTERISTICS
■
Four independent 10BASE-T transceivers
compliant with IEEE 802.3 Section 14
(10BASE-T MAUs)
■
Direct interface with AMD's Am79C983A IMR2™
repeater device
■
On-chip filtering
— Eliminates external transmit and receive filters
— Meets IEEE 802.3 (Section 14.3) electrical
requirements
— Enables port switching when used with the IMR2
device
■
Automatic polarity detection and correction
■
Serial management interface allows transfer of
command and status data between the QuIET
device and a controller (IMR2 or other device)
■
Standard Ethernet (Normal) and Full-Duplex
modes
■
Extended distance option to accommodate
lines longer than 100 meters
■
Test functions pr ovided for Loopback, Link T est,
Reverse Polarity, and Jabber
■
44-pin PLCC CMOS device with a single 5-V
supply
GENERAL DESCRIPTION
The Am79C988A Quad Integrated Ethernet Transceiver
(QuIET) device consists of four independent 10BASE-T
transceivers which are compliant with the IEEE 802.3
Section 14 (
Medium Attachment Unit for 10BASE-T
Cabling
) standard. When combined with AMD's
Integrated Multiport Repeater 2 (IMR2™) chip, the
QuIET device provides a system-level solution to
designing a managed 10BASE-T repeater.
The QuIET device includes on-chip filtering for both
transmit and receive functions, thus eliminating the
need for external filters. On-chip filter ing meets IEEE
802.3 (Section 14.3) electrical requirements. The
QuIET device provides automatic polarity detection and
correction and can operate in either normal or fullduplex mode.
The QuIET device interfaces directly with the Pseudo
AUI (PAUI™) ports on the IMR2 (Am79C983A) device
and can also be connected to standard AUI ports. Command and status data are exchanged with the IMR2
device via a serial management interface. Port switching can be easily implemented with the IMR2/QuIET
chipset to move individual ports between multiple Ethernet segments under software control.
For application examples on building fully-managed
repeaters using the QuIET and IMR2 devices, refer to
AMD’s
IMR2 T echnical Manual
(PID 19898A).
The QuIET chip is packaged in a 44-pin plastic leaded
chip carrier (PLCC). The device is fabricated in CMOS
technology and requires a single 5-V supply.
2 Am79C988A
PRELIMINARY
BLOCK DIAGRAM
QuIET Device
PDO[0]
PAUI Port
Line Drivers
and Receivers
PDO Squelch
Line Driver and
Wave-Shaping
TXD+
TXD-
TXD[0]+
TXD[0]-
PDI[0]
PCI[0]
PDO[1]
PAUI Port
Line Drivers
and Receivers
PDO Squelch
PDI[1]
PCI[1]
PDO[2]
PAUI Port
Line Drivers
and Receivers
PDO Squelch
PDI[2]
PCI[2]
PDO[3]
PAUI Port
Line Drivers
and Receivers
PDO Squelch
PDI[3]
PCI[3]
Internal Bias Reference
and Phase-Lock Loop
Serial Management Port
Control and Status
REXT
SDATA
DIR
CLK
RST
Collision, Loopback,
Jabber and Link Test
Line Receiver and
Smart Squelch
RXD+
RXD-
RXD[0]+
RXD[0]-
Line Driver and
Wave-Shaping
TXD+
TXD-
TXD[1]+
TXD[1]-
Line Receiver and
Smart Squelch
RXD+
RXD-
RXD[1]+
RXD[1]-
Line Driver and
Wave-Shaping
TXD+
TXD-
TXD[2]+
TXD[2]-
Line Receiver and
Smart Squelch
RXD+
RXD-
RXD[2]+
RXD[2]-
Line Driver and
Wave-Shaping
TXD+
TXD-
TXD[3]+
TXD[3]-
Line Receiver and
Smart Squelch
RXD+
RXD-
RXD[3]+
RXD[3]-
19880B-1
Am79C988A 3
PRELIMINARY
RELATED AMD PRODUCTS
Part No.
Description
Am79C981
Integrated Multiport Repeater+ (IMR+™)
Am79C982
b
asic Integrated Multiport Repeater (
b
IMR™)
Am79C983A Integrated Multiport Repeater 2 (IMR2™)
Am79C987 Hardware Implemented Management Information Base (HIMIB™)
Am7990 Local Area Network Controller for Ethernet (LANCE)
Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver
Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)
Am79C98 Twisted Pair Ethernet Transceiver (TPEX)
Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)
Am79C900 Integrated Local Area Communications Controller (ILACC™)
Am79C940 Media Access Controller for Ethernet (MACE™)
Am79C960 PCnet™-ISA Single-Chip Ethernet Controller (for ISA bus)
Am79C961 PCnet™-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft® Plug n’ Pla y® Support)
Am79C961A PCnet™-ISA II Full Duplex Single-Chip Ethernet Controller for ISA
Am79C965 PCnet™-32 Single-Chip 32-Bit Ethernet Controller
Am79C970 PCnet™-PCI Single-Chip Ethernet Controller (for PCI bus)
Am79C970A PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus)
Am79C974 PCnet™-SCSI Combination Ethernet and SCSI Controller for PCI Systems
4 Am79C988A
PRELIMINARY
CONNECTION DIAGRAM
1
44
43
42
5
4
3
2
6 41
40
7
8
9
10
11
12
13
14
15
16
17
23
24
25
26
19
20
21
22
18 27
28
39
38
37
36
35
34
33
32
31
30
29
DVSS
RST
REXT
TEST
DIR
CLK
SDATA
DVDD
TXD3+
TXD3AVSS
PDI0
PDO0
AVDD
TXD0+
TXD0-
AVSS
TXD1+
TXD1-
AVDD
TXD2+
TXD2-
RXD3-
RXD3+
AVSS
RXD2-
RXD2+
AV
DD
RXD1-
RXD1+
AVSS
RXD0-
RXD0+
PCI0
PDO1
PDI1
PCI1
PDO2
PDI2
PDO3
PDI3
PCI2
PCI3
DVSS
Am79C988A
19880B-2
Am79C988A 5
PRELIMINARY
LOGIC DIAGRAM
LOGIC SYMBOL
Ports
PAUI
TP
TP
TP
TP
Serial
Interface
PAUI
PAUI
PAUI
19880B-3
PDO
PDI
PCI
DIR
SDATA
CLK
RST
TXD+
TXD-
RXD+
RXD-
DV
SS
AV
SS
DV
DD
AV
DD
Twisted
Pair Ports
(4 Ports)
Pseudo Attachment
Unit Interface
(PAUI) Ports
(4 Ports)
Am79C988
Serial
Management
Interface
A
19880B-4
6 Am79C988A
PRELIMINARY
ORDERING INFORMATION
Standard Products
AMD standard products are available in se v eral packages and oper ating ranges. The order number (Valid Combination) is f ormed
by a combination of:
Valid Combinations
Valid Combinations table
list configurations planned to be
supported in volume for this device. Consult the local AMD
sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Am79C988B
OPTIONAL PROCESSING
Blank = Standard processing
TEMPERATURE RANGE
C = Commercial (0˚C to +70˚C)
P A CKA GE TYPE
J = 44-pin Plastic Leaded chip carrier
(PL 044)
SPEED OPTION
Not applicable
J C
DEVICE NUMBER/DESCRIPTION
Am79C988B
Quad Integrated Ethernet
Transceiver (QuIET™)
Valid Combinations
Am79C988B JC\T
Am79C988A 7
PRELIMINARY
PIN DESCRIPTION
Analog
PDO
0-3
Pseudo AUI Data Output
Input
Single-ended receiver . Data input from the IMR2 device .
PDI
0-3
Pseudo AUI Data Input
Output
Single-ended output driver. Data output to the
IMR2 device.
PCI
0-3
Pseudo AUI Collision Input
Output
Single-ended output driver. Collision output to the
IMR2 device.
TXD+
0-3
, TXD-
0-3
Transmit Data
Output
10BASE-T port differential drivers.
RXD+
0-3
, RXD-
0-3
Receive Data
Input
10BASE-T port differential receivers.
REXT
External Resistor
Input
REXT must be tied to AV
DD
through a 13 k Ω ± 1%
resistor.This provides the current ref erence f or all internal analog functions.
AV
DD
Analog Power
Power Pin
These pins supply +5-V power to the analog portion of
the device. These pins should be decoupled and kept
separate from the digital power plane.
AV
SS
Analog Ground
Ground Pin
These pins provide the ground reference f or the analog
portions of the QuIET circuitry.
Digital
SDATA
Serial Data
Input/Output
Transfers command and status data between the
QuIET device and the IMR2 chip.
DIR
Direction
Input
Selects the direction of command data and status data
transfer between the QuIET device and the IMR2 chip.
RST
Reset
Input, Active Low
Resets the internal registers of the QuIET device.
CLK
Clock
Input
20-Mhz clock signal. The clock signal should be the
same one that is used by all IMR2 devices connected
to the QuIET chip.
TEST
Input, Active High
Reserved for factory use only. This pin does have an
internal pull-down, but should be tied LOW for
normal operation.
DV
DD
Digital Power
Power Pin
These pins supply +5-V power to the digital portion of
the device. These pins should be decoupled and kept
separate from the analog power plane.
DV
SS
Digital Ground
Ground Pin
These pins provide the ground reference for the digital
portions of the QuIET circuitry.
Note: All digital I/O pins are CMOS and TTL compatible .
8 Am79C988A
PRELIMINARY
FUNCTIONAL DESCRIPTION
Overview
The Am79C988A Quad Integrated Ethernet Transceiver
(QuIET
™
) device consists of four independent 10BASE-T
transceivers which are compliant with the IEEE 802.3 Section 14 (
Medium Attachment Unit for 10BASE-T Cabling
)
standard. The QuIET device includes on-chip filtering for
both transmit and receive functions, thus eliminating the
need for external filters. It provides automatic polarity
detection and correction and can operate in either normal
or full-duplex mode.
The QuIET device interfaces directly with the Pseudo
AUI (PAUI
™
) ports on the IMR2 (Am79C983A) device.
PAUI ports are functionally equivalent to the AUI interface as described in IEEE 802.3 Section 7, but are
single-ended and do not have the drive capability
specified in the standard. The QuIET device can also
be connected to standard AUI ports. Command and
status data is exchanged with the IMR2 device via a
serial management interface.
Twisted Pair Transmitters
Each TXD port is a differential twisted pair driver. When
properly terminated, TXD meets the 10BASE-T transmitter electrical requirements as specified in IEEE 802.3
Section 14.3.1.2. Proper termination, Figure 1, consists
of a single 110 ohm +
1% resistor across TXD+ and TXDand a 1:1 standard Ethernet transformer. A common
mode may be required for EMI considerations. An external capacitor is not required. The load is a twisted
pair cable that meets IEEE 802.3, Section 14.4 requirements. The cable is terminated at the other end by a
100 ohm load.
The TXD signal is filtered on the chip to reduce harmonic
content per IEEE 802.3 Section 14.3.2.1 (10BASE-T).
Since filtering is performed by the QuIET device, the
TXD signal can be connected directly to a standard
transformer. External filter modules are not required.
Figure 1. TXD Termination
Twisted Pair Receivers
Each RXD port is a differential twisted-pair receiver.
When properly terminated, RXD ports will meet the electrical requirements for 10BASE-T receivers as specified
in IEEE 802.3, Section 14.3.1.3. Proper termination is
shown in Figure 2. Each receiver has internal filtering and
does not require external filter modules.
Figure 2. RXD Termination
Receive squelch threshold voltage can be programmed
for extended distance mode. In this mode, the differential
receive threshold is reduced to allow cable lengths greater
than the 100 meters specified in the IEEE 802.3 Standard.
Polarity Detection and Reversal
The receive function includes the ability to invert the polarity of the signals appearing at the RXD+
pair if the
polarity of the received signal is reversed (such as in the
case of a wiring error). The polarity detection function is
activated following Reset or Link F ail, and will rev erse the
receive polarity based on both the polarity of any previous
Link Test Pulses and the polarity of subsequent packets
with a valid End Transmit Delimiter (ETD).
When in the Link Fail State, the QuIET de vice will recognize Link Test Pulses of either positive or negative polarity . Exit from the Link Fail state is caused by the reception
of five-to-sev en consecutive Link Test Pulses of identical
polarity . Both Link Test Pulses and packets are used to
determine the initial receive polarity . Once correct polarity
is established, the receiver subsequently accepts only
Link Test Pulses that are recognized as TRUE rather than
inverted.
The Link Test pulse follows the template of Figure
14-12 of the IEEE 802.3 10BASE-T standard.
Link Test Function
The Link Test function is implemented as specified in
the IEEE 802.3 10BASE-T standard. A Link Test pulse
is transmitted if a port has been idle for a period of more
than approximately 16 (+/-8) milliseconds (ms).
The QuIET device monitors the 10BASE-T ports for
packet and Link Pulse activity. If neither a packet nor a
Link Test pulse is receiv ed for 79 ms to 102 ms, the port
will enter the Link Test Fail State and the QuIET de vice
will inhibit the transmit and receive functions for that
port. Link pulses are transmitted when idle conditions
are met. When a packet or five-to-seven consecutive
Link Test pulses is received, the port exits the Link Fail
State and transmit/receive functions are restored.
19880B-5
TXD+
TXD-
110 Ω
1:1
Twisted Pair
100 Ω
RXD+
RXD-
1:1
Twisted Pair
100 Ω
100 Ω
19880B-6
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