AMD Advanced Micro Devices AM79C985KCW, AM79C985JC Datasheet
PRELIMINARY
Am79C985
enhanced Integrated Multiport Repeater Plus (eIMR+™)
DISTINCTIVE CHARACTERISTICS
■
Repeater functions compliant with IEEE 802.3
Repeater Unit specifications
■
Direct interface with the Am79C987 Hardware
Implemented Management Information Base
(HIMIB™) device for building a basic managed
multiport repeater
■
Full software backwards compatibility with
existing hub designs using Integrated Multiport
Repeater Plus (IMR+™)/HIMIB devices
■
Network management and optional feature
accessibility through a dedicated serial
management port
■
Four integral 10BASE-T transceivers with onchip filtering eliminating the need for external
filter modules on the 10BASE-T transmit-data
(TXD) and receive-data (RXD) lines
■
One Reversible Attachment Unit Interface
(RAUI™) port used either as a standard IEEEcompliant AUI port for connection to a Medium
Attachment Unit (MAU) or a reversed port for
direct connection to a Media Access Controller
(MAC)
■
Low cost suitable for managed multiport
repeater designs
■
Number of repeater ports easily expandable
with support for up to seven eIMR+ devices
without the need for an external arbiter
■
All ports capable of being individually isolated
(partitioned) in response to excessive collision
conditions or fault conditions
■
Flexible LED support for individual port status
and network utilization LEDs
■
Programmable extended distance mode on RXD
lines allowing connection to cables longer than
100 meters
■
Link Test function and Link Test pulse
transmission capable of being disabled through
the management port allowing devices that do
not implement the Link Test function to work
with the eIMR+ device
■
Programmable automatic polarity detection and
correction option permitting automatic
recovery from wiring errors
■
Full amplitude and timing regeneration for
retransmitted waveforms
■
CMOS device with a single +5-V supply
GENERAL DESCRIPTION
The enhanced Integrated Multiport Repeater Plus
(eIMR+) device is a VLSI integrated circuit that provides a system-level solution to designing managed
multiport repeaters. The device integrates the repeater
functions specified in Section 9 of the IEEE 802.3
standard and Twisted Pair Transceiver functions complying with the 10BASE-T standard.
The eIMR+ device provides f our Twisted Pair (TP) ports
and one reversible AUI (RAUI) port for direct connection to a MAC. The total number of ports per repeater
unit can be increased by connecting multiple eIMR+
devices through their expansion ports, hence, minimizing the total cost per repeater port.
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
The eIMR+ device also provides a connection to the
Am79C987 HIMIB device. The HIMIB device monitors
all the necessary counters, attributes, actions, and
notifications specified by IEEE 802.3, Section 19
(Layer Management f or 10 Megabit per second (Mbps)
Baseband Repeaters). When the eIMR+ and HIMIB
devices are used together as a chip set, they provide a
cost-effective solution to the problem of designing
10BASE-T basic managed multiport repeaters.
The device is fabricated in CMOS technology and
requires a single +5-V supply.
Publication# 20651 Rev: B Amendment/0
Issue Date: January 1998
BLOCK DIAGRAM
TX
MUX
Preamble
PRELIMINARY
Jam Sequence
SELI[1:0]
ACK
SELO
COL
Expansion Port
DAT
JAM
LDA[4:0], LDB[4:0]
STR
LDGA, LDGB
LDC[2:0]
ACT[7:0]
LED
Interface
SI
SI_D
Test
SO
SCLK
AMODE
CRS_I
and
Port
Management
CRS
FIFO
Decoder
Manchester
RX
RX
AUI
Port
DI±
CI±
MUX
MUX
DO±
Lock
Phase
FIFO
CONTROL
Loop
TP
RXD±
0
Port
TXD±
Encoder
Manchester
Control
eIMR+ Chip
3
TP
Port
TXD±
RXD±
Link T est
Partitioning
Reset
RST
Clock
Gen
CLK
Timers
20651B-1
.
2 Am79C985
PRELIMINARY
ORDERING INFORMATION
Standard Products
AMD standard products are available in se v eral packages and oper ating ranges. The order number (Valid Combination) is f ormed
by a combination of the elements below.
Am79C985
J
\W
C
ALTERNATE PACKAGING OPTION
\W = Trimmed and formed in a tray
TEMPERATURE RANGE
C = Commercial (0˚C to +70˚C)
P ACKA GE TYPE
J = 84-Pin Plastic Leaded Chip Carrier (PL 084)
K = 100-Pin Plastic Quad Flat Pack (PQR100)
SPEED OPTION
Not Applicable
Valid Combinations
Am79C985 JC, KC\W
DEVICE NUMBER/DESCRIPTION
Am79C985
enhanced Integrated Multiport Repeater Plus (eIMR+)
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am79C985 3
RELATED PRODUCTS
PRELIMINARY
Part No.
Am7990
Am7992B Serial Interface Adapter (SIA)
Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver
Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)
Am79C98 Twisted Pair Ethernet Transceiver (TPEX)
Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)
Am79C981 Integrated Multiport Repeater Plus (IMR+™)
Am79C982 basic Integrated Multiport Repeater (bIMR™)
Am79C983 Integrated Multiport Repeater 2 (IMR2™)
Am79C984A enhanced Integrated Multiport Repeater (eIMR™)
Am79C987 Hardware Implemented Management Information Base (HIMIB™)
Am79C988 Quad Integrated Ethernet Transceiver (QuIET™)
Am79C900 Integrated Local Area Communications Controller (ILACC™)
Am79C940 Media Access Controller for Ethernet (MACE™)
Am79C960 PCnet™-ISA Single-Chip Ethernet Controller (for ISA bus)
Am79C961 PCnet™-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft® Plug n’ Play® Support)
Am79C961A PCnet™-ISA II Full Duplex Single-Chip Ethernet Controller for ISA
Am79C965 PCnet™-32 Single-Chip 32-Bit Ethernet Controller
Am79C970 PCnet™-PCI Single-Chip Ethernet Controller (for PCI bus)
Am79C970A PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus)
Am79C974 PCnet™-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Local Area Network Controller for Ethernet (LANCE)
Description
.
4 Am79C985
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
RELATED PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
CONNECTION DIAGRAMS (PL 084) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
CONNECTION DIAGRAMS (PQR100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
LOGIC SYMBOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
LOGIC DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PIN DESIGNATIONS (PL084) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Listed by Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PIN DESIGNATIONS (PQR100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Listed by Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AUI Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Twisted Pair Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Expansion Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Management Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LED Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
FUNCTIONAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Basic Repeater Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Repeater Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Signal Regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Jabber Lockup Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Collision Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Fragment Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Auto Partitioning/Reconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Detailed Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
AUI Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
TP Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Twisted Pair Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Connection to Alternate Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Twisted Pair Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Link Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Visual Status Monitoring (LED) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Network Activity Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Internal Arbitration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
IMR+ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Management Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
eIMR+ /HIMIB Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Management Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Command/Response Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Port Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Management Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
SET (Write Commands) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Get (Read Commands) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SYSTEMS APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
eIMR+ to TP Port Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Twisted Pair Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Twisted Pair Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PRELIMINARY
Am79C985 5
PRELIMINARY
AUI Port Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Internal Arbitration Mode Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
IMR+ Mode External Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
eIMR+ Internal Arbitration Mode Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
IMR+ Mode External Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Visual Status Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
DC CHARACTERISTICS over Commercial operating ranges unless otherwise specified . . . . . .35
SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
KEY TO SWITCHING WAVEFORMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SWITCHING TEST CIRCUIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
APPENDIX A - SECURITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
6 Am79C985
PRELIMINARY
CONNECTION DIAGRAMS (PL 084)
REXT
AVSS
DI+
DI–
VDD
CI+
CI–
AVSS
DO+
DO–
AMODE
STR
DVSS
CRS_I
SI_D
VDD
RST
CLK
DVSS
SELI_0
SELI_1
12
13
14
15
16
17
18
19
20
21
23
24
25
26
27
28
29
30
31
32
RXD3–
102211
33
34
SELO
RXD3+
RXD2–
8
9
35
36
COL
DVSS
RXD1–
RXD2+
7
6
38
37
DAT
ACK
RXD0–
RXD1+
4
5
40
39
JAM
VDD
TXD3–
VDD
RXD0+
3
2
1
eIMR+
Am79C985
41
42
43
SI
CRS
DVSS
AVSS
TXD3+
84
83
45
44
SO
SCLK
TXD2+
TXD2–
81
82
46
47
VDD
ACT0
VDD
80
48
ACT1
TXD1–
TXD1+
78
79
50
49
ACT2
DVSS
TXD0–
AVSS
77
51
ACT4
ACT3
TXD0+
76
52
ACT5
75
53
VDD
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
ACT6
LDC2
LDC1
LDC0
VDD
LDGB
LDGA
LDB4
DVSS
LDA4
LDB3
LDA3
DVSS
LDB2
LDA2
VDD
LDB1
LDA1
DVSS
LDB0
LDA0
ACT7
20651B-2
Am79C985 7
PRELIMINARY
CONNECTION DIAGRAMS (PQR100)
RXD3+
RXD2–NCRXD2+
RXD1–
RXD1+
99
98
97969594939291908988878685
RXD3–
NC
NC
NC
REXT
AVSS
DI+
DI–
VDD
CI+
CI–
AVSS
DO+
DO–
AMODE
STR
DVSS
CRS_I
SI_D
VDD
RST
NC
CLK
DVSS
SELI_0
SELI_1
NC
NC
NC
SELO
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
RXD0–
RXD0+
VDD
TXD3–
TXD3+
eIMR+
Am79C985
AVSS
TXD2–
TXD2+
VDD
TXD1–
TXD1+
AVSS
848281
83
TXD0–
TXD0+
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
VDD
NC
NC
NC
LDC2
LDC1
LDC0
VDD
LDGB
LDGA
LDB4
DVSS
LDA4
LDB3
LDA3
DVSS
LDB2
LDA2
VDD
LDB1
LDA1
NC
DVSS
LDB0
LDA0
ACT7
NC
NC
NC
ACT6
COL
NC
DVSS
ACK
DAT
VDD
JAM
CRS
SI
DVSS
SO
VDD
SCLK
8 Am79C985
ACT0
ACT1
ACT2
DVSS
ACT3
ACT4
ACT5
20651B-3
LOGIC SYMBOL
Management
Expansion
Port
Test and
Port
PRELIMINARY
V
DAT
JAM
ACK
COL
SELO
SELI[1:0]
SI
SO
SCLK
AMODE
STR
CRS_I
CRS
SI_D
CLK
RST
DD
Am79C985
LDA[4:0], LDB[4:0]
TXD+
TXD–
RXD+
RXD–
DO+
DO–
DI+
DI–
CI+
CI–
LDGA, LDGB
LDC[2:0]
ACT[7:0]
Twisted Pair
Ports
(4 Ports)
AUI
LED
Interface
LOGIC DIAGRAM
LED
Port
Control
Port
DV
SS
AUI
Repeater
State
Machine
AV
SS
20651B-4
Expansion
Port
Twisted Pair
Port 0
Twisted Pair
Port 3
20651B-5
Am79C985 9
PIN DESIGNATIONS (PL 084)
Listed by Pin Number
PRELIMINARY
Pin No.
1
2 TXD3- 23 STR 44 SCLK 65 LDB3
3 VDD 24 DVSS 45 VDD 66 LDA4
4 RXD0+ 25 CRS_I 46 ACT0 67 DVSS
5 RXD0- 26 SI_D 47 ACT1 68 LDB4
6 RXD1+ 27 VDD 48 ACT2 69 LDGA
7 RXD1- 28 RST 49 DVSS 70 LDGB
8 RXD2+ 29 CLK 50 ACT3 71 VDD
9 RXD2- 30 DVSS 51 ACT4 72 LDC0
10 RXD3+ 31 SELI_0 52 ACT5 73 LDC1
11 RXD3- 32 SELI_1 53 ACT6 74 LDC2
12 REXT 33 SELO 54 ACT7 75 VDD
13 AVSS 34 COL 55 LDA0 76 TXD0+
14 DI+ 35 DVSS 56 LDB0 77 TXD015 DI- 36 ACK 57 DVSS 78 AVSS
16 VDD 37 DAT 58 LDA1 79 TXD1+
17 CI+ 38 VDD 59 LDB1 80 TXD118 CI- 39 JAM 60 VDD 81 VDD
19 AVSS 40 CRS 61 LDA2 82 TXD2+
20 DO+ 41 DVSS 62 LDB2 83 TXD221 DO- 42 SI 63 DVSS 84 AVSS
Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
TXD3+ 22 AMODE 43 SO 64 LDA3
10 Am79C985
PIN DESIGNATIONS (PQR100)
Listed by Pin Number
PRELIMINARY
Pin No.
1
2 NC 27 NC 52 NC 77 NC
3 NC 28 NC 53 NC 78 NC
4 NC 29 NC 54 NC 79 NC
5 REXT 30 SELO 55 ACT7 80 VDD
6 AVSS 31 COL 56 LDA0 81 TXD0+
7 DI+ 32 DVSS 57 LDB0 82 TXD0-
8 DI- 33 NC 58 DVSS 83 AVSS
9 VDD 34 ACK 59 NC 84 TXD1+
10 CI+ 35 DAT 60 LDA1 85 TXD111 CI- 36 VDD 61 LDB1 86 VDD
12 AVSS 37 JAM 62 VDD 87 TXD2+
13 DO+ 38 CRS 63 LDA2 88 TXD214 DO- 39 DVSS 64 LDB2 89 AVSS
15 AMODE 40 SI 65 DVSS 90 TXD3+
16 STR 41 SO 66 LDA3 91 TXD317 DVSS 42 SCLK 67 LDB3 92 VDD
18 CRS_I 43 VDD 68 LDA4 93 RXD0+
19 SI_D 44 ACT0 69 DVSS 94 RXD020 VDD 45 ACT1 70 LDB4 95 RXD1+
21 RST 46 ACT2 71 LDGA 96 RXD122 NC 47 DVSS 72 LDGB 97 RXD2+
23 CLK 48 ACT3 73 VDD 98 NC
24 DVSS 49 ACT4 74 LDC0 99 RXD225 SELI_0 50 ACT5 75 LDC1 100 RXD3+
Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
RXD3- 26 SELI_1 51 ACT6 76 LDC2
Note:
1. NC = No Connection.
Am79C985 11
PRELIMINARY
PIN DESCRIPTION
AUI Port
DI+, DI–
Data In
Differential Input
DI± are differential, Manchester receiver pins. The
signals comply with IEEE 802.3, Section 7.
DO+, DO–
Data Out
Differential Output
DO± are differential, Manchester output driver pins. The
signals comply with IEEE 802.3, Section 7.
CI+, CI–
Collision Input
Differential Input/Output
CI± are differential, Manchester I/O signals. As an input,
CI is a collision-receive indicator . As an output, CI generates a 10-MHz signal if the eIMR+ device senses a
collision.
Twisted Pair Ports
TXD+
Transmit Data
Differential Output
TXD± are 10BASE-T port differential drivers (4 ports).
RXD+
Receive Data
Differential Input
RXD± are 10BASE-T port differential receive inputs
(4 ports).
0-3
0-3
, TXD–
, RXD–
0-3
0-3
Expansion Bus
DAT
Data
Input/Output/3-State
If the SELO
collision conditions, the eIMR+ device drives NRZ data
onto the DAT line, regenerating the preamble if necessary. During a collision, when JAM is HIGH, D A T is used
to differentiate between single-port (DAT=1) and multiport (DAT=0) collisions. DAT is an output when ACK is
asserted and the eIMR+ device’s ports are active; DAT
is an input when ACK is asserted and the ports are
inactive. If ACK is not asser ted, DAT is in the high-impedance state. It is recommended that DAT be pulled
up or down via a high value resistor.
JAM
Jam
Input/Output/3-State
The active eIMR+ device drives J AM HIGH, if it detects
a collision condition on one or more of its ports. The
and ACK pins are asserted during non-
state of the DAT pin is used in conjunction with JAM to
indicate a single port (DA T =1) or multiport (DAT=0) collision. J AM is in the high-impedance state if neither the
SEL
nor ACK signal is asserted. It is recommended that
JAM be pulled up or down via a high value resistor.
SELI
0-1
Select In
Input, Active LOW
When the expansion bus is configured f or Internal Arbitration mode, these signals indicate that another eIMR+
device is active; SELI0 or SELI1 is driven by SELO from
the upstream device. At reset, SELI0 selects between
the Internal Arbitration mode and the IMR+ mode of the
expansion bus; a HIGH selects the Inter nal Arbitration
mode and a LOW selects the IMR+ mode.
SELI_1 SELI_0
X 1 Internal
X 0 IMR+
Arbitration
Mode
SELO
Select Out
Output, Active LOW
If the expansion bus is configured f or Internal Arbitration
mode, an eIMR+ device drives this pin LOW when it is
active or when either of its SELI
pins is LOW. An
0-1
active eIMR+ device is defined as having one or more
ports receiving or colliding and/or is still transmitting
data from the internal FIFO, or extending a pack et to the
minimum of 96 bit times. When the expansion bus is
configured for IMR+ mode, SELO
is active when the
eIMR+ device is active (acquiring the functionality of the
REQ pin on the Am79C981 IMR+ device).
ACK
Acknowledge
Input/Output, Active LOW, Open Drain
This signal is asserted to indicate that an eIMR+ device
is active. It also signals to the other eIMR+ devices the
presence of a valid collision status on the JAM line and
valid data on the DAT line. When the eIMR+ device is
configured for Internal Arbitration mode, A
CK is an I/O,
and must be pulled to VDD via a minimum equivalent
resistance of 1 k
for IMR+ mode, A
When the eIMR+ device is configured
Ω.
CK is an input driven by an external
arbiter.
COL
Collision
Input/Output, Active LOW, Open Drain
When asserted, COL indicates that more than one
eIMR+ device is active. Each eIMR+ device generates
the Collision Jam sequence independently. When the
eIMR+ device is configured for Internal Arbitration
12 Am79C985
PRELIMINARY
mode, COL
minimum equivalent resistance of 1 k
is an I/O and must be pulled to VDD via a
Ω.
When the
eIMR+ device expansion port is configured for IMR+
mode, COL
is an input driven by an external arbiter.
Management Port
AMODE
AUI Mode
Input
At reset, this pin sets the AUI port to either normal or
reversed mode. If AMODE is LOW at the rising edge of
, the AUI port is set to the normal mode; if AMODE
RST
is HIGH, the AUI port is set to the reversed mode.
CRS
Carrier Sense
Output
The states of the internal carrier-sense signals for the
AUI port and the four twisted-pair ports are output continuously on this pin. The output is a serial bit stream
synchronized to CLK. When two eIMR+ devices share
a common HIMIB device, CRS on the first de vice must
be connected to the CRS_I (input) of the second eIMR+
device.
CRS_I
Carrier Sense In
Input
CRS_I is used when two eIMR+ devices share a common HIMIB device. The CRS output from the first eIMR+
should be input to the second eIMR+ via this pin. Internally, the second eIMR+ appends the information on
CRS_I to its own carrier-sense information and outputs
the combined result to the HIMIB chip via its CRS pin.
At the rising edge of RST
eIMR+ device’ s management mode. CRS_I HIGH indicates that only a single eIMR+ device is connected to
the HIMIB chip. CRS_I LOW indicates that two eIMR+
devices are connected to a HIMIB chip.
SCLK
Serial Clock In
Input
Serial data (input or output) is clocked (in or out) on the
rising edge of the signal on this pin. SCLK is asynchronous to CLK and can operate at frequencies up to 10
MHz.
SI
Serial In
Input
The SI pin is used as a test/management serial input
port. Management commands are clocked in on this pin
synchronous to the SCLK input.
At reset, SI sets the state of the Automatic P olarity Reversal function. If SI is HIGH at the rising edge of RST,
, CRS_I is used to set the
Automatic Polarity Reversal is disabled. If SI is LOW at
the rising edge of RST
, Automatic Polarity Reversal is
enabled.
SI_D
Serial Input Append
Input
SI_D is used when two eIMR+ devices share a common
HIMIB device. The SO output from the first eIMR+ device should be input to the second eIMR+ chip via this
pin. Internally, the second eIMR+ chip appends the
SI_D data to its own serial data stream and outputs the
result to the HIMIB device via its SO pin.
When two eIMR+ devices are connected to a HIMIB
device, the HIMIB device has attribute counters for the
AUI port on only one of the eIMR+ devices. That eIMR+
device is referred to as the
other device is referred to as the
primary
secondary
eIMR+ device. The
eIMR+ de-
vice.
At the rising edge of RST
, the combination of CRS_I
and SI_D is used to set the eIMR+ device’s management mode. If CRS_I is HIGH, the state of SI_D is ignored and the eIMR+ device is configured as a single
eIMR+. If CRS_I is LOW, SI_D HIGH indicates that the
eIMR+ device is the secondary device. If CRS_I is LOW
and SI_D is LOW, the eIMR+ device is configured as
the primary device.
Two eIMR+ Devices
CRS_I SI_D
0
0
1
1
0
1
0
1
Single
eIMR+
Device
√
√
Primary
eIMR+
Device
√
Secondary
eIMR+
Device
√
SO
Serial Out
Output
The SO pin is used as a management command serial
output port. Responses to management commands are
clocked out on this pin synchronous to the SCLK input.
STR
Store
Input
The HIMIB device uses this input to communicate with
the eIMR+ device. STR connects to an internal pull-up
resistor. The resistance value is sufficiently high to allow
the STR pins of two eIMR+ devices to be connected
together without presenting an excessive load to the
HIMIB device.
Am79C985 13
PRELIMINARY
LED Interface
LDA
LED Drivers
Output, Open Drain
LDA
respectively. LDA0 and LDB0 indicate the status of the
AUI port; LDA
four TP ports. The port attributes monitored by LDA
and LDB
LDGA
Global LED Driver, Bank A
Output, Open Drain
LDGA is the Global LED driver for LED Bank A. The
signal represents global CRS or COL conditions. In a
multiple-eIMR+ configuration, LDGA from each of the
eIMR+ devices can be tied together to drive a single
global LED in Bank A.
LDGB
Global LED Driver, Bank B
Output, Open Drain
LDGB is the Global LED driver for LED Bank B. The
signal represents global CRS or JAB conditions. In a
multiple eIMR+ configuration, LDGB from each of the
eIMR+ devices can be tied together to drive a single
global LED in Bank B.
LDC
LED Control
Input
These pins select the attributes that will be displayed
on LDA
grammed to display two attributes , the attribute associated with the periodic blink takes precedence.
ACT
Activity Display
Output, Open Drain
These signals drive the activity LEDs, which indicate
the percentage of network utilization. The displa y is updated every 250 ms.
, LDB
0-4
0-4
0-2
0-7
0-4
and LDB
are programmed by three pins, LDC
0-4
, LDB
0-4
drive LED Bank A and LED Bank B,
0-4
and LDB
1-4
, LDGA, and LDGB. If an LED is pro-
0-4
indicate the status of the
1-4
0-2
0-4
.
Miscellaneous Pins
RST
Reset
Input, Active LOW
When RST is LOW, the eIMR+ device resets to its default state. On the rising (trailing) edge of RST, the
eIMR+ also monitors the state of the SELI
AMODE pins, to configure the operating mode of the
device. In multiple eIMR+ systems, the falling (leading)
edge of the RST signal must be synchronized to CLK.
CLK
Master Clock In
Input
This pin is a 20-MHz clock input.
REXT
External Reference
Input
This pin is used for an internal current reference. It must
be tied to VDD via a 13-k
Ω resistor with 1% tolerance.
VDD
Power
Power Pin
This pin supplies power to the device.
AVSS
Analog Ground
Ground Pin
This pin is the ground reference for the differential
receivers and drivers.
DVSS
Digital Ground
Ground Pin
This pin is the ground reference for all the digital logic
in the eIMR+ device.
, SI, and
0-1
14 Am79C985
PRELIMINARY
FUNCTIONAL DESCRIPTION
The Am79C985 eIMR+ device is a single-chip implementation of an IEEE 802.3/Ethernet repeater (or hub).
It is offered with four integr al 10BASE-T ports plus one
RAUI port comprising the basic repeater. The eIMR+
device is also expandab le, enabling the implementation
of high port count repeaters based on several eIMR+
devices.
The eIMR+ device interfaces directly with AMD’s
Am79C987 HIMIB device. This allows hardware designers to implement a fully managed multiport repeater, as specified by the IEEE 802.3 standard,
Section 19,
Repeaters
used as a chip set, the HIMIB device maintains complete repeater and per-port statistics, which can be accessed on demand through an 8-bit parallel interface.
The eIMR+ chip complies with the full set of repeater
basic functions as defined in Section 9 of ISO 8802.3
(ANSI/IEEE 802.3c). The basic repeater functions are
summarized in the paragraphs below.
Layer Management f or 10 Mbps Baseband
. When the eIMR+ and HIMIB devices are
Basic Repeater Functions
The Am79C985 chip implements the basic repeater
functions as defined by Section 9.5 of the ANSI/IEEE
802.3 specification.
Repeater Function
If any single network port senses the start of a valid
packet on its receive lines, the eIMR+ device will retransmit the received data to all other enabled network
ports (except when contention exists among any of the
ports or when the receive port is par titioned). To allow
multiple eIMR+ device configurations, the data will also
be repeated on the expansion bus data line (DAT).
Signal Regeneration
When retransmitting a packet, the eIMR+ device ensures that the outgoing packet complies with the IEEE
802.3 specification in terms of preamble structure and
timing characteristics. Specifically, data packets repeated by the eIMR+ device will contain a minimum of
56 preamble bits before the Start-of-Frame Delimiter . In
addition, the eIMR+ restores the voltage amplitude of
the repeated waveform to levels specified in the IEEE
802.3 specification. Finally, the eIMR+ device restores
signal symmetry to repeated data packets, removing jitter and distortion caused by the network cabling. Jitter
present at the output of the AUI port will be better than
0.5 ns; jitter at the TP outputs will be better than 1.5 ns .
The start-of-packet propagation delay for a repeater set
is the time delay between the first edge transition of a
data packet on its input port to the first edge transition
of the repeated packet on its output ports. The start-ofpacket propagation delay for the eIMR+ is within the
specification given in Section 9.5.5.1 of the IEEE 802.3
standard.
Jabber Lockup Protection
The eIMR+ device implements a built-in jabber protection scheme to ensure that the network is not disabled
by the transmission of excessively long data packets.
This protection scheme causes the eIMR+ device to interrupt transmission for 96 bit-times if the device has
been transmitting continuously for more than 65,536 bit
times. This is referred to as MAU Jabber Lockup Protection (MJLP). The MJLP status for the eIMR+ device
can be read through the Management Port, using the
Get MJLP Status command.
Collision Handling
The eIMR+ device will detect and respond to collision
conditions as specified in the IEEE 802.3 specification.
Repeater configurations consisting of multiple eIMR+
devices also comply with the IEEE 802.3 specification,
using status signals provided by the expansion bus. In
particular, a repeater based on one or more eIMR+ devices will handle the transmit collision and one-port-left
collision conditions correctly, as specified in Section 9
of the IEEE 802.3 specification.
Fragment Extension
If the total packet length received is less than 96 bits,
including preamble, the eIMR+ device will extend the
repeated packet length to 96 bits by appending a Jam
sequence to the original fragment.
Auto Partitioning/Reconnection
Any of the TP ports or the A UI port can be partitioned if
the duration or frequency of collisions becomes excessive. The eIMR+ device will continue to transmit data
packets to a partitioned port, but will not respond, as a
repeater, to activity on the partitioned port’s receiver.
The eIMR+ device will monitor the port and reconnect
it once certain criteria are met. The criteria for reconnection are specified by the IEEE 802.3 standard. In
addition to the standard reconnection algorithm, the
eIMR+ device implements an alternative reconnection
algorithm, which provides a more robust partitioning
function for the TP ports and/or AUI port. The eIMR+
device partitions each TP port and the AUI port separately and independently of other network ports.
The eIMR+ device will partition an enabled network
port if either of the following conditions occurs at that
port:
1. A collision condition exists continuously for more
than 2048 bit times. (AUI port—SQE signal active;
TP port—simultaneous transmit and receive).
2. A collision condition occurs during each of 32 con-
secutive attempts to transmit to that port.
In the AUI port, a collision condition is indicated by an
active SQE signal. In a TP port, a collision condition is
Am79C985 15
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