AMD Advanced Micro Devices AM79C983AKCW, AM79C983AKC Datasheet

PRELIMINARY

Am79C983A

Integrated Multiport Repeater 2 (IMR2™)

DISTINCTIVE CHARACTERISTICS

Repeater functionality compliant with IEEE

802.3 Repeater Unit speciﬁcations

Hardware implementation of Management Information Base (MIB) with all of the counters, attributes, actions, and notiﬁcations speciﬁed by IEEE 802.3 Section 19

Twelve pseudo AUI (PAUI™) ports to support multiple media types via direct connection to external transceivers

One IEEE-compliant AUI port

One reversible AUI (RAUI™) port that can be programmed as a second AUI port or used to connect directly to a media access controller (MAC)

Direct interface with the AMD Am79C988A QuIET™ (Quad Integrated Ethernet T ransceiver) to support 10BASE-T repeater designs

(Layer Management)

Port switching support to allow individual ports to be switched between multiple Ethernet backplanes under software control

Remote Monitoring (RMON) Register Bank to provide direct support for etherStatsEntry and etherStatsHistory object groups of the RMON MIB (IETF RFC1757)

Packet Report Port to provide packet information for deriving objects in the Host, HostTopN, and Matrix groups of the RMON MIB (IETF RFC1578)

Two user-selectable expansion bus modes: IMR/IMR+ compatible mode and asynchronous mode

Simple 8-bit microprocessor interface

Full LED support

132-pin PQFP CMOS device with a single 5-V supply

GENERAL DESCRIPTION

The Am79C983A Integrated Multiport Repeater 2 (IMR2) chip is a VLSI integrated circuit that provides a system-level solution to designing intelligent (managed) multiport repeaters. When the IMR2 device is combined with the Quad Integrated Ethernet Transceiver (QuIET) device, it provides a cost-effective solution to designing 10BASE-T managed repeaters. The IMR2 device integrates the repeater functions speciﬁed by Section 9 ( (

Layer Management f or 10 Mb/s Baseband Repeaters

of the IEEE 802.3 standard. The Am79C983A IMR2 device provides 1 standard

Attachment Unit Interface (AUI) port, 12 Pseudo Attachment Unit Interface (PAUI) ports, and 1 Reversible AUI (RAUI) port for direct connection to a media access controller (MAC). The pseudo AUI ports can be connected to external transceivers to support multiple media types, including 10BASE2, 10BASE-T, and 10BASE-FL/FOIRL. The pseudo AUI ports can be turned off individually (without external circuitry) to allow the switching of transceiver

Repeater Unit

) and Section19

ports between IMR2 devices. This capability allows multiple IMR2 devices to be connected to a single set of transceivers, thus allowing straightforward implementations of port switching applications.

The IMR2 device also provides a Hardware Implemented Management Information Base (HIMIB™), which is a super set of the functions provided by the Am79C987 HIMIB device. All of the necessary counters, attributes, actions, and notiﬁcations speci-

)

ﬁed by Section 19 of the IEEE 802.3 standard are included in the IMR2 device. To facilitate the design of managed repeaters, the IMR2 device implements a simple 8-bit microprocessor interface.

Support for an RMON MIB, as speciﬁed by the Internet Engineering Task Force (IETF) RFC 1757, is provided. Direct support is from an RMON Register Bank. Additional support is provided by the Packet Report Port, which supplies information that can be used in conjunction with a microprocessor to derive various RMON MIB attributes. With systems using multiple IMR2 de-

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

Publication# 19879 Rev: B Amendment/0 Issue Date: April 1997

PRELIMINARY

vices, the information is passed to a designated IMR2 device that transfers the information to a MAC.

For application examples on building fully-managed repeaters using the IMR2 and QuIET devices, refer to AMD’s

IMR2 Technical Manual

(PID 19898A).

2 Am79C983A

BLOCK DIAGRAM

PRELIMINARY

DO±

DI± CI±

RDO±

RDI± RCI±

PDO

PDI PCI

PDO

PDI PCI

PDAT

PCLK

PENAI

PENAO

PTAG

PDRV

AUI Port

RAUI

Port

PAUI

Port 0

PAUI

Port 11

Packet Report Port

Manchester

Attributes and

Control Registers

(HIMIB)

Decoder

PLL

Encoder

IMR2

Repeater

Engine

Receiver

MAC

Engine

FIFO

Control

Preamble

Jam

Expansion Bus

LED Interface

Interface

Microprocessor

RDY

INT

LD[7:0] BSEL CRS

COLX PART LINK POL

D[7:0]

CS C/D

RD WR

DAT

REQ ACK

COL

JAM ECLK

MACEN

FRAME

XMODE

MCLK

RST

XENA

Transceiver

Interface

SDATA[3:0] DIR[1:0]

19879B-1

Am79C983A 3

RELATED AMD PRODUCTS

PRELIMINARY

Part No.

Am79C981 Am79C982 Am79C987 Hardware Implemented Management Information Base (HIMIB™) Am79C988A Quad Integrated Ethernet Transceiver (QuIET™) Am7990 Local Area Network Controller for Ethernet (LANCE) Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE) Am79C98 Twisted Pair Ethernet Transceiver (TPEX) Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+) Am79C900 Integrated Local Area Communications Controller (ILACC™) Am79C940 Media Access Controller for Ethernet (MACE™) Am79C960 PCnet™-ISA Single-Chip Ethernet Controller (for ISA bus) Am79C961 PCnet™-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft® Plug n’ Play® Support) Am79C961A PCnet™-ISA II Full Duplex Single-Chip Ethernet Controller for ISA Am79C965 PCnet™-32 Single-Chip 32-Bit Ethernet Controller Am79C970 PCnet™-PCI Single-Chip Ethernet Controller (for PCI bus) Am79C970A PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus) Am79C974 PCnet™-SCSI Combination Ethernet and SCSI Controller for PCI Systems

Description

Integrated Multiport Repeater+ (IMR+™)

asic Integrated Multiport Repeater (bIMR™)

4 Am79C983A

PRELIMINARY

CONNECTION DIAGRAM

PQFP

DO–

DO+

DI– DI+ CI– CI+

DVSS

MACEN

COL ACK

XMODE

REQ

DAT

JAM

VDD

ECLK

FRAME

DVSS

PDRV

PDAT

PTAG

PCLK

DVSS

PENAO

PENAI

DVSS

MATCHI

ATCHO

VDD

INT

RDY

DVSS

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

VDD

PCI[11]

PDI[11]

1321131

130

343536

PCI[10]

PDI[10]

AVSS

PCI[9]

129

128

127

126

3839404142

PDI[9]

AVSS

125

124

PCI[8]

PDI[8]

PCI[7]

123

122

121

434445

PDI[7]

PCI[6]

PDI[6]

AVSS

120

119

118

117

Am79C983

474849

PCI[5]

PDI[5]

116

115

515253

VDD

114

PCI[4]

PDI[4]

113

112

PCI[3]

PDI[3]

111

110

555657

PCI[2]

PDI[2]

109

108

PCI[1]

PDI[1]

107

106

596061

PCI[0]

PDI[0]

105

104

626364

VDD

103

RDI–

102

RDI+

101

AVSS

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67

RDO– RDO+ RCI– RCI+ DVSS DIR[1] DIR[0] SDATA[3] DVSS SDATA[2] SDATA[1] SDATA[0] VDD XENA

RST

DVSS MCLK DVSS BSEL CRS COLX PART LINK VDD POL LD[7] LD[6] DVSS LD[5] LD[4] DVSS LD[3] LD[2]

C/D

DATA[7]

DATA[6]

DATA[5]

DVSS

DATA[3]

DATA[4]

DATA[0]

DATA[2]

DATA[1]

VDD

PDO[11]

PDO[8]

PDO[9]

PDO[10]

DVSS

PDO[7]

PDO[6]

VDD

PDO[5]

PDO[4]

DVSS

PDO[2]

PDO[3]

VDD

PDO[1]

PDO[0]

LD[0]

LD[1]

19879B-2

Am79C983A 5

LOGIC SYMBOL

AUI

RAUI

PRELIMINARY

DO± DI± CI±

RDO± RDI± RCI±

DAT

REQ ACK COL

JAM

ECLK

MACEN

FRAME

Expansion Bus

LOGIC DIAGRAM

PAUI

(12)

Packet

Report

Port

PDO PDI PCI

PDAT PCLK

PENAI PENAO PTAG PDRV

MCLK

RST

XENA

XMODE

Am79C983

LD[7:0]

BSEL

CRS COLX PART

LINK

POL

D[7:0]

C/D

RDY

INT

SDATA [3:0]

DIR [1:0]

LED Interface

Microprocessor Interface

Transceiver Interface

19879B-3

RAUI

Port

AUI

Port

PAUI

Port 0

Expansion

Bus

Repeater

State

Machine

PAUI

Port 11

6 Am79C983A

Packet

Report Port

Transceiver

Interface

Microprocessor

Interface

LED

Interface

MAC

Engine

19879B-4

PRELIMINARY

ORDERING INFORMATION Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

Am79C983A

ALTERNATE PACKAGING OPTION

\W = Trimmed and formed in a tray

OPTIONAL PROCESSING

Blank = Standard processing

TEMPERATURE RANGE

C = Commercial (0˚C to +70˚C)

PACKAGE TYPE

K = Plastic Quad Flat Pack (PQB 132)

DEVICE VARIATION

Blank = Security not included. S = Security included. (See Appendix.)

DEVICE NUMBER/DESCRIPTION

Am79C983A Integrated Multiport Repeater 2 (IMR2)

Valid Combinations

Am79C983A KC, KC\W

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Am79C983A 7

PRELIMINARY

TABLE OF CONTENTS

DISTINCTIVE CHARACTERISTICS.................................................................................................... 1

GENERAL DESCRIPTION................................................................................................................... 1

BLOCK DIAGRAM ............................................................................................................................... 3

RELATED AMD PRODUCTS............................................................................................................... 4

CONNECTION DIAGRAM....................................................................................................................5

LOGIC SYMBOL...................................................................................................................................6

LOGIC DIAGRAM ................................................................................................................................ 6

ORDERING INFORMATION.................................................................................................................7

Standard Products.......................................................................................................................... 7

PIN DESIGNATIONS..........................................................................................................................12

PIN DESCRIPTION............................................................................................................................ 13

Pseudo AUI Pins........................................................................................................................... 13

RAUI Port Pins.............................................................................................................................. 13

AUI Pins........................................................................................................................................ 13

Expansion Bus Pins...................................................................................................................... 13

Packet Report Port........................................................................................................................ 14

Microprocessor Interface .............................................................................................................. 15

LED Interface................................................................................................................................ 15

Miscellaneous Pins....................................................................................................................... 15

Transceiver Device Interface........................................................................................................ 15

FUNCTIONAL DESCRIPTION............................................................................................................17

Overview....................................................................................................................................... 17

Basic Repeater Functions............................................................................................................. 17

Repeater Function ..................................................................................................................17

Signal Regeneration ...............................................................................................................17

Jabber Lockup Protection .......................................................................................................17

Collision Handling ...................................................................................................................17

Fragment Extension ...............................................................................................................17

Auto Partitioning/Reconnection ..............................................................................................17

Basic Management Functions....................................................................................................... 18

Repeater Management ...........................................................................................................18

RMON ....................................................................................................................................18

Packet Reports .......................................................................................................................18

Detailed Functions........................................................................................................................ 22

Reset ......................................................................................................................................22

Hardware Reset............................................................................................................... 22

Software Reset ................................................................................................................ 22

Expansion Bus .......................................................................................................................22

Synchronous Mode Operation......................................................................................... 23

Asynchronous Mode Operation ....................................................................................... 24

Packet Statistics .....................................................................................................................24

Packet Report Port........................................................................................................... 24

RAUI Port......................................................................................................................... 25

Error Packet Statistics ............................................................................................................26

Transceiver Interface.................................................................................................................... 26

PAUI Ports ..............................................................................................................................26

QuIET Device Control and Status Data Interface ...................................................................26

QuIET Device Control and Status Data Interface Operation ........................................... 26

Control and Status for Non-QuIET Transceivers............................................................. 27

Visual Status Monitoring (LED) Support....................................................................................... 27

Using AUI/RAUI for 10BASE-T Ports .....................................................................................28

Intrusion Protection....................................................................................................................... 28

Timer Values ..........................................................................................................................29

8 Am79C983A

PRELIMINARY

Microprocessor Interface .............................................................................................................. 29

Management Functions ..........................................................................................................29

Status Register ................................................................................................................ 30

Source Address Match Register .............................................................................. 30

Total Octets.............................................................................................................. 31

Transmit Collisions................................................................................................... 31

Configuration Register ............................................................................................. 31

Repeater Status....................................................................................................... 31

QuIET Device Transceiver ID Register.................................................................... 31

Repeater Device and Revision Register.................................................................. 32

Device Configuration................................................................................................ 32

Register Bank 1: Interrupts.............................................................................................. 32

Port Partition Status Change Interrupt..................................................................... 32

Runts with Good FCS Interrupt................................................................................ 32

Link Status Change Interrupt ................................................................................... 32

Loopback Error Change Interrupt............................................................................. 33

Polarity Change Interrupt......................................................................................... 33

SQE Test Error Change Interrupt............................................................................. 33

Source Address Changed Interrupt.......................................................................... 33

Intruder Interrupt ...................................................................................................... 33

Source Address Match Interrupt .............................................................................. 33

Data Rate Mismatch Interrupt.................................................................................. 34

Transceiver Interface Status.................................................................................... 34

Transceiver Interface Change Interrupt ................................................................... 34

Jabber Interrupt........................................................................................................ 34

Partition Status Change Interrupt Enable................................................................. 34

Runts with Good FCS Interrupt Enable.................................................................... 34

Link Status Change Interrupt Enable....................................................................... 35

Loopback Error Change Interrupt Enable ................................................................ 35

Polarity Change Interrupt Enable............................................................................. 35

SQE Test Error Change Interrupt Enable ................................................................ 35

Source Address Changed Interrupt Enable ............................................................. 35

Intruder Interrupt Enable.......................................................................................... 35

Multicast Address Pass Enable................................................................................ 36

Data Rate Mismatch Interrupt Enable...................................................................... 36

Last Source Address Compare Enable.................................................................... 36

Preferred Address Compare Enable........................................................................ 36

Transceiver Interface Changed Interrupt Enable..................................................... 36

Jabber Interrupt Enable............................................................................................ 36

Alternative Reconnection Algorithm Enable............................................................. 37

Link Test Enable ...................................................................................................... 37

Link Pulse Transmit Enable ..................................................................................... 37

Automatic Receiver Polarity Reversal Enable.......................................................... 37

SQE Mask Enable.................................................................................................... 37

Port Enable/Disable ................................................................................................. 37

Port Switching Control.............................................................................................. 37

Extended Distance Enable....................................................................................... 38

Automatic Last Source Address Intrusion Control ................................................... 38

Automatic Preferred Source Address Intrusion Control........................................... 38

Last Source Address Lock Control........................................................................... 38

Partitioning Status of Ports....................................................................................... 39

Link Test Status of Ports.......................................................................................... 39

Loopback Error Status ............................................................................................. 39

Receive Polarity Status............................................................................................ 39

Am79C983A 9

PRELIMINARY

SQE Test Status ...................................................................................................... 39

etherStatsOctets ...................................................................................................... 39

etherStatsPkts.......................................................................................................... 39

etherStatsBroadcastPkts.......................................................................................... 40

etherStatsMulticastPkts.............................................................................................40

etherStatsCRCAlignErrors........................................................................................40

etherStatsUndersizePkts.......................................................................................... 40

etherStatsOversizePkts............................................................................................ 40

etherStatsFragments................................................................................................ 40

etherStatsJabbers.................................................................................................... 40

etherStatsCollisions ................................................................................................. 40

etherStats64Octets .................................................................................................. 40

etherStats65to127Octets ......................................................................................... 40

etherStats128to255Octets ....................................................................................... 40

etherStats256to511Octets ....................................................................................... 40

etherStats512to1023Octets ..................................................................................... 40

etherStats1024to1518Octets ................................................................................... 40

Activity...................................................................................................................... 40

Device ID.................................................................................................................. 40

Sample Error Status................................................................................................. 40

Report Packet Size .................................................................................................. 41

STATS Control......................................................................................................... 41

Readable Frames..................................................................................................... 42

Readable Octets ...................................................................................................... 42

Frame Check Sequence (FCS) Errors..................................................................... 42

Alignment Errors ...................................................................................................... 42

Frames Too Long..................................................................................................... 42

Short Events............................................................................................................. 43

Runts........................................................................................................................ 43

Collisions.................................................................................................................. 43

Late Events.............................................................................................................. 43

Very Long Events..................................................................................................... 43

Data Rate Mismatches............................................................................................. 43

Auto Partitions.......................................................................................................... 44

Source Address Changes........................................................................................ 44

Readable Broadcast Frames ................................................................................... 44

Last Source Address................................................................................................ 44

Readable Multicast Frames ..................................................................................... 44

Preferred Source Address........................................................................................ 44

SYSTEM APPLICATIONS..................................................................................................................45

IMR2 to QuIET Connection........................................................................................................... 45

Other Media.................................................................................................................................. 45

MAC Interface............................................................................................................................... 45

RAUI Port ...............................................................................................................................45

PR Port Configuration ............................................................................................................45

Port Switching............................................................................................................................... 48

ABSOLUTE MAXIMUM RATINGS .....................................................................................................50

OPERATING RANGES................................................................................................................. 50

DC CHARACTERISTICS over operating ranges unless otherwise specified............................... 50

SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified............... 51

KEY TO SWITCHING WAVEFORMS................................................................................................ 54

SWITCHING WAVEFORMS.............................................................................................................. 54

Master Clock (MCLK) Timing........................................................................................................ 54

10 Am79C983A

PRELIMINARY

Expansion Bus Asynchronous Clock (ECLK) Timing ...................................................................54

Expansion Bus Input Timing - Synchronous Mode....................................................................... 55

Expansion Bus Output Timing - Synchronous Mode ....................................................................55

Expansion Port Collision Timing - Synchronous Mode .................................................................56

Packet Report Port Timing............................................................................................................ 56

Expansion Port Input Timing - Asynchronous Mode..................................................................... 56

Expansion Port Output Timing - Asynchronous Mode.................................................................. 57

PAUI PDO Transmit...................................................................................................................... 57

PAUI PCI Receive......................................................................................................................... 57

PAUI Receive................................................................................................................................ 58

(R)AUI Timing................................................................................................................................58

(R)AUI Receive .............................................................................................................................58

Microprocessor Bus Interface Timing ...........................................................................................59

PHYSICAL DIMENSIONS.................................................................................................................. 60

Am79C983A 11

PRELIMINARY

PIN DESIGNATIONS Listed by Pin Number

Pin No

Pin Name

1 2

DO- 34 WR 67 LD[2] 100

DO+ 35 RD 68 LD[3] 101 RDI+

Pin No

3 DI- 36 CS 69 DV 4 DI+ 37 C/D 70 LD[4] 103 V 5 CI- 38 D[7] 71 LD[5] 104 PDI[0] 6 CI+ 39 D[6] 72 DV 7 DV

40 8 MACEN 41 D[4] 74 LD[7] 107 PCI[1] 9 COL 42 DV

10 ACK 43 D[3] 76 V 11 XMODE 44 D[2] 77 LINK 110 PDI[3] 12 REQ 45 D[1] 78 PART 111 PCI[3] 13 DAT 46 D[0] 79 COLX 112 PDI[4] 14 JAM 47 V 15 V 16

ECLK 49 PDO[10] 82 DV 17 FRAME 50 PDO[9] 83 MCLK 116 PCI[5] 18 DV 19

PDRV 52 DV

20 PDAT 53 PDO[7] 86 XENA 119 PCI[6] 21 PTAG 54 PDO[6] 87 V 22 PCLK 55 V 23 DV

56 24 PENAO 57 PDO[4] 90 SDATA[2] 123 PCI[8] 25 PENAI 58 DV

59 27 MATCHI 60 PDO[2] 93 DIR[0] 126 PCI[9] 28 MATCHO 61 V 29 30 V

PS 62 PDO[1] 95 DV

63 31 INT 64 LD[0] 97 RCI- 130 PDI[11] 32 RDY 65 LD[1] 98 RDO+ 131 PCI[11] 33 DV

Pin Name

Pin No

Pin Name

Pin No. Pin Name

102

105

D[5] 73 LD[6] 106 PDI[1]

POL 108 PDI[2]

109

CRS 113 PCI[4]

PDO[11] 81 BSEL 114 V

PDO[8] 84 DV

RST 118 PDI[6]

SDATA[0] 121 PCI[7]

115

117

120

PDO[5] 89 SDATA[1] 122 PDI[8]

124

PDO[3] 92 SDATA[3] 125 PDI[9]

DIR[1] 127 AV

128

PDO[0] 96 RCI+ 129 PCI[10]

NC 99 RDO- 132 V

RDI-

PCI[0]

PCI[2]

PDI[5]

PDI[7]

PDI[10]

12 Am79C983A

PRELIMINARY

PIN DESCRIPTION Pseudo AUI Pins

PDO

0-11

Pseudo AUI Data Output Output/High Impedance

PDO is a single-ended output driver. PDO can be placed into a high impedance state, allowing multiple IMR2 devices to connect to a single QuIET device (port switching). The output data is Manchester encoded.

PDI

0-11

Pseudo AUI Receive Data Input Input

The input data is Manchester encoded.

0-11

PCI Pseudo AUI Collision Input Input

PAUI port collision data receiver. A 10-MHz square wa ve indicates a collision has been detected on that port.

RAUI Port Pins

RDO+, RDOReversible AUI Data Output Output

RDO is a differential, Manchester output driver.

RDI+, RDIReversible AUI Data Input Input

RDI is a differential, Manchester receiver.

RCI+, RCIReversible AUI Collision Input Input/Output

RCI is a differential I/O. As an input, RCI receives a collision indication. As an output, RCI gener ates a 10-MHz square wave when a collision is sensed.

PS Output

This pin is reserved for factory use.

AUI Pins

DO+, DOAUI Data Output Output

AUI port differential driver. Manchester encoded data.

DI+, DIAUI Data Input Input

AUI port differential receiv er. Manchester encoded data.

CI+, CIAUI Collision Input Input

AUI port collision differential receiver.

Expansion Bus Pins

DAT Data Input/Output/High Impedance

The IMR2 device drives the DAT line with NRZ data when both REQ and ACK pins are asserted. DAT is an input if only the ACK signal is asserted. If REQ and A CK are not asserted, DAT enters a high impedance state. During collision when JAM is HIGH, DAT is used to signal a multiport (DAT=0) or single port (DAT=1) condition.

JAM Jam Input/Output/High Impedance

This pin is an output if the device is the only active IMR2 device. An IMR2 de vice is deﬁned as active when it has one or more ports receiving or colliding, is in the state where it is still transmitting data from the internal FIFO, or is extending a packet to the minimum 96-bit times. If active, the IMR2 device drives the JAM pin HIGH to indicate that it is in a Collision state when both REQ and ACK pins are asserted. JAM is an input if only the ACK signal is asserted. If REQ and A CK are not asserted, JAM enters a high impedance state.

REQ Request Output, Active LOW

This pin is driven LOW when the IMR2 device senses activity. An IMR2 device is deﬁned as ACTIVE when it has one or more ports receiving or colliding, is in the state where it is still transmitting data from the internal FIFO, or is extending a packet to the minimum 96-bit times. The assertion of this signal signiﬁes that the IMR2 device requires the D AT and JAM lines to transfer repeated data and collision status information to other IMR2 devices.

ACK Acknowledge Input, Active LOW

When this signal is asserted by an external arbiter, it signals to the requesting IMR2 device that it may drive the DAT and JAM pins. It signals to other IMR2 devices the presence of valid collision status on the JAM line and valid data on the DAT line.

Am79C983A 13

PRELIMINARY

COL Collision Input, Active LOW

When this pin is asserted by an external arbiter, it signiﬁes that more than one IMR2 device is active and that each IMR2 device should generate the Collision Jam Sequence independently.

ECLK Bus Clock Input/Output

Data transitions on the expansion bus on DAT are synchronized to this clock. ECLK is a 10-MHz output clock when DAT is transmitting and a 10-MHz input clock when DAT is receiving. ECLK is only used when the expansion bus is operated in the asynchronous mode. ECLK should be terminated to ground with a 1 kΩ resistor. ECLK should be ignored in the synchronous mode.

CEN

MA MAC Enable Input, Active LOW

When this pin is asserted, data on the expansion bus is included in MIB statistics. This is typically used when a MAC is driving the expansion bus.

MATCHO

This pin should be tied to +5 V through a 1 kΩ ±10% resistor.

MATCHI

This pin should be tied to +5 V through a 1 kΩ ±10% resistor.

FRAME Packet Framing Signal Input/Output, Active LOW

FRAME deﬁnes the beginning and end of a packet. FRAME indicates valid data on the DAT pin when the expansion bus is in the asynchronous mode. FRAME is an output on the IMR2 device when it is transmitting ov er the expansion bus. It is an input on all other IMR2 devices.

XMODE Expansion Bus Mode Input

XMODE determines the mode of the expansion bus. XMODE should not be changed after RST. Although changing XMODE after RST will change the expansion bus mode, the operation is unpredictable. Therefore, it is recommended that XMODE be tied either HIGH or LOW, depending on the desired expansion bus mode.

XMODE Mode

1 Asynchronous 0 Synchronous (IMR/IMR+)

XENA Port Enable Input

XENA sets the default mode of the ports. It is used when RST transitions from LOW to HIGH.

XENA Default

1 All ports are enabled. 0 All ports are disabled. The output drivers

are in a high impedance state.

Note: XENA only controls the default state. Once reset is completed, the enabling and disabling of ports is under software control. It is recommended that XENA be tied either HIGH or LOW, depending on the desired default state.

Packet Report Port

PDAT Packet Report Output, High Impedance

PDAT outputs the beginning portion of a packet followed by packet status information. The size of the beginning portion is user programmable. If a second packet arrives bef ore PDAT ﬁnishes transmitting status information, the second packet and corresponding status information are not transmitted over PDAT. The packet is aborted on collision.

PENAI Packet Report Enable Input Input, Active LOW

PENAI senses when another device is transmitting over PDAT.

PENAO Packet Report Enable Output Output, Active LOW, Open Drain

PENAO is TRUE when the IMR2 device is transmitting data over PD AT . If a second packet arrives bef ore PD AT is ﬁnished transmitting status information, PENAO remains active for the second packet.

PDRV Packet Drive Output, Active LOW

PDRV is TRUE when the IMR2 device is transmitting data over PD AT . If a second packet arrives bef ore PD AT is ﬁnished transmitting status, PDR V goes FALSE after the status is transmitted.

PCLK Packet Report Clock Output, High Impedance

PCLK is a 10-MHz clock. PDAT transitions are synchronized to PCLK.

14 Am79C983A

PRELIMINARY

PTAG Packet Tag Output, HIGH Impedance, Active LOW

PTAG indicates when the status frame is being transmitted over PDAT. It is asserted when the status frame is transmitted.

Microprocessor Interface

D[7:0] Microprocessor Data Input/Output

These pins are inputs when either CS or WR are LO W. They are outputs when CS wise, these pins are high impedance.

CS Chip Select Input, Active LOW

This pin enables the IMR2 device to read from or write to the microprocessor data bus.

C/D Control/Data Input

This pin is used to select either a control register or a data register in the IMR2 device and is normally connected to the least signiﬁcant bit of the address bus.

RD Read Strobe Input, Active LOW

Initiates read operation.

WR Write Strobe Input, Active LOW

Initiates write operation.

RDY Ready Output, Active HIGH, Open Drain

RDY is dr iven LOW at the start of every READ or WRITE cycle. RDY is released when the IMR2 device is ready to complete the transaction.

INT Interrupt Output, Active LOW, Open Drain

The Interrupt pin is driven LOW when any of the unmasked (enabled) interrupts occur.

and RD are LOW. Other-

LED Interface

LD[7:0] LED Drivers Output

LD is the status output and is transmitted as 2 bytes. The byte number (high or low) is determined by BSEL.

BSEL Byte Select

Output

When BSEL is LOW, LD[7:0] is transmitting the status of the ﬁrst eight P A UI ports (ports P BSEL is HIGH, LD[7:0] is transmitting the status of the rest of the PAUI ports (por ts P11 through P8), the AUI port, the RAUI port, and the expansion bus.

CRS Carrier Sense Strobe Output

When CRS is HIGH, LD [7:0] has carrier sense status.

COLX Collision Status Output

When COLX is HIGH, LD [7:0] has collision status.

PART Partitioning Status Output

When PART is HIGH, LD [7:0] has partitioning status.

LINK Link Status Output

When LINK is HIGH, LD [7:0] has link status.

POL Polarity Status Output

When POL is HIGH, LD [7:0] has polarity status.

through P0). When

Miscellaneous Pins

RST Reset Input

When RST is LOW, the IMR2 device resets to its default state.

MCLK Master Clock Input

MCLK is a 20-MHz clock input.

Transceiver Device Interface

SDATA [3:0] Serial Data Input/Output

SDATA carries command and status data between the IMR2 device and the QuIET device (or other connected transceiver).

Pin Transceiver Ports

SDATA [0] PAUI [3:0] SDATA [1] PAUI [7:4] SDATA [2] PAUI [11:8] SDATA [3] Arbitrary ports

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DIR Direction Output

DIR sets the direction of data on SDATA[3:0] The settings are as follows:

DIR[1:0] Function

00 01 SDATA is a high impedance output.

10 SDATA is a high impedance output. 11 IMR2 device drives SDATA with commands.

T ransceiv er (QuIET de vice) drives SDATA with status and device ID.

Power Pin

These pins supply +5 V power.

Analog Ground Ground Pin

These pins provide the ground reference for the analog portions of the IMR2 circuitr y. These pins should be decoupled and kept separate from the digital ground plane.

DVss Digital Ground Ground Pin

These pins provide the ground reference for the digital portions of the IMR2 circuitr y. These pins should be decoupled and kept separate from the analog power plane.

16 Am79C983A

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FUNCTIONAL DESCRIPTION Overview

The Am79C983A Integrated Multiport Repeater 2 device provides a system-level solution to designing IEEE

802.3 managed repeaters. It includes 12 pseudo AUI (PAUI) ports for single-ended connections to external transceivers. The IMR2 device interfaces directly with AMD's Am79C988A Quad Integrated Ethernet Transceiver (QuIET) device for 10BASE-T implementations. The PAUI ports can be turned off individually to enable port switching applications. In addition, the IMR2 device has a standard AUI port and a reversible AUI (RAUI) port for a direct connection to a MAC.

The IMR2 device provides a Hardware Implemented Management Information Base (HIMIB) which contains all of the necessary counters, attributes, actions, and notiﬁcations speciﬁed by Section 19 of the IEEE 802.3 standard. Support for an RMON MIB, as speciﬁed by the Internet Engineering Task Force (IETF) RFC 1757, is also provided. Direct support is from an RMON Register Bank. Additional support is provided by the P ac ket Report Port, which supplies packet information that can be used in conjunction with a microprocessor to derive various RMON MIB attributes.

Basic Repeater Functions

The IMR2 repeater functions are summarized below. An overview of IMR2 management functions is presented under

Repeater Function

If any single network port of a repeater system senses the start of a valid packet on its receive lines, the IMR2 device will retransmit the received data to all other enabled network ports unless a collision is detected. The repeated data will also be presented on the DAT line of the expansion bus to f acilitate designs utilizing multiple IMR2 devices. The IMR2 device fully complies with Section 9.5.1 of the IEEE 802.3 speciﬁcations.

Signal Regeneration

When retransmitting a packet, the IMR2 device ensures that the outgoing packet complies with the IEEE

802.3 speciﬁcation in terms of preamble structure. Data packets repeated by the IMR2 device will contain a minimum of 56 preamble bits before the Start of Frame Delimiter.

The IMR2 device, by virtue of its inter nal Phase Lock Loop and Manchester Encoder/Decoder, will ensure correct regeneration of the repeated signal at its PAUI and AUI outputs. If the outputs of the IMR2 device are connected to QuIET device transceivers , the 10BASE-T outputs of the QuIET devices will meet the IEEE 802.3 signal symmetry requirements. If other types of transceivers are used, the signal characteristics will depend, in part, on the transceiver.

Basic Management Functions

Jabber Lockup Protection

The IMR2 chip implements a built-in jabber protection scheme to ensure that the network is not disabled due to transmission of excessively long data packets. This protection scheme will automatically interrupt the transmitter circuits of the IMR2 device for 96-bit times , if the IMR2 device has been transmitting continuously for more than 65,536 bit times. This is referred to as MAU Jabber Lockup Protection (MJLP). The MJLP status for the IMR2 chip can be read from the Repeater Status Register.

Collision Handling

The IMR2 chip will detect and respond to collision conditions as speciﬁed in the IEEE 802.3 speciﬁcation. A multiple IMR2 device repeater implementation also complies with the speciﬁcation because of the interIMR2 chip status communication provided by the expansion port. Speciﬁcally, a repeater based on one or more IMR2 devices will handle correctly the transmit collision and one-port-left collision conditions as speciﬁed in Section 9 of the IEEE 802.3 speciﬁcation.

Fragment Extension

If the total packet length received b y the IMR2 de vice is less than 96 bits, including preamble, the IMR2 chip will extend the repeated packet length to 96 bits by appending a Jam sequence to the original fragment. Note that in a few cases, it is possib le for the IMR2 device to generate a sequence 97 bits in length when the expansion bus is operated in the asynchronous mode.

Auto Partitioning/Reconnection

Any of the IMR2 ports can be partitioned under excessive duration or frequency of collision conditions. Once a port is par titioned, the IMR2 device will continue to transmit data packets to a partitioned port, but will not respond (as a repeater) to activity on the partitioned port’s receiver. The IMR2 chip will monitor the port and reconnect it once certain criteria indicating por t “wellness” are met. The criteria for reconnection are speciﬁed by the IEEE 802.3 standard. In addition to the standard reconnection algorithm, the IMR2 device implements an alternative reconnection algorithm which provides a more robust partitioning function. Each port is partitioned and/ or reconnected separately and independently of other network ports.

Either one of the following conditions occurring on any enabled IMR2 device network port will cause the port to partition:

a. An SQE signal active for more than 2048 bit times. b. A collision condition occurs during each of 32 con-

secutive attempts to transmit to that port. Once a network port is partitioned, the IMR2 de vice will

reconnect that port if the following is met:

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a. Standard reconnection algorithm—A data packet longer than 512-bit times (nominal) is transmitted or received by the partitioned port without a collision.

b. Alternate reconnection algorithm—A data packet longer than 512-bit times (nominal) is transmitted by the partitioned port without a collision.

Basic Management Functions

Repeater Management

The IMR2 management functions are a super-set of the those provided by the AMD’s IMR+/HIMIB device chipset. The IMR2 device contains the complete set of repeater and port functions as deﬁned in ANSI/IEEE

Repeater Management Standard

802.3, All mandatory and optional capabilities are supported. These include the Basic Control, Perf ormance Monitoring, and Address Tracking packages. Additionally, Node Address Mapping, MAU Management speciﬁc functions, and intrusion protection functions are included. Support is also provided for the RMON MIB RFC 1757.

All information is stored in registers which can be accessed through the Microprocessor Interface (Node Processor Port). The register location is deﬁ ned by a register bank and an address within that register bank. Address and data of the registers are multiplex ed using the C/D pin. The register address is selected by writing to the Node Processor Port with C/D HIGH. The register data is selected by writing or reading to the Node Processor Port with C/D LOW.

Many of the registers are larger than 1 byte. For these registers, consecutive accesses to register data (equal to the number of bytes in the register) are required. The order is LSByte to MSByte. For a write operation, if the address changes before all the bytes are written, the register is not changed to the new value.

The Status Register is accessed by reading the Node Processor Port with the C/D pin HIGH. This reduces the number of operations necessary to access the Status Register.

All bit ﬁelds are ordered such that the left most bit is the most signiﬁcant bit. Unused register banks, ports and register numbers are reserved and should not be accessed as this may cause device malfunction. When specifying the register bank or port number, the following format is used:

C Port Write

MSB

0 P4 P3 P2 P1 P0

, (Section 19).

LSB

P4:0 represent the Register Bank or Port Number, organized as follows:

P = P

4 P3 P2 P1 P0

P Port/Register Bank

0 Repeater Registers 1 Interrupt Registers 2 Interrupt Control Registers 3 Port Control Registers 4 Port Status Registers 5 RMON Registers 7 Packet Report Registers

16- 30 Port Attributes

The register to be accessed for reading or writing is speciﬁed by writing the following control byte to the C register:

C Port Write

MSB

R = R

4 R3 R2 R1 R0

1 R4 R3 R2 R1 R0

LSB

Figure 1 shows the Management Register Map, and Table 1 shows register banks and register assignments within the register banks.

RMON

Remote monitoring (RMON) functions are designed to give the management system the capability to remotely monitor the hub for diagnostic purposes. The rules for RMON are described in the RMON MIB (as of this writing IETF RFC1578).

The IMR2 device provides direct support for both the statistics and history object groups. Indirect support is provided for the alarm, host, hostTopN, event, and matrix groups. Direct support is provided via the RMON register set and relevant attribute registers. Indirect support is provided through the Packet Report Port.

Packet Reports

The IMR2 device generates status information on every packet that it repeats. The data is transmitted over the Packet Report Port. The data format consists of the beginning of the packet followed by a packet tag and statistical data on the packet.

Preamble DA SA T/L Packet Data

Var. Length Tag & FCS Status

Port No., New

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