AMD Advanced Micro Devices AM79C982-8JC, AM79C982-4JC Datasheet

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PRELIMINARY

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Am79C982

IMR)

asic Integrated Multiport Repeater (

DISTINCTIVE CHARACTERISTICS

Fully backward-compatible with existing IMR/IMR+ device non-managed hub designs

—Pin/socket-compatible with the Am79C980

(IMR) and Am79C981 (IMR+) devices

Repeater functions comply with IEEE 802.3 Repeater Unit speciﬁcations

Four and eight 10BASE-T port options available Low-cost, ﬂexible solutions suitable for

non-managed repeater designs Integral 10BASE-T transceivers utilize the

required predistortion transmission technique Attachment unit interface (AUI) port allows

connectivity with 10BASE-5 (Ethernet) and 10BASE-2 (Cheapernet) networks, as well as 10BASE-F and/or Fiber Optic Inter-Repeater Link (FOIRL) segments

Minimum mode facilitates LED implementation and provides four LED display options for port status

Built-in pulse stretching for carrier sense LED display

On-board PLL, Manchester encoder/decoder, LED display and FIFO

Expandable to increase number of repeater ports

All ports can be separately isolated (partitioned) in response to excessive collision conditions or fault conditions

Network management and optional features are accessible through a dedicated serial management port

Twisted-pair Link Test capability conforming to the 10BASE-T standard. The receive Link Test function can be optionally disabled through the management port to facilitate interoperability with devices that do not implement the Link Test function

Programmable option of Automatic Polarity Detection and Correction permits automatic recovery due to wiring errors

Full amplitude and timing regeneration for retransmitted waveforms

Preamble loss effects eliminated by deep FIFO CMOS device features high integration and low

power with a single +5 V supply

GENERAL DESCRIPTION

asic Integrated Multiport Repeater (

The is a VLSI circuit that provides a system-level solution to designing a compliant 802.3 repeater incorporating 10BASE-T transceivers. The device integrates the Repeater functions speciﬁed by Section 9 of the IEEE 802.3 standard and twisted-pair Transceiver functions complying to the 10BASE-T standard. The Am79C982-4 provides four and the Am79C982-8 provides eight integral twisted-pair medium attachment units (MAUs), and an attachment unit interface (AUI) port in an 84-pin plastic leaded chip carrier (PLCC).

A network based on the 10BASE-T standard uses unshielded twisted-pair cables, therefore providing an economical solution to networking by allowing the use

Publication# 19406 Rev: BAmendment/0 Issue Date: January 1999

IMR™) chip

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

of low-cost unshielded twisted-pair (UTP) cable or existing telephone wiring.

The total number of ports per repeater unit can be increased by connecting multiple their expansion ports, hence minimizing the total cost per repeater port. Furthermore, a general-purpose attachment unit interface (AUI) provides connection capability to 10BASE-5 (Ethernet) and 10BASE-2 (Cheapernet) coaxial networks, as well as 10BASE-F and/or Fiber Optic Inter-Repeater Link (FOIRL) ﬁber segments. Network management and test functions are provided through TTL-compatible I/O pins.

The device is fabricated in CMOS technology and requires a single +5 V supply.

IMR devices through

1-3

AMD

BLOCK DIAGRAM

DI± CI±

DO±

RXD±

TXD± TXP±

RXD±

TXD± TXP±

RST

Note: n=3 for Am79C982-4 and n=7 for Am79C982-8.

AUI Port

Port

TP Port n (Note)

Reset

Clock

Gen

MUX

PRELIMINARY

Manchester

Decoder

Phase =

Locked

Loop

Manchester

Encoder

bIMR Chip

Control

Partitioning

Link Test

Timers

FIFO

Control

Preamble

Jam Sequence

Expansion Port

Test

and

Management

Port

MUX

REQ ACK

COL

DAT JAM

SI SO

SCLK TEST CRS STR

19406B-1

RELATED AMD PRODUCTS

Part No. Description

Am79C98 Twisted Pair Ethernet Transceiver (TPEX) Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+) Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver Am79C981 Integrated Multiport Repeater Plus (IMR+) Am79C987 Hardware Implemented Management Information Base (HIMIB) Am79C940 Media Access Controller for Ethernet (MACE) Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE) Am79C900 Integrated Local Area Communications Controller (ILACC) Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus) Am79C961 PCnet-ISA Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller Am79C970 PCnet-PCI Single-Chip Ethernet Controller (for PCI bus) Am79C974 PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems

Single-Chip Ethernet Controller for ISA (with Microsoft Plug n’ Play Support)

1–4

Am79C982

CONNECTION DIAGRAM

CI+

CI–

DI+

PRELIMINARY

PLCC

RXD0+

DI–

RXD0–

AVSSRXD1+

RXD2+

RXD1–

RXD2–

RDX3+

RXD3–

RXD4+

RXD4–

RXD5+

RXD5–

RXD6+

RXD6–

RXD7+

DO–

DO+

TXD0+ TXD0–

TXP0+

TXP0–

TXD1+ TXD1– TXP1+

TXP1– TXD2+ TXD2– TXP2+

TXP2–

TXD3+ TXD3–

TXP3+

12 13 14

16 17 18

20 21

24 25

26 27 28 29 30

33343536 5352515049484746454443424140393837

TXP3–

STR

CRS

1234567891011

bIMR Chip

Am79C982-8

RST

TEST

SCLK

X1X

75767778798081828384

RXD7–

TXD7+

TXD7–

69 68 67 66

65 64 63 62

ACK

COL

JAM

DAT

REQ

TXP7+ TXP7– DV

TXD6+ TXD6–

TXP6+ TXP6– TXD5+

TXD5– TXP5+ TXP5– DV

TXD4+ TXD4– DV

TXP4+ TXP4–

19406B-2

Am79C982 1-5

CONNECTION DIAGRAM

PRELIMINARY

PLCC

DO– DO+

NC NC

TXD0+ TXD0– TXP0+

TXP0–

NC NC NC NC

TXD1+ TXD1–

TXP1+

CI+

12 13 14

16 17 18

20 21

24 25

26 27 28 29 30

33343536 5352515049484746454443424140393837

CI–

DI+

DI–

} (Note)

AVSSRXD0+

} (Note)

RXD0–

bIMR Chip

Am79C982-4

RDX1+

1234567891011

RXD1–

} (Note)

RXD2+

RXD2–

} (Note)

75767778798081828384

RXD3+

74 73 72 71

69 68 67 66

65 64 63 62

RXD3– TXD3+ TXD3–

TXP3+ TXP3–

NC NC NC NC TXD2+ TXD2– TXP2+ TXP2– DVDD NC NC

NC NC

TXP1–

STR

CRS

TEST

SCLK

RST

Note:

Recommended to be tied together.

1-6 Am79C982

X1X

ACK

COL

JAM

DAT

REQ

19406B-3

LOGIC SYMBOL

Management

Port

AUI

PRELIMINARY

DO+ DO–

DI+ DI–

CI+ CI–

SCLK SI SO

X2 X1 TEST

RST

DD AVDD

Am79C982

SS AVSS

TXD+ TXP+

TXD– TXP–

RXD+ RXD–

DAT JAM

ACK COL REQ

CRS STR

AMD

Twisted Pair

Ports

(4 or 8 Ports)

Expansion

Port

Activity

Monitor

LOGIC DIAGRAM

Management

Port

Twisted Pair

Port 0

AUI

Repeater

State

Machine

19406B-4

Expansion

Port

Twisted Pair

Port n (Note)

Note: n=3 for Am79C982-4 and n=7 for Am79C982-8.

Am79C982

19406B-5

1–7

PRELIMINARY

ORDERING INFORMATION Standard Products

AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below.

Am79C982 J C

DEVICE NUMBER/DESCRIPTION

Am79C982 basic Integrated Multiport Repeater (bIMR)

Valid Combinations

Am79C982-4 JC Am79C982-8 JC

OPTIONAL PROCESSING

Blank = Standard Processing

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

PACKAGE TYPE

J = 84-Pin Plastic Leaded Chip Carrier (PL 084)

SPEED OPTION

–8 = bIMR 8 10BASE-T ports –4 = bIMR 4 10BASE-T ports

Valid Combinations

Valid combinations list conﬁgurations planned to be supported in volume for this device. Consult the local AMD sales ofﬁce to conﬁrm availability of speciﬁc valid combinations and to check on newly released combinations.

1–8 Am79C982

PRELIMINARY

PIN DESCRIPTION ACK

Acknowledge Input, Active LOW

When this input is asserted, it signals to the requesting

IMR device that it may control the DAT and JAM pins.

If the

IMR chip is not requesting control of the DAT line

(REQ

pin HIGH), then the assertion of the ACK signal indicates the presence of valid collision status on the JAM or valid data on the DAT line.

Analog Power Power Pin

These pins supply +5 V to the RXD+/– receivers, the DI+/– and CI+/– receivers, the DO+/– drivers, the inter-

nal PLL, and the internal voltage reference of the

IMR device. These power pins should be decoupled and kept separate from other power and ground planes.

Analog Ground Ground Pin

These pins are the 0 V reference for AV

COL

Expansion Collision Input, Active LOW

When this input is asserted by an external arbiter, it sig-

niﬁes that more than one each

IMR device should generate the Collision Jam

IMR device is active and that

sequence independently.

CI+, CI–

Control In Input

AUI port differential receiver. Signals comply with IEEE

802.3, Section 7.

CRS

Carrier Sense Output

The states of the internal carrier sense signals for the AUI port and the eight twisted-pair ports are serially output on this pin continuously. The output serial bit stream is synchronized to the X

The resolution of the CRS signal is 2 ms. The incoming data is sampled repeatedly during each 2-ms period. If any activity occurs (regardless of length) during any 2-ms period, this activity will be latched. At the start of the next 2-ms period the

latches for each port. For any port for which activity

clock.

IMR device will examine the

occurred, the corresponding bit in the CRS output stream will remain set for the 2-ms period and will be reset at the end of this period.

DAT

Data Input/Output/3-State

In non-collision conditions, the active

IMR device will drive DAT with NRZ data, including regenerated preamble. During collision, when JAM = HIGH, DAT is used to signal a multiport (DAT = 0) or single-port (DAT = 1) condition.

When A

CK is not asserted, DAT is in high impedance. If REQ and ACK are both asserted, then DAT is an output. If ACK is asserted and REQ not asserted, then DAT is an input.

This pin needs to be either pulled up or pulled down through a high-value resistor.

DI+, DI–

Data In Input

AUI port differential receiver. Signals comply with IEEE

802.3, Section 7.

DO+, DO–

Data Out Output

AUI port differential driver. Signals comply with IEEE

802.3, Section 7.

Digital Power Power Pin

These pins supply +5 V to the logic portions of the chip and the TXP+/–, TXD+/–, and DO+/– line drivers.

Digital Ground Ground Pin

These pins are the 0 V reference for DV

Pin # DV

19 16 TP ports 0 & 1 drivers 28 31 TP ports 2 & 3 drivers

43, 49 35, 37, 46, 51

59 56 TP ports 4 & 5 drivers 68 71 TP ports 6 & 7 drivers

Pin # Function

Core logic and expansion and control pins

IMR

Am79C982 1–9

PRELIMINARY

JAM

Jam Input/Output/3-State

When JAM is asserted, the state of DAT will indicate either a multiport (DAT = 0) or single-port (DAT = 1) collision condition.

When A If REQ and ACK are both asserted, then JAM is an output. If ACK is asserted and REQ not asserted, then JAM is an input.

This pin needs to be either pulled up or pulled down through a high-value resistor.

CK is not asserted, JAM is in high impedance.

REQ

Request Output, Active LOW

This pin is driven LOW when the

IMR chip is active when it has one or more ports receiving or colliding or is in the state where it is still transmitting data from the internal FIFO. The assertion of this signal signiﬁes that the ing the use of the DAT and JAM lines for the transfer of repeated data or collision status to other

IMR chip is active. A

IMR device is request-

IMR devices.

RST

Reset Input, Active LOW

Driving this pin LOW resets the internal logic of the

IMR device. Reset should be synchronized to the X clock if either expansion or port activity monitor is used.

RXD+

Receive Data Input

10BASE-T port differential receive inputs (4 or 8 ports).

, RXD–

0–7

(RXD+

, RXD–

0–3

)

SCLK

Serial Clock Input

In normal operating mode, serial data (input or output) is clocked (in or out) on the rising edge of the signal on this pin. SCLK is asynchronous to X1 and can operate up to 10 MHz. In Minimum mode, this pin, together with the SI pin, controls which information is output on the SO pin.

Serial In Input

In normal operating mode, the SI pin is used for test/ management serial input port. Management commands are clocked in on this pin synchronous to the SCLK input. In Minimum mode, this pin, together with the SCLK pin, controls which information is output on the SO pin.

In Minimum mode, the state of SI at the deassertion of RST

signal determines the programming of automatic

polarity detection/correction for 10BASE-T ports.

Serial Out Output

In normal operating mode, the SO pin is used for test/ management serial output port. Management results are clocked out on this pin synchronous to the SCLK input. In Minimum mode, the SO pin is used to output the various status information serially based on the state of the SI and SCLK pins.

SCLK SI SO Output

0 0

0 1 Bit Rate Error (all ports)

1 0

1 1 Port Partitioning Status (all ports)

TP Ports Receive Polarity Status + AUI SQE Test Error Status

TP Ports Link Status + AUI Loopback Status

STR

Store Output

The STR pin goes HIGH for two X1 clock cycle times after the nine carrier sense bits are output on the CRS pin. Note that the carrier sense signals arriving from each port are latched internally, so that an active tran-

sition is remembered between samples.

TEST

Test Pin Input, Active HIGH

This pin should be tied LOW for normal operation. If this pin is driven HIGH, then the bIMR device can be programmed for Loopback Test mode. Also, if this pin is HIGH when the RST pin is deasserted, the bIMR device will enter the Minimum mode. An inverted version of the RST signal can be used to program the device into the Minimum mode.

Test SI Functions

0 0 Normal Management Mode 0 1 Normal Management Mode 1 0 Minimum Mode, Receive

Polarity Correction Disabled

1 1 Minimum Mode, Receive

Polarity Correction Enabled

1–10 Am79C982

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