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PRELIMINARY
Am79C981
Integrated Multiport Repeater Plus™ (IMR+™)
DISTINCTIVE CHARACTERISTICS
Enhanced version of AMD’s Am79C980
Integrated Multiport Repeater™ (IMR™) chip
with the following enhancements:
—Additional management port features
— Minimum mode provides support for an extra
four LED outputs per port for additional status in
non-intelligent repeater designs
—Pin/socket-compatible with the Am79C980
IMR chip
—Fully backward-compatible with existing IMR
device designs
Interfaces directly with the Am79C987 HIMIB™
device to build a fully managed multiport
repeater
CMOS device features high integration and low
power with a single +5 V supply
Repeater functions comply with IEEE 802.3
Repeater Unit specifications
Eight integral 10BASE-T transceivers utilize the
required predistortion transmission technique
Attachment unit interface (AUI) port allows
connectivity with 10BASE-5 (Ethernet) and
10BASE-2 (Cheapernet) networks, as well as
10BASE-F and/or Fiber Optic Inter-Repeater
Link (FOIRL) segments
On-board PLL, Manchester encoder/decoder,
and FIFO
Expandable to increase number of repeater
ports
All ports can be separately isolated (partitioned)
in response to excessive collision conditions or
fault conditions
Network management and optional features are
accessible through a dedicated serial
management port
Twisted-pair Link Test capability conforming to
the 10BASE-T standard. The receive Link Test
function can be optionally disabled through the
management port to facilitate interoperability
with devices that do not implement the Link Test
function
Programmable option of Automatic Polarity
Detection and Correction permits automatic
recovery due to wiring errors
Full amplitude and timing regeneration for
retransmitted waveforms
Preamble loss effects eliminated by deep FIFO
GENERAL DESCRIPTION
The Integrated Multiport Repeater Plus (IMR+) chip is a
VLSI circuit that provides a system-level solution to designing a compliant 802.3 repeater incorporating
10BASE-T transceivers. The device integrates the
Repeater functions specified by Section 9 of the IEEE
802.3 standard and Twisted-Pair Transceiver functions
complying with the 10BASE-T standard. The Am79C981
provides eight integral twisted-pair medium attachment
units (MAUs) and an attachment unit interface (AUI) port
in an 84-pin plastic leaded chip carrier (PLCC).
A network based on the 10BASE-T standard uses unshielded twisted-pair cables, thereby providing an economical solution to networking by allowing the use of
low-cost unshielded twisted-pair (UTP) cable or existing
telephone wiring.
The total number of ports per repeater unit can be increased by connecting multiple IMR+ devices through
Publication# 17306 Rev: BAmendment/0
Issue Date: January 1999
This document contains information on a product under development at Advanced Micro Devices. The
information is intended to help you evaluate this product. AMD reserves the right to change or discontinue
work on this proposed product without notice.
their expansion ports, minimizing the total cost per repeater port. Furthermore, a general-purpose attachment unit interface (AUI) provides connection capability
to 10BASE-5 (Ethernet) and 10BASE-2 (Cheapernet)
coaxial networks, as well as 10BASE-F and/or Fiber
Optic Inter-Repeater Link (FOIRL) fiber segments. Network management and test functions are provided
through TTL-compatible I/O pins.
The IMR+ device interfaces directly with AMD’s
Am79C987 Hardware Implemented Management Information Base™ (HIMIB) chip to build a fully managed
multiport repeater as specified by the IEEE 802.3
(Layer Management for 10 Mb/s Baseband Repeaters)
standard. When the IMR+ and HIMIB devices are
interconnected, complete repeater and per-port statistics are maintained and can be accessed on demand
using a simple 8-bit parallel interface.
1-71
AMD
PRELIMINARY
For application examples on building a fully managed
repeater using the IMR+ and HIMIB devices, refer to
AMD’s IEEE 802.3 Repeater Technical Manual
(PID#17314A) and the ISA-HUB
TM
User Manual
(PID # 17642A).
BLOCK DIAGRAM
DI±
CI±
DO±
RXD±
TXD±
TXP±
RXD±
TXD±
TXP±
RST
AUI
Port
TP
Port
0
TP
Port
7
Reset
RX
MUX
Manchester
Decoder
Phase =
Locked
Loop
Manchester
Encoder
IMR+ Chip
Partitioning
The device is fabricated in CMOS technology and requires a single +5 V supply.
FIFO
Preamble
Jam Sequence
FIFO
Control
Control
Expansion Port
Link Test
TX
MUX
REQ
ACK
COL
DAT
JAM
X
1
X
2
Clock
Gen
Timers
RELATED AMD PRODUCTS
Part No. Description
Am79C98 Twisted Pair Ethernet Transceiver (TPEX)
Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)
Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver
Am79C987 Hardware Implemented Management Information Base (HIMIB)
Am79C940 Media Access Controller for Ethernet (MACE)
Am7990 Local Area Network Controller for Ethernet (LANCE)
Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)
Am79C900 Integrated Local Area Communications Controller (ILACC)
Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)
Am79C961 PCnet-ISA
Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller
Am79C970 PCnet-PCI Single-Chip Ethernet Controller (for PCI bus)
Am79C974 PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems
+
Single-Chip Ethernet Controller for ISA (with Microsoft Plug n’ Play Support)
Test
and
Management
Port
SI
SO
SCLK
TEST
CRS
STR
17306B-1
1–72
Am79C981
CONNECTION DIAGRAM
CI+
CI–
DI+
PRELIMINARY
PLCC
RXD0+
DI–
RXD0–
AVSSRXD1+
RXD2+
RXD1–
RXD2–
RDX3+
DD
RXD3–
AV
RXD4+
RXD4–
RXD5+
RXD5–
RXD6+
RXD6–
RXD7+
DO–
DO+
TXD0+
TXD0–
DV
SS
TXP1+
TXP1–
DV
DD
TXD1+
TXD1–
TXP1+
TXP1–
TXD2+
TXD2–
TXP2+
TXP2–
DV
DD
TXD3+
TXD3–
DV
SS
TXP3+
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33343536 5352515049484746454443424140393837
SO
TXP3–
SS
DV
STR
DV
SS
CRS
SI
SCLK
1234567891011
IMR+ Chip
Am79C981
X1X
DD
RST
DV
TEST
75767778798081828384
74
RXD7–
73
TXD7+
72
TXD7–
71
DV
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
2
SS
DV
ACK
COL
DD
DV
JAM
SS
DV
DAT
REQ
SS
TXP7+
TXP7–
DV
DD
TXD6+
TXD6–
TXP6+
TXP6–
TXD5+
TXD5–
TXP5+
TXP5–
DV
DD
TXD4+
TXD4–
DV
SS
TXP4+
TXP4–
17306B-2
Am79C981 1–73
AMD
LOGIC SYMBOL
Management
Port
AUI
PRELIMINARY
DV
DO+
DO–
DI+
DI–
CI+
CI–
SCLK
SI
SO
X2
X1
TEST
RST
DV
DD AVDD
Am79C981
SS AVSS
TXD+
TXP+
TXD–
TXP–
RXD+
RXD–
DAT
JAM
ACK
COL
REQ
CRS
STR
Twisted Pair
Ports
(8 Ports)
Expansion
Port
Port
Activity
Monitor
LOGIC DIAGRAM
Management
Port
Twisted Pair
Port 0
AUI
Repeater
State
Machine
17306B-3
Expansion
Port
Twisted Pair
Port 7
1–74
17306B-4
Am79C981
PRELIMINARY
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed
by a combination of the elements below.
Am79C981 J C
DEVICE NUMBER/DESCRIPTION
Am79C981
Integrated Multiport Repeater Plus (IMR+)
Valid Combinations
Am79C981 JC
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
PACKAGE TYPE
J = 84-Pin Plastic Leaded Chip Carrier (PL 084)
SPEED
Not Applicable
Valid Combinations
Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am79C981 1–75
PRELIMINARY
PIN DESCRIPTION
ACK
Acknowledge
Input, Active LOW
When this input is asserted, it signals to the requesting
IMR+ device that it may control the DAT and JAM pins.
If the IMR+ chip is not requesting control of the DAT line
pin HIGH), then the assertion of the ACK signal
(REQ
indicates the presence of valid collision status on the
JAM or valid data on the DAT line.
AV
DD
Analog Power
Power Pin
These pins supply the +5 V to the RXD+/– receivers,
the DI+/– and CI+/– receivers, the DO+/– drivers, the
internal PLL, and the internal voltage reference of the
IMR+ device. These power pins should be decoupled
and kept separate from other power and ground
planes.
AV
SS
Analog Ground
Ground Pin
These pins are the 0 V reference for AV
DD
.
COL
Expansion Collision
Input, Active LOW
When this input is asserted by an external arbiter, it signifies that more than one IMR+ device is active and that
each IMR+ device should generate the Collision Jam
sequence independently.
CI+, CI–
Control In
Input
AUI port differential receiver. Signals comply with IEEE
802.3, Section 7.
CRS
Carrier Sense
Output
The states of the internal carrier sense signals for the
AUI port and the eight twisted-pair ports are serially
output on this pin continuously. The output serial bit
stream is synchronized to the X
clock.
1
DAT
Data
Input/Output/3-State
In non-collision conditions, the active IMR+ device will
drive DAT with NRZ data, including regenerated preamble. During collision, when JAM = HIGH, DAT is
used to signal a multiport (DAT = 0) or single-port
(DAT = 1) condition.
When A
CK is not asserted, DAT is in high impedance.
If REQ and ACK are both asserted, then DAT is an output. If ACK is asserted and REQ not asserted, then
DAT is an input.
This pin needs to be either pulled up or pulled down
through a high-value resistor.
DI+, DI–
Data In
Input
AUI port differential receiver. Signals comply with IEEE
802.3, Section 7.
DO+, DO–
Data Out
Output
AUI port differential driver. Signals comply with IEEE
802.3, Section 7.
DV
DD
Digital Power
Power Pin
These pins supply +5 V to the logic portions of the
IMR+ chip and the TXP+/–, TXD+/–, and DO+/– line
drivers.
DV
SS
Digital Ground
Ground Pin
These pins are the 0 V reference for DV
DV
Pin # DV
DD
19 16 TP ports 0 & 1 drivers
28 31 TP ports 2 & 3 drivers
43, 49 35, 37, 46, 51
59 56 TP ports 4 & 5 drivers
68 71 TP ports 6 & 7 drivers
Pin # Function
SS
Core logic and expansion
and control pins
DD
.
JAM
Jam
Input/Output/3-State
When JAM is asserted, the state of DAT will indicate
either a multiport (DAT = 0) or single-port (DAT = 1) collision condition.
When A
If REQ and ACK are both asserted, then JAM is an output. If ACK is asserted and REQ not asserted, then
JAM is an input.
This pin needs to be either pulled up or pulled down
through a high-value resistor.
CK is not asserted, JAM is in high impedance.
1–76 Am79C981
PRELIMINARY
REQ
Request
Output, Active LOW
This pin is driven LOW when the IMR+ chip is active.
An IMR+ chip is active when it has one or more ports
receiving or colliding or is in the state where it is still
transmitting data from the internal FIFO. The assertion
of this signal signifies that the IMR+ device is requesting the use of the DAT and JAM lines for the transfer of
repeated data or collision status to other IMR+ devices.
RST
Reset
Input, Active LOW
Driving this pin LOW resets the internal logic of the
IMR+ device. Reset should be synchronized to the X
clock if either expansion or port activity monitor is used.
RXD+
, RXD–
0–7
0–7
Receive Data
Input
10BASE-T port differential receive inputs (8 ports).
SCLK
Serial Clock
Input
In normal operating mode, serial data (input or output)
is clocked (in or out) on the rising edge of the signal on
this pin. SCLK is asynchronous to X
and can operate
1
up to 10 MHz. In Minimum mode, this pin, together with
the SI pin, controls which information is output on the
SO pin.
SI
Serial In
Input
In normal operating mode, the SI pin is used for test/
management serial input port. Management commands are clocked in on this pin synchronous to the
SCLK input. In Minimum mode, this pin, together with
the SCLK pin, controls which information is output on
the SO pin.
In Minimum mode, the state of SI at the deassertion of
signal determines the programming of automatic
RST
polarity detection/correction for 10BASE-T ports.
SO
Serial Out
Output
In normal operating mode, the SO pin is used for test/
management serial output port. Management results
are clocked out on this pin synchronous to the SCLK
input. In Minimum mode, the SO pin is used to serially
output the various status information based on the
state of the SI and SCLK pins.
SCLK SI SO Output
0 0
0 1 Bit Rate Error (all ports)
1 0
1 1 Port Partitioning Status (all ports)
TP Ports Receive Polarity Status + AUI
SQE Test Error Status
TP Ports Link Status + AUI Loopback
Status
STR
Store
Input/Output
1
As an output, this pin goes HIGH for two X
times after the nine carrier sense bits are output on the
CRS pin. Note that the carrier sense signals arriving
from each port are latched internally, so that an active
transition is remembered between samples. The accuracy of the carrier sense signals produced in this manner is 10 bit times (1 µ s).
When used in conjunction with the HIMIB device, the
STR pin will be configured as an input automatically
after a hardware reset. The HIMIB device uses this
input to communicate with the IMR+ device. When
used with the HIMIB chip, this pin must be pulled up via
a high-value resistor.
TEST
Test Pin
Input, Active HIGH
This pin should be tied LOW for normal operation. If
this pin is driven HIGH, then the IMR+ device can be
programmed for Loopback Test mode. Also, if this pin is
HIGH when the RST
vice will enter the Minimum mode. An inverted version
of the RST signal can be used to program the device
into the Minimum mode.
Test SI Functions
0 0 Normal Management Mode
0 1 Normal Management Mode
1 0
1 1
pin is deasserted, the IMR+ de-
Minimum Mode, Receive Polarity
Correction Disabled
Minimum Mode, Receive Polarity
Correction Enabled
clock cycle
1
Am79C981 1–77
PRELIMINARY
TXD+
0–7
, TXD–
0–7
Transmit Data
Output
10BASE-T port differential drivers (8 ports).
TXP+
0–7
, TXP–
0–7
Transmit Predistortion
Output
10BASE-T transmit waveform predistortion control
differential outputs (8 ports).
X
1
Crystal 1
Crystal Connection
The internal clock generator uses a 20 MHz crystal attached to pins X
and X
1
. Alternatively, an external
2
20MHz CMOS clock signal can be used to drive this
pin.
X
2
Crystal 2
Crystal Connection
The internal clock generator uses a 20 MHz crystal attached to pins X
and X
1
. If an external clock source is
2
used, this pin should be left unconnected.
1–78 Am79C981
PRELIMINARY
FUNCTIONAL DESCRIPTION
The Am79C981 Integrated Multiport Repeater Plus device is a single chip implementation of an IEEE
802.3/Ethernet repeater (or hub). In addition to the eight
integral 10BASE-T ports plus one AUI port comprising
the basic repeater, the IMR+ chip also provides the
hooks necessary for complex network management
and diagnostics. The IMR+ device is also expandable,
enabling the implementation of high port count repeaters based on several IMR+ devices.
The IMR+device interfaces directly with AMD’s
Am79C987 Hardware Implemented Management Information Base (HIMIB) device to allow a fully managed
multiport repeater to be implemented as specified by the
Layer Management for 10 Mb/s Baseband Repeaters
Standard. When the IMR+ and HIMIB devices are used
as a chip set, the HIMIB device maintains complete repeater and per port statistics which can be accessed on
demand by a microprocessor through a simple 8-bit parallel port.
The IMR+ chip complies with the full set of repeater basic functions as defined in section 9 of ISO 8802.3
(ANSI/IEEE 802.3c). These functions are summarized
below.
Repeater Function
If any single network port senses the start of a valid
packet on its receive lines, then the IMR+ device will retransmit the received data to all other enabled network
ports. The repeated data will also be presented on the
DAT line to facilitate multiple-IMR+ device repeater
applications.
Signal Regeneration
When re-transmitting a packet, the IMR+ device ensures that the outgoing packet complies with the 802.3
specification in terms of preamble structure, voltage amplitude, and timing characteristics. Specifically, data
packets repeated by the IMR+ chip will contain a minimum of 56 preamble bits before the Start of Frame Delimiter. In addition, the voltage amplitude of the repeated
packet waveform will be restored to levels specified in
the 802.3 specification. Finally, signal symmetry is restored to data packets repeated by the IMR+ device,
removing jitter and distortion caused by the network
cabling.
Jabber Lockup Protection
The IMR+ chip implements a built-in jabber protection
scheme to ensure that the network is not disabled due to
transmission of excessively long data packets. This protection scheme will automatically interrupt the transmitter circuits of the IMR+ device for 96-bit times if the IMR+
device has been transmitting continuously for more than
65,536-bit times. This is referred to as MAU Jabber
Lockup Protection (MJLP). The MJLP status for the
AMD
IMR+ chip can be read through the Management Port
using the Get MJLP Status command (M bit returned).
CollisionHandling
The IMR+ chip will detect and respond to collision conditions as specified in 802.3. A multiple-IMR+ device repeater implementation also complies with the 802.3
specification due to the inter-IMR+ chip status communication provided by the expansion port. Specifically, a
repeater based on one or more IMR+ devices will handle the transmit collision and one-port-left collision conditions correctly as specified in Section 9 of the 802.3
specification.
Fragment Extension
If the total packet length received by the IMR+ device is
less than 96 bits, including preamble, the IMR+ chip will
extend the repeated packet length to 96 bits by appending a Jam sequence to the original fragment.
Auto Partitioning/Reconnection
Any of the integral TP ports and AUI port can be partitioned under excessive duration or frequency of collision conditions. Once partitioned, the IMR+ device will
continue to transmit data packets to a partitioned port,
but will not respond (as a repeater) to activity on the partitioned port’s receiver. The IMR+ chip will monitor the
port and reconnect it once certain criteria indicating port
‘wellness’ are met. The criteria for reconnection are
specified by the 802.3 standard. In addition to the standard reconnection algorithm, the IMR+ device implements an alternative reconnection algorithm which
provides a more robust partitioning function for the TP
ports and/or the AUI port. Each TP port and the AUI port
are partitioned and/or reconnected separately and independently of other network ports.
Either one of the following conditions occuring on any
enabled IMR+ device network port will cause the port to
partition:
a. A collision condition exists continuously for a time
between 1024- to 2048-bit times (AUI port—SQE
signal active; TP port—simultaneous transmit and
receive)
b. A collision condition occurs during each of 32 con-
secutive attempts to transmit to that port.
Once a network port is partitioned, the IMR+ device will
reconnect that port if the following is met:
a.Standard reconnection algorithm—A data packet
longer than 512-bit times (nominal) is transmitted or
received by the partitioned port without a collision.
b. Alternate reconnection algorithm—A data packet
longer than 512-bit times (nominal) is transmitted by
the partitioned port without a collision.
Am79C981
1–79
AMD
PRELIMINARY
The reconnection algorithm option (standard or alternate) is a global function for the TP ports, i.e. all TP ports
use the same reconnection algorithm. The AUI
reconnection algorithm option is programmed independently of the TP port reconnection option.
Link Test
The integral TP ports implement the Link Test function
as specified in the 802.3 10BASE-T standard. The IMR+
device will transmit Link Test pulses to any TP port after
that port’s transmitter has been inactive for more than 8
to 17 ms. Conversely, if a TP port does not receive any
data packets or Link Test pulses for more than 65 to
132 ms and the Link Test function is enabled for that
port then that port will enter link fail state. A port in link
fail state will be disabled by the IMR+ chip (repeater
transmit and receive functions disabled) until it receives
either four consecutive Link Test pulses or a data packet. The Link Test receive function itself can be disabled
via the IMR+ chip management port on a port-by-port
basis to allow the IMR+ device to interoperate with pre10BASE-T twisted pair networks that do not implement
the Link Test function. This interoperability is possible
because the IMR+ device will not allow the TP port to enter link fail state, even if no Link Test pulses or data
packets are being received. Note however that the
IMR+ chip will always transmit Link Test pulses to all TP
ports regardless of whether or not the port is enabled,
partitioned, in link fail state, or has its Link Test receive
function disabled.
Polarity Reversal
The TP ports have the optional (programmable) ability
to invert (correct) the polarity of the received data if the
TP port senses that the received data packet waveform
polarity is reversed due to a wiring error. This receive
circuitry polarity correction allows subsequent packets
to be repeated with correct polarity. This function is executed once following reset or link fail, and has a
programmable enable/disable option on a port-by-port
basis. This function is disabled upon reset and can be
enabled via the IMR+ chip Management Port.
Reset
The IMR+ device enters reset state when the RST pin is
driven LOW. After the initial application of power, the
RST pin must be held LOW for a minimum of 150 µs
(3000 X1 clock cycles). If the RST pin is subsequently
asserted while power is maintained to the IMR+ device,
a reset duration of only 4 µs is required. The IMR+ chip
continues to be in the reset state for 10 X1 clocks
(0.5 µs) following the rising edge of RST. During reset,
the output signals are placed in their inactive states.
This means that all analog signals are placed in their idle
states, bidirectional signals (except STR signal) are not
driven, active LOW signals are driven HIGH, and all active HIGH signals and the STR pin are driven LOW.
An internal circuit ensures that a minimum reset pulse is
generated for all internal circuits. For a RST input with a
slow rising edge, the input buffer threshold may be
crossed several times due to ripple on the input
waveform.
In a multiple IMR+ chip repeater the RST signal should
be applied simultaneously to all IMR+ devices and
should be synchronized to the external X1 clock. Reset
synchronization is also required when accessing the
PAM (Port Activity Monitor).
The SI signal should be held HIGH for at least 500 ns following the rising edge of RST.
Table 1 summarizes the state of the IMR+ chip following
reset.
Table 1. IMR+ Chip After Reset
Function State After Reset Pull Up/Pull Down
Active LOW outputs HIGH No
Active HIGH outputs LOW No
SO Output HIGH No
DAT, JAM HI-IMPEDANCE Either
STR LOW Pull Up*
Transmitters (TP and AUI) IDLE No
Receivers (TP and AUI) ENABLED Terminated
AUI Partitioning/Reconnection Algorithm STANDARD ALGORITHM N/A
TP Port Partitioning/Reconnection Algorithm STANDARD ALGORITHM N/A
Link Test Function for TP Ports ENABLED, TP PORTS IN LINK FAIL N/A
Automatic Receiver Polarity Reversal Function DISABLED N/A
*Only when used with the HIMIB device.
1–80
Am79C981
PRELIMINARY
Expansion Port
The IMR+ chip Expansion Port is comprised of five pins;
two are bi-directional signals (DAT and JAM), two are input signals (ACK and COL), and one is an output signal
(REQ). These signals are used when a multiple-IMR+
device repeater application is employed. In this configuration, all IMR+ chips must be clocked synchronously
with a common clock connected to the X1 inputs of all
IMR+ devices. Reset needs to be synchronized to
X1 clock.
The IMR+ device expansion scheme allows the use of
multiple IMR+ chips in a single board repeater or a
modular multiport repeater with a backplane architecture. The DAT pin is a bidirectional I/O pin which can be
used to transfer data between the IMR+ devices in a
multiple-IMR+ chip design. The data sent over the DAT
line is in NRZ format and is synchronized to the common
clock. The JAM pin is another bidirectional I/O pin that is
used by the active IMR+ chip to communicate its internal
status to the remaining (inactive) IMR+ devices. When
JAM is asserted HIGH, it indicates that the active IMR+
device has detected a collision condition and is generating Jam Sequence. During this time when JAM is asserted HIGH, the DAT line is used to indicate whether
the active IMR+ chip is detecting collision on one port
only or on more than one port. When DAT is driven
HIGH by the IMR+ chip (while JAM is asserted by the
IMR+ chip), then the active IMR+ device is detecting a
collision condition on one port only. This ‘one-port-left’
signaling is necessary for a multiple-IMR+ device repeater to function correctly as a single multiport repeater
unit. The IMR+ chip also signals the ‘one port left’ collision condition in the event of a runt packet or collision
fragment; this signal will continue for one expansion port
bus cycle (100 ns) before deasserting REQ.
The arbitration for access to the bussed bi-directional
signals (DAT and JAM) is provided by one output (REQ)
and two inputs (ACK and COL). The IMR+ chip asserts
the REQ pin to indicate that it is active and wishes to
drive the DAT and JAM pins. An external arbiter senses
the REQ lines from all the IMR+ devices and asserts the
ACK line when one and only one IMR+ chip is asserting
its REQ line. If more than one IMR+ chip is asserting its
REQ line, the arbiter must assert the COL signal, indi-
cating that more than one IMR+ device is active. More
AMD
than one active IMR+ device at a time constitutes a collision condition, and all IMR+ devices are notified of this
occurence via the COL line of the Expansion Port.
Note that a transition from multiple IMR+ devices arbitrating for the DAT and JAM pins (with COL asserted,
ACK deasserted) to a condition when only one IMR+
chip is arbitrating for the DAT and JAM pins (with ACK
asserted, COL deasserted) involves one expansion port
bus cycle (100 ns). During this transitional bus cycle,
COL is deasserted, ACK is asserted, and the DAT and
JAM pins are not driven. However, each IMR+ device
will remain in the collision state (transmitting jam sequence) during this transitional bus cycle. In subsequent expansion port bus cycles (REQ and ACK still
asserted), the IMR+ devices will return to the ‘master
and slaves’ condition where only one IMR+ device is active (with collision) and is driving the DAT and JAM pins.
An understanding of this sequence is crucial if nonIMR+ devices (such as an Ethernet controller) are connected to the expansion bus. Specifically, the last
device to back off of the Expansion Port after a multiIMR+ chip collision must assert the JAM line until it too
drops its request for the Expansion Port.
External Arbiter
A simple arbitration scheme is required when multiple
IMR+ devices are connected together to increase the total number of repeater ports. The arbiter should have
one input (REQ1...REQn) for each of the n IMR+ devices to be used, and two global outputs (COL and
ACK). This function is easily implemented in a PAL
vice, with the following logic equations:
ACK= REQ1 & REQ2 & REQ3 & ....REQn
+ REQ1
& REQ2 & REQ3 & ....REQn
•
•
•
+ REQ1 & REQ2 & REQ3 & .... REQn
COL= ACK & (REQ1 + REQ2 + REQ3 + ... REQn)
Above equations are in positive logic, i.e., a variable is
true when asserted.
A single PALCE16V8 will perform the arbitration function for a repeater based on several IMR+ devices.
de-
Am79C981
1–81
AMD
ASYNC
RESET
1/2 ’74
D
D FF
CK
XTAL
OSC.
PRELIMINARY
Bus transceivers needed
REQ2REQ3REQ1
COL
ARBITER
ACK
ACK
REQ
ACK
COL
Q
RST
X1
ACK
COL
RST
X1
REQ
Am79C981
IMR+ Chip
1
REQ
Am79C981
IMR+ Chip
2
DAT
JAM
DAT
JAM
if DAT and JAM buses
exceed 100 pF loading.
DIR
AB
Note 1
Note 1:
Direction DIR
B → A LOW
A → B HIGH
Figure 1. Multiple IMR+ Devices
Modular Repeater Design
The expansion port of the IMR+ chip also allows for
modular expansion. By sharing the arbitration duties between a backplane bus architecture and several separate repeater modules one can build an expandable
repeater based on modular ‘plug-in’ cards. Each
ACK
COL
RST
X1
REQ
Am79C981
IMR+ Chip
3
DAT
JAM
repeater module performs the local arbitration function
for the IMR+ devices on that module, and provides signals to the backplane for use by a global arbiter.
For more detailed information, see AMD’s IEEE 802.3
Repeater Technical Manual, PID# 17314A.
17306B-5
1–82
Am79C981
PRELIMINARY
Repeater MAC Interconnection
Because all repeated data in the IMR+ chip or multiIMR+ chip design is available on the Expansion Port, all
network traffic can be monitored by an external Media
Access Controller (MAC) device such as the Am7990,
Am79C900, Am79C940, or Am79C960. A repeater with
such a controller is capable of providing extensive hub
management functions, as well as being addressable as
a network node. The MAC device can gather statistics
and data concerning the state of the hub and the
Am79C960 PCnet-ISA
PALCE16V8
COL
JAM
DAT
DONE_COUNT
Q0
Q1
Q2
Counter
Q3
PALCE22V10
Q4
Q5
Q6
NEW96
ARST
TCK
20MHz
RESET
TxC
DONE_COUNT
NEW96
REQ1
network, and the network addressability allows a remote
management station to monitor this statistical data and
to request actions to be performed by the repeater (i.e.
port enable/disable).
Figure 2 shows how to interface a repeater based on
multiple IMR+ devices to an Ethernet controller such as
the Am79C900 ILACC or the Am7990 LANCE. For more
information on this design, refer to AMD’s IEEE 802.3
Repeater Technical Manual, PID# 17314A.
Am7990 LANCE
Am79C900 ILACC
Am79C940 MACE
or
RTS
RTS
PALCE16V8
CDTCDT
JAM
DAT
RENA
RXD
CRS
DATA
SYNC
Interface
RXC
RXC
RTSCLK
RCKEN
ACKCLK
ACK
TCK
RTSCLK
Arbiter
ACK
XCOL
REQ2
ACKCLK
COLCLK
TCK
REQn
CDT
RTS
TCK
AMD
TXD
TXD
TCK
ARST
DAT
X1
20 MHz Osc.
JAM
IMR+1
DAT
X1
JAM
IMR+2
COL
ACK
RST
REQ
COL
ACK
RST
REQ
Figure 2. Expandable Modular Repeater
DAT
JAM
X1
14396C-033A
COL
IMR+n
ACK
REQ
RST
17306B-6
Am79C981
1–83
AMD
PRELIMINARY
Management Port
The IMR+ device management functions are enabled
when the TEST pin is tied LOW. The management commands are byte oriented data and are input serially on
the SI pin. Any responses generated during execution of
a management command are output serially in a byteoriented format by the IMR+ device on the SO pin. Both
the input and output data streams are clocked with the
rising edge of the SCLK pin. The serial command data
stream and any associated results data stream are
structured in a manner similar to the RS232 serial data
format, i.e., one Start Bit followed by eight Data Bits.
The externally generated clock at the SCLK pin can be
either a free running clock synchronized to the input bit
patterns or a series of individual transitions meeting the
Command Execution Phase Results Phase
SCLK
setup and hold times with respect to the input bit pattern.
If the latter method is used, it is to be noted that 20 SCLK
clock transitions are required for proper execution of
management commands that produce SO data, and
that 14 SCLK clock transitions are needed to execute
management commands that do not produce SO data.
Management Commands
The following section details the operation of each management command available in the IMR+ chip. In all
cases, the individual bits in each command byte are
shown with the MSB on the left and the LSB on the right.
Data bytes are received and transmitted LSB first and
MSB last. See Table 2 for a summary of the management commands.
Next Command
SO
SCLK
SO
SI
STRTD0 D1D2D3D4D5D6 D7
STRTD0 D1D2D3D4D5D6 D7
17306B-17
Management Command/Response Timing
Command Execution Phase Next Command Execution Phase
SI
STRTD0 D1D2D3D4D5D6 D7 STRTD0 D1D2D3D4D5D6 D7
17306B-18
Management Command Timing with No Response
1–84
Am79C981
PRELIMINARY
Table 2. Management Port Command Summary
Commands SI Data SO Data
Set (Write) Opcodes
IMR+ Chip Programmable Options 0000 1CSA
Alternate AUI Partitioning Algorithm 0001 1111
Alternate TP Partitioning Algorithm 0001 0000
AUI Port Disable 0010 1111
AUI Port Enable 0011 1111
TP Port Disable 0010 0###
TP Port Enable 0011 0###
Disable Link Test Function (per TP port) 0100 0###
Enable Link Test Function (per TP port) 0101 0###
Disable Automatic Receiver Polarity Reversal (per TP port) 0110 0###
Enable Automatic Receiver Polarity Reversal (per TP port) 0111 0###
Get (Read) Opcodes
AUI Port Status (B, S, L Cleared) 1000 1111 PBSL 0000
TP Port Partitioning Status 1000 0000 C7...C0
Bit Rate Status of TP ports 1010 0000 E7...E0
Link Test Status of TP ports 1101 0000 L7...L0
Receive Polarity Status of all TP ports 1110 0000 P7...P0
MJLP Status 1111 0000 M000 0000
Version 1111 1111 XXXX 0001
AUI Port Status (S, L Cleared) 1000 1011 PBSL 0000
AUI Port Status (B Cleared) 1000 1101 PBSL 0000
AUI Port Status (None Cleared) 1000 1001 PBSL 0000
AMD
Notes:
1. Unused opcodes are reserved for future use.
2. ### is the port number (000 to 111 for TP0 to TP7)
Am79C981
1–85
AMD
PRELIMINARY
SET (Write) Opcodes
IMR+ Chip Programmable Options
SI data: 0000 1CSA
SO data: None
IMR+ Chip Programmable Options can be enabled (dis-
abled) by setting (resetting) the appropriate bit in the
command string. The three programmable bits are:
C—CI Reporting; S—AUI SQE Test Mask, and
A—Alternative Port Activity Monitor (PAM) Function.
These options can be enabled (disabled) by setting (resetting) the appropriate bit in the command string.
When writing to this register through the Am79C987
HIMIB device, the A and C bits should not be changed
(A=0, C=1).
C—CI Reporting
Setting this bit alters the function of the STR pin. In this
mode, the STR pin becomes an input in response to the
AMD’s Am79C987 HIMIB device. Upon deassertion of
RST, the HIMIB automatically sets this bit following IMR/
IMR+ device type detection.
When this mode is selected, the CRS output bit string
format is modified to include CI carrier bit (in addition to
AUI carrier). This bit occupies the bit position immediately preceding the AUI bit in the CRS bit string (10 bits)
output. Note that the AUI bit gets asserted if either the CI
or DI signal pairs are active.
S—AUI SQE Test Mask
Setting this bit allows the IMR+ chip to ignore activity on
the CI signal pair, in the SQE Test Window, following a
transmission on the AUI port. This event occurs when
the attached MAU has the SQE Test option enabled,
therefore generating a burst of CI activity following every
transmission. This is interpreted by the IMR+ device as
a collision, causing the IMR+ device to generate a full
Jam pattern. Although the MAU attached to a repeater is
required not to have its SQE test function active, this is a
common installation error, causing difficulty in diagnosing network throughput problems.
The SQE Test Window, as defined by the IEEE 802.3
(Section 7.2.2.2.4), is from 6-bit times to 34-bit times
(0.6 µs to 3.4 µs). This includes delay introduced by a
50 m AUI. CI activity that occurs outside this window is
not ignored and is treated as true collision.
A—Alternative Port Activity Monitor (PAM)
Function
Setting the Alternative Port Activity Monitor Function allows the PAM function to be altered such that the Carrier
Sense data is presented unmodified. In default operation the PAM output (Carrier Sense bits in the CRS bit
stream) are masked if the port is either disabled or partitioned. This does not allow the Repeater Management
software to sense activity on all segments at all times.
The ability to monitor partitioned or disabled ports allows
fault tolerance to be built into the Repeater Management
software.
Alternate AUI Port Partitioning Algorithm
SI data: 00011111
SO data: None
The AUI port Partitioning/Reconnection scheme can be
programmed for the alternate (transmit only) reconnection algorithm by invoking this command. To return the
AUI back to the standard (transmit or receive)
reconnection algorithm, it is necessary to reset the
IMR+ device. Standard partitioning algorithm is selected upon reset.
Alternate TP Ports Partitioning Algorithm
SI data: 00010000
SO data: None
The TP ports Partitioning/Reconnection scheme can be
programmed for the alternate (transmit only)
reconnection algorithm by invoking this command. All
TP ports are affected as a group by this command. To
return the TP ports back to the standard (transmit or receive) reconnection algorithm, it is necessary to reset
the IMR+ device. The standard partitioning algorithm is
selected upon reset.
AUI Port Disable
SI data: 00101111
SO data: None
The AUI port will be disabled upon receiving this command. Subsequently, the IMR+ chip will ignore all inputs
(Carrier Sense and SQE) appearing at the AUI port and
will not transmit any data or Jam Sequence on the AUI
port. Issuing this command will also cause the AUI port
to have its internal partitioning state machine forced to
its idle state. Therefore, a Partitioned Port may be reconnected by first disabling and then re-enabling
the port.
Note that enabling this function does not prevent the reporting of this condition by the IMR+ device and the two
functions operate independently.
1–86
Am79C981
PRELIMINARY
AUI Port Enable
SI data: 00111111
SO data: None
This command enables a previously disabled AUI port.
Note that a partitioned AUI port may be reconnected by
first disabling (AUI Port Disable Command) and then reenabling the port with this command.
All ports are enabled upon reset.
TP Port Disable
SI data: 00100###
SO data: None
(### is TP port number)
The TP port designated in the command byte will be disabled upon receiving this command. Subsequently, the
IMR+ device will ignore all inputs appearing at the disabled port’s receive pins and will not transmit any data or
JAM Sequence on that port’s transmit pins. Issuing this
command will also cause a TP port to have its partitioning state machine returned to its Idle State (Port Reconnected). Therefore, a partitioned port may be
reconnected by first disabling and then re-enabling the
port. The disabled port will continue to report correct
Link Test Status.
TP Port Enable
SI data: 00110###
SO data: None
(### is TP port number)
This command enables a previously disabled TP port.
Re-enabling a disabled port causes the port to be placed
into Link Test Fail state. This ensures that packet fragments received on the port are not repeated to the rest of
the network. Note that to force a TP port into the Link Fail
state and/or to reconnect a partitioned TP port, the port
should first be disabled (TP Port Disable Command)
and then re-enabled with this command. All ports are
enabled upon reset.
AMD
Enable Link Test Function of a TP Port
SI data: 01010###
SO data: None
(### is TP port number)
This command re-enables the Link Test Function in the
TP port designated in the command byte. This command executes only if the designated TP port has had
the Link Test Function disabled by the Disable Link Test
Function command. Otherwise, the command is ignored. Link Test is enabled upon reset.
Disable Automatic Receiver Polarity Reversal
SI data: 01100###
SO data: None
(### is TP port number)
This command disables the Automatic Receiver Polarity
Reversal Function for the TP port designated in the
command byte. If this function is disabled on a TP port
with reverse polarity (due to a wiring error), then the TP
port will fail Link Test due to the reversed polarity of the
Link Pulses. If the Link Test Function is also disabled on
the TP port, then the received reversed polarity packets
would be repeated to all other network ports in the IMR+
chip as inverted data. Automatic Polarity reversal is disabled upon reset.
Enable Automatic Receiver Polarity Reversal
SI data: 01110###
SO data: None
(### is TP port number)
This command enables the Automatic Receiver Polarity
Reversal Function for the TP port designated in the
command byte. If enabled in a TP port, the IMR+ chip
will automatically invert the polarity of that TP port’s receiver circuitry if the TP port is detected as having
reversed polarity (due to a wiring error). After reversing
the receiver polarity, the TP port could then receive subsequent (reverse polarity) packets correctly.
Disable Link Test Function of a TP Port
SI data: 01000###
SO data: None
(### is TP port number)
This command disables the Link Test Function at the TP
port designated in the command byte, i.e., the TP port
will no longer be disconnected due to Link Fail. A TP port
which has its Link Test Function disabled will continue to
transmit Link Test Pulses. If a twisted pair port has Link
Test disabled, then reading the Link Test Status indicates it being in Link Test Pass.
Am79C981
GET (Read) Opcodes
AUI Port Status
SI data: 10001111
SO data: PBSL0000
The combined AUI status allows a single instruction to
be used for monitoring AUI port. The four status bits reported are:
1–87
AMD
PRELIMINARY
PPartitioning Status. This bit is 0 if the AUI port is
partitioned and 1 if connected.
BBit Rate Error. This bit is set to 1 if there has been
an instance of FIFO Overflow or Underflow,
caused by data received at the AUI port. This bit is
cleared when the status is read.
SSQE Test Status. This bit is set to 1 if SQE Test is
detected by the IMR+ chip. This bit is cleared
when the status is read. A MAU attached to a repeater must have SQE Test disabled. This bit is
set even if the AUI port is disabled or partitioned.
LLoop Back Error. The MAU attached to the AUI is
required to loopback data transmitted to DO onto
the DI circuit. If loopback carrier is not detected by
the IMR+ device, then this bit is set to 1 to report
this condition. This bit is cleared when the status is
read. For a repeater this is the only indication of a
broken or missing MAU.
Alternate AUI Port Status
SI data: 10001111
SO data: PBSL0000
There are three further variations of the above command, allowing selective clearing of a combination of B,
S, and L bits. They are primarily included for use by the
HIMIB chip. These are:
Alternative 1.
SI data: 10001011
SO data: PBSL0000
B is not cleared. S and L are cleared.
Alternative 2.
Bit Rate Error Status of TP Ports
SI data: 10100000
SO data: E7...............E0
This allows a single command to be used to report Bit
Rate Error condition (FIFO Overflow or Underflow) of all
Twisted Pair ports. The 8 bits of the output pattern correspond to each of the 8 TP ports, with least significant bit
corresponding to port 0.
The status bit for a port is set to 1 if there has been an
instance when data received from that port has caused
a FIFO error.
All status bits stay set until the status is read.
Link Test Status of TP Ports
SI data: 11010000
SO data: L7...............L0
Ln = 0 TP Port n in Link Test Fail
Ln = 1 TP Port n in Link Test Pass
The Link Test Status of all eight TP ports are accessed
by this command. A disabled port continues to report
correct Link Test Status. Re-enabling a disabled port
causes the port to be placed into Link Test Fail state.
This ensures that packet fragments received on the port
are not repeated to the rest of the network.
Receive Polarity Status of TP Ports
SI data: 11100000
SO data: P7...............P0
Pn = 0 TP Port n Polarity Correct
Pn = 1 TP Port n Polarity Reversed
SI data: 10001101
SO data: PBSL0000
S and L are not cleared. B is cleared.
Alternative 3.
SI data: 10001001
SO data: PBSL0000
None of S, B and L are cleared.
TP Port Partitioning Status
SI data: 10000000
SO data: P7.................P0
Pn = 0 TP port n partitioned
Pn = 1 TP port n connected
The partitioning Status of all eight TP ports are accessed by this command. If a port is disabled, reading it
partitioning status will indicate that it is connected.
1–88
Am79C981
The statuses of all eight TP port polarities are accessed
with this command. The IMR+ chip has the ability to detect and correct reversed polarity on the TP ports’
RXD+/– pins. If the polarity is detected as reversed for a
TP port, then the IMR+ chip will set the appropriate bit in
this command’s result byte only if the Polarity Reversal
Function is enabled for that port.
MJLP Status
SI data: 11110000
SO data: M00000000
Each IMR+ chip contains an independent MAU Jabber
Lock Up Protection Timer. The timer is designed to inhibit the IMR+ device transmit function, if it has been
transmitting continuously for more than 65536 Bit
Times. The MJLP Status bit (M) is set to 1 if this
happens. This bit remains set and is only cleared when
the MJLP status is read by using this command.
PRELIMINARY
Version
SI data: 11111111
SO data: XXXX0001
This command (1111 1111) can be used to determine
the device version.
The IMR+ chip responds by the bit pattern:XXXX 0001
The IMR chip (Am79C980) responds by the bit pattern:
XXXX 0000
Minimum Mode
The Minimum Mode reconfigures the IMR+ device
Management Port and is intended to provide support for
the low end, non-managed repeaters, requiring minimal
external logic to provide LED indication of:
■Twisted Pair Ports Link Status indication and AUI
Loopback Status
■Port Partitioning Status
■Twisted Pair Ports Receiver Polarity Status and
AUI SQE Test Error Status
■Port Bit Rate Error Status
The Minimum Mode is selected by controlling the state
of the TEST pin while RST is asserted. If TEST is High
(asserted), while reset is active (RST LOW), then Minimum Mode is selected. The state of SI pin, at the
deassertion of the RST signal, determines whether the
IMR+ chip is to be programmed for Automatic Polarity
Detection/Correction.
When entering the Minimum Mode, the TEST input has
to be deasserted on the rising edge of reset. A maximum
delay of 100 ns is allowed to account for slow devices.
The following table summarizes the different modes
available.
AMD
In Minimum Mode, the SO pin is used to serially output
the various status information based on the state of the
SI and SCLK pins. A summary of the status information
is provided in the following table.
SCLK SI SO Output
0 0 TP Ports Receive Polarity Status +
AUI SQE Test Error Status.
0 1 Bit Rate Error (all ports).
1 0 TP Ports Link Status + AUI
LoopBack Status
1 1 Port Partitioning Status (all ports)
When SI = 0 then SO will output the related AUI status
bits (LoopBack or SQE), followed by the 8 TP status bits
(Link or Polarity), starting with the TP port 0.
When SI = 1, the Port Partitioning Status or Port Bit Rate
Error Status are scanned out with the AUI first and TP
ports following. TP Port 0 is scanned out first.
Note that the Bit Rate Error, AUI Loopback, and AUI
SQE Test Error status bits stay set until they are
scanned out.
The state of SI and SCLK inputs is checked at the end of
every STR cycle. The rising edge of the X1 clock, occurring before falling edge of STR, is used to strobe in the
state of the SI and SCLK pins.
In this Minimum Mode, the Management Port mode is
not active. To exit the Minimum mode, the IMR+ device
must reset into the normal Management Port mode.
Test SI Functions
0 0 Normal Management Mode
0 1 Normal Management Mode
1 0 Minimum Mode, Receive
Polarity Correction disabled
1 1 Minimum Mode, Receive
Polarity Correction enabled
Am79C981
1–89
X1
AMD
ASYNC
RESET
PRELIMINARY
XTAL
OSC
1/2 ’74
CK
D
1/2 ’74
QD
CK Q
CLR
X1
Am79C981
X2
IMR+ Chip
Q
RST
TEST
SCLK SI
SO
STR
TCK
TCK
CK
SI
CK
T
P
P
6
7
Figure 3. Minimum Mode, Non-Intelligent Repeater Example
Register
T
T
P
5
SIPO
A
T
U
P
I
0
17306B-7
TCK
(Note 1)
CRS
(Note 2)
SO
(Note 3)
STR
CRS
AUI
SO
AUI
CRS
TP0
SO
TP0
CRS
TP1
SO
TP1SOTP2SOTP3SOTP4SOTP5SOTP6
CRS
TP2
CRS
TP3
CRS
TP4
Notes:
1. Externally generated signal illustrates internal IMR+ chip clock phase relationship.
2. CRS timing with the C-bit cleared (IMR+ Chip Programmable Options)
3. For Minimum Hub Mode
Figure 4. Management Port Minimum Mode and
Port Activity Monitor Signal Relationship
Port Activity Monitor
Two pins, CRS and STR, are used to serially output the
state of the internal Carrier Sense signals from the AUI
and the eight TP ports. This function together with external hardware and/or software can be used to monitor repeater receive and/or collision activity.
The following diagram shows typical external hardware
employed to convert the serial bit stream into parallel
form. The accuracy of the CRS signals is 10 Bit Times
(BT) (1 µs). Specifically, a transition to active state by
any of the internal carrier sense bits that lasts for less
than 10BT is latched internally and is used to set the appropriate bit during the next sample period.
CRS
TP5
CRS
TP6
CRS
TP7
SO
TP7
CRS
AUI
SO
AUI
17306B-8
1–90
Am79C981
ASYNC
RESET
XTAL
OSC
1/2 ’74
CK
D
PRELIMINARY
1/2 ’74
QD
CK Q
CLR
X1
Am79C981
X2
IMR+ Chip
Q
RST
TCK
TCK
CRS
STR
Figure 5a. Port Activity Monitor Implementation
Shift Register
CK
SI
SIPO
CK Register
A
T
T
T
P
P
P
5
6
7
T
U
P
I
0
Carrier Sense Outputs
17306B-9
AMD
12 91011
X1
RST
TCK
(Note1)
CRS
AUI TP0 TP1 TP7 X AUI TP0
(Note 2)
STR
(Note 3)
Notes:
1. Externally generated signal illustrates internal IMR+ chip clock phase relationship.
2. IMR+ chip standalone, X will be low. When attached to a HIMIB device, X reflects the state of the CI pair.
3. STR signal is not available when the IMR+ chip is attached to HIMIB device, and must be generated externally.
Figure 5b. Port Activity Monitor Implementation (Continued)
17306B-10
Am79C981
1–91
AMD
PRELIMINARY
Loopback Test Mode
The IMR+ chip can be programmed to enter Loopback
Mode on all network ports. This is accomplished by first
driving the TEST pin HIGH, then clocking (using the
SCLK pin) a minimum of three 0s into the SI pin. This
causes the IMR+ chip to loop all received data on each
port back to each port’s corresponding transmit outputs.
Specifically, the AUI DI input is passed unaltered to the
AUI DO output, and each RXD input on the twisted pair
ports is passed (unaltered) to the respective TXD and
TEST
SI
SCLK
TXP outputs. Only receive data that passes the required
amplitude squelch criteria is looped back to the transmit
outputs. Note that the data is looped back unaltered,
meaning that no signal retiming or regeneration takes
place. Therefore, any signal distortion present on the receive data paths will be retransmitted.
In Minimum Mode, the Loopback Test Mode cannot be
accessed. The IMR+ device will return to normal operation when the TEST pin is again driven LOW.
Figure 6. Programming the IMR+ Device for Loopback Mode
17306B-11
1–92
Am79C981
PRELIMINARY
IMR+ Chip External Components
Figure 6 shows a typical twisted pair port external components schematic. The resistors used should have a
1% tolerance to ensure interoperability with 10BASE-T
compliant networks. The filters and pulse transformers
are necessary devices that have a major influence on
the performance and compliance of the 10BASE-T ports
of the repeater. Specifically, the transmitted waveforms
are heavily influenced by the filter characteristics and
the twisted pair receivers employ several criteria to continuously monitor the incoming signal’s amplitude and
timing characteristics to determine when and if to assert
the internal carrier sense. For these reasons, it is crucial
that the values and tolerances of the external components be as specified. Several manufacturers produce a
module that combines the functions of the transmit and
receive filters and the pulse transformers into one
package.
AMD
Filter &
Transformer
Notes:
Am79C981
TXD+
TXP+
TXD–
TXP–
RXD+
RXD–
61.9Ω
422Ω
61.9Ω
422Ω
1.21KΩ
Note 2
100Ω
XMT
Filter
Note 1
RCV
Filter
Module
1:1
1:1
RJ45
Connector
TD+
3
TD–
6
RD+
1
RD–
2
17306B-12
1. Compatible filter modules, with a brief description of package type and features are included in the Appendix.
2. The resistor values are recommended for general purpose use and should allow compliance to the 10BASE-T specification
for template fit and jitter performance. However, the overall performance of the transmitter is also affected by the transmit
filter configuration.
Figure 7a. Typical TP Port External Components
Am79C981
DO+
DO–
DI+
DI–
CI+
CI–
40.2Ω
40.2Ω
40.2Ω 40.2Ω
0.1µF
Pulse
Transformer
Note 1
0.1µF
AUI
Connector
3
10
5
12
2
9
Optional ANLG GND
17306B-13
Notes:
1. Compatible AUI transformer modules, with a brief description of package type and features are included in the Appendix.
±
2. The differential input DI
and the CI± pairs are externally terminated by two 40.2 Ω ±1% resistors and one optional commonmode bypass capacitor. The differential input impedance, ZIDF, and the common-mode input impedance, ZICM, are specified so that the Ethernet specification for cable termination impedance is met using standard 1% resistor terminators. If SIP
Ω
devices are used, 39
is the nearest usable equivalent value.
Figure 7b. Typical AUI Port Components
Am79C981
1–93
AMD
PRELIMINARY
APPLICATIONS
A fully managed multiport repeater can be easily built by
interfacing the IMR+ chip with the Hardware Implemented Management Information Base (HIMIB),
Am79C987 device. The HIMIB device interfaces with all
common Microprocessor System Busses with a
Host
System
Bus
Address
Decode
Data
Buffer
CS
HIMIB
C/D
D [7–0]
RD
WR
RDY
INT
minimum of external logic. Note that additional buffering
of DAT and JAM are required for most applications. For
more information, refer to AMD’s IEEE 802.3 Repeater
Technical Manual (PID# 17314A).
Expansion
Bus
DAT
JAM
CRS
STR
SI
SO
SCLK
ACK
COL
RST
CK
CRS
STR
SI
SO
SCLK
X1
IMR+
REQ
Figure 8. Simplified ISA-HUB Block Diagram
17306B-14
1–94
Am79C981
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage Temperature –65°C to +150°C. . . . . . . . . . .
Ambient Temperature Under Bias 0 to 70°C. . . . . . .
Supply Voltage referenced to
or DVSS (AVDD, DVDD) –0.3 to +6 V. . . . . . . . . .
AV
SS
Stresses above those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent device failure. Functionality
at or above these limits is not implied. Exposure to absolute
OPERATING RANGES
Commercial (C) Devices
Temperature (T
Supply Voltage (AV
Operating ranges define those limits between which the funtionality of the device is guaranteed
.
) 0 to +70°C. . . . . . . . . . . . . . . .
A
, DVDD) 5 V to ±5%. . . . . . .
DD
AMD
maximum ratings for extended periods may affect device
reliability.
DC CHARACTERISTICS over operating ranges unless otherwise specified
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
Digital I/O
V
V
IH
V
OL
V
OH
I
IL
V
ILX X1
V
IHX X1
I
ILX
I
IHX
AUI Port
I
IAXD
V
AICM
V
AIDV
V
ASQ
V
ATH
V
AOD
V
AODI
V
AOD
OFF DO Differential Idle Output Current RL = 78 Ω (Note 1) –1 +1 mA
I
AOD
V
AOCM
Input LOW Voltage DVSS = 0.0 V –0.5 0.8 V
IL
Input HIGH Voltage 2.0 DVDD+0.5 V
Output LOW Voltage IOL = 4.0 mA – 0.4 V
Output HIGH Voltage IOH = –0.4 mA 2.4 – V
Input Leakage Current DVSS<VIN<DV
DD
–10µA
(also DAT and JAM as inputs)
Crystal Input LOW Voltage DVSS = 0.0 V –0.5 1.0 V
Crystal Input HIGH Voltage DVSS = 0.0 V 3.8 DVDD+0.5 V
Crystal Input LOW Current VIN = DV
Crystal Input HIGH Current VIN = DV
Input Current at DI+/- AV
SS
< V
SS
DD
< AV
IN
DD
–10µA
–10µA
–500 +500 µA
and CI+/- pairs
DI+,DI-,CI+,CI- Open Circuit Input IIN = 0A, AVSS = 0 V AVDD – 3.0 AVDD–1.0 V
Common Mode Voltage (bias)
Differential Mode Input AV
= 5.0 V –2.5 +2.5 V
DD
Voltage Range (DI, CI)
DI, CI Squelch Threshold –275 –160 mV
DI Switching Threshold (Note 1) –35 +35 mV
Differential Output Voltage RL = 78 Ω 620 1100 mV
|(DO+) – (DO-)|
DO Differential Output RL = 78 Ω –25 +25 mV
Voltage Imbalance
OFF DO Differential Idle Output Voltage RL = 78 Ω –40 +40 mV
DO+/- Common Mode Output Voltage RL = 78 Ω 2.5 AV
DD
V
Am79C981
1–95
AMD
PRELIMINARY
DC CHARACTERISTICS (continued)
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
Twisted Pair Ports
I
IRXD
R
RXD
V
TIVB
V
TID
V
TSQ+
V
TSQ-
V
THS+
V
THS-
V
RXDTH
V
TXH
V
TXL
V
TXI
V
TXOFF
R
TXD
R
TXP
Power Supply Current
I
DD
Power supply current (transmitting f
Input current at RXD+/- AVSS<VIN<AV
DD
–500 +500 µA
RXD differential input resistance (Note 1) 10 – KΩ
RXD+,RXD- open circuit input IIN = 0 mA AVDD–3.0 AVDD–1.5 V
voltage (bias)
Differential Mode input voltage AVDD = 5.0 V –3.1 +3.1 V
range (RXD)
RXD positive squelch threshold Sinusoid 5 MHz <f< 10 MHz 300 520 mV
(peak)
RXD negative squelch threshold Sinusoid 5 MHz <f< 10 MHz –520 –300 mV
(peak)
RXD post-squelch positive threshold Sinusoid 5 MHz <f< 10 MHz 150 293 mV
(peak)
RXD post-squelch negative threshold Sinusoid 5 MHz <f< 10 MHz –293 –150 mV
(peak)
RXD switching threshold (Note 1) –60 +60 mV
TXD+/- and TXP+/- output DVSS = 0 V DVDD–0.6 DV
DD
HIGH voltage (Note 2)
TXD+/- and TXP+/- output DVDD = 5 V DV
SS DVSS
+0.6 V
LOW voltage (Note 2)
TXD+/- and TXP+/- differential –40 +40 mV
output voltage imbalance
TXD+/- and TXP+/- differential DVDD = 5 V – 40 mV
idle output voltage
TXD+/- differential driver (Note 1) – 40 Ω
output impedance
TXP+/- differential driver (Note 1) – 80 Ω
output impedance
Power supply current (idle) f
= 20 MHz – 180 mA
X1
= 20 MHz – 300 mA
X1
–no TP load)
Power supply current (transmitting f
= 20 MHz – (Note 8) mA
X1
–with TP load)
V
1–96
Am79C981
PRELIMINARY
AMD
SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
Clock and Reset
t
X1
t
X1H
t
X1L
t
X1R
t
X1F
t
PRST
t
RST
t
RSTSET
t
RSTHLD
Management Port
t
SCLK
t
SCLKH
t
SCLKL
t
SCLKR
t
SCLKF
t
SISET
t
SIHLD
t
SODLY
t
X1HCRS
t
X1HSTH
t
X1HSTL
t
TESTSET
t
TESTHLD
t
STRSET
t
STRHLD
Expansion Port
t
X1HRL
t
X1HRH
t
X1HDR
t
X1HDZ
X1 Clock Period 49.995 50.005 ns
X1 Clock HIGH 20 30 ns
X1 Clock LOW 20 30 ns
X1 Clock Rise Time – 10 ns
X1 Clock Fall Time – 10 ns
Reset pulse width after power on 150 – µs
(RST pin LOW)
Reset pulse width 4 – µs
(RST pin LOW)
RST HIGH setup time with 20 – ns
respect to X1 Clock
RST LOW hold time with 0 – ns
respect to X1 Clock
SCLK Clock Period 100 – ns
SCLK Clock HIGH 30 – ns
SCLK Clock LOW 30 – ns
SCLK Clock Rise Time – 10 ns
SCLK Clock Fall Time – 10 ns
SI input setup time with respect to SCLK 10 – ns
rising edge
SI input hold time with 10 – ns
respect to SCLK rising edge
SO output delay with CL = 100 pF – 40 ns
respect to SCLK rising edge
X1 rising edge to CRS valid CL = 100 pF 5 40 ns
X1 rising edge to STR HIGH CL = 100 pF – 40 ns
X1 rising edge to STR LOW CL = 100 pF – 40 ns
TEST input setup time with respect to 10 – ns
SCLK rising edge
TEST input hold time with respect to 10 – ns
SCLK rising edge
STR setup time 5 – ns
STR hold time 12 – ns
X1 rising edge to REQ driven LOW CL = 100 pF 14 40 ns
X1 rising edge to REQ driven HIGH CL = 100 pF 14 40 ns
X1 rising edge to DAT/JAM driven CL = 100 pF 14 40 ns
X1 rising edge to DAT/JAM not driven CL = 100 pF 14 40 ns
Am79C981
1–97
AMD
PRELIMINARY
SWITCHING CHARACTERISTICS (continued)
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
Expansion Port (Continued)
t
DJSET
t
DJHOLD
t
CASET
t
CAHOLD
t
MHSET
t
MHHLD
t
SCLKSET
t
SCLKHLD
AUI Port
t
DOTD
t
DOTR
t
DOTF
t
DORM
t
DOETD
t
PWODI
t
PWKDI
t
PWOCI
t
PWKCI
Twisted Pair Ports
t
TXTD
t
TR
t
TF
t
TM
t
TETD
t
PWKRD
t
PERLP
t
PWLP
t
PWPLP
DAT/JAM setup time 10 – ns
DAT/JAM hold time 14 – ns
COL/ACK setup time 5 – ns
COL/ACK hold time 14 – ns
TEST setup time with respect to RST 200 – ns
to enter Minimum Hub Mode
TEST hold time with respect to RST 0 100 ns
to enter Minimum Hub Mode
SI, SCLK set up time with respect to X1 50 – ns
SI, SCLK hold time with respect to X1 50 – ns
X1 rising edge to DO toggle – 30 ns
DO+,DO- rise time (10% to 90%) 2.5 5.0 ns
DO+,DO- fall time (90% to 10%) 2.5 5.0 ns
DO+,DO- rise and fall time mismatch – 1.0 ns
DO+/- End of Transmission 275 375 ns
DI pulse width accept/reject |VIN| > |V
|1545ns
ASQ
threshold (Note 3)
DI pulse width maintain/turn-off |VIN| > |V
| 136 200 ns
ASQ
threshold (Note 4)
CI pulse width accept/reject |VIN| > |V
|1026ns
ASQ
threshold (Note 5)
CI pulse width maintain/turn-off |VIN| > |V
| 90 160 ns
ASQ
threshold (Note 6)
X1 rising edge to TXD+,TXP+ – 50 ns
TXD-,TXP- transition delay
TXD+,TXD-,TXP+,TXP- rise time – 20 ns
TXD+,TXD-,TXP+,TXP- fall time – 20 ns
TXD+,TXD-,TXP+,TXP- rise – 6 ns
and fall time mismatch
Transmit End of Transmission 275 375 ns
RXD pulse width maintain/turn-off |VIN| > |V
| 130 200 ns
THS
threshold (Note 7)
Idle signal period 8 24 ms
Idle Link Test pulse width (TXD+) 75 120 ns
Idle Link Test pulse width (TXP+,TXP-) 40 60 ns
1–98
Am79C981
PRELIMINARY
AMD
SWITCHING CHARACTERISTICS (continued)
Notes:
1. Parameter not tested.
2. Uses switching test load.
3. DI pulses narrower than t
4. DI pulses narrower than t
(min) will be rejected; pulses wider than t
PWODI
(min) will maintain internal DI carrier sense on; pulses wider than t
PWKDI
DI carrier sense off.
5. CI pulses narrower than t
6. CI pulses narrower than t
(min) will be rejected; pulses wider than t
PWOCI
(min) will maintain internal CI carrier sense on; pulses wider than t
PWKCI
internal CI carrier sense off.
7. RXD pulses narrower than t
(min) will maintain internal RXD carrier sense on; pulse wider than t
PWKRD
turn internal RXD carrier sense off.
8. For the typical twisted pair load as shown in Figure 7, using a 100
Ω
cable, an additional 28 mA (max) of IDD current is
required for each twisted pair port used. Less than 18% of the power associated with this additional current is dissipated
by the IMR+ chip; the remainder is dissipated externally in the twisted pair load and cable.
(max) will turn internal DI carrier sense on.
PWODI
(max) will turn internal
PWKDI
(max) will turn internal CI carrier sense on.
PWOCI
(max) will turn
PWKCI
PWKRD
(max) will
Am79C981
1–99
AMD
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
PRELIMINARY
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
Don’t Care
Any Change
Permitted
Does Not
Apply
Will Be
Steady
Will Be
Changing
from H to L
Will Be
Changing
from L to H
Changing
State
Unknown
Center
Line is High
Impedance
“Off” State
SWITCHING WAVEFORMS
X1
t
X1R
t
X1H
t
t
X1F
X1
t
X1L
Clock Timing
KS000010
17306B-15
1–100
Am79C981
PRELIMINARY
SWITCHING WAVEFORMS
X1
t
RSTHLD
RST
t
t
RST
or t
PRST
TCK*
Notes:
t
refers to synchronous Reset Timing.
RSTSET
*Externally generated (Figure 4) signal illustrates internal IMR+ device clock phase relationships.
Reset Timing
t
SCLK tSCLKF tSCLKR
RSTSET
AMD
17306B-16
SCLK
SI/TEST
SO
t
SCLKH tSCLKL
t
SODLY
Management Port Clock Timing
t
SISET
t
TESTSET tTESTHLD
t
t
SODLY
SIHLD
17306B-19
Am79C981
1–101
AMD
SWITCHING WAVEFORMS
X1
TCK*
REQ
ACK
COL
DAT
JAM
PRELIMINARY
t
DJSET tDJHOLD
IN
Note:
*Externally generated (Figure 4) signal illustrates internal IMR+ chip clock phase relationships.
Expansion Port Input Timing
X1
TCK*
t
X1HRL tX1HRH
REQ
t
ACK
COL
CASET
t
X1HDR
t
CAHOLD
t
X1HDZ
t
CASET
17306B-20
DAT
JAM
OUT
Note:
*Externally generated (Figure 4) signal illustrates internal IMR+ chip clock phase relationships.
Expansion Port Output Timing
1–102
Am79C981
17306B-21
SWITCHING WAVEFORMS
X1
TCK*
t
X1HRL tX1HRH
REQ
ACK
t
CASET
COL
DAT
JAM
IN IN
t
CAHOLD
PRELIMINARY
t
CASET
AMD
Note:
*Externally generated (Figure 4) signal illustrates internal IMR+ chip clock phase relationships.
Expansion Port Collision Timing
Test
t
RST
MHSET
t
MHHLD
17306B-23
To Enter Minimum Mode
X1
STR
t
X1HSTH
t
X1HSTL
17306B-22
SI,
SCLK
Don’t Care
t
SCLKSETtSCLKHLD
Minimum Mode
Am79C981
Don’t Care
17306B-24
1–103
AMD
SWITCHING WAVEFORMS
X1
t
DOTD
D0+
D0–
DO+/–
PRELIMINARY
1
0111010ETD
t
DOTR
t
DOTF
AUI DO Timing Diagram
t
DOETD
40 mV
100 mV max.
0 V
t
DOETD
17306B-25
DI+/–
V
ASQ
t
PWODI
t
PWKDI
80-Bit Times
AUI Port DO ETD Waveform
AUI Receive Timing Diagram
t
PWKDI
17306B-26
17306B-27
1–104
Am79C981
SWITCHING WAVEFORMS
CI+/–
V
ASQ
t
PWOCI
01
X1
t
TXTD
TXD+
TXP+
PRELIMINARY
t
PWKCI
t
PWKCI
AUI Collision Timing Diagram
10111010ETD
t
TXTD
t
TXTR
t
XTXTF
t
TXETD
AMD
17306B-28
TXD–
TXP–
17306B-29
TP Ports Output Timing Diagram
Am79C981
1–105
AMD
SWITCHING WAVEFORMS
t
PWPLP
TXD+
TXP+
TXD–
TXP–
t
PWLP tPERLP
V
TSQ+
t
PWPLP
PRELIMINARY
TP Idle Link Test Pulse
t
PWKRD
17306B-30
RXD+/–
V
TSQ–
t
PWKRD
t
PWKRD
TP Receive Timing Diagram
V
THS+
V
THS–
17306B-31
1–106
Am79C981
SWITCHING TEST CIRCUITS
DO+
DO–
PRELIMINARY
AV
DD
100 pF
Includes Test
Jig Capacitance
AV
SS
AUI DO Switching Test Circuit
DV
DD
AMD
52.3 Ω
Test Point
154 Ω
17306B-32
TXD+
TXD–
TXP+
TXP–
100 pF
Includes Test
Jig Capacitance
TXD Switching Test Circuit
100 pF
Includes Test
Jig Capacitance
294 Ω
715 Ω
DV
DV
Test Point
294 Ω
SS
17306B-33
DD
Test Point
715 Ω
DV
SS
17306B-34
TXP Outputs Test Circuit
Am79C981
1–107
APPENDIX
10BASE-T INTERFACE
A
The table below lists the recommended resistor values and filter and transformer modules for the IMR+ device.
IMR+ Device Compatible 10BASE-T Media Interface Modules
¶ Manufacturer Part # Package Description
Bel Fuse S556-5999-32 16-pin SMD Transmit and receive filters, transformers and common mode chokes.
Bel Fuse 0556-2006-14 10-pin SIL Transmit and receive filters, transformers and common mode chokes.
Bel Fuse A556-2006-DE 16-pin 0.3" DIL Transmit and receive filters and transformers.
Bel Fuse A556-2006-00 16-pin DIL Transmit filter, transformers and common mode choke. Receive filter and
Halo Electronics FS02-101Y4 "Slim SIP" Transmit and receive filters and transformers.
Halo Electronics FS12-101Y4 "Slim SIP" Transmit and receive filters and transformers, transmit common mode reduction
Halo Electronics FS22-101Y4 "Slim SIP" Transmit and receive filters, transformers and common mode chokes.
Halo Electronics FD02-101G 16-pin 0.3" DIL Transmit and receive filters and transformers.
Halo Electronics FD12-101G 16-pin 0.3" DIL Transmit and receive filters and transformers, transmit common mode choke.
Halo Electronics FD22-101G 16-pin 0.3" DIL Transmit and receive filters, transformers and common mode chokes.
Halo Electronics FD22-101R2 16-pin 0.3" DIL Termination and equalization resistors, transmit and receive filters, transformers
Nano Pulse 5408-37 16-pin SMD 7 pole transmit and receive filters with 1CT:1CT Xfmrs (transmit & receive) and a
Nano Pulse 5408-40 9-pin SIP 7 pole transmit and receive filters with 1CT:1CT Xfmrs (transmit & receive) and a
Nano Pulse 6612-21 12-pin DIL 7 pole transmit and receive filters with 1CT:1CT Xfmrs (transmit & receive) and a
PCA Electronics EPA1990A 16-pin 0.3" DIL Transmit and receive filters and transformers.
PCA Electronics EPA1990AG SMT device Transmit and receive filters and transformers.
PCA Electronics EPA2013D 16-pin 0.3" DIL Transmit and receive filters and transformers, transmit common mode choke.
PCA Electronics EPA2013DG SMT device Transmit and receive filters and transformers, transmit common mode choke.
Pulse Engineering 78Z034C 16-pin DIL Transmit and receive filters and transformers, transmit common mode chokes.
Pulse Engineering 78Z1120B-01 16-pin DIL Transmit and receive filters and transformers.
Pulse Engineering 78Z1122B-01 16-pin DIL Transmit and receive filters, transformers and common mode chokes.
Pulse Engineering PE-68017S 10-pin SIL Transmit and receive filters, transformers and common mode chokes.
Pulse Engineering PE-68026 16-pin SMT Transmit and receive filters, transformers and common mode chokes.
Pulse Engineering PE-68056 16-pin SMT Transmit and receive filters, transformers and common mode chokes.
Pulse Engineering PE-68032 13-pin PCMCIA-SMT Transmit and receive filters and transformers, transmit common mode chokes.
TDK TLA-3M601-RS 10-pin SIP Transmit and receive filters and transformers, transmit common mode chokes.
TDK TLA-3M102(-T) 16-pin SMD Integrated resistors, transmit and receiv e filters and transformers, transmit common
TDK TLA-3M103(-T) 16-pin SMD Transmit and receive filters and transformers, transmit common mode chokes.
Valor Electronics PT3877 16-pin 0.3" DIL Transmit and receive filters and transformers.
Valor Electronics PT3983 8-pin 0.3" DIL Transmit and receive common mode chokes.
Valor Electronics FL1012 16-pin 0.3" DIL Transmit and receive filters and transformers, transmit common mode chokes.
transformer.
choke.
and common mode chokes.
separate common mode choke for each channel.
separate common mode choke for each channel.
separate common mode choke for each channel.
mode chokes.
1-108 Am79C981
APPENDIX B
Glossary
Active Status
In a non-collision state, an IMR+ chip is considered active if it is receiving data on any one of its network ports,
or is in the process of broadcasting (repeating) FIFO
data from a recently completed data reception. In a collision state (the IMR+ device is generating Jam Sequence), an IMR+ device is considered active if any one
or more network ports is receiving data. The IMR+ device asserts the REQ line to indicate that it is active.
Collision
In a carrier sense multiple access/collision detection
(CSMA/CD) network such as Ethernet, only one node
can successfully transfer data at any one time. When
two or more separate nodes (DTEs or repeaters) are simultaneously transmitting data onto the network, a Collision state exists. In a repeater using one or more IMR+
devices, a Collision state exists when more than one
network port is receiving data at any instant, or when
any one or more network ports receives data while the
IMR+ device is transmitting (repeating) data, or when
the CI+/- pins become active (nominal 10 MHz signal)
on the AUI port.
Jam Sequence
A signal consisting of alternating 1s and 0s that is generated by the IMR+ device when a Collision state is detected. This signal is transmitted by the IMR+ device to
indicate to the network that one or more network ports in
the repeater is involved in a collision.
Network Port
Any of the eight 10BASE-T ports or the AUI port present
in the IMR+ device (i.e. not the Expansion Port or the
Management Port).
Partitioning
A network port on a repeater has been partitioned if the
repeater has internally ‘disconnected’ it from the repeater due to localized faults that would otherwise bring the
entire network down. These faults are generally cable
shorts and opens that tend to cause excessive collisions
at the network ports. The partitioned network port will be
internally re-connected if the network port starts behaving correctly again, usually when successful ‘collisionless’ transmissions and/or receptions resume.
Receive Collision
A network port is in a Receive Collision state when it detects collision and is not one of the colliding network
‘nodes’. This applies mainly to a non-transmitting AUI
port because a remote collision is clearly identified by
the presence of a nominal 10 MHz signal on the CI+/pins. However, any repeater port would be considered
to be in a receive collision state if the repeater unit is receiving data from that port as the ‘one-port-left’ in the
collision sequence.
Transmit Collision
A network port is in a Transmit Collision state when collision occurs while that port is transmitting. On the AUI
port, Transmit Collision is indicated by the presence of a
nominal 10 MHz signal on the CI+/- pins while the AUI
port is transmitting on the DO+/- pins. On a 10BASE-T
port, Transmit Collision occurs when incoming data appears on the RXD+/- pins while the 10BASE-T port is
transmitting on the TXD+/- and TXP+/- pins.
1-110 Am79C981
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