AMD Advanced Micro Devices AM79C981JC Datasheet

■

PRELIMINARY

Am79C981

Integrated Multiport Repeater Plus™ (IMR+™)

DISTINCTIVE CHARACTERISTICS

Enhanced version of AMD’s Am79C980 Integrated Multiport Repeater™ (IMR™) chip with the following enhancements:

—Additional management port features — Minimum mode provides support for an extra

four LED outputs per port for additional status in non-intelligent repeater designs

—Pin/socket-compatible with the Am79C980

IMR chip

—Fully backward-compatible with existing IMR

device designs

Interfaces directly with the Am79C987 HIMIB™ device to build a fully managed multiport repeater

CMOS device features high integration and low power with a single +5 V supply

Repeater functions comply with IEEE 802.3 Repeater Unit speciﬁcations

Eight integral 10BASE-T transceivers utilize the required predistortion transmission technique

Attachment unit interface (AUI) port allows connectivity with 10BASE-5 (Ethernet) and 10BASE-2 (Cheapernet) networks, as well as

10BASE-F and/or Fiber Optic Inter-Repeater Link (FOIRL) segments

On-board PLL, Manchester encoder/decoder, and FIFO

Expandable to increase number of repeater ports

All ports can be separately isolated (partitioned) in response to excessive collision conditions or fault conditions

Network management and optional features are accessible through a dedicated serial management port

Twisted-pair Link Test capability conforming to the 10BASE-T standard. The receive Link Test function can be optionally disabled through the management port to facilitate interoperability with devices that do not implement the Link Test function

Programmable option of Automatic Polarity Detection and Correction permits automatic recovery due to wiring errors

Full amplitude and timing regeneration for retransmitted waveforms

Preamble loss effects eliminated by deep FIFO

GENERAL DESCRIPTION

The Integrated Multiport Repeater Plus (IMR+) chip is a VLSI circuit that provides a system-level solution to designing a compliant 802.3 repeater incorporating 10BASE-T transceivers. The device integrates the Repeater functions speciﬁed by Section 9 of the IEEE

802.3 standard and Twisted-Pair Transceiver functions complying with the 10BASE-T standard. The Am79C981 provides eight integral twisted-pair medium attachment units (MAUs) and an attachment unit interface (AUI) port in an 84-pin plastic leaded chip carrier (PLCC).

A network based on the 10BASE-T standard uses unshielded twisted-pair cables, thereby providing an economical solution to networking by allowing the use of low-cost unshielded twisted-pair (UTP) cable or existing telephone wiring.

The total number of ports per repeater unit can be increased by connecting multiple IMR+ devices through

Publication# 17306 Rev: BAmendment/0 Issue Date: January 1999

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

their expansion ports, minimizing the total cost per repeater port. Furthermore, a general-purpose attachment unit interface (AUI) provides connection capability to 10BASE-5 (Ethernet) and 10BASE-2 (Cheapernet) coaxial networks, as well as 10BASE-F and/or Fiber Optic Inter-Repeater Link (FOIRL) ﬁber segments. Network management and test functions are provided through TTL-compatible I/O pins.

The IMR+ device interfaces directly with AMD’s Am79C987 Hardware Implemented Management Information Base™ (HIMIB) chip to build a fully managed multiport repeater as speciﬁed by the IEEE 802.3 (Layer Management for 10 Mb/s Baseband Repeaters) standard. When the IMR+ and HIMIB devices are interconnected, complete repeater and per-port statistics are maintained and can be accessed on demand using a simple 8-bit parallel interface.

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PRELIMINARY

For application examples on building a fully managed repeater using the IMR+ and HIMIB devices, refer to AMD’s IEEE 802.3 Repeater Technical Manual (PID#17314A) and the ISA-HUB

User Manual

(PID # 17642A).

BLOCK DIAGRAM

DI± CI±

DO±

RXD±

TXD± TXP±

RXD±

TXD± TXP±

RST

AUI Port

Port

Reset

MUX

Manchester

Decoder

Phase = Locked

Loop

Manchester

Encoder

IMR+ Chip

Partitioning

The device is fabricated in CMOS technology and requires a single +5 V supply.

FIFO

Preamble

Jam Sequence

FIFO

Control

Expansion Port

Link Test

MUX

REQ ACK

COL

DAT JAM

Clock

Gen

Timers

RELATED AMD PRODUCTS

Part No. Description

Am79C98 Twisted Pair Ethernet Transceiver (TPEX) Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+) Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver Am79C987 Hardware Implemented Management Information Base (HIMIB) Am79C940 Media Access Controller for Ethernet (MACE) Am7990 Local Area Network Controller for Ethernet (LANCE) Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE) Am79C900 Integrated Local Area Communications Controller (ILACC) Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus) Am79C961 PCnet-ISA Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller Am79C970 PCnet-PCI Single-Chip Ethernet Controller (for PCI bus) Am79C974 PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems

Single-Chip Ethernet Controller for ISA (with Microsoft Plug n’ Play Support)

Test

and

Management

Port

SI SO

SCLK TEST CRS STR

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Am79C981

CONNECTION DIAGRAM

CI+

CI–

DI+

PRELIMINARY

PLCC

RXD0+

DI–

RXD0–

AVSSRXD1+

RXD2+

RXD1–

RXD2–

RDX3+

RXD3–

RXD4+

RXD4–

RXD5+

RXD5–

RXD6+

RXD6–

RXD7+

DO– DO+

TXD0+ TXD0–

TXP1+

TXP1–

TXD1+ TXD1– TXP1+

TXP1– TXD2+ TXD2– TXP2+

TXP2–

TXD3+ TXD3–

TXP3+

12 13 14

16 17 18

20 21

24 25

26 27 28 29 30

33343536 5352515049484746454443424140393837

TXP3–

STR

CRS

SCLK

1234567891011

IMR+ Chip

Am79C981

X1X

RST

TEST

75767778798081828384

RXD7–

TXD7+

TXD7–

DV 70 69

68 67 66

65 64 63 62 61 60 59 58 57

56 55 54

ACK

COL

JAM

DAT

REQ

TXP7+

TXP7–

TXD6+

TXD6–

TXP6+

TXP6–

TXD5+

TXD5–

TXP5+

TXP5–

TXD4+

TXD4–

TXP4+

TXP4–

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Am79C981 1–73

AMD

LOGIC SYMBOL

Management

Port

AUI

PRELIMINARY

DO+ DO–

DI+ DI–

CI+ CI–

SCLK SI SO

X2 X1 TEST

RST

DD AVDD

Am79C981

SS AVSS

TXD+ TXP+

TXD– TXP–

RXD+ RXD–

DAT JAM

ACK COL REQ

CRS STR

Twisted Pair

Ports

(8 Ports)

Expansion

Port

Activity

Monitor

LOGIC DIAGRAM

Management

Port

Twisted Pair

Port 0

AUI

Repeater

State

Machine

17306B-3

Expansion

Port

Twisted Pair

Port 7

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ORDERING INFORMATION Standard Products

AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below.

Am79C981 J C

DEVICE NUMBER/DESCRIPTION

Am79C981 Integrated Multiport Repeater Plus (IMR+)

Valid Combinations

Am79C981 JC

OPTIONAL PROCESSING

Blank = Standard Processing

OPERATING CONDITIONS

C = Commercial (0°C to +70°C)

PACKAGE TYPE

J = 84-Pin Plastic Leaded Chip Carrier (PL 084)

SPEED

Not Applicable

Valid Combinations

Valid combinations list conﬁgurations planned to be supported in volume for this device. Consult the local AMD sales ofﬁce to conﬁrm availability of speciﬁc valid combinations and to check on newly released combinations.

Am79C981 1–75

PRELIMINARY

PIN DESCRIPTION ACK

Acknowledge Input, Active LOW

When this input is asserted, it signals to the requesting IMR+ device that it may control the DAT and JAM pins. If the IMR+ chip is not requesting control of the DAT line

pin HIGH), then the assertion of the ACK signal

(REQ indicates the presence of valid collision status on the JAM or valid data on the DAT line.

Analog Power Power Pin

These pins supply the +5 V to the RXD+/– receivers, the DI+/– and CI+/– receivers, the DO+/– drivers, the internal PLL, and the internal voltage reference of the IMR+ device. These power pins should be decoupled and kept separate from other power and ground planes.

Analog Ground Ground Pin

These pins are the 0 V reference for AV

COL

Expansion Collision Input, Active LOW

When this input is asserted by an external arbiter, it signiﬁes that more than one IMR+ device is active and that each IMR+ device should generate the Collision Jam sequence independently.

CI+, CI–

Control In Input

AUI port differential receiver. Signals comply with IEEE

802.3, Section 7.

CRS

Carrier Sense Output

The states of the internal carrier sense signals for the AUI port and the eight twisted-pair ports are serially output on this pin continuously. The output serial bit stream is synchronized to the X

clock.

DAT

Data Input/Output/3-State

In non-collision conditions, the active IMR+ device will drive DAT with NRZ data, including regenerated preamble. During collision, when JAM = HIGH, DAT is used to signal a multiport (DAT = 0) or single-port (DAT = 1) condition.

When A

CK is not asserted, DAT is in high impedance. If REQ and ACK are both asserted, then DAT is an output. If ACK is asserted and REQ not asserted, then DAT is an input.

This pin needs to be either pulled up or pulled down through a high-value resistor.

DI+, DI–

Data In Input

AUI port differential receiver. Signals comply with IEEE

802.3, Section 7.

DO+, DO–

Data Out Output

AUI port differential driver. Signals comply with IEEE

802.3, Section 7.

Digital Power Power Pin

These pins supply +5 V to the logic portions of the IMR+ chip and the TXP+/–, TXD+/–, and DO+/– line drivers.

Digital Ground Ground Pin

These pins are the 0 V reference for DV

Pin # DV

19 16 TP ports 0 & 1 drivers 28 31 TP ports 2 & 3 drivers

43, 49 35, 37, 46, 51

59 56 TP ports 4 & 5 drivers 68 71 TP ports 6 & 7 drivers

Pin # Function

Core logic and expansion and control pins

JAM

Jam Input/Output/3-State

When JAM is asserted, the state of DAT will indicate either a multiport (DAT = 0) or single-port (DAT = 1) collision condition.

When A If REQ and ACK are both asserted, then JAM is an output. If ACK is asserted and REQ not asserted, then JAM is an input.

This pin needs to be either pulled up or pulled down through a high-value resistor.

CK is not asserted, JAM is in high impedance.

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PRELIMINARY

REQ

Request Output, Active LOW

This pin is driven LOW when the IMR+ chip is active. An IMR+ chip is active when it has one or more ports receiving or colliding or is in the state where it is still transmitting data from the internal FIFO. The assertion of this signal signiﬁes that the IMR+ device is requesting the use of the DAT and JAM lines for the transfer of repeated data or collision status to other IMR+ devices.

RST

Reset Input, Active LOW

Driving this pin LOW resets the internal logic of the IMR+ device. Reset should be synchronized to the X clock if either expansion or port activity monitor is used.

RXD+

, RXD–

0–7

Receive Data Input

10BASE-T port differential receive inputs (8 ports).

SCLK

Serial Clock Input

In normal operating mode, serial data (input or output) is clocked (in or out) on the rising edge of the signal on this pin. SCLK is asynchronous to X

and can operate

up to 10 MHz. In Minimum mode, this pin, together with the SI pin, controls which information is output on the SO pin.

Serial In Input

In normal operating mode, the SI pin is used for test/ management serial input port. Management commands are clocked in on this pin synchronous to the SCLK input. In Minimum mode, this pin, together with the SCLK pin, controls which information is output on the SO pin.

In Minimum mode, the state of SI at the deassertion of

signal determines the programming of automatic

RST polarity detection/correction for 10BASE-T ports.

Serial Out Output

In normal operating mode, the SO pin is used for test/ management serial output port. Management results are clocked out on this pin synchronous to the SCLK

input. In Minimum mode, the SO pin is used to serially output the various status information based on the state of the SI and SCLK pins.

SCLK SI SO Output

0 0

0 1 Bit Rate Error (all ports)

1 0

1 1 Port Partitioning Status (all ports)

TP Ports Receive Polarity Status + AUI SQE Test Error Status

TP Ports Link Status + AUI Loopback Status

STR

Store Input/Output

As an output, this pin goes HIGH for two X times after the nine carrier sense bits are output on the CRS pin. Note that the carrier sense signals arriving from each port are latched internally, so that an active transition is remembered between samples. The accuracy of the carrier sense signals produced in this manner is 10 bit times (1 µ s).

When used in conjunction with the HIMIB device, the STR pin will be conﬁgured as an input automatically after a hardware reset. The HIMIB device uses this input to communicate with the IMR+ device. When used with the HIMIB chip, this pin must be pulled up via a high-value resistor.

TEST

Test Pin Input, Active HIGH

This pin should be tied LOW for normal operation. If this pin is driven HIGH, then the IMR+ device can be programmed for Loopback Test mode. Also, if this pin is HIGH when the RST vice will enter the Minimum mode. An inverted version of the RST signal can be used to program the device into the Minimum mode.

Test SI Functions

0 0 Normal Management Mode 0 1 Normal Management Mode

1 0

1 1

pin is deasserted, the IMR+ de-

Minimum Mode, Receive Polarity Correction Disabled

Minimum Mode, Receive Polarity Correction Enabled

clock cycle

Am79C981 1–77

PRELIMINARY

TXD+

0–7

, TXD–

0–7

Transmit Data Output

10BASE-T port differential drivers (8 ports).

TXP+

0–7

, TXP–

0–7

Transmit Predistortion Output

10BASE-T transmit waveform predistortion control differential outputs (8 ports).

Crystal 1 Crystal Connection

The internal clock generator uses a 20 MHz crystal attached to pins X

and X

. Alternatively, an external

20MHz CMOS clock signal can be used to drive this pin.

Crystal 2 Crystal Connection

The internal clock generator uses a 20 MHz crystal attached to pins X

and X

. If an external clock source is

used, this pin should be left unconnected.

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PRELIMINARY

FUNCTIONAL DESCRIPTION

The Am79C981 Integrated Multiport Repeater Plus device is a single chip implementation of an IEEE

802.3/Ethernet repeater (or hub). In addition to the eight integral 10BASE-T ports plus one AUI port comprising the basic repeater, the IMR+ chip also provides the hooks necessary for complex network management and diagnostics. The IMR+ device is also expandable, enabling the implementation of high port count repeaters based on several IMR+ devices.

The IMR+device interfaces directly with AMD’s Am79C987 Hardware Implemented Management Information Base (HIMIB) device to allow a fully managed multiport repeater to be implemented as specified by the Layer Management for 10 Mb/s Baseband Repeaters Standard. When the IMR+ and HIMIB devices are used as a chip set, the HIMIB device maintains complete repeater and per port statistics which can be accessed on demand by a microprocessor through a simple 8-bit parallel port.

The IMR+ chip complies with the full set of repeater basic functions as defined in section 9 of ISO 8802.3 (ANSI/IEEE 802.3c). These functions are summarized below.

Repeater Function

If any single network port senses the start of a valid packet on its receive lines, then the IMR+ device will retransmit the received data to all other enabled network ports. The repeated data will also be presented on the DAT line to facilitate multiple-IMR+ device repeater applications.

Signal Regeneration

When re-transmitting a packet, the IMR+ device ensures that the outgoing packet complies with the 802.3 specification in terms of preamble structure, voltage amplitude, and timing characteristics. Specifically, data packets repeated by the IMR+ chip will contain a minimum of 56 preamble bits before the Start of Frame Delimiter. In addition, the voltage amplitude of the repeated packet waveform will be restored to levels specified in the 802.3 specification. Finally, signal symmetry is restored to data packets repeated by the IMR+ device, removing jitter and distortion caused by the network cabling.

Jabber Lockup Protection

The IMR+ chip implements a built-in jabber protection scheme to ensure that the network is not disabled due to transmission of excessively long data packets. This protection scheme will automatically interrupt the transmitter circuits of the IMR+ device for 96-bit times if the IMR+ device has been transmitting continuously for more than 65,536-bit times. This is referred to as MAU Jabber Lockup Protection (MJLP). The MJLP status for the

AMD

IMR+ chip can be read through the Management Port using the Get MJLP Status command (M bit returned).

CollisionHandling

The IMR+ chip will detect and respond to collision conditions as specified in 802.3. A multiple-IMR+ device repeater implementation also complies with the 802.3 specification due to the inter-IMR+ chip status communication provided by the expansion port. Specifically, a repeater based on one or more IMR+ devices will handle the transmit collision and one-port-left collision conditions correctly as specified in Section 9 of the 802.3 specification.

Fragment Extension

If the total packet length received by the IMR+ device is less than 96 bits, including preamble, the IMR+ chip will extend the repeated packet length to 96 bits by appending a Jam sequence to the original fragment.

Auto Partitioning/Reconnection

Any of the integral TP ports and AUI port can be partitioned under excessive duration or frequency of collision conditions. Once partitioned, the IMR+ device will continue to transmit data packets to a partitioned port, but will not respond (as a repeater) to activity on the partitioned port’s receiver. The IMR+ chip will monitor the port and reconnect it once certain criteria indicating port ‘wellness’ are met. The criteria for reconnection are specified by the 802.3 standard. In addition to the standard reconnection algorithm, the IMR+ device implements an alternative reconnection algorithm which provides a more robust partitioning function for the TP ports and/or the AUI port. Each TP port and the AUI port are partitioned and/or reconnected separately and independently of other network ports.

Either one of the following conditions occuring on any enabled IMR+ device network port will cause the port to partition:

a. A collision condition exists continuously for a time

between 1024- to 2048-bit times (AUI port—SQE signal active; TP port—simultaneous transmit and receive)

b. A collision condition occurs during each of 32 con-

secutive attempts to transmit to that port.

Once a network port is partitioned, the IMR+ device will reconnect that port if the following is met:

a.Standard reconnection algorithm—A data packet

longer than 512-bit times (nominal) is transmitted or received by the partitioned port without a collision.

b. Alternate reconnection algorithm—A data packet

longer than 512-bit times (nominal) is transmitted by the partitioned port without a collision.

Am79C981

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AMD

PRELIMINARY

The reconnection algorithm option (standard or alternate) is a global function for the TP ports, i.e. all TP ports use the same reconnection algorithm. The AUI reconnection algorithm option is programmed independently of the TP port reconnection option.

Link Test

The integral TP ports implement the Link Test function as specified in the 802.3 10BASE-T standard. The IMR+ device will transmit Link Test pulses to any TP port after that port’s transmitter has been inactive for more than 8 to 17 ms. Conversely, if a TP port does not receive any data packets or Link Test pulses for more than 65 to 132 ms and the Link Test function is enabled for that port then that port will enter link fail state. A port in link fail state will be disabled by the IMR+ chip (repeater transmit and receive functions disabled) until it receives either four consecutive Link Test pulses or a data packet. The Link Test receive function itself can be disabled via the IMR+ chip management port on a port-by-port basis to allow the IMR+ device to interoperate with pre10BASE-T twisted pair networks that do not implement the Link Test function. This interoperability is possible because the IMR+ device will not allow the TP port to enter link fail state, even if no Link Test pulses or data packets are being received. Note however that the IMR+ chip will always transmit Link Test pulses to all TP ports regardless of whether or not the port is enabled, partitioned, in link fail state, or has its Link Test receive function disabled.

Polarity Reversal

The TP ports have the optional (programmable) ability to invert (correct) the polarity of the received data if the TP port senses that the received data packet waveform polarity is reversed due to a wiring error. This receive circuitry polarity correction allows subsequent packets

to be repeated with correct polarity. This function is executed once following reset or link fail, and has a programmable enable/disable option on a port-by-port basis. This function is disabled upon reset and can be enabled via the IMR+ chip Management Port.

Reset

The IMR+ device enters reset state when the RST pin is driven LOW. After the initial application of power, the RST pin must be held LOW for a minimum of 150 µs (3000 X1 clock cycles). If the RST pin is subsequently asserted while power is maintained to the IMR+ device, a reset duration of only 4 µs is required. The IMR+ chip continues to be in the reset state for 10 X1 clocks (0.5 µs) following the rising edge of RST. During reset, the output signals are placed in their inactive states. This means that all analog signals are placed in their idle states, bidirectional signals (except STR signal) are not driven, active LOW signals are driven HIGH, and all active HIGH signals and the STR pin are driven LOW.

An internal circuit ensures that a minimum reset pulse is generated for all internal circuits. For a RST input with a slow rising edge, the input buffer threshold may be crossed several times due to ripple on the input waveform.

In a multiple IMR+ chip repeater the RST signal should be applied simultaneously to all IMR+ devices and should be synchronized to the external X1 clock. Reset synchronization is also required when accessing the PAM (Port Activity Monitor).

The SI signal should be held HIGH for at least 500 ns following the rising edge of RST.

Table 1 summarizes the state of the IMR+ chip following reset.

Table 1. IMR+ Chip After Reset

Function State After Reset Pull Up/Pull Down

Active LOW outputs HIGH No Active HIGH outputs LOW No SO Output HIGH No DAT, JAM HI-IMPEDANCE Either STR LOW Pull Up* Transmitters (TP and AUI) IDLE No Receivers (TP and AUI) ENABLED Terminated AUI Partitioning/Reconnection Algorithm STANDARD ALGORITHM N/A TP Port Partitioning/Reconnection Algorithm STANDARD ALGORITHM N/A Link Test Function for TP Ports ENABLED, TP PORTS IN LINK FAIL N/A Automatic Receiver Polarity Reversal Function DISABLED N/A

*Only when used with the HIMIB device.

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PRELIMINARY

Expansion Port

The IMR+ chip Expansion Port is comprised of five pins; two are bi-directional signals (DAT and JAM), two are input signals (ACK and COL), and one is an output signal (REQ). These signals are used when a multiple-IMR+ device repeater application is employed. In this configuration, all IMR+ chips must be clocked synchronously with a common clock connected to the X1 inputs of all IMR+ devices. Reset needs to be synchronized to X1 clock.

The IMR+ device expansion scheme allows the use of multiple IMR+ chips in a single board repeater or a modular multiport repeater with a backplane architecture. The DAT pin is a bidirectional I/O pin which can be used to transfer data between the IMR+ devices in a multiple-IMR+ chip design. The data sent over the DAT line is in NRZ format and is synchronized to the common clock. The JAM pin is another bidirectional I/O pin that is used by the active IMR+ chip to communicate its internal status to the remaining (inactive) IMR+ devices. When JAM is asserted HIGH, it indicates that the active IMR+ device has detected a collision condition and is generating Jam Sequence. During this time when JAM is asserted HIGH, the DAT line is used to indicate whether the active IMR+ chip is detecting collision on one port only or on more than one port. When DAT is driven HIGH by the IMR+ chip (while JAM is asserted by the IMR+ chip), then the active IMR+ device is detecting a collision condition on one port only. This ‘one-port-left’ signaling is necessary for a multiple-IMR+ device repeater to function correctly as a single multiport repeater unit. The IMR+ chip also signals the ‘one port left’ collision condition in the event of a runt packet or collision fragment; this signal will continue for one expansion port bus cycle (100 ns) before deasserting REQ.

The arbitration for access to the bussed bi-directional signals (DAT and JAM) is provided by one output (REQ) and two inputs (ACK and COL). The IMR+ chip asserts the REQ pin to indicate that it is active and wishes to drive the DAT and JAM pins. An external arbiter senses the REQ lines from all the IMR+ devices and asserts the ACK line when one and only one IMR+ chip is asserting its REQ line. If more than one IMR+ chip is asserting its REQ line, the arbiter must assert the COL signal, indi- cating that more than one IMR+ device is active. More

AMD

than one active IMR+ device at a time constitutes a collision condition, and all IMR+ devices are notified of this occurence via the COL line of the Expansion Port.

Note that a transition from multiple IMR+ devices arbitrating for the DAT and JAM pins (with COL asserted, ACK deasserted) to a condition when only one IMR+ chip is arbitrating for the DAT and JAM pins (with ACK asserted, COL deasserted) involves one expansion port bus cycle (100 ns). During this transitional bus cycle, COL is deasserted, ACK is asserted, and the DAT and JAM pins are not driven. However, each IMR+ device will remain in the collision state (transmitting jam sequence) during this transitional bus cycle. In subsequent expansion port bus cycles (REQ and ACK still asserted), the IMR+ devices will return to the ‘master and slaves’ condition where only one IMR+ device is active (with collision) and is driving the DAT and JAM pins. An understanding of this sequence is crucial if nonIMR+ devices (such as an Ethernet controller) are connected to the expansion bus. Specifically, the last device to back off of the Expansion Port after a multiIMR+ chip collision must assert the JAM line until it too drops its request for the Expansion Port.

External Arbiter

A simple arbitration scheme is required when multiple IMR+ devices are connected together to increase the total number of repeater ports. The arbiter should have one input (REQ1...REQn) for each of the n IMR+ devices to be used, and two global outputs (COL and ACK). This function is easily implemented in a PAL vice, with the following logic equations:

ACK= REQ1 & REQ2 & REQ3 & ....REQn

+ REQ1

& REQ2 & REQ3 & ....REQn

•

+ REQ1 & REQ2 & REQ3 & .... REQn

COL= ACK & (REQ1 + REQ2 + REQ3 + ... REQn)

Above equations are in positive logic, i.e., a variable is true when asserted.

A single PALCE16V8 will perform the arbitration function for a repeater based on several IMR+ devices.



de-

Am79C981

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ASYNC RESET

1/2 ’74

D FF

XTAL OSC.

PRELIMINARY

Bus transceivers needed

REQ2REQ3REQ1

COL

ARBITER

ACK

REQ

ACK COL

RST

ACK

COL RST

REQ

Am79C981

IMR+ Chip

REQ

Am79C981

IMR+ Chip

DAT

JAM

DAT

JAM

if DAT and JAM buses exceed 100 pF loading.

DIR

Note 1

Note 1:

Direction DIR

B → A LOW A → B HIGH

Figure 1. Multiple IMR+ Devices

Modular Repeater Design

The expansion port of the IMR+ chip also allows for modular expansion. By sharing the arbitration duties between a backplane bus architecture and several separate repeater modules one can build an expandable repeater based on modular ‘plug-in’ cards. Each

ACK

COL

RST

REQ

Am79C981

IMR+ Chip

DAT

JAM

repeater module performs the local arbitration function for the IMR+ devices on that module, and provides signals to the backplane for use by a global arbiter.

For more detailed information, see AMD’s IEEE 802.3 Repeater Technical Manual, PID# 17314A.

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