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Am79C978VCW
Datasheet
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AMD Advanced Micro Devices Am79C978VCW, Am79C978KCW Datasheet

PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 22206 Rev: B Amendment/0 Issue Date: November 1998
Refer to AMD’s Website (www.amd.com) for the latest information.
Am79C978
PCnet™- Home Single-Chip 1/10 Mbps PCI Home Networking Controller
DISTINCTIVE CHARACTERISTICS
■
Fully integrated 1 Mbps HomePNA Physical Layer (PHY) as defined by Home Phoneline Networking Alliance (HomePNA) specification
1.0 — Optimized for home networking applications
over ordinary copper telephone wire
— In-band control features:
Adjustable power and speed levels 32 bits of reserved in-band messaging piggy-
backed on Ethernet packet
— Register programmable features:
Power control Performance registers Speed control Major frame timing parameters programma-
ble: ISBI, AID ISBI, pulse width, inter-symbol time
■
Fully integrated 10 Mbps PHY interface — Comprehensive Auto-Negotiation
implementation — Full-duplex capability — Optimized for 10BASE-T applications
■
Integrated Fast Ethernet controller for the Peripheral Component Interconnect (PCI) bus
— 32-bit glueless PCI host interface — Supports PCI clock frequency from DC to
33 MHz independent of network clock — Supports network operation with PCI clock
from 15 MHz to 33 MHz — High performance bus mastering
architecture with integrated Direct Memory
Access (DMA) Buffer Management Unit for
low CPU and bus utilization — PCI draft specification revision 2.2 compliant — Supports PCI Subsystem/Subvendor ID/
Vendor ID pr ogramming through the
EEPROM interface — Supports both PCI 5.0-V and 3.3-V signaling
environments
— Plug and Play compatible — Supports an unlimited PCI burst length — Big endian and little endian byte alignments
supported
— Implements optional PCI power management
event (PME) pin
■
Dual-speed CSMA/CD (10 Mbps and 100 Mbps) Media Access Controller (MAC) compliant with IEEE/ANSI 802.3 Ethernet standard
■
Compliant with HomePNA specification 1.0
■
Media Independent Interface (MII) for connecting external 10/100 Mbps transceivers
— IEEE 802.3u compliant MII — Intelligent Auto-Poll™ external PHY status
monitor and interrupt
— Supports both auto-negotiable and non-
auto-negotiable external PHYs
— Supports 10BASE-T, 100BASETX/FX,
100BASET4, and 100BASET2 IEEE 802.3 compliant MII PHYs at full-duplex or half­duplex
■
Full-duplex operation supported on the MII port with independent Transmit (TX) and Receive (RX) channels
■
Supports PC98/PC99 and Net PC specifications — Implements full OnNow features including
pattern matching and link status wake-up
events — Implements Magic Packet™ mode — Magic Packet mode and the physical address
loaded from EEPROM at power up without
requiring PCI clock — Supports PCI Bus Power Management
Interface specification revision 1.1 — Supports Advanced Configuration and
Power Interface (ACPI) specification version
1.0
— Supports Network Device Class Power
Management specification version 1.0a
2 Am79C978
PRELIMINARY
■
Independent internal TX and RX FIFOs — Programmable FIFO watermarks for both TX
and RX operations
— RX frame queuing for high latency PCI bus
host operation
— Programmable allocation of buffer space
between RX and TX queues
■
Extensive programmable internal/external loopback capabilities
■
EEPROM interface supports jumperless design and provides through-chip programming
— Supports full programmability of half-/full-
duplex operation through EEPROM mapping
— Programmable PHY reset output pin capable
of resetting external PHY without the need for buffering
■
Extensive programmable LED status support
■
Look-Ahead Packet Processing (LAPP) data handling technique reduces system overhead
by allowing protocol analysis to begin before the end of a receive frame
■
Includes Programmable Inter Packet Gap (IPG) to address less network aggressive MAC controllers
■
Offers the Modified Back-Off algorithm to address the
Ethernet Capture Effect
■
IEEE 1149.1-compliant JTAG Boundary Scan test access port interface and NAND tree test mode for board-level production connectivity test
■
Software compatible with AMD’s PCnet™ Family and LANCE/C-LANCE register and descriptor architecture
■
Very low power consumption
■
+3.3 V power supply along with 5 V tolerant I/Os enable broad system compatibility
■
Available in 144-pin TQFP and 160-pin PQFP packages
GENERAL DESCRIPTION
The Am79C978 controller is the first in a series of home networking products from AMD. The Am79C978 controller is fabricated in an advanced low po wer 3.3 V CMOS process to provide low operating current for power sensitive applications.
The Am79C978 controller contains an Ethernet Con­troller based on the Am79C971 Fast Ethernet control­ler, a physical layer device for supporting the 802.3 standard for 10BASE-T, and a physical layer device f or data networking at speeds up to 1 Mbps over ordinary residential telephone wiring.
The integrated PCI Ethernet controller is a highly inte­grated 32-bit full-duplex, 10/100 Mbps Ethernet con­troller solution designed to address high-performance system application requirements. It is a flexible bus­mastering device that can be used in any application, including network ready PCs. The bus master architec­ture provides high data throughput and low CPU and system bus utilization.
The integrated Ethernet transceiver is a physical layer device supporting the IEEE 802.3 standards for 10BASE-T. It provides all of the PHY la yer functions re­quired to support 10 Mbps data transfer speeds.
The integrated HomePNA transceiver is a physical layer de vice that enables data netw orking at speeds up to 1 Mbps over common residential phone wiring re­gardless of topology and without disrupting telephone (POTS) service.
The 32-bit multiplexed bus interface unit provides a di­rect interface to the PCI local bus, simplifying the de­sign of an Ethernet or home network node in a PC
system. The device has built-in support for both little and big endian byte alignment. The integrated home networking controller’s adv anced CMOS design allo ws the bus interface to be connected to either a +5.0 V or a +3.3 V signaling environment. A compliant IEEE
1149.1 JT A G test interface f or board level testing is also provided, as well as a NAND tree test structure for those systems that do not support the JTAG interface.
The integrated Am79C978 home networking controller is also compliant with the PC98, PC99, and Net PC specifications. It includes the full implementation of the Microsoft OnNow and ACPI specifications, which are backward compatible with Magic Packet technology, and is compliant with the PCI Bus Pow er Management Interface specification by supporting the four power management states (D0, D1, D2, and D3), the optional PME
pin, and the necessary configuration and data
registers. The integrated Am79C978 home networking controller
is a complete Ethernet or home network node inte­grated into a single VLSI de vice. It contains a bus inter­face unit, a Direct Memory Access (DMA) Buffer Management Unit, an ISO/IEC 88023 (IEEE 802.3) compliant Media Access Controller (MAC), a Transmit FIFO and a large Receive FIFO, and an IEEE 802.3u compliant MII. Both IEEE 802.3 compliant full-duplex and half-duplex operations are supported on the MII in­terface. 10/100 Mbps operation is suppor ted through the MII interface.
The integrated Am79C978 home networking controller is register compatible with the LANCE (Am7990) and C-LANCE (Am79C90) Ethernet controllers and all
Am79C978 3
PRELIMINARY
Ethernet controllers in the PCnet Family (
except
ILACC™ (Am79C900)), including PCnet-ISA (Am79C960), PCnet-ISA+ (Am79C961), PCnet-ISA II (Am79C961A), PCnet-32 (Am79C965A), PCnet-PCI (Am79C970), PCnet-PCI II (Am79C970A), PCnet-
FAST
(Am79C971), and PCnet-
FAST+
(Am79C972). The Buffer Management Unit supports the LANCE and PCnet descriptor software models.
The integrated Am79C978 controller supports auto­configuration in the PCI configuration space. Additional integrated controller configuration parameters, includ-
ing the unique IEEE physical address, can be read from an external non-volatile memory (EEPROM) im­mediately following system reset.
In addition, the Am79C978 controller provides pro­grammable on-chip LED drivers for transmit, receive, collision, link integrity, Magic Packet status, speed, ac­tivity, power output, address match, full-duplex, or 100 Mbps status.
4 Am79C978
PRELIMINARY
BLOCK DIAGRAM
CLK RST
AD[31:0]
C/BE[3:0]
PAR
FRAME
TRDY
IRDY
STOP
IDSEL
DEVSEL
REQ
GNT PERR SERR
INTA
PCI Bus
Interface
Unit
Buffer
Management
Unit
Bus Rcv
FIFO
Bus Xmt
FIFO
FIFO
Control
Network
Port
Manager
MAC
Rcv
FIFO
12K
SRAM
MAC
Xmt
FIFO
JTAG
Port
Control
OnNow
Power
Management
Unit
802.3 MAC Core
93C46
EEPROM
Interface
LED
Control
PME
PG
TCK
TMS
TDI
TDO
Transmit
State
Machine
MII
Interface
MII
Management
MDIO
Receive
State
Machine
PHY Control
Link
Monitor
Auto
Negotiation
10 Mbps PHY
Transmit
State
Machine
MII
Interface
Receive
State
Machine
Drive
Control
Analog
Front
End
10 BASE-T
TX±
RX±
LED0 LED1 LED2 LED3 LED4
EECS EESK EEDI
EEDO
MII
Management
MDIO
RXD(3:0)/TXD(3:0)
PHY
Control
Link
Monitor
HRTXRXP/N
MDC
1Mbps HomePNA PHY
MDC
Clock
Reference
XTAL2
XTAL1
22206B-1
Am79C978 5
PRELIMINARY
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
BLOCK DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
CONNECTION DIAGRAM (144 TQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
CONNECTION DIAGRAM (160 PQFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PIN DESIGNATIONS (PQL144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Listed By Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Listed By Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
PIN DESIGNATIONS (PQL144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Listed By Driver Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Magic Packet Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Board Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
EEPROM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Ethernet Network Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
HomePNA PHY Network Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
BASIC FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MII Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MII Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
MII Network Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
MII Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
MII Management Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Auto-Poll External PHY Status Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Network Port Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
10BASE-T PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
PCI and JTAG Configuration Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Slave Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Slave I/O Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Expansion ROM Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Slave Cycle Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Disconnect When Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Disconnect Of Burst Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Master Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Bus Acquisition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Bus Master DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Basic Non-Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Basic Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
6 Am79C978
PRELIMINARY
Basic Non-Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Basic Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Target Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Disconnect With Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Disconnect Without Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Master Initiated Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Preemption During Non-Burst Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Preemption During Burst Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Master Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Advanced Parity Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Initialization Block DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Non-Burst FIFO DMA Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Burst FIFO DMA Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Re-Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Descriptor Rings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Transmit Descriptor Table Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Receive Descriptor Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Receive Frame Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Software Interrupt Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
10/100 Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Transmit and Receive Message Data Encapsulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Destination Address Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Error Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Media Access Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Medium Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Collision Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Transmit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Automatic Pad Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Transmit Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Loss of Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Late Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SQE Test Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Receive Function Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Address Matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Automatic Pad Stripping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Receive Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Loopback Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Miscellaneous Loopback Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Full-Duplex Link Status LED Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
PHY/MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
10BASE-T Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Twisted Pair Receive Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Am79C978 7
PRELIMINARY
Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Collision Detect Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Jabber Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Reverse Polarity Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Soft Reset Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
1 Mbps HomePNA PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
HomePNA PHY Medium Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
HomePNA Symbol Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Time Interval Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
ACCESS ID Intervals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Symbol 0 (SYNC interval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SYNC Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SYNC Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
AID Symbols 1 through 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
AID Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
AID Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Collisions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
JAM Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ACCESS ID Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Silence Interval (AID symbol 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Data Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Data Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Data Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Data Symbol RLL25 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Management Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Header AID Remote Control Word Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
PHY Control and Management Block (PCM Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Register Administration for 10BASE-T PHY Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Description of the Methodology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
No SRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Low Latency Receive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Direct SRAM Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Automatic EEPROM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
EEPROM Auto-Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Direct Access to the Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
EEPROM-Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
EEPROM MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Power Savings Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Power Management Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
OnNow Wake-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Link Change Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
OnNow Pattern Match Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Pattern Match RAM (PMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Magic Packet Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
IEEE 1149.1 (1990) Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Boundary Scan Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
TAP Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Supported Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Instruction Register and Decoding Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Other Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
NAND Tree Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8 Am79C978
PRELIMINARY
H_RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
S_RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Power on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Software Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
PCI Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Address PROM Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Word I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Double Word I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
PCI Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
PCI Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
PCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
PCI Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
PCI Programming Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
PCI Sub-Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
PCI Base-Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
PCI Latency Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
PCI Header Type Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
PCI I/O Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
PCI Memory Mapped I/O Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
PCI Subsystem Vendor ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
PCI Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
PCI Expansion ROM Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
PCI Capabilities Pointer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
PCI Interrupt Line Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
PCI Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
PCI MIN_GNT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
PCI MAX_LAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
PCI Capability Identifier Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
PCI Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
PCI Power Management Capabilities Register (PMC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
PCI Power Management Control/Status Register (PMCSR) . . . . . . . . . . . . . . . . . . . . . . . . . .112
PCI PMCSR Bridge Support Extensions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
PCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
RAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
RAP: Register Address Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Control and Status Registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
CSR0: Controller Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
CSR1: Initialization Block Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
CSR2: Initialization Block Address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
CSR3: Interrupt Masks and Deferral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
CSR4: Test and Features Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
CSR5: Extended Control and Interrupt 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
CSR6: RX/TX Descriptor Table Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
CSR7: Extended Control and Interrupt 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
CSR8: Logical Address Filter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
CSR9: Logical Address Filter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
CSR10: Logical Address Filter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
CSR11: Logical Address Filter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
CSR12: Physical Address Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
CSR13: Physical Address Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
CSR14: Physical Address Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Am79C978 9
PRELIMINARY
CSR15: Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
CSR16: Initialization Block Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR17: Initialization Block Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR18: Current Receive Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR19: Current Receive Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR20: Current Transmit Buffer Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR21: Current Transmit Buffer Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR22: Next Receive Buffer Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR23: Next Receive Buffer Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR24: Base Address of Receive Ring Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR25: Base Address of Receive Ring Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR26: Next Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR27: Next Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR28: Current Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR29: Current Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR30: Base Address of Transmit Ring Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR31: Base Address of Transmit Ring Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR32: Next Transmit Descriptor Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR33: Next Transmit Descriptor Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
CSR34: Current Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
CSR35: Current Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
CSR36: Next Next Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
CSR37: Next Next Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
CSR38: Next Next Transmit Descriptor Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
CSR39: Next Next Transmit Descriptor Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
CSR40: Current Receive Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
CSR41: Current Receive Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
CSR42: Current Transmit Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
CSR43: Current Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
CSR44: Next Receive Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
CSR45: Next Receive Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
CSR46: Transmit Poll Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
CSR47: Transmit Polling Interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
CSR48: Receive Poll Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
CSR49: Receive Polling Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
CSR58: Software Style. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
CSR60: Previous Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
CSR61: Previous Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
CSR62: Previous Transmit Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
CSR63: Previous Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
CSR64: Next Transmit Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
CSR65: Next Transmit Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
CSR66: Next Transmit Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
CSR67: Next Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
CSR72: Receive Ring Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
CSR74: Transmit Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
CSR76: Receive Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
CSR78: Transmit Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
CSR80: DMA Transfer Counter and FIFO Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . .140
CSR82: Transmit Descriptor Address Pointer Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
CSR84: DMA Address Register Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
CSR85: DMA Address Register Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
CSR86: Buffer Byte Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
CSR88: Chip ID Register Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
CSR89: Chip ID Register Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
CSR92: Ring Length Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
CSR100: Bus Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
CSR112: Missed Frame Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
10 Am79C978
PRELIMINARY
CSR114: Receive Collision Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
CSR116: OnNow Power Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
CSR122: Advanced Feature Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
CSR124: Test Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
CSR125: MAC Enhanced Configuration Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Bus Configuration Registers (BCRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
BCR0: Master Mode Read Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
BCR1: Master Mode Write Active. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
BCR2: Miscellaneous Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
BCR4: LED 0 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
BCR5: LED1 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
BCR6: LED2 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
BCR7: LED3 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
BCR9: Full-Duplex Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
BCR16: I/O Base Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
BCR17: I/O Base Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
BCR18: Burst and Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
BCR19: EEPROM Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
BCR20: Software Style. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
BCR22: PCI Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
BCR23: PCI Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
BCR24: PCI Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
BCR25: SRAM Size Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
BCR26: SRAM Boundary Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
BCR27: SRAM Interface Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
BCR28: Expansion Bus Port Address Lower (Used for Flash/EPROM and SRAM Accesses)169
BCR29: Expansion Port Address Upper (Used for Flash/EPROM Accesses). . . . . . . . . . . . .169
BCR30: Expansion Bus Data Port Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
BCR31: Software Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
BCR32: PHY Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
BCR33: PHY Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
BCR34: PHY Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
BCR35: PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
BCR36: PCI Power Management Capabilities (PMC) Alias Register . . . . . . . . . . . . . . . . . . .174
BCR37: PCI DATA Register 0 (DATA0) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
BCR38: PCI DATA Register 1 (DATA1) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
BCR39: PCI DATA Register 2 (DATA2) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
BCR40: PCI DATA Register 3 (DATA3) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
BCR41: PCI DATA Register 4 (DATA4) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
BCR42: PCI DATA Register 5 (DATA5) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
BCR43: PCI DATA Register 6 (DATA6) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
BCR44: PCI DATA Register 7 (DATA7) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
BCR45: OnNow Pattern Matching Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
BCR46: OnNow Pattern Matching Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
BCR47: OnNow Pattern Matching Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
BCR48: LED4 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
BCR49: PHY Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
BCR50-BCR55: Reserved Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
10BASE-T PHY Management Registers (TBRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
TBR0: 10BASE-T PHY Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
TBR1: 10BASE-T Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
TBR2 and TBR3: 10BASE-T PHY Identifier (Registers 2 and 3). . . . . . . . . . . . . . . . . . . . . . .184
TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4). . . . . . . . . . . . . . . .185
TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) . . . . . . . . . . . .186
TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6) . . . . . . . . . . . . . . . . . . .187
TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register 7) . . . . . . . . . . . . . . . . . . .187
Reserved Registers (Registers 8-15, 18, 20-23, and 25-31) . . . . . . . . . . . . . . . . . . . . . . . . . .187
TBR16: 10BASE-T INTERRUPT Status and Enable Register (Register 16). . . . . . . . . . . . . .188
Am79C978 11
PRELIMINARY
TBR17: 10BASE-T PHY Control/Status Register (Register 17). . . . . . . . . . . . . . . . . . . . . . . .189
TBR19: 10BASE-T PHY Management Extension Register (Register 19) . . . . . . . . . . . . . . . .190
Reserved Register: 10BASE-T Configuration Register (Register 22) . . . . . . . . . . . . . . . . . . .190
Reserved Register: 10BASE-T Carrier Status Register (Register 23). . . . . . . . . . . . . . . . . . .190
TBR24: 10BASE-T Summary Status Register (Register 24) . . . . . . . . . . . . . . . . . . . . . . . . . .190
1 Mbps HomePNA PHY Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
HPR0: HomePNA PHY MII Control (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
HPR1: HomePNA PHY MII Status (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
HPR2 and HPR3: HomePNA PHY MII PHY ID (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . .193
HPR4-HPR7: HomePNA PHY Auto-Negotiation (Registers 4 - 7). . . . . . . . . . . . . . . . . . . . . .193
Reserved Registers: HPR8 - HPR15, HPR17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
HPR16: HomePNA PHY Control (Register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
HPR18 and HPR19: HomePNA PHY TxCOMM (Registers 18 and 19). . . . . . . . . . . . . . . . . .194
HPR20 and HPR21: HomePNA PHY RxCOMM (Registers 20 and 21) . . . . . . . . . . . . . . . . .195
HPR22: HomePNA PHY AID (Register 22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
HPR23: HomePNA PHY Noise Control (Register 23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
HPR24: HomePNA PHY Noise Control 2 (Register 24). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
HPR25: HomePNA PHY Noise Statistics (Register 25). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
HPR26: HomePNA PHY Event Status (Register 26). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
HPR27: HomePNA PHY Event Status (Register 27). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
HPR28: HomePNA PHY ISBI Control (Register 28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
HPR29: HomePNA PHY Tx Control (Register 29). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
Initialization Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
RLEN and TLEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
RDRA and TDRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
LADRF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
PADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
Receive Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
RMD0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
RMD1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
RMD2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
RMD3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
TMD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
TMD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
TMD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
TMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
PCI Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Bus Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
10BASE-T PHY Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
1 Mbps HomePNA PHY Management Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
REGISTER PROGRAMMING SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
Am79C978 Programmable Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES . . . . . . . . . . . . . . . . . . . .221
SWITCHING CHARACTERISTICS: BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
Analog I/O - PECL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
10BASE-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
PMD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
PECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
10BASE-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE. . . . . . . . . . . . . . . . . . .228
12 Am79C978
PRELIMINARY
SWITCHING WAVEFORMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
SWITCHING TEST CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . .234
PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
PQL144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
PQR160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
APPENDIX A - ALTERNATIVE METHOD FOR INITIALIZATION. . . . . . . . . . . . . . . . . . . . . . . . . . A-1
APPENDIX B - LOOK-AHEAD PACKET PROCESSING (LAPP) CONCEPT . . . . . . . . . . . . . . . . B-1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Outline of LAPP Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
LAPP Software Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
LAPP Rules for Parsing Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6
Buffer Size Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
An Alternative LAPP Flow: Two-Interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8
LIST OF FIGURES
Figure 1. Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 2. Frame Format at the MII Interface Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 3. Slave Configuration Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 4. Slave Configuration Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 5. Slave Read Using I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 6. Slave Write Using Memory Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 7. Expansion ROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 8. Disconnect of Slave Cycle When Busy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 9. Disconnect of Slave Burst Transfer - No Host Wait States. . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 10. Disconnect of Slave Burst Transfer - Host Inserts Wait States. . . . . . . . . . . . . . . . . . . . . 42
Figure 11. Address Parity Error Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12. Slave Cycle Data Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 13. Bus Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 14. Non-Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 15. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 16. Non-Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 17. Burst Write Transfer (EXTREQ = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 18. Disconnect With Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 19. Disconnect Without Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 20. Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 21. Preemption During Non-Burst Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 22. Preemption During Burst Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 23. Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 24. Master Cycle Data Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 25. Initialization Block Read In Non-Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 26. Initialization Block Read In Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 27. Descriptor Ring Read In Non-Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 28. Descriptor Ring Read In Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 29. Descriptor Ring Write In Non-Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 30. Descriptor Ring Write In Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 31. FIFO Burst Write at Start of Unaligned Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 32. FIFO Burst Write at End of Unaligned Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 33. 16-Bit Software Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 34. 32-Bit Software Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 35. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 36. IEEE 802.3 Frame and Length Field Transmission Order . . . . . . . . . . . . . . . . . . . . . . . . 75
Am79C978 13
PRELIMINARY
Figure 37. 10BASE-T Transmit and Receive Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 38. HomePNA PHY Framing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 39. AID Symbol Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 40. AID Symbol Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 41. Transmit Data Symbol Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 42. Receive Symbol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 43. RLL 25 Coding Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 44. Block Diagram No SRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 45. Block Diagram Low Latency Receive Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 46. LED Control Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 47. OnNow Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 48. Pattern Match RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 49. NAND Tree Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 50. NAND Tree Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 51. Address Match Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 52. Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 56. Normal and Tri-State Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 57. CLK Waveform for 5 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 58. CLK Waveform for 3.3 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 59. Input Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 60. Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 61. Output Tri-State Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 62. EEPROM Read Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 63. Automatic PREAD EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 64. JTAG (IEEE 1149.1) TCK Waveform for 5 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 65. JTAG (IEEE 1149.1) Test Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 66. Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 67. Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 68. MDC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 69. Management Data Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 70. Management Data Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure B-1. LAPP Timeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-4
Figure B-2. LAPP 3 Buffer Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5
Figure B-3. LAPP Timeline for Two-Interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-9
Figure B-4. LAPP 3 Buffer Grouping for Two-Interrupt Methods . . . . . . . . . . . . . . . . . . . . . . . . . . .B-10
LIST OF TABLES
Table 1. Interrupt Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 2. External Clock/Crystal Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 3. PCI Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 4. PCI Software Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 5. Slave Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 6. Slave Configuration Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 7. Master Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 8. Descriptor Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 9. Descriptor Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 10. Receive Address Match. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 11. Auto-Negotiation Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 12. HomePNA PHY Pulse Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 13. Access ID Symbol Pulse Positions and Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 14. Blanking Interval Speed Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 15. Master Station Control Word Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 16. Slave Station Control Word Status Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 17. MII Control Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 18. EEPROM Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 19. LED Default Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 20. IEEE 1149.1 Supported Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
14 Am79C978
PRELIMINARY
Table 21. BSR Mode Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 22. Device ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 23. NAND Tree Pin Sequence (160 PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 24. NAND Tree Pin Sequence (144 TQFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 25. PCI Configuration Space Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 26. I/O Map in Word I/O Mode (DWIO = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 27. Legal I/O Accesses in Word I/O Mode (DWIO = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 28. I/O Map in DWord I/O Mode (DWIO = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 29. Legal I/O Accesses in Double Word I/O Mode (DWIO =1) . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 30. Loopback Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 31. Software Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 32. Receive Watermark Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 33. Transmit Start Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 34. Transmit Watermark Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 35. BCR Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 36. ROMTNG Programming Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 37. PHY Select Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 38. EEDET Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 39. Interface Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 40. Software Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 41. SRAM_BND Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 42. EBCS Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 43. CLK_FAC Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 44. FMDC Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 45. APDW Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 46. Am79C978 10BASE-T PHY Management Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 47. TBR0: 10BASE-T PHY Control Register (Register 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 48. TBR1: 10BASE-T PHY Status Register (Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 49. TBR2: 10BASE-T PHY Identifier (Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 50. TBR3: 10BASE-T PHY Identifier (Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 51. TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . 185
Table 52. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Base Page
Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 53. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Next Page
Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 54. TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6). . . . . . . . . . . . . . . . . 187
Table 55. TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register 7). . . . . . . . . . . . . . . . . 187
Table 56. TBR16: 10BASE-T INTERRUPT Status and Enable Register (Register 16) . . . . . . . . . . . 188
Table 57. TBR17: 10BASE-T PHY Control/Status Register (Register 17) . . . . . . . . . . . . . . . . . . . . . 189
Table 58. TBR19: 10BASE-T PHY Management Extension Register (Register 19). . . . . . . . . . . . . . 190
Table 59. TBR24: 10BASE-T Summary Status Register (Register 24). . . . . . . . . . . . . . . . . . . . . . . . 190
Table 60. HPR0: HomePNA PHY MII Control (Register 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 61. HPR1: HomePNA PHY MII Status (Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 62. HPR2 and HPR3: HomePNA PHY MII ID (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . 193
Table 63. HPR4-HPR7: HomePNA PHY Auto-Negotiation (Registers 4 - 7) . . . . . . . . . . . . . . . . . . . 193
Table 64. HPR 16: HomePNA PHY Control (Register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 65. HPR18 and HPR19: HomePNA PHY TxCOMM (Registers 18 and 19) . . . . . . . . . . . . . . . 195
Table 66. HPR20 and HPR21: HomePNA PHY RxCOMM (Registers 20 and 21) . . . . . . . . . . . . . . . 195
Table 67. HPR22: HomePNA PHY AID (Register 22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 68. HPR23: HomePNA PHY Noise Control (Register 23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 69. HPR24: HomePNA PHY Noise Control 2 (Register 24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 70. HPR25: HomePNA PHY Noise Statistics (Register 25) . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 71. HPR26: HomePNA PHY Event Status (Register 26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 72. HPR27: HomePNA PHY Event Status (Register 27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 73. HPR28: HomePNA PHY ISBI Control (Register 28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 74. HPR29: HomePNA PHY TX Control (Register 29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 75. Initialization Block (SSIZE32 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 76. Initialization Block (SSIZE32 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Am79C978 15
PRELIMINARY
Table 77. R/TLEN Decoding (SSIZE32 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 78. R/TLEN Decoding (SSIZE32 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 79. Receive Descriptor (SWSTYLE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 80. Receive Descriptor (SWSTYLE = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 81. Receive Descriptor (SWSTYLE = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 82. Transmit Descriptor (SWSTYLE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 83. Transmit Descriptor (SWSTYLE = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 84. Transmit Descriptor (SWSTYLE = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 85. PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 86. Control and Status Registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 87. Bus Configuration Registers (BCRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 88. 10BASE-T PHY Management Registers (TBRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 89. 1 Mbps HomePNA PHY Management Registers (HPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 90. Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 91. Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table A-1. Registers for Alternative Initialization Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1
16 Am79C978
PRELIMINARY
RELATED AMD PRODUCTS
Part No. Description Controllers
Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)
Integrated Controllers
Am79C930 PCnet™-Mobile Single Chip Wireless LAN Media Access Controller Am79C940B Media Access Controller for Ethernet (MACE™) Am79C961A PCnet-ISA II Full Duplex Single-Chip Ethernet Controller for ISA Bus Am79C965A PCnet-32 Single-Chip 32-Bit Ethernet Controller for 486 and VL Buses Am79C970A PCnet-PCI II Full Duplex Single-Chip Ethernet Controller for PCI Local Bus Am79C971 PCnet-
FAST
Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
Am79C972 PCnet-
FAST
+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
Manchester Encoder/Decoder
Am7992B Serial Interface Adapter (SIA)
Physical Layer Devices (Single-Port)
Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver (TAP) Am79761 Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHY™-SD) Am79C98 Twisted Pair Ethernet Transceiver (TPEX) Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+) Am79C873 10/100 Mbps Ethernet Physical Layer Transceiver (NetPHY™-1)
Physical Layer Devices (Multi-Port)
Am79C871 Quad Fast Ethernet Transceiver for 100BASE-X Repeaters (QFEXr™) Am79C988B Quad Integrated Ethernet Transceiver (QuIET™) Am79C989 Quad Ethernet Switching Transceiver (QuEST™)
Integrated Repeater/Hub Devices
Am79C981 Integrated Multiport Repeater Plus (IMR+) Am79C982 Basic Integrated Multiport Repeater (bIMR) Am79C983A Integrated Multiport Repeater 2 (IMR2™) Am79C984A Enhanced Integrated Multiport Repeater (eIMR™) Am79C985 Enhanced Integrated Multiport Repeater Plus (eIMR+™) Am79C987 Hardware Implemented Management Information Base (HIMIB™)
Am79C978 17
PRELIMINARY
CONNECTION DIAGRAM (144 TQFP)
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
56
57
58
59
60
61
62
98
99
100
101
102
103
104
54
55
53
108 107 106 105
31
4 5 6 7 8 9 10 11
1 2 3
28 29 30
12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27
32 33 34
35 36
IDSEL
AD23
VSSB
AD22
VDD_PCI
AD21 AD20
VDD AD19 AD18
VSSB
AD17
VDD_PCI
AD16
C/BE2
VSS
FRAME
IRDY VSSB TRDY
VDD_PCI
DEVSEL
STOP
VDD PERR SERR VSSB
PAR
VDD_PCI
C/BE1
AD15
VSS AD14 AD13
VSSB
AD12
C/BE3
AD24
AD25
VSSB
AD26
VDD_PCI
AD27
AD28
AD29
AD30
VSS
VSSB
AD31
VDD_PCI
REQ
GNT
PCI_CLK
RST
INTAPGVDD
TDI
VSSB
TDO
VDDB
TMS
TCK
PME
VSS
EECS
VSSB
EESK/LED1
LED2
VDDB
EEDI/LED0
EEDO/LED3
RX­DVDDRX RX+ DVSSX TX­DVDDTX TX+ DVDDD IREF DVSSD DVSSA DVDDA PHY_RST DVDDA_HR VSSB VDDB HRTRXP VDDHR HRTRXN VSSHR VDDCO XTAL1 XTAL2 VSS VDD XCLK/XTAL LED4 MDIO VSSB MDC RXD3 RXD2 VDDB RXD1 RXD0 VSS
AD11
VDD_PCI
AD10
AD9
AD8
C/BE0
VSSB
AD7
VDD_PCI
AD6
AD5
VDD
AD4
AD3
VSSB
AD2
VDD_PCI
AD1
AD0
VSS
VDD
CRS
VSSB
COL
TXD3
TXD2
TXD1
VDD
VDDB
TXD0
TX_EN
TX_CLK
VSSB
RX_ER
RX_CLK
RX_DV
132
131
130
129
128
127
126
125
124
123
122
144
143
142
141
140
139
138
137
136
135
134
133
121
120
119
118
117
116
115
114
113
112
111
110
109
4243444546474849505152
40
41
373839
Am79C978
22206B-2
18 Am79C978
PRELIMINARY
CONNECTION DIAGRAM (160 PQFP)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC NC
IDSEL
AD23
VSSB
AD22
VDD_PCI
AD21 AD20
VDD AD19 AD18
VSSB
AD17
VDD_PCI
AD16
C/BE2
VSS
FRAME
IRDY
VSSB
TRDY
VDD_PCI
DEVSEL
STOP
VDD
PERR SERR
VSSB
PAR
VDD_PCI
C/BE1
AD15
VSS AD14 AD13
VSSB
AD12
NC NC
414243444546474849505152535455565758596061626364656667686970717273747576777879
80
NC
NC
AD11
VDD_PCI
AD10
AD9
AD8
C/BE0
VSSB
AD7
VDD_PCI
AD6
AD5
VDD
AD4
AD3
VSSB
AD2
VDD_PCI
AD1
AD0
VSS
VDD
CRS
VSSB
COL
TXD3
TXD2
TXD1
VDD
VDDB
TXD0
TX_EN
TX_CLK
VSSB
RX_ER
RX_CLK
RX_DV
NC
NC
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
NCNCC/BE3
AD24
AD25
VSSB
AD26
VDD_PCI
AD27
AD28
AD29
AD30
VSS
VSSB
AD31
VDD_PCI
REQ
GNT
PCI_CLK
RST
INTAPGVDD
TDI
VSSB
TDO
VDDB
TMS
TCK
PME
VSS
EECS
VSSB
EESK/LED1
LED2
VDDB
EEDI/LED0
EEDO/LED3NCNC
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
RX­DVDDRX RX+ DVSSX TX­DVDDTX TX+ DVDDD IREF DVSSD DVSSA DVDDA PHY_RST DVDDA_HR VSSB VDDB HRTRXP VDDHR HRTRXN VSSHR VDDCO XTAL1 XTAL2 VSS VDD XCLK/XTAL LED4 MDIO VSSB MDC RXD3 RXD2 VDDB RXD1 RXD0 VSS NC NC NC NC
Am79C978
22206B-3
Am79C978 19
PRELIMINARY
PIN DESIGNATIONS (PQL144) Listed By Pin Number
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
IDSEL 37 AD11 73 VSS 109 EEDO/LED3 2 AD23 38 VDD_PCI 74 RXD0 110 EEDI/LED0 3 VSSB 39 AD10 75 RXD1 111 VDDB 4 AD22 40 AD9 76 VDDB 112 LED2 5 VDD_PCI 41 AD8 77 RXD2 113 EESK/LED1 6 AD21 42 C/BE0 78 RXD3 114 VSSB 7 AD20 43 VSSB 79 MDC 115 EECS 8 VDD 44 AD7 80 VSSB 116 VSS 9 AD19 45 VDD_PCI 81 MDIO 117 PME 10 AD18 46 AD6 82 LED4 118 TCK 11 VSSB 47 AD5 83 XCLK/XTAL 119 TMS 12 AD17 48 VDD 84 VDD 120 VDDB 13 VDD_PCI 49 AD4 85 VSS 121 TDO 14 AD16 50 AD3 86 XTAL2 122 VSSB 15 C/BE2 51 VSSB 87 XTAL1 123 TDI 16 VSS 52 AD2 88 VDDCO 124 VDD 17 FRAME 53 VDD_PCI 89 VSSHR 125 PG 18 IRDY 54 AD1 90 HRTRXN 126 INTA 19 VSSB 55 AD0 91 VDDHR 127 RST 20 TRDY 56 VSS 92 HRTRXP 128 PCI_CLK 21 VDD_PCI 57 VDD 93 VDDB 129 GNT 22 DEVSEL 58 CRS 94 VSSB 130 REQ 23 STOP 59 VSSB 95 DVDDA_HR 131 VDD_PCI 24 VDD 60 COL 96 PHY_RST 132 AD31 25 PERR 61 TXD3 97 DVDDA 133 VSSB 26 SERR 62 TXD2 98 DVSSA 134 VSS 27 VSSB 63 TXD1 99 DVSSD 135 AD30 28 PAR 64 VDD 100 IREF 136 AD29 29 VDD_PCI 65 VDDB 101 DVDDD 137 AD28 30 C/BE1 66 TXD0 102 TX+ 138 AD27 31 AD15 67 TX_EN 103 DVDDTX 139 VDD_PCI 32 VSS 68 TX_CLK 104 TX- 140 AD26 33 AD14 69 VSSB 105 DVSSX 141 VSSB 34 AD13 70 RX_ER 106 RX+ 142 AD25 35 VSSB 71 RX_CLK 107 DVDDRX 143 AD24 36 AD12 72 RX_DV 108 RX- 144 C/BE3
20 Am79C978
PRELIMINARY
PIN DESIGNATIONS (PQR160) Listed By Pin Number
Pin No.
Pin
Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
NC 41 NC 81 NC 121 NC 2 NC 42 NC 82 NC 122 NC 3 IDSEL 43 AD11 83 NC 123 EEDO/LED3 4 AD23 44 VDD_PCI 84 NC 124 EEDI/LED0 5 VSSB 45 AD10 85 VSS 125 VDDB 6 AD22 46 AD9 86 RXD0 126 LED2 7 VDD_PCI 47 AD8 87 RXD1 127 EESK/LED1 8 AD21 48 C/BE0 88 VDDB 128 VSSB 9 AD20 49 VSSB 89 RXD2 129 EECS 10 VDD 50 AD7 90 RXD3 130 VSS 11 AD19 51 VDD_PCI 91 MDC 131 PME 12 AD18 52 AD6 92 VSSB 132 TCK 13 VSSB 53 AD5 93 MDIO 133 TMS 14 AD17 54 VDD 94 LED4 134 VDDB 15 VDD_PCI 55 AD4 95 XCLK/XTAL 135 TDO 16 AD16 56 AD3 96 VDD 136 VSSB 17 C/BE2 57 VSSB 97 VSS 137 TDI 18 VSS 58 AD2 98 XTAL2 138 VDD 19 FRAME 59 VDD_PCI 99 XTAL1 139 PG 20 IRDY 60 AD1 100 VDDCO 140 INTA 21 VSSB 61 AD0 101 VSSHR 141 RST 22 TRDY 62 VSS 102 HRTRXN 142 PCI_CLK 23 VDD_PCI 63 VDD 103 VDDHR 143 GNT 24 DEVSEL 64 CRS 104 HRTRXP 144 REQ 25 STOP 65 VSSB 105 VDDB 145 VDD_PCI 26 VDD 66 COL 106 VSSB 146 AD31 27 PERR 67 TXD3 107 DVDDA_HR 147 VSSB 28 SERR 68 TXD2 108 PHY_RST 148 VSS 29 VSSB 69 TXD1 109 DVDDA 149 AD30 30 PAR 70 VDD 110 DVSSA 150 AD29 31 VDD_PCI 71 VDDB 111 DVSSD 151 AD28 32 C/BE1 72 TXD0 112 IREF 152 AD27 33 AD15 73 TX_EN 113 DVDDD 153 VDD_PCI 34 VSS 74 TX_CLK 114 TX+ 154 AD26 35 AD14 75 VSSB 115 DVDDTX 155 VSSB 36 AD13 76 RX_ER 116 TX- 156 AD25 37 VSSB 77 RX_CLK 117 DVSSX 157 AD24 38 AD12 78 RX_DV 118 RX+ 158 C/BE3 39 NC 79 NC 119 DVDDRX 159 NC 40 NC 80 NC 120 RX- 160 NC
Am79C978 21
PRELIMINARY
PIN DESIGNATIONS (PQL144) Listed By Group
Pin Name
Pin Function Type Voltage Driver
No. of
Pins
HomePNA PHY Network Ports
HRTXRXP/N
Receive/Transmit Data I/O 3.3 NA 2 XTAL1 Crystal Input (20 MHz XTAL/60 MHz CLK) I 3.3 - 1 XTAL2 Crystal Output (20 MHz XTAL) O 3.3 XTAL 1 XCLK/XTAL Oscillator/Crystal Select I 3.3 - 1
10BASE-T Network Ports
TX±
Serial T ransmit Data O 3.3 NA 2 RX± Serial Receive Data I 3.3 - 2 IREF Tied to GND via a 12 k Ω 1% resistor I 3.3 - 1 PHY_RST Buffered PCI RST signal O 3.3 OMII1 1
MII
TX_CLK
MII T r ansmit Clock I 3.3 - 1 TXD[3:0] MII Tr ansmit Data O 3.3 OMII1 4 TX_EN MII Transmit Enable O 3.3 OMII1 1 RX_CLK MII Receive Clock I 3.3 - 1 RXD[3:0] MII Receive Data I 3.3 - 4 RX_ER MII Receive Error I 3.3 - 1 RX_DV MII Receive Data Valid I 3.3 - 1 MDC MII Management Data Clock O 3.3 OMII2 1 MDIO MII Management Data I/O I/O 3.3 TSMII 1 CRS Carrier Sense I 3.3 - 1 COL Collision I 3.3 - 1
Magic Packet
PME
Power Management Event O 3.3 OD6 1 PG Power Good I 3.3 - 1
Host CPU Interface
PCI_CLK
CPU Clock I 3.3/5 - 1 C/BE[3:0] Bus Command Byte Enable I/O 3.3/5 TS3 4 AD[31:0] Address/Data I/O 3.3/5 TS3 32 DEVSEL Device Select I/O 3.3/5 STS6 1 FRAME Cycle Frame I/O 3.3/5 STS6 1 GNT Bus Grant I 3.3/5 - 1 IDSEL Initialization Device Select I 3.3/5 - 1 INTA Interrupt O 3.3/5 OD6 1 IRDY Initiator Ready I/O 3.3/5 STS6 1 PAR Parity I/O 3.3/5 STS6 1 PERR Parity Error I/O 3.3/5 STS6 1 REQ Bus Request O 3.3/5 TS3 1 RST Reset I 3.3/5 - 1 SERR System Error I/O 3.3/5 OD6 1
22 Am79C978
PRELIMINARY
Pin Name
Pin Function Type Voltage Driver
No. of
Pins
ST
OP Stop I/O 3.3/5 STS6 1
TRDY Target Ready I/O 3.3/5 STS6 1
EEPROM/LED Interface
EECS
Chip Select O 3.3 O6 1 EEDI/LED0 Data In/LED0 I/O 3.3 LED 1 EESK/LED1 Serial Clock/LED1 O 3.3 LED 1 LED2 LED2 O 3.3 LED 1 EEDO/LED3 Data Out/LED3 O 3.3 LED 1 LED4 LED4 O 3.3 LED 1
Test Access Port Interface (JTAG)
TCLK
Test Clock I 3.3 - 1 TMS Test Mode Select I 3.3 - 1 TDI Test Data In I 3.3 - 1 TDO Test Data Out O 3.3 TS6 1
Power/Ground
DVDDTX
Transceiver Digital Power P 3.3 - 1 DVDDRX Transceiver Digital Power P 3.3 - 1 VDD_PCI Digital power for the PCI bus P 3.3 - 9 VDDB Digital power for the PCI bus P 3.3 - 5 VDD Digital power P 3.3 - 7 VDDHR Digital power for HomePNA PHY P 3.3 - 1 DVDDA Transceiver Analog Power P 3.3 - 1 DVDDD Transceiver Digital Power P 3.3 - 1 VDDCO Crystal Oscillator Power P 3.3 - 1 DVDDA_HR Transceiver Analog Power P 3.3 - 1 DVSSD Transceiver Digital Ground G 0 - 1 DVSSA Transceiver Analog Ground G 0 - 1 DVSSX Transceiver Ground G 0 - 1 VSSB Digital I/O Ground G 0 - 15 VSS Digital Ground G 0 - 7 VSSHR HomePNA PHY Analog Ground G 0 - 1
Am79C978 23
PRELIMINARY
PIN DESIGNATIONS (PQR160) Listed By Group
Pin Name
Pin Function Type Voltage Driver
No. of
Pins
HomePNA PHY Network Ports
HRTXRXP/N
Receive/Transmit Data I/O 3.3 NA 2 XTAL1 Crystal Input (20 MHz XTAL/60 MHz CLK) I 3.3 - 1 XTAL2 Crystal Output (20 MHz XTAL) O 3.3 XTAL 1 XCLK/XTAL Oscillator/Crystal Select I 3.3 - 1
10BASE-T Network Ports
TX±
Serial T ransmit Data O 3.3 NA 2 RX± Serial Receive Data I 3.3 - 2 IREF Tied to GND via a 12 k Ω 1% resistor I 3.3 - 1 PHY_RST Buffered PCI RST signal O 3.3 OMII1 1
MII
TX_CLK
MII T r ansmit Clock I 3.3 - 1 TXD[3:0] MII Tr ansmit Data O 3.3 OMII1 4 TX_EN MII Transmit Enable O 3.3 OMII1 1 RX_CLK MII Receive Clock I 3.3 - 1 RXD[3:0] MII Receive Data I 3.3 - 4 RX_ER MII Receive Error I 3.3 - 1 RX_DV MII Receive Data Valid I 3.3 - 1 MDC MII Management Data Clock O 3.3 OMII2 1 MDIO MII Management Data I/O I/O 3.3 TSMII 1 CRS Carrier Sense I 3.3 - 1 COL Collision I 3.3 - 1
Magic Packet
PME
Power Management Event O 3.3 OD6 1 PG Power Good I 3.3 - 1
Host CPU Interface
PCI_CLK CPU Clock I 3.3/5 - 1 C/BE[3:0] Bus Command Byte Enable I/O 3.3/5 TS3 4 AD[31:0] Address/Data I/O 3.3/5 TS3 32 DEVSEL Device Select I/O 3.3/5 STS6 1 FRAME Cycle Frame I/O 3.3/5 STS6 1 GNT Bus Grant I 3.3/5 - 1 IDSEL Initialization Device Select I 3.3/5 - 1 INTA Interrupt O 3.3/5 OD6 1 IRDY Initiator Ready I/O 3.3/5 STS6 1 PAR Parity I/O 3.3/5 STS6 1 PERR Parity Error I/O 3.3/5 STS6 1 REQ Bus Request O 3.3/5 TS3 1 RST Reset I 3.3/5 - 1 SERR System Error I/O 3.3/5 OD6 1
24 Am79C978
PRELIMINARY
Pin Name Pin Function Type Voltage Driver
No. of
Pins
STOP Stop I/O 3.3/5 STS6 1 TRDY Target Ready I/O 3.3/5 STS6 1
EEPROM/LED Interface
EECS Chip Select O 3.3 O6 1 EEDI/LED0 Data In/LED0 I/O 3.3 LED 1 EESK/LED1 Serial Clock/LED1 O 3.3 LED 1 LED2 LED2 O 3.3 LED 1 EEDO/LED3 Data Out/LED3 O 3.3 LED 1 LED4 LED4 O 3.3 LED 1
Test Access Port Interface (JTAG)
TCLK Test Clock I 3.3 - 1 TMS Test Mode Select I 3.3 - 1 TDI Test Data In I 3.3 - 1 TDO Test Data Out O 3.3 TS6 1
Power/Ground
DVDDTX Transceiver Digital Power P 3.3 - 1 DVDDRX Transceiver Digital Power P 3.3 - 1 VDD_PCI Digital power for the PCI bus P 3.3 - 9 VDDB Digital power for the PCI bus P 3.3 - 5 VDD Digital power P 3.3 - 7 VDDHR Digital power for HomePNA PHY P 3.3 - 1 DVDDA Transceiver Analog Power P 3.3 - 1 DVDDD Transceiver Digital Power P 3.3 - 1 VDDCO Crystal Oscillator Power P 3.3 - 1 DVDDA_HR Transceiver Analog Power P 3.3 - 1 DVSSD Transceiver Digital Ground G 0 - 1 DVSSA Transceiver Analog Ground G 0 - 1 DVSSX Transceiver Ground G 0 - 1 VSSB Digital I/O Ground G 0 - 15 VSS Digital Ground G 0 - 7 VSSHR HomePNA PHY Analog Ground G 0 - 1
Am79C978 25
PRELIMINARY
PIN DESIGNATIONS Listed By Driver Type
The following table describes the various types of out­put drivers used in the Am79C978 controller. All I
OL
and
I
OH
values shown in the table apply to 3.3 V signaling.
A sustained tri-state signal is a low active signal that is driven high for one clock period bef ore it is left floating.
TX is a differential output driver. Its characteristics and those of XTAL2 output are described in the
DC CHAR-
ACTERISTICS
section.
Driver Name Type IOL (mA) IOH (mA) Load (pF)
LED LED 12 0.4 50 O6 Totem Pole 6 0.4 50 OD6 Open Drain 6 NA 50 TS3 Tri-State 3 2 50 TS6 Tri-State 6 2 50 STS6 Sustained Tri-State 6 2 50 OMII1 T ri-State 4 4 50 OMII2 T ri-State 4 4 390 TSMII Tri-State 4 4 470
26 Am79C978
PRELIMINARY
ORDERING INFORMATION Standard Products
AMD standard products are available in se veral pac kages and operating ranges. The order number (V alid Combination) is formed by a combination of the elements below.
Am79C978
TEMPERATURE RANGE
C = Commercial (0° C to +70° C)
SPEED OPTION
PACKAGE TYPE
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Valid Combinations
DEVICE NUMBER/DESCRIPTION
Not applicable
K = Plastic Quad Flat Pack (PQR160) V = Thin Quad Flat Pack (PQL144)
Am79C978 PCnet-Home Single-Chip 1/10 Mbps PCI Home Networking Controller
Valid Combinations
Am79C978
KC\W VC\W
ALTERNATE PACKAGING OPTION
\W = Trimmed and formed in a tray
\W
C
K\V
Am79C978 27
PRELIMINARY
PIN DESCRIPTIONS PCI Interface AD[31:0]
Address and Data Input/Output
Address and data are multiplexed on the same bus in­terface pins. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). Dur ing the subsequent clocks, AD[31:0] contain data. Byte or­dering is little endian by default. AD[7:0] are defined as the least significant byte (LSB) and AD[31:24] are de­fined as the most significant byte (MSB). F or FIFO data transfers, the Am79C978 controller can be pro­grammed for big endian b yte ordering. See CSR3, bit 2 (BSWP) for more details.
During the address phase of the transaction, when the Am79C978 controller is a bus master , AD[31:2] will ad­dress the active Double Word (DWord). The Am79C978 controller always drives AD[1:0] to '00' dur­ing the address phase indicating linear burst order. When the Am79C978 controller is not a bus master , the AD[31:0] lines are continuously monitored to determine if an address match exists for slave transfers.
During the data phase of the transaction, AD[31:0] are driven by the Am79C978 controller when performing bus master write and slave read operations. Data on AD[31:0] is latched by the Am79C978 controller when performing bus master read and slav e write operations.
When RST is active, AD[31:0] are inputs f or NAND tree testing.
C/BE[3:0]
Bus Command and Byte Enables Input/Output
Bus command and byte enables are multiple x ed on the same bus interface pins. During the address phase of the transaction, C/BE[3:0] define the bus command. During the data phase, C/BE[3:0] are used as byte en­ables. The byte enables define which physical byte lanes carry meaningful data. C/BE0 applies to byte 0 (AD[7:0]) and C/BE3 applies to byte 3 (AD[31:24]). The function of the byte enables is independent of the byte ordering mode (BSWP, CSR3, bit 2).
When RST is active, C/BE[3:0] are inputs for NAND tree testing
.
PCI_CLK
Clock Input
This clock is used to drive the system bus interf ace and the internal buffer management unit. All bus signals are sampled on the rising edge of PCI_CLK and all param­eters are defined with respect to this edge. The Am79C978 controller normally operates over a fre­quency range of 10 to 33 MHz on the PCI bus due to networking demands. The Am79C978 controller will
support a clock frequency of 0 MHz after certain pre­cautions are taken to ensure data integrity. This clock or a derivation is not used to drive any network func­tions.
When RST is active, PCI_CLK is an input for NAND tree testing
.
DEVSEL
Device Select Input/Output
The Am79C978 controller drives DEVSEL LOW when it detects a transaction that selects the device as a tar­get. The device samples DEVSEL to detect if a target claims a transaction that the Am79C978 controller has initiated.
When RST is active, DEVSEL is an input f or NAND tree testing
.
FRAME
Cycle Frame Input/Output
FRAME is driven by the Am79C978 controller when it is the bus master to indicate the beginning and duration of a transaction. FRAME is asserted to indicate a bus transaction is beginning. FRAME is asserted while data transfers continue. FRAME is deasserted before the final data phase of a transaction. When the Am79C978 controller is in slave mode, it samples FRAME to determine the address phase of a transac­tion.
When RST is active, FRAME is an input f or NAND tree testing
.
GNT
Bus Grant Input
This signal indicates that the access to the bus has been granted to the Am79C978 controller.
The Am79C978 controller supports bus parking. When the PCI bus is idle and the system arbiter asserts GNT without an active REQ from the Am79C978 controller, the device will drive the AD[31:0], C/BE[3:0], and PAR lines.
When RST is active, GNT is an input for NAND tree testing
.
IDSEL
Initialization Device Select Input
This signal is used as a chip select for the Am79C978 controller during configuration read and write transac­tions.
When RST is active, IDSEL is an input for NAND tree testing
.
28 Am79C978
PRELIMINARY
INTA
Interrupt Request Output
An attention signal which indicates that one or more of the following status flags is set: EXDINT, IDON, MERR, MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT, TXSTRT, UINT, MCCINT, MPDTINT, MAPINT, MRE­INT, and STINT. Each status flag has either a mask or an enable bit which allows for suppression of INTA as­sertion. Table 1 shows the flag descriptions. By default INTA is an open-drain output. For applications that need a high-active edge-sensitive interrupt signal, the INT
A pin can be configured for this mode by setting IN-
TLEVEL (BCR2, bit 7) to Table 1.
When RST is active, INTA is the output for NAND tree testing.
IRDY
Initiator Ready Input/Output
IRD Y indicates the ability of the initiator of the transac­tion to complete the current data phase. IRDY is used in conjunction with TRDY. Wait states are inserted until both IRDY and TRDY are asserted simultaneously. A data phase is completed on any clock when both IRDY and TRD Y are asserted.
When the Am79C978 controller is a bus master, it as­serts IRDY during all write data phases to indicate that valid data is present on AD[31:0]. Dur ing all read data phases, the device asserts IRD
Y to indicate that it is
ready to accept the data. When the Am79C978 controller is the target of a trans-
action, it checks IRDY during all write data phases to determine if valid data is present on AD[31:0]. During all read data phases, the device checks IRDY to deter­mine if the initiator is ready to accept the data.
When RST is active, IRDY is an input for NAND tree testing
.
PAR
Parity Input/Output
Parity is even parity across AD[31:0] and C/BE[3:0]. When the Am79C978 controller is a bus master , it gen­erates parity during the address and write data phases. It checks parity during read data phases. When the Am79C978 controller operates in slave mode , it checks parity during every address phase. When it is the target of a cycle, it checks parity during write data phases and it generates parity during read data phases.
When RST is active, PAR is an input for NAND tree testing
.
PERR
Parity Error Input/Output
During any slave write transaction and any master read transaction, the Am79C978 controller asserts PERR when it detects a data parity error and reporting of the error is enabled by setting PERREN (PCI Command register, bit 6) to 1. During any master write transaction, the Am79C978 controller monitors PERR to see if the target reports a data parity error.
When RST is active, PERR is an input for NAND tree testing
.
REQ
Bus Request Input/Output
The Am79C978 controller asserts REQ pin as a signal that it wishes to become a bus master. REQ is driven high when the Am79C978 controller does not request the bus. In Power Management mode, the REQ pin will not be driven.
Table 1. Interrupt Flags
Name Description Mask Bit Interrupt Bit
EXDINT
Excessive Deferral
CSR5, bit 6 CSR5, bit 7
IDON
Initialization Done
CSR3, bit 8 CSR0, bit 8
MERR Memory Error CSR3, bit 11 CSR0, bit 11 MISS Missed Frame CSR3, bit 12 CSR0, bit 12
MFCO
Missed Frame Count Over­flow
CSR4, bit 8 CSR4, bit 9
MPINT
Magic Packet Interrupt
CSR5, bit 3 CSR5, bit 4
RCVCCO
Receive Collision Count Overflow
CSR4, bit 4 CSR4, bit 5
RINT
Receive Interrupt
CSR3, bit 10 CSR0, bit 10 SINT System Error CSR5, bit 10 CSR5, bit 11 TINT
Transmit Interrupt
CSR3, bit 9 CSR0, bit 9 TXSTRT Transmit Start CSR4, bit 2 CSR4, bit 3
UINT User Interrupt CSR4, bit 7 CSR4, bit 6
MCCINT
MII Management Command Complete Interrupt
CSR7, bit 4 CSR7, bit 5
MPDTINT
MII PHY Detect T ransition Interrupt
CSR7, bit 0 CSR7, bit 1
MAPINT
MII Auto-Poll Interrupt
CSR7, bit 6 CSR7, bit 7
MREINT
MII Management Frame Read Error Interrupt
CSR7, bit 8 CSR7, bit 9
STINT
Software Timer Interrupt
CSR7, bit 10 CSR7, bit 11
Am79C978 29
PRELIMINARY
When RST is active, REQ is an input for NAND tree testing
.
RST
Reset Input
When RST is asserted LOW and the PG pin is HIGH, then the Am79C978 controller performs an internal system reset of the type H_RESET (HARDWARE_RESET, see section on RESET). RST must be held for a minimum of 30 clock periods. While in the H_RESET state, the Am79C978 controller will disable or deassert all outputs. RST may be asynchro­nous to clock when asserted or deasserted.
When the PG pin is LOW, RST
disables all of the PCI
pins except the PME pin.
When RST is LOW and PG is HIGH, NAND tree testing is enabled.
SERR
System Error Output
During any slave transaction, the Am79C978 controller asserts SERR when it detects an address parity error, and reporting of the error is enabled by setting PER­REN (PCI Command register, bit 6) and SERREN (PCI Command register, bit 8) to 1.
By default SERR is an open-drain output. For compo­nent test, it can be programmed to be an active-high totem-pole output.
When RST is active, SERR is an input for NAND tree testing
.
STOP
Stop Input/Output
In slave mode, the Am79C978 controller drives the STOP signal to inform the bus master to stop the cur­rent transaction. In bus master mode, the Am79C978 controller checks STOP to determine if the target wants to disconnect the current transaction.
When RST is active, STOP is an input for NAND tree testing
.
TRDY
Target Ready Input/Output
TRDY indicates the ability of the target of the transac­tion to complete the current data phase. W ait states are inserted until both IRDY and TRDY are asserted simul­taneously. A data phase is completed on any clock when both IRDY and TRDY are asserted.
When the Am79C978 controller is a bus master, it checks TRD Y during all read data phases to determine if valid data is present on AD[31:0]. During all write data phases, the device checks TRDY to determine if the target is ready to accept the data.
When the Am79C978 controller is the target of a trans­action, it asserts TRD
Y during all read data phases to indicate that valid data is present on AD[31:0]. Dur ing all write data phases, the device asserts TRDY to indi­cate that it is ready to accept the data.
When RST is active, TRDY is an input for NAND tree testing
.
Magic Packet Interface PME
Power Management Event Output, Open Drain
PME is an output that can be used to indicate that a power management ev ent (a Magic Packet, an OnNow pattern match, or a change in link state) has been de­tected. The PME
pin is asserted when either
1. PME_STATUS and PME_EN are both 1,
2. PME_EN_OVR and MPMAT are both 1, or
3. PME_EN_OVR and LCDET are both 1. The PME signal is asynchronous with respect to the
PCI clock. See the
Power Saving Mode
section for de-
tailed description.
PG
Power Good Input
The PG pin has two functions: (1) it puts the de vice into Magic Packet mode, and (2) it blocks any resets when the PCI bus power is off.
When PG is LOW and either MPPEN or MPMODE is set to 1, the device enters Magic Packet mode.
When PG is LOW, a LOW assertion of the PCI RST pin will only cause the PCI interface pins (except for PME) to be put in the high impedance state. The internal logic will ignore the assertion of RST.
When PG is HIGH, assertion of the PCI RST pin causes the controller logic to be reset and the configu­ration information to be loaded from the EEPROM.
Note: PG input should be k ept high during NAND tree testing.
Board Interface
Note: Before programming the LED pins, see the
description of LEDPE in BCR2, bit 12.
LED0
LED0 Output
This output is designed to directly drive an LED . By de­fault, LED0 indicates an active link connection. This pin can also be programmed to indicate other network sta­tus (see BCR4). The LED0 pin polarity is programma­ble, but by default it is active LOW. When the LED0 pin polarity is programmed to active LOW, the output is an open drain driver. When the LED0 pin polarity is pro-
30 Am79C978
PRELIMINARY
grammed to active HIGH, the output is a totem pole driver.
Note: The LED0 pin is multiplexed with the EEDI pin.
LED1
LED1 Output
This output is designed to directly drive an LED . By de­fault, LED1 indicates receive activity on the network. This pin can also be programmed to indicate other net­work status (see BCR5). The LED1 pin polarity is pro­grammable, but by default, it is active LOW. When the LED1 pin polarity is programmed to active LOW, the output is an open drain driver. When the LED1
pin po­larity is programmed to active HIGH, the output is a totem pole driver.
Note: The LED1 pin is multiplexed with the EESK pin.
The LED1 pin is also used during EEPROM Auto­Detection to determine whether or not an EEPROM is present at the Am79C978 controller interface. At the last rising edge of CLK while RST is active LOW, LED1 is sampled to determine the value of the EEDET bit in BCR19. It is important to maintain adequate hold time around the rising edge of the CLK at this time to ensure a correctly sampled value. A sampled HIGH value means that an EEPROM is present, and EEDET will be set to 1. A sampled LOW value means that an EE­PROM is not present, and EEDET will be set to 0. See the
EEPROM Auto-Detection
section for more details.
If no LED circuit is to be attached to this pin, then a pull­up or pull-down resistor must be attached instead in order to ground the EEDET setting.
WARNING: The input signal level of LED1 must be in­sured for correct EEPROM detection before the deas­sertion of RST.
LED2
LED2 Output
This output is designed to directly drive an LED. This pin can be programmed to indicate various network status (see BCR6). The LED2 pin polarity is program­mable, but by default it is active LOW. When the LED2 pin polarity is programmed to active LOW, the output is an open drain driver . When the LED2 pin polarity is pro­grammed to active HIGH, the output is a totem pole driver.
LED3
LED3 Output
This output is designed to directly drive an LED . By de­fault, LED3 indicates transmit activity on the network. This pin can also be programmed to indicate other net­work status (see BCR7). The LED3 pin polarity is pro­grammable, but by default it is active LOW. When the LED3 pin polarity is programmed to active LOW, the output is an open drain driver. When the LED3 pin po-
larity is programmed to active HIGH, the output is a totem pole driver.
Special attention must be given to the external circuitry attached to this pin. When this pin is used to drive an LED while an EEPROM is used in the system, then buffering may be required between the LED3
pin and the LED circuit. If an LED circuit w ere directly attached to this pin, it may create an IOL requirement that could not be met by the serial EEPROM attached to this pin. If no EEPROM is included in the system design or low current LEDs are used, then the LED3
signal may be directly connected to an LED without buffering. For more details regarding LED connection, see the sec­tion on
LED Support
.
Note: The LED3 pin is multiple x ed with the EEDO pin.
LED4
LED4 Output
This output is designed to directly drive an LED. This pin can be programmed to indicate various network status (see BCR48). The LED4 pin polarity is program­mable, but by default it is active LOW. When the LED4 pin polarity is programmed to active LOW, the output is an open drain driver . When the LED4 pin polarity is pro­grammed to active HIGH, the output is a totem pole driver.
EEPROM Interface EECS
EEPROM Chip Select Output
This pin is designed to directly interface to a serial EE­PROM that uses the 93C46 EEPROM interface proto­col. EECS is connected to the EEPROM’s chip select pin. It is controlled by either the Am79C978 controller during command portions of a read of the entire EE­PROM, or indirectly by the host system by writing to BCR19, bit 2.
EEDI
EEPROM Data In Output
This pin is designed to directly interface to a serial EEPROM that uses the 93C46 EEPROM interf ace pro­tocol. EEDI is connected to the EEPROM’s data input pin. It is controlled by either the Am79C978 controller during command portions of a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 0.
Note: The EEDI pin is multiplexed with the LED0 pin.
EEDO
EEPROM Data Out Input
This pin is designed to directly interface to a serial EEPROM that uses the 93C46 EEPROM interf ace pro­tocol. EEDO is connected to the EEPROM’s data out­put pin. It is controlled by either the Am79C978
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